Owen Anderson
bb6315d1e4
Add Thumb2 encodings for comparison and shift operators.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 19:58:36 +00:00
Owen Anderson
a99e778ed8
Add correct Thumb2 encodings for mvn and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 18:45:17 +00:00
Jim Grosbach
11bbeecdf1
Add FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 18:36:48 +00:00
Jim Grosbach
17e967eac2
Nuke redundant encoding bit set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 18:17:24 +00:00
Kalle Raiskila
38e0c9ba57
Improve code layout, mostly indentation.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119142 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 10:12:32 +00:00
Chris Lattner
b46443a686
Wire up primitive support in the assembler backend for writing .o files
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directly on the mac. This is very early, doesn't support relocations and
has a terrible hack to avoid .machine from being printed, but despite
that it generates an bitwise-identical-to-cctools .o file for stuff like
this:
define i32 @test() nounwind { ret i32 42 }
I don't plan to continue pushing this forward, but if anyone else was
interested in doing it, it should be really straight-forward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 08:49:58 +00:00
Chris Lattner
b7035d0442
split out an encoder for memri operands, allowing a relocation to be plopped
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into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 08:22:03 +00:00
Chris Lattner
17e2c18835
add support for encoding the lo14 forms used for a few PPC64 addressing
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modes. For example, we now get:
ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00]
; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 08:02:41 +00:00
Chris Lattner
f3b6e06679
fix a regression with the new instprinter: we lost the ability to
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print DBG_VALUE instructions. This should unbreak the llvm-gcc-powerpc-darwin9
buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119132 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 07:52:06 +00:00
Chris Lattner
85cf7d737d
implement the start of support for lo16 and ha16, allowing us to get stuff like:
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lis r4, ha16(__ZL4init) ; encoding: [0x3c,0x80,A,A]
; fixup A - offset: 0, value: ha16(__ZL4init), kind: fixup_ppc_ha16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 06:33:39 +00:00
Chris Lattner
b719437325
add a fixup for conditional branches, giving us output like this:
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beq cr0, LBB0_4 ; encoding: [0x41,0x82,A,0bAAAAAA00]
; fixup A - offset: 0, value: LBB0_4, kind: fixup_ppc_brcond14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 06:12:22 +00:00
Chris Lattner
8d70411dcd
change direct branches to encode with the same encoding method
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as direct calls. Change conditional branches to encode with
their own method, simplifying the JIT encoder and making room
for adding an mc fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 06:09:35 +00:00
Chris Lattner
019aef6df7
eliminate a now-unneeded operand printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 06:01:10 +00:00
Chris Lattner
a9d9ab9673
split call operands out to their own encoding class, simplifying
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code in the JIT. Use this to form the first fixup for the PPC backend,
giving us stuff like this:
bl L_foo$stub ; encoding: [0b010010AA,A,A,0bAAAAAA01]
; fixup A - offset: 0, value: L_foo$stub, kind: fixup_ppc_br24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:57:53 +00:00
Chris Lattner
7192eb8732
add proper encoding for MTCRF instead of using a hack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:19:25 +00:00
Chris Lattner
2ac190238e
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:19:05 +00:00
Chris Lattner
a04084e777
add basic encoding support for immediates and registers, allowing us
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to encode all of these instructions correctly (for example):
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x01,0x00,0x08]
stwu r1, -64(r1) ; encoding: [0x94,0x21,0xff,0xc0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 04:51:55 +00:00
Chris Lattner
a2d602529d
add a dummy entry to fix a build error
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119117 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 04:47:16 +00:00
Chris Lattner
5ffe38ef6a
Implement a basic MCCodeEmitter for PPC. This doesn't handle
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fixups yet, and doesn't handle actually encoding operand values,
but this is enough for llc -show-mc-encoding to show the base
instruction encoding information, e.g.:
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00]
stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00]
Ltmp0:
lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00]
cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00]
beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 04:16:32 +00:00
Chris Lattner
84a04adf3a
dissolve some more hacks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:53:53 +00:00
Chris Lattner
0fe7184ba1
fix some fixme's, removing dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:51:13 +00:00
Chris Lattner
ab63864564
remove asmstrings (which can never be printed) from pseudo
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instructions, allowing is to eliminate some dead operand
printing methods from the instprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119113 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:48:58 +00:00
Chris Lattner
374c608fca
strength reduce TOC temp label generation, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:42:54 +00:00
Chris Lattner
cb22fa6536
rip out a ton of old instruction printing junk now that the
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new instprinting logic is there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:39:06 +00:00
Evan Cheng
fbc8c67992
Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:30:30 +00:00
Chris Lattner
3a4dd305ac
Turn on the new instprinter by default.
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The only change in the output is:
1) we get a better comment on mfcr, we get:
mfcr r2 ; cr2
instead of:
mfcr r2 ; 32
2) we no longer emit $stub's on powerpc/leopard. The Leopard
linker autosynthesizes them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:27:05 +00:00
Chris Lattner
6d2ff122af
convert the operand bits into bitfields since they are all combinable in
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different ways. Add $non_lazy_ptr support, and proper lowering for
global values.
Now all the ppc regression tests pass with the new instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 03:13:19 +00:00
Chris Lattner
1e61e69d40
add targetoperand flags for jump tables, constant pool and block address
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nodes to indicate when ha16/lo16 modifiers should be used. This lets
us pass PowerPC/indirectbr.ll.
The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC. I have a terrible hack in the meantime, but this will have
to be revisited at some point.
Last major conversion item left is global variable references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119105 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 02:46:57 +00:00
Chris Lattner
dd57417c08
remove some extraneous quotes to make the new instprinter match.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 02:43:46 +00:00
Chris Lattner
65a0adb597
silence a ton of warnings from clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 01:45:44 +00:00
Anton Korobeynikov
a460e4a142
Attempt to unbreak cmake-based builds
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 00:48:12 +00:00
Anton Korobeynikov
3346491223
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 00:06:54 +00:00
Anton Korobeynikov
78b4fee8fd
Whitespace cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 00:06:05 +00:00
Chris Lattner
b908258d59
implement support for the MO_DARWIN_STUB TargetOperand flag,
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and have isel apply to to call operands as required. This allows
us to get $stub suffixes on label references on ppc/tiger with the
new instprinter, fixing two tests. Only 2 to go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 23:42:06 +00:00
Chris Lattner
21d272874b
tidy up, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 23:32:42 +00:00
Chris Lattner
749ba48fab
with the picbase nonsense starting to be figured out, implement
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lowering support for MovePCtoLR[8]. Down to 4 failures again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:56:43 +00:00
Chris Lattner
142b531e02
move the pic base symbol stuff up to MachineFunction
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since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:48:15 +00:00
Chris Lattner
4fd0ea0166
simplify getPICBaseSymbol a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119088 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:37:11 +00:00
Chris Lattner
6135a96792
reimplement ppc asmprinter "toc" handling to use a VariantKind
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on the operand, required for .o file writing and fixing
the PowerPC/mult-alt-generic-powerpc64.ll failure with the new
instprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:22:59 +00:00
Chris Lattner
2ead458ae8
lower PPC::MFCRpseud when transforming to MC, avoiding calling
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the aborting printSpecial() method. This gets us to 8 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 22:03:15 +00:00
Chris Lattner
959fb3dd5c
make the stubbed-out printer methods abort instead of
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printing nothing. This gets us back up to 24 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:54:34 +00:00
Chris Lattner
b2e477f546
wire up a few more things, down to 4 test failures, all
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about handling $stub, lo/hi etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:51:37 +00:00
Chris Lattner
fd6688f59a
properly wire up the instprinter to the ppc64 backend, down to 5 failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119081 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:42:53 +00:00
Chris Lattner
2e35248f14
implement pretty printing support for the various pseudo
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ops the asmprinter supported, fixing PowerPC/rlwimi2.ll
among others. Down to 20 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:39:51 +00:00
Chris Lattner
58d014f603
Wire up symbol hi/lo printing. We don't print hi()/lo(), but this gets
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us further along. Only 28 failures now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119079 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:33:07 +00:00
Chris Lattner
1520fd6095
implement basic support for symbol operand lowering,
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and printing support for call operands. Down to 77 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:20:46 +00:00
Chris Lattner
77ec256be6
trim #includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:16:04 +00:00
Chris Lattner
a7217c824d
switch PPC to a simplified MCInstLowering model.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:12:33 +00:00
Chris Lattner
8d63ba8260
fix PPC.h to not pull in TargetMachine.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:09:28 +00:00
Chris Lattner
30e2cc254b
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:00:02 +00:00
Chris Lattner
1612a619f1
even more simplifications. ARM MCInstLowering is now just
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a single function instead of a class. It doesn't need the
complexity that X86 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:58:38 +00:00
Chris Lattner
b16ddb1fb3
more shrinkification
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:41:53 +00:00
Chris Lattner
de36af4c15
more simplifications.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:40:08 +00:00
Chris Lattner
112f2390e1
simplify and tidy up
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:31:06 +00:00
Chris Lattner
fdb2ded765
implement basic support for memory operands and crbit operands,
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this fixes 3 more ppc tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:22:56 +00:00
Chris Lattner
99889132f3
implement several trivial operand printers, reducing
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failures in CodeGen/PowerPC from 120 -> 117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:11:21 +00:00
Chris Lattner
0d1b7d9e3d
Implement support for printing register and immediate operands,
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add support for darwin vs aix syntax. We now can print instructions
like this:
add r3, r3, r4
blr
and (in aix mode):
add 3, 3, 4
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:02:39 +00:00
Chris Lattner
293ef9ae0f
stub out PPCMCInstLowering, add a new option that uses it and the new
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instprinter when -enable-ppc-inst-printer is passed to llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 19:53:02 +00:00
Chris Lattner
60d5b5fdee
stub out a powerpc MCInstPrinter implementation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 19:40:38 +00:00
Chris Lattner
1139691e3a
move all the target's asmprinters into the main target. The piece
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that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:43:56 +00:00
Chris Lattner
0094345184
move PPCAsmPrinter into the main PPC library, like ARM and X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119054 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:33:33 +00:00
Chris Lattner
02bc19438f
fix cmake
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:27:11 +00:00
Chris Lattner
c476ed93f1
remove JIT support from the Alpha backend. The JIT will be moving to MC,
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and the Alpha backend isn't MCized yet. Approved by Andrew.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:24:41 +00:00
Chris Lattner
b0269cd2c8
random acts of tidiness.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119049 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:09:50 +00:00
Owen Anderson
83da6cd5e2
Second attempt at providing correct encodings for Thumb2 binary operators.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 05:37:38 +00:00
Peter Collingbourne
948cf0289f
Recognise 32-bit ror-based bswap implementation used by uclibc
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 19:54:30 +00:00
Peter Collingbourne
983611836c
Support ; as asm separator
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119006 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 19:54:23 +00:00
Bill Wendling
c93989a060
Comment out the defms until they're activated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 11:20:05 +00:00
Bill Wendling
ddc918b379
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:57:02 +00:00
Bill Wendling
1f4abcfa5c
Convert the modes to lower case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:43:34 +00:00
Bill Wendling
04863d06fb
Minor cleanups:
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:40:19 +00:00
Bill Wendling
6c470b806f
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
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future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 09:09:38 +00:00
Daniel Dunbar
115a3dd066
MC: Simplify Mach-O and ELF object writer implementations.
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- What was I thinking?????
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 07:33:40 +00:00
Wesley Peck
90eff7337d
Fixed error and re-enabled MBlaze MC disassembler tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 05:48:21 +00:00
Evan Cheng
c47f7d643e
Conditional moves are slightly more expensive than moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 05:14:20 +00:00
Wesley Peck
ec57d53342
1. Adding test cases for MBlaze MC disassembler.
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2. Fixing several errors in disassembler uncovered by test cases.
3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 02:37:59 +00:00
Evan Cheng
63f3544a7f
Add conditional move of large immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 02:25:14 +00:00
Jim Grosbach
df7e0f8d5d
Swap multiclass operand order for consistency with other patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 01:28:30 +00:00
Jim Grosbach
0f6e33b0c8
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 01:07:20 +00:00
Jim Grosbach
9e0bfb5829
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
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flag for the LDRT/STRT family instructions as a side effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:35:48 +00:00
Dan Gohman
0e65eb2065
Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:31:40 +00:00
Evan Cheng
e5e0ef180e
Fix an obvious typo which inverted an immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:27:47 +00:00
Wesley Peck
24d06f2be5
1. Adding missing immediate mode asm parser test cases.
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2. Fixing improper immediate mode reverse subtract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:03:46 +00:00
Eric Christopher
84e86c0156
Temporarily revert this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:50:48 +00:00
Evan Cheng
11c11f8ab0
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:46:13 +00:00
Wesley Peck
8bfdd87714
Fixing improperly encoded reverse subtract instructions in MBlaze backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:41:10 +00:00
Owen Anderson
b9a643e2cd
Revert r118939 while I work out why it broke some buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:36:03 +00:00
Wesley Peck
41400da31e
1. Finishing MBlaze MC asm parser test cases
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2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:30:17 +00:00
Owen Anderson
7a6b810dcb
Attemt to provide correct encodings for Thumb2 binary operators.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:18:11 +00:00
Evan Cheng
893d7fe209
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:03:38 +00:00
Eric Christopher
c0394c0b8c
Make this happen for ARM like x86. Don't entirely bail out when
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an address is in a different block, get it into a register and go
from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 22:52:32 +00:00
Evan Cheng
875a6ac09a
Add conditional mvn instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 22:42:47 +00:00
Jim Grosbach
e1634e9351
Zap a copy/paste-o bit of dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:29:10 +00:00
Jim Grosbach
2716e25c2c
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
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to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:28:15 +00:00
Owen Anderson
5de6d841a5
First stab at providing correct Thumb2 encodings, start with adc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:12:40 +00:00
Evan Cheng
529916ca4a
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 20:32:20 +00:00
Jim Grosbach
b39e6488ee
Kill more unused stuff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 19:27:45 +00:00
Jim Grosbach
a0a6a47c02
Remove unused class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 19:24:53 +00:00
Dan Gohman
52668c9a30
When the definition of an address value is in a different block
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from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 19:14:00 +00:00
Chris Lattner
269f10b316
accept lret as an alias for lretl, fixing the reopened part of PR8592
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 18:54:56 +00:00
Jim Grosbach
d75c3f136b
Fill in the default predication bits for ARM unconditional branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 18:13:26 +00:00
Jim Grosbach
80f9e6724f
Encoding for ARM LDRSB instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 17:52:59 +00:00
Chris Lattner
6b5e3978e3
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 17:41:20 +00:00
Chris Lattner
a29aae7aca
tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 17:24:29 +00:00
Kalle Raiskila
7ea1ab5f41
Fix memory access lowering on SPU, adding
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support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 10:14:03 +00:00
Eric Christopher
d0c82a683e
Fix up a few more spots of addrmode2 (or not) changes that were
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missed. Update some comments accordingly.
Fixes rdar://8652289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 09:48:30 +00:00
Dale Johannesen
0e03456a65
Remove possibly useful info from comment, per Chris.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 00:43:18 +00:00
Bruno Cardoso Lopes
7d5652dcd5
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 00:38:32 +00:00
Jim Grosbach
e50e6bcd90
Start of support for binary emit of 16-it Thumb instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 23:41:09 +00:00
Owen Anderson
8f14391314
Fill out support for Thumb2 encodings of NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 23:12:55 +00:00
Wesley Peck
48bcda4dd6
The BRK instruction in the MicroBlaze is a branch-and-link.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 22:21:08 +00:00
Wesley Peck
ef5b390263
Fix tblgen instruction errors exposed by MC asm parser tests
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Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 21:40:53 +00:00
Owen Anderson
57dac88f77
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 21:36:43 +00:00
Eric Christopher
79ab2fe01a
Revert the accidental commit I made reverting the previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:50:14 +00:00
Jim Grosbach
d1d5a39cad
ARM fixup encoding for direct call instructions (BL).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:05:40 +00:00
Eric Christopher
6c50119ba3
Revert this temporarily.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:47:02 +00:00
Eric Christopher
391f228e7e
Change the prologue and epilogue to use push/pop for the low ARM registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:26:03 +00:00
Owen Anderson
c7139a6f0d
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
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More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:07:48 +00:00
Wesley Peck
60f923c5e2
Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118807 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:41:33 +00:00
Chris Lattner
af510f16ec
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:23:57 +00:00
Jim Grosbach
c466b937db
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:04:49 +00:00
Chris Lattner
1e68fdb946
add pr#
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 17:17:56 +00:00
Jim Grosbach
7eab97f260
Encoding for ARM LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 16:55:29 +00:00
Rafael Espindola
3f2d13c98e
Remove some explicit arguments to getELFSection. This is
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a leftover from the removal of isExplicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 03:40:25 +00:00
Jim Grosbach
928f3325a7
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616
Fix encoding of Ra register for ARM smla* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691
ARM STRH encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b
Move LDM predicate operand encoding into base clase. Add STM missing STM
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encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e
Fix ARM encoding of non-return LDM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca
Fix ARM encoding of LDM+Return instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:12:48 +00:00
Nate Begeman
bf5be2654e
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 21:35:41 +00:00
Jim Grosbach
7c7ddb21c3
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
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double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
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VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes
c4bb67c8d9
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 02:13:22 +00:00
Bill Wendling
8ea974039a
Emit a '!' if this is a "writeback" register or memory address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
cc8d10e1a8
Rename a parameter to avoid confusion with a local variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 00:08:58 +00:00
Bill Wendling
8e8b18bcfa
Emit the warning about the register list not being in ascending order only once.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 23:45:59 +00:00
Bill Wendling
5fa22a1975
s/std::vector/SmallVector/
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 23:28:44 +00:00
Bill Wendling
c3236753d6
Delete the allocated vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:51:42 +00:00
Bob Wilson
66f6c79450
Define the subtarget feature for the architecture version,
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as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:47 +00:00
Bob Wilson
54f9256380
Do not use MEMBARRIER_MCR for any Thumb code.
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It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:44 +00:00
Bill Wendling
7729e06c12
Two types of instructions have register lists:
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* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:44:22 +00:00
Jim Grosbach
3a2429a86c
Change the ARMConstantPoolValue modifier string to an enumeration. This will
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help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 21:36:17 +00:00
Jim Grosbach
c9962aca8f
Handle ARM constant pool values that need an explicit reference to the '.'
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pseudo-label. (TLS stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:40:22 +00:00
Chris Lattner
274191fa70
add a case we fail to devirt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:37:28 +00:00
Jim Grosbach
16cb3763c5
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:22:26 +00:00
Jim Grosbach
5df08d8f55
Further MCize ARM constant pool values. This allows basic PIC references for
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object file emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:45:04 +00:00
Jim Grosbach
e0ee08e367
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:43:54 +00:00
Jim Grosbach
d92354c574
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
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a left shift by zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:38:15 +00:00
Jim Grosbach
a9a0dde872
ARM .word data fixups don't need an adjustment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:36:59 +00:00
Bruno Cardoso Lopes
9e03061b2f
Fix trailing whitespace and style, no functionality change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:25:34 +00:00
Jim Grosbach
54fea632b1
Add encoder method for ARM load/store shifted register offset operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:20:53 +00:00
Jim Grosbach
679cbd3b21
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
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constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 01:37:15 +00:00
Bill Wendling
5e559a22c1
Revert r118457 and r118458. These won't hold for GPRs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 00:30:18 +00:00
Bill Wendling
4b97c55648
Get the register and count from the register list operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:51:20 +00:00
Bill Wendling
3734ef3fb4
reglist has two operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:50:20 +00:00
Bill Wendling
87f4f9a946
The "addRegListOperands()" function returns the start register and the total
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number of registers in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:49:57 +00:00
Owen Anderson
c24cb3551e
Add support for ARM's specialized vector-compare-against-zero instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:21:22 +00:00
Bruno Cardoso Lopes
2c2304c623
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:42:32 +00:00
Bill Wendling
85c3f24da3
Add "write back" bit encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:28:03 +00:00
Bruno Cardoso Lopes
a84ad90c06
Fix PR8211
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:24:59 +00:00
Wesley Peck
0a67d92938
Adding working version of assembly parser for the MBlaze backend
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Major cleanup of whitespace and formatting issues in MBlaze backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:40:01 +00:00
Dale Johannesen
7179d1e5c0
Revert 118422 in search of bot verdancy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:17:22 +00:00
Jason W Kim
69ad7138b7
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 17:58:07 +00:00
Jason W Kim
6cecceb2f6
Complete listing of ARM/MC/ELF relocation enums
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 16:47:27 +00:00
Che-Liang Chiou
df65963a34
Add generating function declaration for PTX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 03:06:08 +00:00
Che-Liang Chiou
3278c4260c
Add physical register counting functions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118397 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 03:00:52 +00:00
Che-Liang Chiou
d77f2a45aa
Add a dummy PTXMCAsmStreamer class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 02:58:44 +00:00
Bill Wendling
5991487c10
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:39:58 +00:00
Bill Wendling
b32e7844e9
Revert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:32:40 +00:00
Duncan Sands
1ac7c9979a
Fix a README item: when doing a comparison with the result
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of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07 16:12:23 +00:00
Bill Wendling
e8399c6e01
In this context, a reglist is a reg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07 13:08:28 +00:00
Chris Lattner
689cf3cb62
implement aliases for div/idiv that have an explicit A register operand,
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implementing rdar://8431864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:41:18 +00:00
Bill Wendling
e717610f53
Add support for parsing register lists. We can't use a bitfield to keep track of
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the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:36:58 +00:00
Chris Lattner
04a75abe23
add aliases for movs between seg registers and mem. There are multiple
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different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:35:34 +00:00
Chris Lattner
d5b2f1aa8c
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:25:39 +00:00
Bill Wendling
8155e5b753
Return the base register of a register list for the "getReg()" method. This is
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to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:19:43 +00:00
Chris Lattner
17671510a7
work-in-progress
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:05:43 +00:00
Bill Wendling
146018fc64
General cleanup:
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- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:42:12 +00:00
Chris Lattner
db28788e4a
go to great lengths to work around a GAS bug my previous patch
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exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
Chris Lattner
8c24b0c699
rework the rotate-by-1 instructions to be defined like the
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shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:23:40 +00:00
Chris Lattner
235705b9ca
change the fp comparison instructions to not have %st0 explicitly
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listed in its asm string, for consistency with the other similar
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 20:55:09 +00:00
Chris Lattner
3af0e7d5cd
move the plethora of fp stack aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 20:47:38 +00:00
Chris Lattner
90fd797dc7
add (and document) the ability for alias results to have
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fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:57:21 +00:00
Bill Wendling
8d5acb7007
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
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(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:56:04 +00:00
Chris Lattner
98c870f87b
generalize alias support to allow the result of an alias to
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add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:25:43 +00:00
Chris Lattner
dea546b623
move fnstsw aliases to .td file, fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:58:32 +00:00
Chris Lattner
7e925cc3c9
move in/out aliases to the .td files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:52:40 +00:00
Chris Lattner
9c1dbc69d7
move sldt, imul, and movabsq aliases from c++ to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:44:26 +00:00
Chris Lattner
fb7000fcbd
correct suffix matching to search for s/l/t suffixes on
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floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:28:02 +00:00
Bill Wendling
12f40e9a63
Fix grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:51:53 +00:00
Bill Wendling
a60f157b7c
Fix grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:48:18 +00:00
Bill Wendling
d68fd9c79e
MatchRegisterName() returns 0 if it can't match the register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:45:34 +00:00
Bill Wendling
1d6a26507b
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
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while the latter doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:40:24 +00:00
Benjamin Kramer
019e378754
Add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:37:16 +00:00
Chris Lattner
5bde734598
fix a bug where we had an implicit assumption that the
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result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 08:20:59 +00:00
Eric Christopher
5e262bc943
Make sure we have movw on the target before using it.
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Fixes 8559.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:53:11 +00:00
Chris Lattner
8caa290a77
move the lcall/ljmp aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:48:45 +00:00
Chris Lattner
02ff6ba6f6
move the "movsd -> movsl" alias to the .td files,
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tidy up the movsx and movzx aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:34:58 +00:00