Chris Lattner
a7217c824d
switch PPC to a simplified MCInstLowering model.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:12:33 +00:00
Chris Lattner
8d63ba8260
fix PPC.h to not pull in TargetMachine.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:09:28 +00:00
Chris Lattner
30e2cc254b
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 21:00:02 +00:00
Chris Lattner
1612a619f1
even more simplifications. ARM MCInstLowering is now just
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a single function instead of a class. It doesn't need the
complexity that X86 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:58:38 +00:00
Chris Lattner
b16ddb1fb3
more shrinkification
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:41:53 +00:00
Chris Lattner
de36af4c15
more simplifications.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:40:08 +00:00
Chris Lattner
112f2390e1
simplify and tidy up
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:31:06 +00:00
Chris Lattner
fdb2ded765
implement basic support for memory operands and crbit operands,
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this fixes 3 more ppc tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:22:56 +00:00
Chris Lattner
99889132f3
implement several trivial operand printers, reducing
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failures in CodeGen/PowerPC from 120 -> 117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:11:21 +00:00
Chris Lattner
0d1b7d9e3d
Implement support for printing register and immediate operands,
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add support for darwin vs aix syntax. We now can print instructions
like this:
add r3, r3, r4
blr
and (in aix mode):
add 3, 3, 4
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 20:02:39 +00:00
Chris Lattner
293ef9ae0f
stub out PPCMCInstLowering, add a new option that uses it and the new
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instprinter when -enable-ppc-inst-printer is passed to llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 19:53:02 +00:00
Chris Lattner
60d5b5fdee
stub out a powerpc MCInstPrinter implementation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 19:40:38 +00:00
Chris Lattner
1139691e3a
move all the target's asmprinters into the main target. The piece
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that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:43:56 +00:00
Chris Lattner
0094345184
move PPCAsmPrinter into the main PPC library, like ARM and X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119054 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:33:33 +00:00
Chris Lattner
02bc19438f
fix cmake
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:27:11 +00:00
Chris Lattner
c476ed93f1
remove JIT support from the Alpha backend. The JIT will be moving to MC,
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and the Alpha backend isn't MCized yet. Approved by Andrew.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:24:41 +00:00
Chris Lattner
b0269cd2c8
random acts of tidiness.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119049 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:09:50 +00:00
Owen Anderson
83da6cd5e2
Second attempt at providing correct encodings for Thumb2 binary operators.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 05:37:38 +00:00
Peter Collingbourne
948cf0289f
Recognise 32-bit ror-based bswap implementation used by uclibc
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 19:54:30 +00:00
Peter Collingbourne
983611836c
Support ; as asm separator
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119006 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 19:54:23 +00:00
Bill Wendling
c93989a060
Comment out the defms until they're activated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 11:20:05 +00:00
Bill Wendling
ddc918b379
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:57:02 +00:00
Bill Wendling
1f4abcfa5c
Convert the modes to lower case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:43:34 +00:00
Bill Wendling
04863d06fb
Minor cleanups:
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 10:40:19 +00:00
Bill Wendling
6c470b806f
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
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future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 09:09:38 +00:00
Daniel Dunbar
115a3dd066
MC: Simplify Mach-O and ELF object writer implementations.
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- What was I thinking?????
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 07:33:40 +00:00
Wesley Peck
90eff7337d
Fixed error and re-enabled MBlaze MC disassembler tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 05:48:21 +00:00
Evan Cheng
c47f7d643e
Conditional moves are slightly more expensive than moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 05:14:20 +00:00
Wesley Peck
ec57d53342
1. Adding test cases for MBlaze MC disassembler.
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2. Fixing several errors in disassembler uncovered by test cases.
3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 02:37:59 +00:00
Evan Cheng
63f3544a7f
Add conditional move of large immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 02:25:14 +00:00
Jim Grosbach
df7e0f8d5d
Swap multiclass operand order for consistency with other patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 01:28:30 +00:00
Jim Grosbach
0f6e33b0c8
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 01:07:20 +00:00
Jim Grosbach
9e0bfb5829
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
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flag for the LDRT/STRT family instructions as a side effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:35:48 +00:00
Dan Gohman
0e65eb2065
Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:31:40 +00:00
Evan Cheng
e5e0ef180e
Fix an obvious typo which inverted an immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:27:47 +00:00
Wesley Peck
24d06f2be5
1. Adding missing immediate mode asm parser test cases.
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2. Fixing improper immediate mode reverse subtract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13 00:03:46 +00:00
Eric Christopher
84e86c0156
Temporarily revert this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:50:48 +00:00
Evan Cheng
11c11f8ab0
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:46:13 +00:00
Wesley Peck
8bfdd87714
Fixing improperly encoded reverse subtract instructions in MBlaze backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:41:10 +00:00
Owen Anderson
b9a643e2cd
Revert r118939 while I work out why it broke some buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:36:03 +00:00
Wesley Peck
41400da31e
1. Finishing MBlaze MC asm parser test cases
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2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:30:17 +00:00
Owen Anderson
7a6b810dcb
Attemt to provide correct encodings for Thumb2 binary operators.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:18:11 +00:00
Evan Cheng
893d7fe209
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 23:03:38 +00:00
Eric Christopher
c0394c0b8c
Make this happen for ARM like x86. Don't entirely bail out when
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an address is in a different block, get it into a register and go
from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 22:52:32 +00:00
Evan Cheng
875a6ac09a
Add conditional mvn instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 22:42:47 +00:00
Jim Grosbach
e1634e9351
Zap a copy/paste-o bit of dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:29:10 +00:00
Jim Grosbach
2716e25c2c
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
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to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:28:15 +00:00
Owen Anderson
5de6d841a5
First stab at providing correct Thumb2 encodings, start with adc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 21:12:40 +00:00
Evan Cheng
529916ca4a
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 20:32:20 +00:00
Jim Grosbach
b39e6488ee
Kill more unused stuff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 19:27:45 +00:00
Jim Grosbach
a0a6a47c02
Remove unused class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 19:24:53 +00:00
Dan Gohman
52668c9a30
When the definition of an address value is in a different block
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from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 19:14:00 +00:00
Chris Lattner
269f10b316
accept lret as an alias for lretl, fixing the reopened part of PR8592
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 18:54:56 +00:00
Jim Grosbach
d75c3f136b
Fill in the default predication bits for ARM unconditional branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 18:13:26 +00:00
Jim Grosbach
80f9e6724f
Encoding for ARM LDRSB instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 17:52:59 +00:00
Chris Lattner
6b5e3978e3
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 17:41:20 +00:00
Chris Lattner
a29aae7aca
tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 17:24:29 +00:00
Kalle Raiskila
7ea1ab5f41
Fix memory access lowering on SPU, adding
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support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 10:14:03 +00:00
Eric Christopher
d0c82a683e
Fix up a few more spots of addrmode2 (or not) changes that were
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missed. Update some comments accordingly.
Fixes rdar://8652289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 09:48:30 +00:00
Dale Johannesen
0e03456a65
Remove possibly useful info from comment, per Chris.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 00:43:18 +00:00
Bruno Cardoso Lopes
7d5652dcd5
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 00:38:32 +00:00
Jim Grosbach
e50e6bcd90
Start of support for binary emit of 16-it Thumb instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 23:41:09 +00:00
Owen Anderson
8f14391314
Fill out support for Thumb2 encodings of NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 23:12:55 +00:00
Wesley Peck
48bcda4dd6
The BRK instruction in the MicroBlaze is a branch-and-link.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 22:21:08 +00:00
Wesley Peck
ef5b390263
Fix tblgen instruction errors exposed by MC asm parser tests
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Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 21:40:53 +00:00
Owen Anderson
57dac88f77
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 21:36:43 +00:00
Eric Christopher
79ab2fe01a
Revert the accidental commit I made reverting the previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:50:14 +00:00
Jim Grosbach
d1d5a39cad
ARM fixup encoding for direct call instructions (BL).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:05:40 +00:00
Eric Christopher
6c50119ba3
Revert this temporarily.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:47:02 +00:00
Eric Christopher
391f228e7e
Change the prologue and epilogue to use push/pop for the low ARM registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:26:03 +00:00
Owen Anderson
c7139a6f0d
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
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More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:07:48 +00:00
Wesley Peck
60f923c5e2
Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118807 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:41:33 +00:00
Chris Lattner
af510f16ec
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:23:57 +00:00
Jim Grosbach
c466b937db
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:04:49 +00:00
Chris Lattner
1e68fdb946
add pr#
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 17:17:56 +00:00
Jim Grosbach
7eab97f260
Encoding for ARM LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 16:55:29 +00:00
Rafael Espindola
3f2d13c98e
Remove some explicit arguments to getELFSection. This is
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a leftover from the removal of isExplicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 03:40:25 +00:00
Jim Grosbach
928f3325a7
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616
Fix encoding of Ra register for ARM smla* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691
ARM STRH encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b
Move LDM predicate operand encoding into base clase. Add STM missing STM
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encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e
Fix ARM encoding of non-return LDM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca
Fix ARM encoding of LDM+Return instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:12:48 +00:00
Nate Begeman
bf5be2654e
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 21:35:41 +00:00
Jim Grosbach
7c7ddb21c3
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
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double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
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VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes
c4bb67c8d9
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 02:13:22 +00:00
Bill Wendling
8ea974039a
Emit a '!' if this is a "writeback" register or memory address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
cc8d10e1a8
Rename a parameter to avoid confusion with a local variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 00:08:58 +00:00
Bill Wendling
8e8b18bcfa
Emit the warning about the register list not being in ascending order only once.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 23:45:59 +00:00
Bill Wendling
5fa22a1975
s/std::vector/SmallVector/
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 23:28:44 +00:00
Bill Wendling
c3236753d6
Delete the allocated vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:51:42 +00:00
Bob Wilson
66f6c79450
Define the subtarget feature for the architecture version,
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as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:47 +00:00
Bob Wilson
54f9256380
Do not use MEMBARRIER_MCR for any Thumb code.
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It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:44 +00:00
Bill Wendling
7729e06c12
Two types of instructions have register lists:
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* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:44:22 +00:00
Jim Grosbach
3a2429a86c
Change the ARMConstantPoolValue modifier string to an enumeration. This will
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help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 21:36:17 +00:00
Jim Grosbach
c9962aca8f
Handle ARM constant pool values that need an explicit reference to the '.'
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pseudo-label. (TLS stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:40:22 +00:00
Chris Lattner
274191fa70
add a case we fail to devirt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:37:28 +00:00
Jim Grosbach
16cb3763c5
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:22:26 +00:00
Jim Grosbach
5df08d8f55
Further MCize ARM constant pool values. This allows basic PIC references for
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object file emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:45:04 +00:00
Jim Grosbach
e0ee08e367
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:43:54 +00:00
Jim Grosbach
d92354c574
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
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a left shift by zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:38:15 +00:00
Jim Grosbach
a9a0dde872
ARM .word data fixups don't need an adjustment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:36:59 +00:00
Bruno Cardoso Lopes
9e03061b2f
Fix trailing whitespace and style, no functionality change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:25:34 +00:00
Jim Grosbach
54fea632b1
Add encoder method for ARM load/store shifted register offset operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:20:53 +00:00
Jim Grosbach
679cbd3b21
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
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constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 01:37:15 +00:00
Bill Wendling
5e559a22c1
Revert r118457 and r118458. These won't hold for GPRs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 00:30:18 +00:00
Bill Wendling
4b97c55648
Get the register and count from the register list operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:51:20 +00:00
Bill Wendling
3734ef3fb4
reglist has two operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:50:20 +00:00
Bill Wendling
87f4f9a946
The "addRegListOperands()" function returns the start register and the total
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number of registers in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:49:57 +00:00
Owen Anderson
c24cb3551e
Add support for ARM's specialized vector-compare-against-zero instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:21:22 +00:00
Bruno Cardoso Lopes
2c2304c623
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:42:32 +00:00
Bill Wendling
85c3f24da3
Add "write back" bit encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:28:03 +00:00
Bruno Cardoso Lopes
a84ad90c06
Fix PR8211
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:24:59 +00:00
Wesley Peck
0a67d92938
Adding working version of assembly parser for the MBlaze backend
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Major cleanup of whitespace and formatting issues in MBlaze backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:40:01 +00:00
Dale Johannesen
7179d1e5c0
Revert 118422 in search of bot verdancy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:17:22 +00:00
Jason W Kim
69ad7138b7
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 17:58:07 +00:00
Jason W Kim
6cecceb2f6
Complete listing of ARM/MC/ELF relocation enums
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 16:47:27 +00:00
Che-Liang Chiou
df65963a34
Add generating function declaration for PTX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 03:06:08 +00:00
Che-Liang Chiou
3278c4260c
Add physical register counting functions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118397 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 03:00:52 +00:00
Che-Liang Chiou
d77f2a45aa
Add a dummy PTXMCAsmStreamer class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 02:58:44 +00:00
Bill Wendling
5991487c10
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:39:58 +00:00
Bill Wendling
b32e7844e9
Revert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:32:40 +00:00
Duncan Sands
1ac7c9979a
Fix a README item: when doing a comparison with the result
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of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07 16:12:23 +00:00
Bill Wendling
e8399c6e01
In this context, a reglist is a reg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07 13:08:28 +00:00
Chris Lattner
689cf3cb62
implement aliases for div/idiv that have an explicit A register operand,
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implementing rdar://8431864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:41:18 +00:00
Bill Wendling
e717610f53
Add support for parsing register lists. We can't use a bitfield to keep track of
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the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:36:58 +00:00
Chris Lattner
04a75abe23
add aliases for movs between seg registers and mem. There are multiple
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different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:35:34 +00:00
Chris Lattner
d5b2f1aa8c
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:25:39 +00:00
Bill Wendling
8155e5b753
Return the base register of a register list for the "getReg()" method. This is
...
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:19:43 +00:00
Chris Lattner
17671510a7
work-in-progress
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:05:43 +00:00
Bill Wendling
146018fc64
General cleanup:
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- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:42:12 +00:00
Chris Lattner
db28788e4a
go to great lengths to work around a GAS bug my previous patch
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exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
Chris Lattner
8c24b0c699
rework the rotate-by-1 instructions to be defined like the
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shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:23:40 +00:00
Chris Lattner
235705b9ca
change the fp comparison instructions to not have %st0 explicitly
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listed in its asm string, for consistency with the other similar
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 20:55:09 +00:00
Chris Lattner
3af0e7d5cd
move the plethora of fp stack aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 20:47:38 +00:00
Chris Lattner
90fd797dc7
add (and document) the ability for alias results to have
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fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:57:21 +00:00
Bill Wendling
8d5acb7007
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
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(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:56:04 +00:00
Chris Lattner
98c870f87b
generalize alias support to allow the result of an alias to
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add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:25:43 +00:00
Chris Lattner
dea546b623
move fnstsw aliases to .td file, fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:58:32 +00:00
Chris Lattner
7e925cc3c9
move in/out aliases to the .td files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:52:40 +00:00
Chris Lattner
9c1dbc69d7
move sldt, imul, and movabsq aliases from c++ to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:44:26 +00:00
Chris Lattner
fb7000fcbd
correct suffix matching to search for s/l/t suffixes on
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floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:28:02 +00:00
Bill Wendling
12f40e9a63
Fix grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:51:53 +00:00
Bill Wendling
a60f157b7c
Fix grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:48:18 +00:00
Bill Wendling
d68fd9c79e
MatchRegisterName() returns 0 if it can't match the register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:45:34 +00:00
Bill Wendling
1d6a26507b
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
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while the latter doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:40:24 +00:00
Benjamin Kramer
019e378754
Add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:37:16 +00:00
Chris Lattner
5bde734598
fix a bug where we had an implicit assumption that the
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result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 08:20:59 +00:00
Eric Christopher
5e262bc943
Make sure we have movw on the target before using it.
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Fixes 8559.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:53:11 +00:00
Chris Lattner
8caa290a77
move the lcall/ljmp aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:48:45 +00:00
Chris Lattner
02ff6ba6f6
move the "movsd -> movsl" alias to the .td files,
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tidy up the movsx and movzx aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:34:58 +00:00
Chris Lattner
414098571b
fix some bugs in the alias support, unblocking changing of "clr" aliases
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from c++ hacks to proper .td InstAlias definitions. Change them!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:31:43 +00:00
Chris Lattner
662e5a30e8
Reimplement BuildResultOperands to be in terms of the result instruction's
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operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:14:44 +00:00
Jim Grosbach
2a301704ea
Hook up the '.code {16|32}' directive to the streamer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:40:53 +00:00
Jim Grosbach
642fc9c24b
Hook up the '.thumb_func' directive to the streamer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:33:53 +00:00
Jim Grosbach
83c4018fcc
Fix past-o.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:11:33 +00:00
Jim Grosbach
ce79299f78
MC'ize the '.code 16' and '.thumb_func' ARM directives.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118301 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:08:08 +00:00
Owen Anderson
36fa3ea566
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 21:57:54 +00:00
Jim Grosbach
8da0a5785c
MC'ize simple ARMConstantValue entry emission (with a FIXME).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 20:34:24 +00:00
Owen Anderson
080c092297
Add codegen and encoding support for the immediate form of vbic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 19:27:46 +00:00
Jim Grosbach
a55661b6bd
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
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(relocations, e.g.), but this will allow simple things to flow through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 18:50:35 +00:00
Jim Grosbach
c9d1439051
Allow targets to specify the MachO CPUType/CPUSubtype information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 18:48:58 +00:00
Jim Grosbach
6d87bca865
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 17:37:13 +00:00
Duncan Sands
1e92ec6886
When passing a huge parameter using the byval mechanism, a long
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sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead. PR7170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 21:16:46 +00:00
Duncan Sands
1e96bab329
In the calling convention logic, ValVT is always a legal type,
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 10:49:57 +00:00
Evan Cheng
416941d50f
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 05:19:35 +00:00
Jim Grosbach
70933266ae
Add ARM fixup info for load/store label references. Probably will need a bit of
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tweaking when we start using it for object file emission or JIT, but it's a
start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 01:12:30 +00:00
Bill Wendling
2f46f1f59c
Add encoding for VSTR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 00:59:42 +00:00
Jim Grosbach
806e80ef42
Teach ARM Target to use the tblgen support for generating an MC'ized
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CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 23:52:49 +00:00
Owen Anderson
60f4870c22
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
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This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 23:15:26 +00:00
Owen Anderson
d966817f3c
Add support for code generation of the one register with immediate form of vorr.
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We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 22:44:51 +00:00
Jim Grosbach
35b2de012d
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 22:03:20 +00:00
Eric Christopher
e5b13cfdd0
Optimize generated code for integer materialization a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 20:21:17 +00:00
Owen Anderson
7a25825033
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
...
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 18:16:27 +00:00
Bob Wilson
d168cef664
Add codegen patterns for VST1-lane instructions. Radar 8599955.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 16:24:53 +00:00
Bob Wilson
3468c2ee20
Check for extractelement with a variable operand for the element number.
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For NEON we had been assuming this was always an immediate constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 16:24:50 +00:00
Duncan Sands
cdfad36b40
Simplify uses of MVT and EVT. An MVT can be compared directly
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 12:17:33 +00:00
Duncan Sands
1440e8b918
Inside the calling convention logic LocVT is always a simple
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 11:35:31 +00:00
Evan Cheng
dfed19fe2c
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 05:14:24 +00:00
Bill Wendling
cdbbec43a8
Put the PC encoding in the correct bit position.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 04:57:44 +00:00
Eric Christopher
000cf708ef
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 04:29:11 +00:00
Bill Wendling
92b5a2eb16
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
Jim Grosbach
2915eb4430
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:35:15 +00:00
Jim Grosbach
0a2287b909
Remove the no longer used 'Modifier' optional operand to the ARM
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printOperand() asm printer helper functions. rdar://8425198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:11:15 +00:00
Jim Grosbach
496e2b2908
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:07:48 +00:00
Jim Grosbach
e6913600c7
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:01:43 +00:00
Evan Cheng
8239daf7c8
Two sets of changes. Sorry they are intermingled.
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 00:45:17 +00:00
Evan Cheng
41957f6eb2
Modify scheduling itineraries to correct instruction latencies (not operand
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latencies) of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 00:40:22 +00:00
Eric Christopher
4c914125c4
Make sure we're only storing a single bit here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:59:09 +00:00
Chris Lattner
491561dcac
per a suggestion by Frits van Bommel, mark all MBlaze Pseudo
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instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:57:05 +00:00
Owen Anderson
f431edae5c
Revert r118097 to fix buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:47:29 +00:00
Chris Lattner
a1ca91af4e
Completely reject instructions that have an operand in their
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:40:41 +00:00
Bill Wendling
0800ce7189
Obsessive formatting changes. No functionality impact.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:53:11 +00:00
Bill Wendling
d3a124db4d
Omit unused parameter name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:46:04 +00:00
Bill Wendling
7292e0a656
Simplify the EncodeInstruction method now that a lot of the special case stuff
...
is handled with the MC encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:44:12 +00:00
Owen Anderson
1ba6064437
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:41:42 +00:00
Bill Wendling
5df0e0a61d
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
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with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00