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151 Commits

Author SHA1 Message Date
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Dale Johannesen
caa8055cf5 change per review 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36519 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-28 00:36:37 +00:00
Dale Johannesen
25c1f9e125 Prevent Thumb code from generating ARM instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36518 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
64f4fa5e0e ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 13:54:47 +00:00
Chris Lattner
120fba91a3 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36222 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 22:39:58 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:30:03 +00:00
Lauro Ramos Venancio
b8a93a45f8 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio
64c88d741e bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 17:57:23 +00:00
Evan Cheng
c70d1849b7 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35207 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:11:30 +00:00
Evan Cheng
9f6636ff0c Fix naming inconsistencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:48:02 +00:00
Evan Cheng
fa775d09c6 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:20:03 +00:00
Evan Cheng
a251570417 Constant generation instructions are re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:09:02 +00:00
Evan Cheng
b38cba928e ARM callseq_end should have a input flag operand so it would be scheduled right after the call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33832 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-03 09:11:58 +00:00
Evan Cheng
c60e76d139 - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33664 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-30 20:37:08 +00:00
Jim Laskey
1ee2925742 Make LABEL a builtin opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-26 14:34:52 +00:00
Evan Cheng
34b12d24a0 Code clean up. Use def : pat instead of defining new instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33368 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-19 20:27:35 +00:00
Evan Cheng
a8e2989ece ARM backend contribution from Apple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-19 07:51:42 +00:00
Rafael Espindola
9985f9f61e implement missing compares 
patch by Lauro
bug fixed by me


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32795 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-31 18:52:39 +00:00
Lauro Ramos Venancio
301009a0fc Implement SELECT_CC (f32/f64) for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-28 13:11:14 +00:00
Rafael Espindola
6547c55988 remove duplicated line 
bug noticed by Lauro


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32761 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio
a8f9f4af54 This patch defines extloadi1 and fixes an internal compiler error on 
arm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32760 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-26 19:30:42 +00:00
Rafael Espindola
a898ce687a more general matching of the MVN instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 17:10:13 +00:00
Rafael Espindola
f64945d83c use MVN to handle small negative constants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32459 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 01:03:11 +00:00
Rafael Espindola
450856d01b add mvn 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32454 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 00:37:38 +00:00
Rafael Espindola
a43f3d4c96 fix truncstorei1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32364 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-08 18:41:21 +00:00
Rafael Espindola
f819a4999a implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 13:58:55 +00:00
Rafael Espindola
6e8c6493f0 initial implementation of addressing mode 2 
TODO: fix lea_addri


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 17:07:32 +00:00
Chris Lattner
3751844b39 remove dead/redundant vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31435 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:48:56 +00:00
Rafael Espindola
9dca7ad78f implement zextload bool and truncstore bool 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31348 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 14:13:27 +00:00
Chris Lattner
578e64a041 implement uncond branch insertion, mark branches with isBranch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31160 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 16:47:57 +00:00
Rafael Espindola
c391d16b49 implement STRB and STRH 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31138 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-23 20:34:27 +00:00
Rafael Espindola
2435786414 use Pat to implement extloadi8 and extloadi16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31052 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 17:05:03 +00:00
Rafael Espindola
20793115a8 implement undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31049 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 13:45:00 +00:00
Rafael Espindola
3692c7ac17 implement extloadi8 and extloadi16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31047 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 12:45:04 +00:00
Rafael Espindola
71d94d8817 add blx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31037 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 16:21:43 +00:00
Rafael Espindola
70673a1a90 add isTerminatortto b and bcond 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31036 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 16:20:57 +00:00
Rafael Espindola
04d88ffdb5 add the FPUnaryOp and DFPUnaryOp classes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31013 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 20:45:22 +00:00
Rafael Espindola
c01c87c8ba add FABSS and FABSD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31012 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 20:33:13 +00:00
Rafael Espindola
3f3a6f6c3b remove extra [] in stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31008 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 18:29:14 +00:00
Rafael Espindola
32bd5f4f6a initial implementation of addressing mode 5 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31002 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 18:04:53 +00:00
Rafael Espindola
f621abca9e add FSTD and FSTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30996 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 13:36:07 +00:00
Rafael Espindola
199dd67c50 add FCPYS and FCPYD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30995 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 13:13:23 +00:00
Rafael Espindola
a605be69c3 add fdivs e fdivd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30988 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 21:50:04 +00:00
Rafael Espindola
0505be03ad expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30987 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 21:10:32 +00:00
Rafael Espindola
27e469ef13 define the DFPBinOp class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30981 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 18:39:22 +00:00
Rafael Espindola
a6f149d548 add the FPBinOp class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30980 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 18:32:36 +00:00
Rafael Espindola
90057aaeb7 define the Addr1BinOp class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30979 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 18:18:14 +00:00
Rafael Espindola
15a6c3e976 define the IntBinOp class and use it to implement the multiply instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30978 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 17:57:20 +00:00
Rafael Espindola
bb1e2fbc68 fix assembly syntax 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30977 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 17:38:12 +00:00
Rafael Espindola
82c678b83c implement LDRB, LDRSB, LDRH and LDRSH 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30976 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 17:17:22 +00:00
Rafael Espindola
bec2e38a91 implement smull and umull 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30975 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 16:33:29 +00:00
Rafael Espindola
6c5ae3edd3 fix some fp condition codes 
use non trapping comparison instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30962 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-14 13:42:53 +00:00
Rafael Espindola
33d06bcfd4 add FNEGS and FNEGD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30932 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 17:37:35 +00:00
Rafael Espindola
5395538307 add SBCS and SUBS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 17:19:20 +00:00
Rafael Espindola
42b62f3f81 implement unordered floating point compares 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30928 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 13:14:59 +00:00
Chris Lattner
65d8c1e8d4 mark call adjustments as modifying the SP 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30911 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-12 18:00:26 +00:00
Evan Cheng
af9db75943 Add properties to ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-11 21:03:53 +00:00
Rafael Espindola
493a7fc5c3 uint <-> double conversion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30862 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 20:38:57 +00:00
Rafael Espindola
667c349feb add fp sub 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30859 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 19:35:01 +00:00
Rafael Espindola
b47e1d033c add double <-> int conversion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30858 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 18:55:14 +00:00
Rafael Espindola
0d9fe764df compare doubles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 16:33:47 +00:00
Rafael Espindola
4b20fbc01d initial support for fp compares. Unordered compares not implemented yet 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 12:56:00 +00:00
Rafael Espindola
2dc0f2b55c add float -> double and double -> float conversion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 17:50:29 +00:00
Rafael Espindola
ecdb9f93c4 add ADDS and ADCS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30830 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 17:18:28 +00:00
Rafael Espindola
e5bbd6d753 implement FUITOS and FUITOD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30803 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-07 14:24:52 +00:00
Rafael Espindola
5aca927ae6 implement FLDD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-07 14:03:39 +00:00
Rafael Espindola
d9ae778125 implement fadds, faddd, fmuls and fmuld 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30801 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-07 13:46:42 +00:00
Rafael Espindola
935b1f8fce add optional input flag to FMRRD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30774 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 20:33:26 +00:00
Rafael Espindola
a284584352 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30754 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 16:48:49 +00:00
Rafael Espindola
cd71da5cf0 Implement floating point constants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30704 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-03 17:27:58 +00:00
Rafael Espindola
9e071f0ae3 fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-02 19:30:56 +00:00
Rafael Espindola
27185190e6 add floating point registers 
implement SINT_TO_FP


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-29 21:20:16 +00:00
Rafael Espindola
3ad5e5cf99 add shifts to addressing mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 12:09:43 +00:00
Rafael Espindola
817e7fdb8b implement SRL and MUL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30262 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 19:24:19 +00:00
Rafael Espindola
7cca7c5317 partial implementation of the ARM Addressing Mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 17:25:40 +00:00
Rafael Espindola
0a200600e7 implement shl and sra 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 17:36:23 +00:00
Rafael Espindola
4e30764d55 add the eor (xor) instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30189 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 16:59:47 +00:00
Rafael Espindola
5c2aa0a4d8 implement unconditional branches 
fix select.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30186 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 12:47:03 +00:00
Rafael Espindola
b52b54d4af add the orr instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30125 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-06 18:03:12 +00:00
Rafael Espindola
cdda88cd12 add the "eq" condition code 
implement a movcond instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 17:19:08 +00:00
Rafael Espindola
6f602de3b6 create a generic bcond instruction that has a conditional code argument 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 16:13:15 +00:00
Rafael Espindola
687bc49d1a initial support for branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 13:45:55 +00:00
Rafael Espindola
3c000bf817 initial support for select 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-21 22:00:32 +00:00
Rafael Espindola
a5dfc835d4 add the and instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29793 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-21 13:58:59 +00:00
Rafael Espindola
f3a335cedf add a "load effective address" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-17 17:09:40 +00:00
Rafael Espindola
ec46ea34dc Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-16 14:43:33 +00:00
Evan Cheng
bb7b844bec CALLSEQ_* produces chain even if that's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:03:33 +00:00
Rafael Espindola
46adf8119d change the addressing mode of the str instruction to reg+imm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-08 20:35:03 +00:00
Rafael Espindola
f4fda80403 add and use ARMISD::RET_FLAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29499 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-03 17:02:20 +00:00
Rafael Espindola
1ed3af11b5 start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29451 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-01 18:53:10 +00:00
Rafael Espindola
44819cb20a implemented sub 
correctly update the stack pointer in the prologue and epilogue


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-21 12:26:16 +00:00
Rafael Espindola
355746359e initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-18 17:00:30 +00:00
Rafael Espindola
84b19be6ab skeleton of a lowerCall implementation for ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-16 01:02:57 +00:00
Rafael Espindola
a4e64359aa add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 11:36:48 +00:00
Rafael Espindola
aefe14299a create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 01:41:35 +00:00
Rafael Espindola
58421d7d08 initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-18 00:08:07 +00:00
Rafael Espindola
85ede37ca9 Expand ret into "CopyToReg;BRIND" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-30 17:33:19 +00:00
Rafael Espindola
a1334cdfb2 On ARM, alignment is in bits 
Add lr as a hard coded operand of bx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28494 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-26 10:56:17 +00:00
Rafael Espindola
dc124a234a implement movri 
add a stub LowerFORMAL_ARGUMENTS


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-18 21:45:49 +00:00