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403 Commits

Author SHA1 Message Date
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Jim Grosbach
b0786b33fa addrmode2 is gone from these, so no need for the reg0 operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 18:11:24 +00:00
Owen Anderson
7011eee9b5 Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 23:33:11 +00:00
Kevin Enderby
9e5887b17e Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 22:44:48 +00:00
Jim Grosbach
4ebbf7b8a8 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 00:50:06 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
Owen Anderson
31d485ec9a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:07:25 +00:00
Owen Anderson
df0caeb6ec Revert r140412. This affects more instructions than intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:02:01 +00:00
Owen Anderson
d256056581 Thumb2 register-shifted-register loads cannot target the PC or the SP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:00:32 +00:00
Owen Anderson
d9346fbb06 tMOVSr is not allowed in an IT block either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:57:20 +00:00
Owen Anderson
9f666b5f2e CPS instructions are UNPREDICTABLE inside IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:47:10 +00:00
Owen Anderson
04c7877894 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
Owen Anderson
ecd1c55790 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:07:10 +00:00
Owen Anderson
cb77551927 Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:30:01 +00:00
Owen Anderson
8b22778431 Fix bitfield decoding based on Eli's feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:04:48 +00:00
Owen Anderson
e4f2df945a Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:42:36 +00:00
Owen Anderson
89db0f690c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:29:48 +00:00
Owen Anderson
705b48ff86 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:08:33 +00:00
Owen Anderson
98c5ddabca Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:38:46 +00:00
Owen Anderson
34626acf7f Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:06:21 +00:00
Owen Anderson
a3157b4026 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 18:56:30 +00:00
Owen Anderson
921d01ae1f LDM writeback is not allowed if Rn is in the target register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:33 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Owen Anderson
441462f932 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Owen Anderson
170580e8f4 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:11:18 +00:00
Owen Anderson
8a83f71301 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:10:42 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:42:28 +00:00
Owen Anderson
6de3c6f1a9 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:24:38 +00:00
Owen Anderson
a1c110045a Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8 Fix 80 columns violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:23:50 +00:00
James Molloy
c047dcade5 Fix up r137380 based on post-commit review by Jim Grosbach. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:02:14 +00:00
Owen Anderson
b45b11bce1 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 22:00:41 +00:00
Owen Anderson
eaca928a37 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:58:27 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:32:08 +00:00
Owen Anderson
9f7e831994 Spelling fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:47:57 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d Update for feedback from Jim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15 ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:09:22 +00:00
Owen Anderson
9bd655dcde Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 06:19:51 +00:00
Owen Anderson
99906830e8 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 18:30:18 +00:00
Owen Anderson
f44082091c Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:40:22 +00:00
Owen Anderson
12a1e3bbcb Be careful not to walk off the end of the operand info list while updating VFP predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:35:46 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:08:43 +00:00
Owen Anderson
e234d02204 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 17:21:43 +00:00
Owen Anderson
82265a2c72 Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:51:38 +00:00
Owen Anderson
6153a036f5 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:45:18 +00:00
Owen Anderson
8e1e60b5f8 Reject invalid imod values in t2CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:44:04 +00:00
Owen Anderson
357ec6850b Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:27:12 +00:00
Owen Anderson
2cbf210450 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:22:06 +00:00
Owen Anderson
b113ec55e8 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 17:56:58 +00:00
Owen Anderson
78affc9ea1 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:31:17 +00:00
Owen Anderson
1dd56f05e1 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:15:25 +00:00
Owen Anderson
14090bf263 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:11:02 +00:00
Jim Grosbach
c40578250d Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 21:58:18 +00:00
Jim Grosbach
70939ee141 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 21:51:27 +00:00
Owen Anderson
0aa38ab1fb Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137838 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:14:48 +00:00
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:44:15 +00:00
Owen Anderson
16280308ac Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:45:44 +00:00
Owen Anderson
ef2865a8ea Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137686 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:38:54 +00:00
Owen Anderson
c537f3be0c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:51:32 +00:00
Owen Anderson
7a2e1770ea Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 18:44:44 +00:00
Owen Anderson
0d09499cf3 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 20:36:11 +00:00
Owen Anderson
79628e92e1 Fix decoding of ARM-mode STRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 20:02:50 +00:00
Owen Anderson
7cdbf086e4 Fix decoding of pre-indexed stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 18:12:39 +00:00
Owen Anderson
3f3570a38b Separate decoding for STREXD and LDREXD to make each work better. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:58:32 +00:00
Jim Grosbach
342ebd5f38 ARM STRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:18:00 +00:00
Owen Anderson
adf2b094cb Add another accidentally omitted predicate operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:08:38 +00:00
Owen Anderson
1fb6673bc2 Add missing predicate operand on SMLA and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:38 +00:00
Owen Anderson
cbfc044acd Fix decoding support for STREXD and LDREXD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:34:58 +00:00
Owen Anderson
508e1d3db5 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:47:56 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:21:46 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:04:56 +00:00
Owen Anderson
71156a6e00 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:00:18 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:55:42 +00:00
Owen Anderson
ae0bc5deaa Improve error checking in the new ARM disassembler. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:24:51 +00:00
Jim Grosbach
59999264e6 ARM LDRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:43:54 +00:00
Owen Anderson
8533ebad6f Add initial support for decoding NEON instructions in Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 19:01:10 +00:00
Owen Anderson
10cbaab7b7 Cleanups based on Nick Lewycky's feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:36:48 +00:00
Owen Anderson
33e57515b1 Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 00:03:03 +00:00
Owen Anderson
de317f40f7 Tighten operand checking of register-shifted-register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:33:27 +00:00
Owen Anderson
c36481c474 Tighten operand checking on memory barrier instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d Tighten operand checking on CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00
Benjamin Kramer
793b811c50 ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:02:50 +00:00
Owen Anderson
51157d2234 Silence an false-positive warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:38:14 +00:00
Owen Anderson
bd9091c18d Tighten Thumb1 branch predicate decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 20:55:18 +00:00
Jim Grosbach
16578b5088 ARM simplify the postidx_reg operand encoding. 
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 16:11:38 +00:00
Owen Anderson
14c903a76b Fix broken encodings for the Thumb2 LDRD/STRD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 23:18:05 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 23:50:40 +00:00
Jim Grosbach
e1cf5902ec ARM SRS instruction parsing, diassembly and encoding support. 
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 20:26:09 +00:00
Jim Grosbach
2c6363a62d ARM assembly parsing and encoding for RFE instruction. 
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 18:47:24 +00:00
Chandler Carruth
ac03e736c7 Rewrite the CMake build to use explicit dependencies between libraries, 
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 00:14:25 +00:00
Owen Anderson
aa3402e280 Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 17:18:57 +00:00
Owen Anderson
7b2958392c Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:36:57 +00:00
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX. 
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:09:25 +00:00
Jim Grosbach
85bfd3b023 ARM cleanup of rot_imm encoding. 
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 21:28:43 +00:00
Chandler Carruth
b35552d440 Clean up a pile of hacks in our CMake build relating to TableGen. 
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 00:09:08 +00:00
Jim Grosbach
580f4a9c1c ARM assembly parsing and encoding for SSAT instruction. 
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 22:20:28 +00:00
Jim Grosbach
4a5ffb399f ARM SSAT instruction 5-bit immediate handling. 
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 23:16:18 +00:00
Jim Grosbach
0632247818 Thumb assembly support for SETEND instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:52:23 +00:00
Owen Anderson
152d4a4bb6 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:38:37 +00:00
Evan Cheng
ee04a6d3a4 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 23:34:39 +00:00
Jim Grosbach
dde038af59 ARM PKH shift ammount operand printing tweaks. 
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 21:40:26 +00:00
Jim Grosbach
a0472dc420 ARM: Tidy up representation of PKH instruction. 
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 20:32:09 +00:00
Owen Anderson
565a036697 Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135442 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 23:25:34 +00:00
Owen Anderson
0af0dc8ac6 Re-apply r135319 with a fix for the constant island pass. 
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 18:50:52 +00:00
Owen Anderson
91ddfc4723 Revert r135319 in an attempt to get to unbreak testers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135343 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 09:17:43 +00:00
Owen Anderson
49e163b6c7 Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 22:49:31 +00:00
Owen Anderson
43967a97cf Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 18:46:47 +00:00
NAKAMURA Takumi
20722b6cda Eliminate "const" from extern const to fix breakeage since r135184 on msvc. 
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 12:50:21 +00:00
Evan Cheng
c60f9b7523 Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 20:59:42 +00:00
Jim Grosbach
9dec507ecb ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:00:31 +00:00
Evan Cheng
22fee2dff4 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-28 20:07:07 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-28 19:10:37 +00:00
Cameron Zwarich
da86a08284 Restore an accidentally removed comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132044 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:48:17 +00:00
Cameron Zwarich
328634598f Change the order of tBX's operands so that the predicate operands come after the 
target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:23 +00:00
Cameron Zwarich
8f161c3a95 Rename tBX_Rm to tBX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:20 +00:00
Johnny Chen
75f4296c7c Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx 
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 17:51:04 +00:00
Johnny Chen
a96581f4f7 Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 20:32:41 +00:00
Kevin Enderby
e23aea28f9 Fix a bug in the case that there is no add or subtract symbol and the offset 
value is zero so it does not add a NULL expr operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 21:02:27 +00:00
Johnny Chen
4aaf3465f7 Fix typo in the comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 23:58:52 +00:00
Johnny Chen
3a96122c4a Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:52:15 +00:00
Johnny Chen
a704bc9354 A8.6.315 VLD3 (single 3-element structure to all lanes) 
The a bit must be encoded as 0.

rdar://problem/9292625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:49:08 +00:00
Johnny Chen
de29a52940 The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 
(single element or n-element structure to all lanes).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:10:45 +00:00
Johnny Chen
cd695fdac1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 19:13:28 +00:00
Johnny Chen
e8d087ad35 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:59:01 +00:00
Johnny Chen
6c7e4147dc Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 
rdar://problem/9280470


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:35:49 +00:00
Johnny Chen
471d73d5d3 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 
rdar://problem/9279440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:04:32 +00:00
Johnny Chen
9bb386a933 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 
rdar://problem/9276651


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 19:46:05 +00:00
Johnny Chen
119af20c7b Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 17:51:02 +00:00
Johnny Chen
55e6419b12 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 23:31:00 +00:00
Johnny Chen
ec51a6225c The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:41:51 +00:00
Johnny Chen
32cefad4b3 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:17:51 +00:00
Johnny Chen
f9ce2cba42 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 18:48:00 +00:00
Johnny Chen
49fdfe3ce5 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 17:09:04 +00:00
Johnny Chen
e77f72d7d2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:14:49 +00:00
Johnny Chen
de16508955 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 23:33:30 +00:00
Johnny Chen
35563fee7b Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:14:35 +00:00
Johnny Chen
f18dfc3a31 Trivial comment fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:51:50 +00:00
Johnny Chen
e679d3331b Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:34:12 +00:00