Owen Anderson
f523e476c2
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Owen Anderson
71e416ac3a
Add isConditionalMove bits to X86 and ARM instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:57:01 +00:00
Chris Lattner
52a261b3c1
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:31:19 +00:00
Evan Cheng
7602acbf3b
Fix LDM_RET schedule itinery.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:57:08 +00:00
Chris Lattner
979b061819
remove some dead code. t2addrmode_imm8s4 is never used in a
...
pattern, so there is no need to define a matching function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 22:51:11 +00:00
Chris Lattner
5bcb8a6112
temporarily revert r112664, it is causing a decoding conflict, and
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the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 16:00:50 +00:00
Bill Wendling
43a6c5e2fc
We have a chance for an optimization. Consider this code:
...
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:41:22 +00:00
Bill Wendling
55c134a261
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
...
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 22:05:23 +00:00
Jim Grosbach
663e339e20
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
...
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 19:49:58 +00:00
Bill Wendling
4822bce4aa
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
...
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 01:47:35 +00:00
Bill Wendling
1f7bf0e1f5
- Add a parameter to T2I_bin_irs for those patterns which set the S bit.
...
- Create T2I_bin_sw_irs to be like T2I_bin_w_irs, but that it sets the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:55:31 +00:00
Bill Wendling
2c4b30ebca
Name ANDflag to ANDS, which is less stupid.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:06:09 +00:00
Bill Wendling
0b4aa7d11b
Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but
...
it sets the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:02:11 +00:00
Jim Grosbach
9f134b5713
Restrict the register to tGPR to make sure the str instruction will be
...
encodable as a 16-bit wide instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 17:02:47 +00:00
Dan Gohman
4b7dff9a79
Revert r112176; it broke test/CodeGen/Thumb2/thumb2-cmn.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 15:50:25 +00:00
Bill Wendling
01b1e1c958
There seems to be a (potential) hardware bug with the CMN instruction and
...
comparison with 0. These two pieces of code should give identical results:
rsbs r1, r1, 0
cmp r0, r1
mov r0, #0
it ls
mov r0, #1
and:
cmn r0, r1
mov r0, #0
it ls
mov r0, #1
However, the CMN gives the *opposite* result when r1 is 0. This is because the
carry flag is set in the CMP case but not in the CMN case. In short, the CMP
instruction doesn't perform a truncate of the (logical) NOT of 0 plus the value
of r0 and the carry bit (because the "carry bit" parameter to AddWithCarry is
defined as 1 in this case, the carry flag will always be set when r0 >= 0). The
CMN instruction doesn't perform a NOT of 0 so there is never a "carry" when this
AddWithCarry is performed (because the "carry bit" parameter to AddWithCarry is
defined as 0).
The AddWithCarry in the CMP case seems to be relying upon the identity:
~x + 1 = -x
However when x is 0 and unsigned, this doesn't hold:
x = 0
~x = 0xFFFF FFFF
~x + 1 = 0x1 0000 0000
(-x = 0) != (0x1 0000 0000 = ~x + 1)
Therefore, we should disable *all* versions of CMN, especially when comparing
against zero, until we can limit when the CMN instruction is used (when we know
that the RHS is not 0) or when we have a hardware fix for this.
(See the ARM docs for the "AddWithCarry" pseudo-code.)
This is related to <rdar://problem/7569620>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 09:07:33 +00:00
Bill Wendling
f0e132c385
Add the "isCompare" attribute to the defm instead of each individual instr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 00:05:48 +00:00
Jakob Stoklund Olesen
00d3dda86f
Don't call tablegen'ed Predicate_* functions in the ARM target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 20:39:04 +00:00
Jim Grosbach
c5ed0134a7
80 column cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 18:39:16 +00:00
Bob Wilson
f955f290c9
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0 ". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 17:23:19 +00:00
Bob Wilson
dc66edaced
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
...
that the high halfword is zero. The shift need not be exactly 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 22:26:55 +00:00
Bob Wilson
22f5dc79c0
Rename sat_shift operand to shift_imm, in preparation for using it for other
...
instructions besides saturate instructions. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 18:27:34 +00:00
Bob Wilson
136e491280
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 03:18:29 +00:00
Bob Wilson
20d8e4e7aa
Add a Thumb2 t2RSBrr instruction for disassembly only.
...
This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 23:24:25 +00:00
Bob Wilson
38aa2871fc
Move the Thumb2 SSAT and USAT optional shift operator out of the
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instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 21:48:10 +00:00
Evan Cheng
ee34987fd5
Really control isel of barrier instructions with cpu feature.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:36:31 +00:00
Evan Cheng
11db068721
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
...
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:22:01 +00:00
Daniel Dunbar
9db683b06c
ARM: Quote $p in an asm string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 04:46:10 +00:00
Evan Cheng
3611d9e25d
CBZ and CBNZ are implemented.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 23:27:11 +00:00
Evan Cheng
5818032521
Delete some unused instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 19:36:22 +00:00
Bill Wendling
c98af3370f
Use the "isCompare" machine instruction attribute instead of calling the
...
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08 05:04:59 +00:00
Bob Wilson
d4d188e502
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31 06:28:10 +00:00
Jim Grosbach
6ccfc507dc
Many Thumb2 instructions can reference the full ARM register set (i.e.,
...
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
Nate Begeman
0e0a20eb38
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 22:48:09 +00:00
Nate Begeman
692433bc2d
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
...
Behave identically to __qadd & __qsub RealView instruction intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 17:56:55 +00:00
Jim Grosbach
7946494ceb
Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 23:17:45 +00:00
Jim Grosbach
f084a5e81d
Using BIC for immediates needs an extra bump for its complexity to get
...
instruction selection to prefer it when possible. rdar://7903972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 16:07:04 +00:00
Jim Grosbach
469bbdb597
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
...
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 23:05:05 +00:00
Jim Grosbach
502e0aa628
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 17:45:16 +00:00
Bob Wilson
fed76ffa56
Add missing address register update to t2LDM_RET instruction.
...
Patch by Brian Lucas. PR7636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 16:02:13 +00:00
Evan Cheng
c36b5b9730
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 05:38:36 +00:00
Eli Friedman
761fa7af9e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 18:20:04 +00:00
Jim Grosbach
a967d1121a
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:27 +00:00
Evan Cheng
86050dc8cc
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Jim Grosbach
18f30e6f5e
Clean up 80 column violations. No functional change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 21:53:11 +00:00
Jim Grosbach
c9792a3c1f
Cosmetic cleanup. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 17:51:20 +00:00
Jim Grosbach
5caeff5c01
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 17:37:40 +00:00
Jim Grosbach
0798eddd07
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:49:24 +00:00
Jim Grosbach
54e13eceff
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:22:21 +00:00
Bob Wilson
a85df80ed7
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:43:08 +00:00
Bob Wilson
c21763fd99
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 22:41:19 +00:00
Bob Wilson
bb7ecb2bf5
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
Evan Cheng
9085f98b32
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:28:01 +00:00
Evan Cheng
5fd1c9be2d
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:07:03 +00:00
Evan Cheng
ea420b20d4
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:52:25 +00:00
Anton Korobeynikov
bd91ea53f8
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 09:15:36 +00:00
Jim Grosbach
29402132f3
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:44:43 +00:00
Jim Grosbach
b1dc393bd5
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:44:35 +00:00
Bob Wilson
ec80e2693a
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
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such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:41:18 +00:00
Bob Wilson
ab3460519e
Remove the writeback flag from ARM's address mode 4. Now that we have separate
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instructions for ld/st with writeback, the flag is completely redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 17:46:45 +00:00
Bob Wilson
815baebe1c
Change ARM ld/st multiple instructions to have variant instructions for
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writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 01:08:20 +00:00
Johnny Chen
c0b5dce3fa
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
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instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98285 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 21:02:50 +00:00
Johnny Chen
ae1757b452
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
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Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 01:13:36 +00:00
Johnny Chen
dd0f3cf189
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
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operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 18:59:38 +00:00
Johnny Chen
a2c618a0f0
MSR (Move to Special Register from ARM core register) requires a mask to specify
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what fields of the CPSR or SPSR are affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 21:39:34 +00:00
Bob Wilson
f5fd499791
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
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immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:56:15 +00:00
Johnny Chen
fb86d78a45
Trivial comment change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05 01:45:46 +00:00
Johnny Chen
267124cff2
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
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of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 22:24:41 +00:00
Johnny Chen
0635fc5c27
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
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Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0 ]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 17:40:44 +00:00
Johnny Chen
e54a3ef087
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
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and STRHT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 18:45:36 +00:00
Johnny Chen
0f7866e796
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
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for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 02:09:43 +00:00
Evan Cheng
bc9d22c99a
Eliminate unused instruction classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 00:43:15 +00:00
Johnny Chen
a43398283d
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
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disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 00:16:28 +00:00
Johnny Chen
10a77e14a0
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 22:11:06 +00:00
Johnny Chen
b5031ad4c0
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
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the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 19:38:59 +00:00
Johnny Chen
93042d1dc8
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
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SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
Johnny Chen
9d3acaa1a0
AL is an optional mnemonic extension for always, except in IT instructions.
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Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 17:57:15 +00:00
Dan Gohman
bc9d98b52d
The mayHaveSideEffects flag is no longer used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 23:47:46 +00:00
Johnny Chen
adc7733a64
Added the follwoing 32-bit Thumb instructions for disassembly only:
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o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
Johnny Chen
6341c5a4c4
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
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and SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 20:25:24 +00:00
Johnny Chen
ce6275fd2c
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 19:05:29 +00:00
Johnny Chen
2333655ed0
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 18:46:43 +00:00
Jim Grosbach
80dc116ce3
80 column cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 21:23:02 +00:00
Jim Grosbach
6417171026
Remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 21:07:46 +00:00
Jim Grosbach
39be8fcfdc
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
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to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 20:42:29 +00:00
Jim Grosbach
a87ded2695
tighten up eh.setjmp sequence a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-08 23:22:00 +00:00
Johnny Chen
9474d550ff
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 19:31:58 +00:00
Jim Grosbach
d5d2baec26
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
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cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 00:08:13 +00:00
Evan Cheng
f609bb8466
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19 00:44:15 +00:00
Jim Grosbach
3482c8003a
Patch by David Conrad:
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"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-18 19:58:49 +00:00
Johnny Chen
d248ffb7d5
Minor change, change the order of two "let Inst{...}" stmts within multiclass
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T2I_bin_ii12rs definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93006 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08 17:41:33 +00:00
Johnny Chen
8314299161
Undo r92785, it caused test failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 22:37:28 +00:00
Johnny Chen
83f1136cfd
Add Rt2 to the asm format string for 32-bit Thumb load/store register dual
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instructions. Thumb does not have the restriction that t2 = t+1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 21:51:46 +00:00
Jim Grosbach
587b072f23
Mark STREX* as earlyclobber for the success result register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 19:44:06 +00:00
Johnny Chen
bbc71b2904
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 02:32:54 +00:00
Johnny Chen
d68e119c0f
Added encoding bits for the Thumb ISA. Initial checkin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 17:24:14 +00:00
Jim Grosbach
7c03dbd8ed
Add ARMv6 memory and sync barrier instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14 21:24:16 +00:00
Jim Grosbach
a623f5a58d
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14 19:24:11 +00:00
Jim Grosbach
c219e4dd59
add Thumb2 atomic and memory barrier instruction definitions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91310 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14 18:56:47 +00:00
Anton Korobeynikov
5cdc3a949a
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24 00:44:37 +00:00
Jim Grosbach
6935efcb66
80 column violations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89718 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24 00:20:27 +00:00
Jim Grosbach
15e6ef886d
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89694 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 20:35:53 +00:00
Evan Cheng
4aedb61d03
Remat VLDRD from constpool. Clean up some instruction property specifications.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 19:57:15 +00:00
Evan Cheng
b9803a8fa6
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:52:48 +00:00
Evan Cheng
5a1cd36019
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 23:13:34 +00:00
Bob Wilson
907eebd5a6
Put BlockAddresses into ARM constant pools.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 20:59:23 +00:00
David Goodwin
2f54a2fd85
Fix schedule model for BFC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 17:28:36 +00:00
Evan Cheng
9eda68988e
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 03:39:36 +00:00
Bob Wilson
ddb16df912
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 05:45:42 +00:00
Dan Gohman
533297b58d
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
Evan Cheng
699bebac4f
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 00:08:59 +00:00
Jim Grosbach
65b7f3af76
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
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immediate operands when they will fit into the using instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 20:44:34 +00:00
Evan Cheng
2095659a85
Match more patterns to movt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 08:15:52 +00:00
Sandeep Patel
47eedaa8fa
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 18:59:48 +00:00
Evan Cheng
0d92f5f768
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 08:22:27 +00:00
Evan Cheng
d20d658675
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 01:33:39 +00:00
Jim Grosbach
c732adf3a1
Add "isBarrier = 1" to return instructions.
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Patch by Sylvere Teissier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 01:35:11 +00:00
Evan Cheng
5adb66a646
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
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instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 09:14:39 +00:00
Anton Korobeynikov
6a2fa325c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
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This should be better than single load from constpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 23:52:58 +00:00
Evan Cheng
e298ab26b1
Enable pre-regalloc load / store multiple pass for Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 09:46:04 +00:00
David Goodwin
ca01a8d4ab
RRX reads CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80699 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 18:32:09 +00:00
Evan Cheng
d17479e845
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 06:59:37 +00:00
Bob Wilson
4f38b383d5
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
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several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21 21:58:55 +00:00
David Goodwin
5d598aaf3d
Update Cortex-A8 instruction itineraries for integer instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 18:00:44 +00:00
Evan Cheng
51f39961c3
Fix revsh pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 05:43:23 +00:00
Evan Cheng
a1efbbdbf3
Shrink ADR and LDR from constantpool late during constantpool island pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 00:32:16 +00:00
Jim Grosbach
f35d21617e
Add missing defs of R2 and D1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 16:59:44 +00:00
David Goodwin
6d3d9c3fc3
Finalize itineraries for cortex-a8 integer multiply
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 15:51:13 +00:00
Jim Grosbach
8db5cce021
Remove unnecessary newline
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 15:12:16 +00:00
Jim Grosbach
1add659b0a
Correct comment wording
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 15:11:43 +00:00
David Goodwin
1a8f36e3ce
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 18:31:53 +00:00
Jim Grosbach
378756c0f2
register naming cleanup (s/ip/r12/)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 15:21:13 +00:00
Evan Cheng
ea253b99e9
Remove an Darwin assembler workaround.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 01:56:42 +00:00
Evan Cheng
4b322e58b7
Shrinkify Thumb2 load / store multiple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 21:11:32 +00:00
Owen Anderson
825b72b057
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Jim Grosbach
5aa1684e5d
Add Thumb2 eh_sjlj_setjmp implementation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78701 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 19:42:21 +00:00
Evan Cheng
1cf5783dd7
80 column violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 08:47:46 +00:00
Owen Anderson
e50ed30282
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Evan Cheng
e8af1f9afe
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 02:37:24 +00:00
Anton Korobeynikov
8e9ece75db
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 23:10:41 +00:00
Evan Cheng
d77c7aba83
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 21:19:10 +00:00
Evan Cheng
861986401e
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 00:34:42 +00:00
David Goodwin
8b7d7ade85
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 16:52:47 +00:00
Evan Cheng
35d6c41fde
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 23:47:55 +00:00
Evan Cheng
fa2ea1a8cf
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 01:41:15 +00:00
Evan Cheng
25f7cfc3cc
Workaround a couple of Darwin assembler bugs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 06:13:52 +00:00
Evan Cheng
13f8b36205
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 01:43:45 +00:00
Evan Cheng
b620724e61
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 00:16:10 +00:00
Evan Cheng
1119776b19
Thumb2 movcc need .w suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 22:21:55 +00:00
David Goodwin
8f65253236
Darwin assembler now recognizes "orn", so remove workaround.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 21:51:41 +00:00
David Goodwin
7c92f3ac99
Darwin assembler now supports "rrx", so remove workaround.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 21:38:40 +00:00
David Goodwin
3e4b22d983
Add missing D* register clobbers for Thumb-2 call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77611 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 18:01:09 +00:00
Evan Cheng
20a2a0aff3
Make sure Thumb2 uses the right call instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 21:26:42 +00:00
Evan Cheng
0531d04d00
- Fix an obvious copy and paste error.
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- Darwin Thumb2 call clobbers r9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 20:10:36 +00:00
Evan Cheng
5657c01949
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 02:18:14 +00:00
Evan Cheng
e7c329bf4b
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 20:53:24 +00:00
David Goodwin
6340632d3b
Remove support for ORN to workaround <rdar://problem/7096522>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 20:51:25 +00:00
David Goodwin
5743854f47
Add workaround for <rdar://problem/7098328>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 18:15:38 +00:00
David Goodwin
3583df7676
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 17:06:49 +00:00
Evan Cheng
6495f63945
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 05:48:47 +00:00
David Goodwin
1f0962756d
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27 23:34:12 +00:00
David Goodwin
752aa7d2fe
Thumb-2 does not have RSC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27 16:39:05 +00:00
David Goodwin
af0d08d55c
Add ".w" suffix for wide thumb-2 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27 16:31:55 +00:00
Evan Cheng
66ac53165e
Change Thumb2 jumptable codegen to one that uses two level jumps:
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Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
Evan Cheng
0b6afa8c71
Uh. It would be useful to actually print the operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77004 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 20:47:38 +00:00
Evan Cheng
789476240d
Make sure thumb2 jumptable entries are aligned.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 18:20:44 +00:00
David Goodwin
5ff58b5c3a
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 00:16:18 +00:00
Evan Cheng
eee839dd3c
Thumb2 does not allow the use of "pc" register as part of the load / store address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-23 23:09:51 +00:00
Evan Cheng
81c102ba66
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
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Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-23 18:26:03 +00:00
David Goodwin
b53cc014d0
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-23 17:06:46 +00:00
Evan Cheng
eadf04992a
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 22:03:29 +00:00
Evan Cheng
756da12ae4
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 06:46:53 +00:00
David Goodwin
c27a4547a3
CMP and TST define CPSR, not use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76489 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 22:13:31 +00:00
Evan Cheng
446c428bf3
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 06:43:01 +00:00
Evan Cheng
06e16587eb
Add a thumb2 pass to insert IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 01:54:42 +00:00
Evan Cheng
c50a1cbf5f
Fix ldm / stm unified syntax; add t2LDM_RET.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75188 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 22:58:39 +00:00
Evan Cheng
5c874172ac
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
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Note, we are not yet generating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75181 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 22:21:59 +00:00
Evan Cheng
cba962dd6b
Correct comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75172 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 20:40:44 +00:00
David Goodwin
f1daf7d8ab
Use common code for both ARM and Thumb-2 instruction and register info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 23:10:31 +00:00
Evan Cheng
e7cbe4118b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 21:03:57 +00:00
David Goodwin
77521f5232
Generalize opcode selection in ARMBaseRegisterInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 20:28:28 +00:00
David Goodwin
334c26473b
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 16:09:28 +00:00
Evan Cheng
e253c951b3
Add Thumb2 movcc instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-07 20:39:03 +00:00
Evan Cheng
40289b041a
Add Thumb2 pkhbt / pkhtb.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74895 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-07 05:35:52 +00:00
Evan Cheng
5b9fcd1c8e
Add some more Thumb2 multiplication instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-07 01:17:28 +00:00
Evan Cheng
36a0aebac2
Add bfc to armv6t2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-06 22:23:46 +00:00
Evan Cheng
d27c9fc403
Add thumb2 sign / zero extend with rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 01:43:10 +00:00
Evan Cheng
2889ccea62
Add Thumb2 load / store multiple instructions. Not used yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74749 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:18:36 +00:00
Evan Cheng
78236f8c8a
t2LDR_PRE etc are loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74741 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:08:19 +00:00
Evan Cheng
6d94f11196
Added indexed stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:06:39 +00:00
Evan Cheng
4fbb9960ad
Sign extending pre/post indexed loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 23:16:11 +00:00
Evan Cheng
e88d5cee9d
Thumb2 pre/post indexed loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 07:28:31 +00:00
Evan Cheng
d770d9e7d1
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 06:38:40 +00:00
David Goodwin
d1fa120aee
Add PIC load and store patterns for Thumb-2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 00:01:13 +00:00
David Goodwin
6647cea111
Thumb-2 load and store double description. But nothing yet creates them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74566 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 22:50:01 +00:00
David Goodwin
73b8f16b36
Add thumb-2 store word, halfword, and byte.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 22:11:34 +00:00
David Goodwin
c9a59b5960
Improve Thumb-2 jump table support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 19:50:22 +00:00
David Goodwin
5e47a9a6e4
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 18:04:13 +00:00
Evan Cheng
f3c21b857b
A few more load instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 02:15:48 +00:00
David Goodwin
baeb911d60
Add Thumb-2 support for TEQ amd TST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 22:49:42 +00:00
David Goodwin
c0309b48b5
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 15:33:01 +00:00
Evan Cheng
055b0310f8
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 07:51:04 +00:00
Evan Cheng
9cb9e6778c
Renaming for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 02:26:13 +00:00
David Goodwin
8eba8e0ca3
Remove outdated comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74357 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 23:39:02 +00:00
David Goodwin
dcdaebc592
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 23:13:13 +00:00
David Goodwin
7ce720b448
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 20:45:56 +00:00
David Goodwin
93d95bd2c3
ADC used to implement adde should use "adcs" opcode instead of "adc".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 18:07:25 +00:00
David Goodwin
83b3593478
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
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Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74288 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 16:10:07 +00:00
Evan Cheng
8de898abc8
Mark a bunch of instructions commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74237 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 00:19:44 +00:00
Evan Cheng
6267422318
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 23:34:10 +00:00
David Goodwin
0919a916bf
Use MVN for ~t2_so_imm immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 23:11:21 +00:00
Evan Cheng
1e249e3705
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 20:59:23 +00:00
Evan Cheng
0aa1d8c52d
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 02:08:06 +00:00
Evan Cheng
b6c29d5512
Add thumb2 add sp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74156 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 01:21:30 +00:00
Evan Cheng
a09b9ca10f
Add Thumb2 pc relative add.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 23:47:58 +00:00
Evan Cheng
b8f7706911
Test instructions operands were printed in the wrong order.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73990 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 19:56:37 +00:00
Evan Cheng
a67efd1226
Proper patterns for thumb2 shift and rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 19:39:13 +00:00
Evan Cheng
e499f97058
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 18:14:38 +00:00
Evan Cheng
83a2129332
Obvious typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 17:54:26 +00:00
Evan Cheng
f49810c7e6
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
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also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 17:48:47 +00:00
Evan Cheng
3850a6ae9d
Replace isTwoAddress with operand constraint.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73947 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 05:23:49 +00:00
Anton Korobeynikov
7c4f7dd43a
Fix asm string from MOVi16
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 23:43:36 +00:00
Anton Korobeynikov
52237119a9
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 18:13:58 +00:00
Anton Korobeynikov
d4022c3fbb
Add placeholder for thumb2 stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 23:41:08 +00:00