Andrew Trick
6e8f4c4048
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 04:28:06 +00:00
Jim Grosbach
f12eee75d1
Use a StringSwitch<> instead of a manually constructed string matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122530 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 00:03:39 +00:00
Jim Grosbach
b0ad9cf935
Remove dead patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 23:20:13 +00:00
Jim Grosbach
940c8e5494
Recognize a few more documented register name aliases for ARM in the asm lexer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 23:19:54 +00:00
Bob Wilson
3c904694fc
Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
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If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 22:45:49 +00:00
Chris Lattner
036609bd7d
Flag -> Glue, the ongoing saga
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 18:28:41 +00:00
Jim Grosbach
9584bd83e6
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 23:26:02 +00:00
Bob Wilson
316009054e
Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.
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Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register. Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up. Radar 8755338.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 06:43:19 +00:00
Eric Christopher
c19aadb8b0
Arm and thumb call instructions are also in different orders.
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Fixes rdar://8782223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 03:50:43 +00:00
Chris Lattner
f1b4eafbfe
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
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something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 02:38:05 +00:00
Eric Christopher
6e90ce21cc
If we're not using reg+reg offset we're using reg+imm, set the opcode
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to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.
Fixes part of rdar://8782207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 02:12:07 +00:00
Bill Wendling
a519d57725
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
...
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 01:57:15 +00:00
Bill Wendling
9a4d2e40a0
Comment cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 01:54:40 +00:00
Rafael Espindola
1ec5bd31fe
Remove the MCObjectFormat class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 05:37:28 +00:00
Rafael Espindola
bff66a86e6
Move some data to the TargetWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 03:27:34 +00:00
Bill Wendling
a68a4fdf37
r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
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ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 02:13:59 +00:00
Bill Wendling
cd080249fc
RemoveUnusedCPEntries can change things. Track it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 01:53:06 +00:00
Bob Wilson
094dd80ecc
Rearrange some Neon multiclasses. No functional changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:42:58 +00:00
Bob Wilson
3deb45149a
Fix result type of Neon floating-point comparisons against zero.
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The result vector elements are always integers. Radar 8782191.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:04:33 +00:00
Bob Wilson
3a75b9bc8f
Add some missing entries in ARMTargetLowering::getTargetNodeName.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:04:26 +00:00
Bill Wendling
976ef86689
During local stack slot allocation, the materializeFrameBaseRegister function
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may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:09:14 +00:00
Bob Wilson
9bb43e1675
Avoid report_fatal_error in ARM's PrintAsmOperand method.
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The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:06:42 +00:00
Jim Grosbach
a3dbd3a244
If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with
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a partial value. rdar://8782954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 19:03:02 +00:00
Jim Grosbach
f0db261e97
Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 18:42:56 +00:00
Jim Grosbach
6ec6eeb692
Handle 2 and 4 byte data blob fixup values for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 18:39:10 +00:00
Rafael Espindola
6024c97ffa
Stub out explicit MCELFObjectTargetWriter interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 17:45:22 +00:00
Rafael Espindola
285b3e5b61
Move createELFObjectWriter to its own header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 16:59:53 +00:00
Daniel Dunbar
1139d5090a
MC/ARM: Use aggressive symbol folding (important for jump tables, for example).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 06:00:24 +00:00
Daniel Dunbar
7b62afac0a
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
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superceded and was effectively dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 02:06:08 +00:00
Bob Wilson
a1f544b62e
Use PairDRegs to implement ConcatVectors. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 01:21:08 +00:00
Jim Grosbach
3efad8fad4
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 19:11:16 +00:00
Daniel Dunbar
5d05d9769e
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
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interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 17:21:02 +00:00
Daniel Dunbar
ae5abd595f
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 16:09:19 +00:00
Daniel Dunbar
aa4b7dd13b
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 16:08:33 +00:00
Daniel Dunbar
2761fc4270
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
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the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay
656b3d22f7
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
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(see PR4579).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 01:34:26 +00:00
Bill Wendling
6baf46dbea
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
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it. I.e., it was always an immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:50:33 +00:00
Bill Wendling
5a54516adf
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
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respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:49:54 +00:00
Bill Wendling
dedec2b89d
Add encodings for Thumb1 Spill and Restore pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:38:41 +00:00
Jim Grosbach
3e333637f1
Thumb1 had two patterns for the same load-from-constant-pool instruction.
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Canonicalize on tLDRpci and remove tLDRcp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:52:36 +00:00
Eric Christopher
836c6245ad
Don't handle -arm-long-calls in fast isel for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:47:29 +00:00
Bill Wendling
7a905a82f7
If we're changing the frame register to a physical register other than SP, we
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need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:32:27 +00:00
Bill Wendling
dc3813750e
Whitespace cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:31:24 +00:00
Bob Wilson
0406356cd4
Add Neon VCVT instructions for f32 <-> f16 conversions.
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Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 22:14:12 +00:00
Jim Grosbach
d481110ef7
Tweak a few pseudo-inst pattern base classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 19:03:16 +00:00
Jim Grosbach
41b1d4e472
The new t2LEApcrel* pseudo instructions need the size specified.
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rdar://8768390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 18:48:45 +00:00
Owen Anderson
47dbd429da
Implement cleanups suggested by Daniel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 18:48:27 +00:00
Bill Wendling
22447ae54b
Add fixups for Thumb LDR/STR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 08:51:02 +00:00
Bill Wendling
bc4224bc6b
Reapply r121808 now that the missing patterns have been supplied.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 01:03:19 +00:00
Bill Wendling
415af3452e
Add some missing patterns now that tLDRB and tLDRH are split into reg and
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immediate versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:58:57 +00:00
Bill Wendling
7d1d8db54a
Revert r121808 until I can fix the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:04:00 +00:00
Jim Grosbach
9d04dc52a5
thumb adr fixup needs alignment just like the t2 version.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:47:35 +00:00
Bill Wendling
345cdb6475
Comments and cleaning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:42:48 +00:00
Bill Wendling
2af0fd3fee
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
...
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:40:49 +00:00
Jim Grosbach
d40963c406
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:28:03 +00:00
Bill Wendling
ee2b350d83
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:26:49 +00:00
Bill Wendling
b6faf65215
Multiclassify the LDR/STR encoding patterns. The only functionality difference
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is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:10:49 +00:00
Jim Grosbach
8d6d7d6e30
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:28:29 +00:00
Jim Grosbach
40edf73a62
Refactor a bit for legibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:10:47 +00:00
Jim Grosbach
00f25fa43e
trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:46:39 +00:00
Jim Grosbach
eb61272150
Make sure to propagate the predicate operands for LEApcrel to ADR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:45:47 +00:00
Owen Anderson
86abd48fd0
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 19:42:53 +00:00
Daniel Dunbar
abfbac52df
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 17:37:16 +00:00
Jim Grosbach
e8eb1ea6ac
Trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 16:25:15 +00:00
Bill Wendling
971321bb70
Use the integer scheduling intrinsic for integer loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 12:33:05 +00:00
Bill Wendling
f4caf69720
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:36:38 +00:00
Evan Cheng
0c1aec1891
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:22:07 +00:00
Owen Anderson
a838a25d59
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
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process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:36:49 +00:00
Bob Wilson
4711d5cda3
Remove the rest of the *_sfp Neon instruction patterns.
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Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:37 +00:00
Bob Wilson
0e6d540d17
Simplify N2VSPat, removing some unnecessary type arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:31 +00:00
Owen Anderson
6b8719fd7d
Revert r121721, which broke buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:51:08 +00:00
Owen Anderson
e8d02539d7
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
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which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:29:52 +00:00
Bob Wilson
4dedddce93
Delete a line that I forgot to revert previously.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:05:55 +00:00
Bob Wilson
1e6f59608b
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
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Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:58:05 +00:00
Bob Wilson
3a6756cb1c
Use pseudo instructions for 2-register Neon instructions for scalar FP.
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Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:05:52 +00:00
Bob Wilson
6dbcea1f8e
Remove unused instruction class arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:05:44 +00:00
Evan Cheng
30fb13f97a
Generalize BFI isel lowering a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 20:32:54 +00:00
Owen Anderson
c266600bec
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
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as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:31:11 +00:00
Jim Grosbach
56a2535474
Use 32-bit types for 32-bit values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:25:46 +00:00
Jim Grosbach
7e294cfcf9
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121708 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:18:13 +00:00
Evan Cheng
a9688c4b57
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-11 04:11:38 +00:00
Jim Grosbach
092e2cd569
Add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 23:41:10 +00:00
Owen Anderson
63ee22065d
Attempt to get Thumb2 branch fixups working properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 23:02:28 +00:00
Owen Anderson
5fd873d8e8
Fix merge error in my last fix to Thumb2 vldr fixups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:53:48 +00:00
Owen Anderson
e2e0f58809
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:46:47 +00:00
Bill Wendling
1591b293d6
The MCFixupKindInfo table needs to be in the order that the enums were
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declared. Add a note specifying this and spruce up the list a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:37:19 +00:00
Owen Anderson
ac00e96273
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:32:08 +00:00
Bob Wilson
746fa17d59
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:13:32 +00:00
Bob Wilson
20d5515aa5
Remove unused arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:13:24 +00:00
Owen Anderson
0f4b60d43a
Fix encoding of Thumb1 LDRB and STRB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 22:11:13 +00:00
Jim Grosbach
7bf4c02789
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:57:34 +00:00
Owen Anderson
808c7d1482
Fix Thumb2 encodings of STREX and LDREX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121579 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:52:38 +00:00
Jim Grosbach
0be099da79
Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:24:18 +00:00
Jim Grosbach
90cc533fda
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 21:05:07 +00:00
Jim Grosbach
683fc3e9af
More trivial cleanup. No need to define the EncoderMethod property type. Can
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just assign to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 20:53:44 +00:00
Jim Grosbach
04da9bf9f1
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 20:51:35 +00:00
Jim Grosbach
a79bd0e1e0
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 20:47:29 +00:00
Bob Wilson
a92bac64cb
Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
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Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed. Add tests for this, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 19:37:42 +00:00
Jim Grosbach
568f528c99
Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR
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instructions to restore a single register rather than an LDM instruction.
rdar://8754999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 18:41:15 +00:00
Jim Grosbach
e246717c3a
Thumb unconditional branch binary encoding. rdar://8754994
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 18:21:33 +00:00
Jim Grosbach
0108645139
Thumb conditional branch binary encodings. rdar://8745367
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 17:13:40 +00:00
Kevin Enderby
44a9e8f869
Fix the leak from r121401 of the Operands erased in the list but not deleted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 01:41:56 +00:00
Bill Wendling
272df516d7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
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t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 21:49:07 +00:00
Owen Anderson
fe7fac74b4
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
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but it gets many more of them correct than it did previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 21:34:47 +00:00
Owen Anderson
05018c2f28
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
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the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 20:27:52 +00:00
Jim Grosbach
b492a7c213
Rename CB/CBZ specific fixup accordingly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:50:12 +00:00
Kevin Enderby
193c3acbe5
Add support for parsing ARM arithmetic instructions that update or don't update
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the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:19:43 +00:00
Jim Grosbach
027d6e8d1c
Rename the encoder method for t_cbtarget to match.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:04:53 +00:00
Jim Grosbach
cf6220a9de
Thumb needs a few different encoding schemes for branch targets. Rename
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t_brtarget to be more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:01:46 +00:00
Jim Grosbach
c6f9261711
ARM stm/ldm instructions require more than one register in the register list.
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Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 18:31:13 +00:00
Jim Grosbach
bfd0daa6a6
tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 16:15:41 +00:00
Jim Grosbach
2a4f0986ac
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 16:14:46 +00:00
Owen Anderson
6b0fa635d5
Fix encoding of the immediate operands on post-indexed LDR and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 02:56:12 +00:00
Eric Christopher
1a48c032bd
Fix up some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121351 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:57:45 +00:00
Owen Anderson
d7b3f5870d
Fix Thumb2 fixups for ldr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:51:07 +00:00
Jim Grosbach
766a63d20e
Add a textual message to the assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:23:51 +00:00
Jim Grosbach
9702e6075c
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
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referencing the stack pointer as they say they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:22:19 +00:00
Jim Grosbach
cde31293d4
When using multiple instructions to reference a frame index, make sure to
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update the opcode when necessary as well as the source register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:22:13 +00:00
Jim Grosbach
a0e23c5e95
The add/sub SP instructions are really pseudos. The assembler should ignore
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them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:21:27 +00:00
Matt Beaumont-Gay
0a29c270b5
Remove unused variables
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:04:43 +00:00
Owen Anderson
8f07943317
Fix typo in Thumb2 branch fixup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 01:02:09 +00:00
Bill Wendling
2fe813af23
Remove extraneous semicolon.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 00:51:54 +00:00
Bill Wendling
797b7aab35
Attempt to make the bit-twiddling readable resulted in the binary value being
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overwritten.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 00:44:33 +00:00
Bill Wendling
09aa3f0ef3
The BLX instruction is encoded differently than the BL, because why not? In
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particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 00:39:08 +00:00
Owen Anderson
fb20d89075
Fix Thumb2 BCC encoding and fixups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 00:27:41 +00:00
Jason W Kim
045869c12a
Style nit and whitespace cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:35:25 +00:00
Jim Grosbach
60fc2ed2bb
Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME
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for more thorough cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:30:19 +00:00
Jim Grosbach
20e0fa698d
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:24:29 +00:00
Jason W Kim
0062db8b4f
Removed dead comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:19:44 +00:00
Jason W Kim
a0871e7927
ARM/MC/ELF TPsoft is now a proper pseudo inst.
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Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:14:44 +00:00
Jim Grosbach
7685ff84ad
T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121311 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:13:01 +00:00
Jim Grosbach
37474e6d68
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:12:09 +00:00
Jim Grosbach
07e9b26371
Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:04:16 +00:00
Bill Wendling
dff2f7151f
Support the "target" encodings for the CB[N]Z instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:01:43 +00:00
Evan Cheng
5d9e016025
Fix an obvious cut-n-paste error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 23:01:18 +00:00
Jim Grosbach
b76dfe06d9
Add operand encoding for Thumb2 addw SP + imm. rdar://8745434
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121305 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 22:50:19 +00:00
Jim Grosbach
7c6d85a981
Parameterize opcode encoding bits for Thumb2 extended precision integer
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multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121301 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 22:38:41 +00:00
Jim Grosbach
5208204899
Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 22:29:28 +00:00
Jim Grosbach
8638692362
Simplify T2 operand assignment notation a bit. No need to specify a bit range
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for the source field when it's the whole thing that's being referenced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 22:10:43 +00:00
Jim Grosbach
0c2c217244
Tweak ARM fixup value adjustments for Thumb to better handle the half-word
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ordering of thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 20:32:07 +00:00
Andrew Trick
6b1207267f
Generalize PostRAHazardRecognizer so it can be used in any pass for
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both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 20:04:29 +00:00
Owen Anderson
cc78f5c09c
Improve comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 19:31:11 +00:00
Jim Grosbach
022ab3779c
Add initializer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 15:36:45 +00:00
Evan Cheng
275bf63115
Add comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 06:29:02 +00:00
Bill Wendling
b8958b031e
Add support for loading from a constant pool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 01:57:09 +00:00
Jim Grosbach
5be6d2af38
Let target asm backends see assembler flags as they go by. Use that to handle
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thumb vs. arm mode differences in WriteNopData().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 01:16:55 +00:00
Owen Anderson
255eafbd49
Simplify the byte reordering logic slightly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121216 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 00:21:33 +00:00
Owen Anderson
d8e351b96f
VLDR fixups need special handling under Thumb. While the encoding is the same,
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the order of the bytes in the data stream is flipped around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay
2bf315f087
Fix a warning about a variable which is only used in an assertion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 23:26:21 +00:00
Bill Wendling
d832fa053b
Cleanup in the Darwin end. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 23:11:00 +00:00
Evan Cheng
06d65f5156
Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal
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vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}
vpush and vpop do not allow gaps in the register list.
rdar://8728956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 23:08:38 +00:00
Bill Wendling
52e635ea35
A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No
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functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 23:05:20 +00:00
Jim Grosbach
d967cd096a
Binary encoding for ARM tLDRspi and tSTRspi.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 21:50:47 +00:00
Owen Anderson
bdf714450b
Fix Thumb2 encoding of the S bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 20:50:15 +00:00
Jim Grosbach
97a884d602
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
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possible. They were duplicates for everything exception the source pattern
before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 20:41:06 +00:00
Evan Cheng
52f21e35e8
Code clean up; no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 20:11:46 +00:00
Evan Cheng
9801b5c822
Code clean up; no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 19:59:34 +00:00
Jim Grosbach
5169220624
Encode the literal field for tCMPzi instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 17:48:24 +00:00
Benjamin Kramer
6aa4943599
Add parens to pacify gcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 15:50:35 +00:00
Jay Foad
40f8f6264d
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
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zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 08:25:19 +00:00
Owen Anderson
eb6779c5b9
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 00:45:21 +00:00
Jim Grosbach
662a816e89
Add fixup for Thumb1 BL/BLX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 23:57:07 +00:00
Rafael Espindola
179821ac1f
Remove the instruction fragment to data fragment lowering since it was causing
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freed data to be read. I will open a bug to track it being reenabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 19:08:48 +00:00
Owen Anderson
c76c59840b
Revert r121021, which broke the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:57:40 +00:00
Jim Grosbach
ba3368ceae
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:47:44 +00:00
Owen Anderson
4c386fc754
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:35:51 +00:00
Jim Grosbach
04f74942f2
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
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the instruction is predicated, reg0 otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:30:57 +00:00
Jim Grosbach
d67641b6f8
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
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not an immediate. It stores either ARM::CPSR or reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:21:12 +00:00
Evan Cheng
04e2b639c1
Eliminate unneeded #include's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
714e07f75d
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120966 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:08:57 +00:00
Evan Cheng
167be80ee7
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:03:45 +00:00
Evan Cheng
f79ed109ec
Remove an unused variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:03:35 +00:00
Evan Cheng
48575f6ea7
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
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difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 22:04:16 +00:00
Bob Wilson
c24130bade
The Thumb tADDrSPi instruction is not valid when the destination is SP.
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Check for that and try narrowing it to tADDspi instead. Radar 8724703.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-04 04:40:19 +00:00
Jim Grosbach
ceab50198e
Encode condition code for Thumb1 conditional branch instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-04 00:20:40 +00:00
Jim Grosbach
ed09087dd3
Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.
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tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 23:54:18 +00:00
Bill Wendling
fb62d550de
Use correct variable names to match the patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 23:44:24 +00:00
Jim Grosbach
1b555d9f96
Match pattern operand names to expected encoding field names. This corrects the
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operand encoding ordering of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 23:21:25 +00:00
Jim Grosbach
4fa102b84e
Remove incorrect BL target encoding (it's similar to, but not the same as the
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ARM instruction). Add encoding of bits 13 and 11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 22:33:42 +00:00
Jim Grosbach
d91f4e40e6
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
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halfword being emitted to the stream first. rdar://8728174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 22:31:40 +00:00
Jim Grosbach
41ad0c4c73
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
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32-bit wide version by adding the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 20:33:01 +00:00
Benjamin Kramer
b3a04d46e8
Remove unused variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:55:37 +00:00
Jim Grosbach
6e57298127
Reduce t2 ldr/str instructions to the correct t1 versions when there's an
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immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:47:11 +00:00
Jason W Kim
2ccf148fba
fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120832 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:40:23 +00:00
Jim Grosbach
0b951ceb02
No need to declare EncoderMethod property anymore; just assign to it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:31:00 +00:00
Jim Grosbach
d253545c17
Add FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 18:37:17 +00:00
Jim Grosbach
2c971ab9d9
Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 18:31:03 +00:00
Bill Wendling
278b6e81c8
Don't overwrite the opcode passed into the T1Special pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 02:02:58 +00:00
Bill Wendling
534a5e4305
Add Thumb encoding for some more instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 01:55:47 +00:00
Bill Wendling
0bdf0c05b9
The tLDR instruction wasn't encoded properly:
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<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>
Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 00:53:22 +00:00
Jim Grosbach
7721e7f279
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 23:05:38 +00:00
Jim Grosbach
1ab4b211ea
When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,
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not thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 16:42:25 +00:00
Jim Grosbach
ce4fadf884
Fix copy/pasto in vmin.f32 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 16:30:58 +00:00
Jim Grosbach
dff84b0325
Add support for binary encoding of ARM 'adr' instructions referencing constant
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pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 00:28:45 +00:00
Evan Cheng
1bf891ae6e
Fix and re-enable tail call optimization of expanded libcalls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 22:59:46 +00:00
Jason W Kim
0c628c2617
fixing style nit: move class static to global static
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 22:46:50 +00:00
Bill Wendling
cf590263cd
Add a post encoder method to the VFP instructions to convert them to the Thumb2
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encoding if we're in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 21:54:50 +00:00
Jim Grosbach
5177f79c37
Use the correct fixup type for ARM VLDR*
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 21:09:40 +00:00
Jim Grosbach
5d14f9be7b
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
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instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:47:31 +00:00
Owen Anderson
9d63d90de5
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:18:46 +00:00
Jason W Kim
1920d82f75
kill trailing space
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:07:22 +00:00
Jim Grosbach
3990d8f89f
10 bits, not 12.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 18:51:32 +00:00
Jim Grosbach
887c0e4cbf
Elaborate on FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 04:01:17 +00:00
Jim Grosbach
baf120fbe8
Move the ARMAsmPrinter class defintiion into a header file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 03:45:07 +00:00
Bill Wendling
ff25116a09
Remove "comparison of integers of different signs" warning by making the
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variable unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:49:04 +00:00
Bill Wendling
43f7b2d370
General cleanups of comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:42:55 +00:00
Jason W Kim
85fed5e0c5
ARM/MC/ELF relocation "hello world" for movw/movt.
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Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
refactor ELFObjectWriter::RecordRelocation more.
Possibly share more code with Darwin?
Lots more relocations...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:40:06 +00:00
Bill Wendling
0480e28fb2
Formatting. It's all the rage!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:36:55 +00:00
Bill Wendling
1d045ee884
More refactoring. This time the T1pI pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:28:08 +00:00
Eric Christopher
564857f776
Refactor load/store handling again. Simplify and make some room for
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reg+reg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:40:24 +00:00
Jan Wen Voung
a63bf704b4
Initialize an ARMConstantPoolValue field.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:38:58 +00:00
Bill Wendling
40062fb747
s/T1pIEncode/T1pILdStEncode/g
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s/T1pIEncodeImm/T1pILdStEncodeImm/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:38:08 +00:00
Bill Wendling
0b424dc6b7
Renaming variables to coincide with documentation. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:32:02 +00:00
Bill Wendling
76f4e10388
Refactor T1sI and T1sIt encodings into helper classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:20:15 +00:00
Bill Wendling
a5a42d9b3c
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
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statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 00:48:44 +00:00
Owen Anderson
ca6945e5e2
Use by-name rather than by-order matching for NEON operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 00:28:25 +00:00
Evan Cheng
3d2125c9db
Enable sibling call optimization of libcalls which are expanded during
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legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:55:39 +00:00
Bill Wendling
3f8c110dc6
Rename operands to match ARM documentation. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:54:45 +00:00
Jim Grosbach
b0708d292b
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:51:41 +00:00
Jim Grosbach
d309b413a5
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120497 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:29:24 +00:00
Jason W Kim
61db62990b
Thanks to JimG for catching this!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:27:18 +00:00
Bill Wendling
2cbc9fe837
Inline classes that were used in only one place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:16:25 +00:00
Bill Wendling
1fd374e9c1
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
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t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:57:21 +00:00
Owen Anderson
80dd3e0612
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
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Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:45:47 +00:00
Jim Grosbach
97dd28fb89
Fix handling of ARM negative pc-relative fixups for loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:40:36 +00:00
Owen Anderson
c7373f8158
Provide Thumb2 encodings for a few miscellaneous instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 20:00:01 +00:00
Jim Grosbach
c02ba66d41
Add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:25:56 +00:00
Owen Anderson
0e1bcdf4f7
Add encoding support for Thumb2 PLD and PLI instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:19:31 +00:00
Eric Christopher
06a86da323
Noticed this on inspection, fix and update some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:14:07 +00:00
Jim Grosbach
2e812e1635
Pseudo-ize ARM MOVPCRX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:56:36 +00:00
Owen Anderson
eb05a8d250
Provide encodings for a few more load/store variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:38:28 +00:00
Jim Grosbach
a0d2c8a40f
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
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rdar://8685712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:30:19 +00:00
Bill Wendling
ef4a68badb
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
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certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 07:44:32 +00:00
Bill Wendling
0e45a5a901
Minor cleanups. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:50:22 +00:00
Bill Wendling
6e46d84eea
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:48:15 +00:00
Bill Wendling
647fea57fd
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
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able to match this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:34:08 +00:00
Jim Grosbach
532c2f1d50
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction
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and which are pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:24:05 +00:00
Bill Wendling
67077419c6
Add some encoding for the adr instruction. Labels still need to be finished.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:18:30 +00:00
Owen Anderson
6af50f7dd1
Correct Thumb2 encodings for a much wider range of loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:14:31 +00:00
Jim Grosbach
5c86a0a2b5
Make a few more ARM pseudo instructions actually use the PseudoInst base class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:09:06 +00:00
Bill Wendling
8ca2fd6665
Predicate encoding should be withing {}s. And general cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:08:20 +00:00
Bill Wendling
194271a76e
Predicate encoding should be withing {}s.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:05:25 +00:00
Bob Wilson
8e0c7b5287
Fix the encoding of VLD4-dup alignment.
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The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:42 +00:00
Bob Wilson
173fb1421a
Rename VLDnDUP instructions with double-spaced registers
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in an attempt to make things a little more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:38 +00:00
Bob Wilson
6c4c982f83
Add support for NEON VLD3-dup instructions.
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The encoding for alignment in VLD4-dup instructions is still a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:35 +00:00
Jim Grosbach
e76473d9ba
Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:51:31 +00:00
Jim Grosbach
6e4221153b
Parameterize ARMPseudoInst size property.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:48:41 +00:00
Jim Grosbach
00a257af5b
Add a few missing initializers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:41:10 +00:00
Jim Grosbach
03f44a04e6
Nuke trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:18:01 +00:00
Jim Grosbach
cd3c7cb915
Nuke a FIXME. No need to be fancier here, as ARM handles constant pools
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locations and formatting specially. rdar://7353441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:09:20 +00:00