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1006 Commits

Author SHA1 Message Date
Akira Hatanaka
7784046012 Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted 
when shift amount is larger than 32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 19:01:49 +00:00
Akira Hatanaka
68698cc20d Make the type of shift amount i32 in order to reduce the number of shift 
instruction definitions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143989 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 18:59:49 +00:00
Akira Hatanaka
bce22b48fe Add 64-bit to 32-bit trunc pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 18:57:41 +00:00
Benjamin Kramer
5908536673 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 20:37:06 +00:00
Daniel Dunbar
b0d9ce567f build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just 
added a layer of indirection with no value (not even conciseness).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 19:04:23 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Akira Hatanaka
feaa4c316f Make changes necessary in LowerFormalArguments to support Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:55:48 +00:00
Akira Hatanaka
e42f33bd15 Make changes necessary in LowerCall to support Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:49:00 +00:00
Akira Hatanaka
2ec69faf26 Add variable IsO32 to MipsTargetLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:47:24 +00:00
Bruno Cardoso Lopes
02dc51806e Corrects previously incorrect $sp change in MipsCompilationCallback. 
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142930 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 17:30:47 +00:00
Bruno Cardoso Lopes
c3f16b316a Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:50:36 +00:00
Bill Wendling
40825fbb40 Coding style cleanups. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 07:40:22 +00:00
Eli Friedman
0851a29b6d Fix misc warnings. Patch by Joe Abbey. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 03:17:34 +00:00
Akira Hatanaka
8ae330ac90 Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:53:29 +00:00
Akira Hatanaka
8f3af87e99 Move class and instruction definitions for conditional moves to a seperate file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
eea367ec97 Revert change made in r142205. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:33:24 +00:00
Akira Hatanaka
bdfd98a080 Redefine count-leading 0s and 1s instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:26:37 +00:00
Akira Hatanaka
89d306669e Redefine mfhi/lo and mthi/lo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:24:15 +00:00
Akira Hatanaka
f1fddcd9e0 Redefine multiply and divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:21:24 +00:00
Akira Hatanaka
2d0a61da62 Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:17:58 +00:00
Akira Hatanaka
363934665d Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142207 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:06:56 +00:00
Akira Hatanaka
a01820a508 Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:01:00 +00:00
Akira Hatanaka
1ce2668c84 Add f128 to datalayout string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141978 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 19:14:50 +00:00
Akira Hatanaka
008b58c4ae Revert r141932, r141936 and r141937. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 17:16:39 +00:00
Akira Hatanaka
91d2cc9cdd Definition of function getMipsRegisterNumbering. 
Patch by Jack Carter and Reed Kotler at Mips. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 03:04:24 +00:00
Akira Hatanaka
2891662cc2 Add definition of class MipsELFWriterInfo. 
Patch by Jack Carter and Reed Kotler at Mips. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 02:55:47 +00:00
Akira Hatanaka
51f72c5a3f Add missing relocation types. 
Patch by Jack Carter and Reed Kotler at Mips. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 02:47:50 +00:00
Akira Hatanaka
36004b93ef Fixup enumerations. 
Patch by Jack Carter at Mips. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 02:38:56 +00:00
Akira Hatanaka
93d2a0a1fa Add more Mips relocation types. 
Patch by Jack Carter at Mips. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141932 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 02:17:30 +00:00
Akira Hatanaka
41f9a430cb Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 01:05:13 +00:00
Akira Hatanaka
6baabc1dd0 Fix encoding of 32-bit integer instructions. Change names of operands and nodes. 
Remove unused classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:56:06 +00:00
Akira Hatanaka
80eb994929 Change name of class to ArithOverflowR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:43:48 +00:00
Akira Hatanaka
2dfd3a9789 Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:38:52 +00:00
Akira Hatanaka
76d9f1c022 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:12:12 +00:00
Akira Hatanaka
c2f3ac9de2 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:05:46 +00:00
Akira Hatanaka
68ad5673e8 Fix function isUnalignedLoadStore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 22:04:01 +00:00
Akira Hatanaka
d8212b2916 Remove unused PatLeaf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141720 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:53:08 +00:00
Akira Hatanaka
7cc037a137 Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:48:01 +00:00
Akira Hatanaka
395d76c5a3 Remove redundancy in setcc patterns using multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141715 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:40:01 +00:00
Akira Hatanaka
b07a3d6897 Use sltiu instead of sltu when a register operand and immediate are compared. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 20:44:43 +00:00
Akira Hatanaka
06f8231bfb Add patterns for conditional branches with 64-bit register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 19:09:09 +00:00
Akira Hatanaka
8191f34797 Add support for 64-bit set-on-less-than instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 18:53:46 +00:00
Akira Hatanaka
3e3427a5c3 Add support for conditional branch instructions with 64-bit register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 18:49:17 +00:00
Akira Hatanaka
1acb7df498 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 01:12:52 +00:00
Akira Hatanaka
a5903acd6b Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:55:05 +00:00
Akira Hatanaka
381e97dcf6 Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141615 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:44:20 +00:00
Akira Hatanaka
43aed32e20 Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141613 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:37:28 +00:00
Akira Hatanaka
7bd19bd519 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:27:28 +00:00
Akira Hatanaka
d55bb38ddc Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141603 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:11:12 +00:00
Akira Hatanaka
4391bb75ec Simplify definition of FP move instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 03:50:18 +00:00
Akira Hatanaka
c9289f6a71 Define classes and multiclasses for FP binary instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 03:38:41 +00:00
Akira Hatanaka
bfca0798cf Define multiclasses for FP-to-FP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 03:29:22 +00:00
Akira Hatanaka
a8de1c1be0 Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 03:19:38 +00:00
Akira Hatanaka
cb518ee5dd Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 02:24:10 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 01:51:51 +00:00
Akira Hatanaka
42be280a28 Fix assertion string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:17:49 +00:00
Akira Hatanaka
41a796e9cc Make sure candidate for delay slot filler is not a return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:16:09 +00:00
Akira Hatanaka
2f52338f50 Add RA to the set of registers that are defined if instruction is a call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:11:44 +00:00
NAKAMURA Takumi
4cbc5a1118 MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 10:11:02 +00:00
Akira Hatanaka
176965f46b Insert space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:22:49 +00:00
Akira Hatanaka
6e4e64859f Do not examine variadic or implicit operands if instruction is a return (jr). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:21:58 +00:00
Akira Hatanaka
0c419a7c4b Clean up function Filler::delayHasHazard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:18:58 +00:00
Akira Hatanaka
0f0c59a0f8 Remove function Filler::insertCallUses. 
Record the registers used and defined by a call in Filler::insertDefsUses.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 02:04:17 +00:00
Akira Hatanaka
7d8e04d5f1 Clean up Filler::findDelayInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:57:46 +00:00
Akira Hatanaka
53120e0a9f Remove function Filler::isDelayFiller. Check if I is the same instruction that 
filled the last delay slot visited.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:30:09 +00:00
Akira Hatanaka
6f818abbe3 Clean up Filler::runOnMachineBasicBlock. Change interface of 
Filler::findDelayInstr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:23:39 +00:00
Akira Hatanaka
98f4d4d2db Define a statistic for the number of slots that were filled with useful 
instructions (instructions that are not NOP).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141149 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:19:13 +00:00
Akira Hatanaka
f2f70c2493 Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before 
I->getDesc().hasDelaySlot() does.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:15:31 +00:00
Akira Hatanaka
cfc3fb5737 Add comments and move assignment statement. If sawStore is true, sawLoad does 
not have to be set.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:09:37 +00:00
Akira Hatanaka
6585b51821 Correct description string of enable-mips-delay-filler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 01:06:57 +00:00
Akira Hatanaka
43e43f7d8b Add support for 64-bit logical NOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0 Add support for 64-bit count leading ones and zeros instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:16:50 +00:00
Akira Hatanaka
dda4a07cd8 Add support for 64-bit divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:06:13 +00:00
Akira Hatanaka
2ad766851d Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer 
registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:38:08 +00:00
Akira Hatanaka
04d3762ff1 Add support for 64-bit integer multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:01:11 +00:00
Akira Hatanaka
36787939b2 Add definitions of instructions which move values between 64-bit integer 
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 19:28:44 +00:00
Akira Hatanaka
09a2e0f794 Register the MC object streamer. 
Patch by Reed Kotler at Mips Technologies.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140887 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 21:29:38 +00:00
Akira Hatanaka
4b6ee7a352 Register Asm backend. Add functions to MipsAsmBackend. 
Patch by Reed Kotler at Mips Technologies.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140886 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 21:23:45 +00:00
Akira Hatanaka
82ea7314ca Add MCELFObjectTargetWriter and MCAsmBackend classes. 
Patch by Reed Kotler at Mips Technologies.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 21:04:02 +00:00
Benjamin Kramer
310c9ea874 Update CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 20:44:33 +00:00
Akira Hatanaka
4520a10fdb Initial implementation of MipsMCCodeEmitter. 
Patch by Reed Kotler at Mips Technologies.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140878 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 20:40:03 +00:00
Akira Hatanaka
c7bafe9241 Add definitions of Mips64 rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 18:51:46 +00:00
Akira Hatanaka
a64556ffda isCommutable should be 0 for DSUBu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:26:36 +00:00
Akira Hatanaka
25a7d94e81 Mips64 shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
f549ab7853 Mips64 arithmetic and logical instructions with one source register and 
immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 02:08:54 +00:00
Akira Hatanaka
a3defb07a0 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 23:52:13 +00:00
Akira Hatanaka
c0be26909f Mips64 arithmetic and logical instructions with two source registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 20:37:56 +00:00
Jakob Stoklund Olesen
5cd4ee7770 Revert r140731, "Define classes for unary and binary FP instructions and use them to define" 
It broke the unit tests.  Please reapply with tests fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 23:59:28 +00:00
Akira Hatanaka
d42ca4607b Define classes for unary and binary FP instructions and use them to define 
multiclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 21:58:01 +00:00
Akira Hatanaka
aa7579025f Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 18:11:19 +00:00
Akira Hatanaka
d9f958375f Remove definitions of branch-on-FP-likely instructions. They are deprecated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 17:56:55 +00:00
Akira Hatanaka
d2d00edc01 Mips64 predicate definitions. Patch by Liu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 17:50:27 +00:00
Akira Hatanaka
6c6db25c10 Remove MipsFPRound. Mips1 is no longer supported. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 23:55:37 +00:00
Akira Hatanaka
8eea4616bf Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside 
of the instruction definitions using Pat<>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:01:01 +00:00
Akira Hatanaka
237e7a278a Fix function MipsRegisterInfo::getRegisterNumbering. 
Return numbers of 64-bit registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140609 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 17:15:27 +00:00
Akira Hatanaka
78fec58c07 Do not add the pass that restores $gp if target is Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 16:58:43 +00:00
Akira Hatanaka
854222fa47 Mark MipsPseudo isPseudo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 04:57:54 +00:00
Akira Hatanaka
f40de9d287 Set register class of a register according to value of HasMips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:55:17 +00:00
Akira Hatanaka
8b4198da9d Define variable HasMips64 in MipsTargetLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:47:02 +00:00
Akira Hatanaka
09dd60feef In single float mode, double precision FP arguments are passed in integer 
registers, so there is no need to check here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:37:50 +00:00
Akira Hatanaka
8aa4b4cb6f Add .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-24 01:40:18 +00:00
Akira Hatanaka
95934844e3 Preparation for adding simple Mips64 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-24 01:34:44 +00:00
Akira Hatanaka
45b73e2f3f Implement N32/64 calling convention. Patch by Liu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 19:08:15 +00:00
Akira Hatanaka
792016bc22 Make FGR64RegisterClass available if target is Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 18:28:39 +00:00
Akira Hatanaka
b1dcff0fe3 Add definitions of 64-bit register files. Add code for returning Mips64's sets of 
callee-saved registers and reserved registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 18:11:56 +00:00
Akira Hatanaka
aaa9fc2e37 Add definitions of 64-bit int registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 02:33:15 +00:00
Akira Hatanaka
373e3a4091 Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 00:58:33 +00:00
Akira Hatanaka
40eda4626d Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:31:54 +00:00
Akira Hatanaka
98f49c4413 Print parentheses in next line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
ebb90dbb54 Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
95a091a0b6 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:57:32 +00:00
Akira Hatanaka
26bcc701a2 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
d27fda49c4 Add F31 to the set of callee-saved registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:35:03 +00:00
Akira Hatanaka
4e41416359 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:26:58 +00:00
Akira Hatanaka
bb7d289aeb Add definition of 64-bit floating registers used for Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:48:47 +00:00
Akira Hatanaka
e33ca9ce1f Add enums and functions for symbols Mips64 uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:09:07 +00:00
Akira Hatanaka
459cad2dfd Mips64 aligns stack on 16-byte boundary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 02:53:37 +00:00
Akira Hatanaka
c56f5ea4c3 Remove unnecessary condition check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 02:41:29 +00:00
Owen Anderson
519020adf1 These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:58:45 +00:00
Akira Hatanaka
0e64f810a5 Undo a change made in r140254. 
MipsArchVersion needs to be initialized to Mips32.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:31:45 +00:00
Akira Hatanaka
47c40a2cf9 MipsArchVersion does not need to be in the initialization list and MipsABI 
should be initialized to UnknownABI.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 16:41:43 +00:00
Akira Hatanaka
2464810ac2 Add a base class for Mips TargetMachines and add Mips64 TargetMachines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 03:00:58 +00:00
Akira Hatanaka
8c1b4bf066 Set ABI if it hasn't been set on the command line. 
Check if architecture & ABI combination is valid.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:45:29 +00:00
Akira Hatanaka
50fa74e8d2 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140229 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:24:25 +00:00
Owen Anderson
317eaf1993 In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 00:25:23 +00:00
Akira Hatanaka
5663344127 Change the names of functions isMips* to hasMips*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:53:09 +00:00
Akira Hatanaka
1daa5bea58 Initial Mips64 support. Patch by Liu with some modifications. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140178 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 20:28:08 +00:00
Akira Hatanaka
da7f5f1c1d Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't 
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:26:02 +00:00
Owen Anderson
98c5ddabca Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:38:46 +00:00
Akira Hatanaka
0b7b6a0856 Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 17:22:51 +00:00
Bruno Cardoso Lopes
c4cc40c001 One more patch towards JIT support for Mips. 
- Add TSFlags for the instruction formats. The idea here is to use
  as much encoding as possible from getBinaryCodeForInstr, and having
  TSFLags formats for that would make it easier to encode most part
  of the instructions (since Mips encodings are pretty straightforward)
- Improve the mips mechanism for compilation callback
- Add Mips specific code for invalidating the instruction cache
- Next patch will address wrong tablegen encoding

Commit msg added by my own but the patch is from Sasa Stankovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 03:00:41 +00:00
Akira Hatanaka
a4b97f327d Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:13:58 +00:00
Akira Hatanaka
48ae99fac4 Support for PSP is gone too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 18:55:33 +00:00
Akira Hatanaka
2152307933 It is not necessary to search for mipsallegrex in target triple string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:35:28 +00:00
Akira Hatanaka
46ac94ba8b O64 will not be supported. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:22:48 +00:00
Akira Hatanaka
5881586745 Make F31 and D15 non-reserved registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:11:26 +00:00
Akira Hatanaka
9a439affd7 Mips32 does not reserve even-numbered floating point registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:31:46 +00:00
Akira Hatanaka
8ddf6531b8 Drop support for Mips1 and Mips2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:45:50 +00:00
Akira Hatanaka
d199d0c59c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:00:51 +00:00
Akira Hatanaka
ad5f0c9e73 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 01:13:27 +00:00
Akira Hatanaka
404507e7d8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 00:13:35 +00:00
James Molloy
b950585cc5 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:24:38 +00:00
Duncan Sands
28b77e968d Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 19:07:46 +00:00
Akira Hatanaka
334b5305a6 Fix typo. Patch by Liu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138866 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:49:04 +00:00
James Molloy
afaf80a13b Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 07:23:29 +00:00
Eli Friedman
4db5acaf48 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 18:23:02 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:08:43 +00:00
Evan Cheng
7801136b95 Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 20:15:21 +00:00
Akira Hatanaka
854a7db117 Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138132 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:59:00 +00:00
Akira Hatanaka
5ac8547a41 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 23:39:37 +00:00
Akira Hatanaka
dbe9a31683 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 20:07:42 +00:00
Bruno Cardoso Lopes
44d12eb998 Clenup and fix encoding for Mips ins and ext instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 16:30:49 +00:00
Akira Hatanaka
667645f814 Changed definition of EXT and INS per Bruno's comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:59:46 +00:00
Akira Hatanaka
511961a44c Add support for half-word unaligned loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137848 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:49:18 +00:00
Akira Hatanaka
77b85b6474 Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:45:08 +00:00
Akira Hatanaka
bb15e117d3 Add support for ext and ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:05:42 +00:00
Akira Hatanaka
614051a1c5 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 03:51:51 +00:00
Akira Hatanaka
8957481e6a Define function MipsMCInstLower::LowerOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 02:21:03 +00:00
Akira Hatanaka
78d1b11aa5 Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 02:15:03 +00:00
Akira Hatanaka
5c21c9e78e Define unaligned load and store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 21:30:06 +00:00
Akira Hatanaka
0285e7d1c1 When constant double 0.0 is lowered, make sure 0 is copied directly from an 
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137484 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 18:09:59 +00:00
Akira Hatanaka
9029cf20e1 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:42:31 +00:00
Akira Hatanaka
1f8d822023 Add isIndirectBranch flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:05:37 +00:00
Eli Friedman
26689ac37e New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. 
I think this completes the basic CodeGen for atomicrmw and cmpxchg.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 21:06:02 +00:00
Chandler Carruth
81fd0ba8ab Actually finish switching to the new system for Target sublibrary 
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 19:55:11 +00:00
Chandler Carruth
ac03e736c7 Rewrite the CMake build to use explicit dependencies between libraries, 
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 00:14:25 +00:00
Oscar Fuentes
4ebc5916e9 Explicitly declare a library dependency of LLVM*Desc to 
LLVM*AsmPrinter.

GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:

../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 02:33:52 +00:00
Eli Friedman
1464846801 Code generation for 'fence' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:21:52 +00:00
Chandler Carruth
b35552d440 Clean up a pile of hacks in our CMake build relating to TableGen. 
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 00:09:08 +00:00
Evan Cheng
4b64e8a9e1 Separate MCInstPrinter registration from AsmPrinter registration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 21:20:24 +00:00
Evan Cheng
7f8dff6571 createXXXMCCodeGenInfo should be static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-23 00:01:04 +00:00
Evan Cheng
e78085a3c0 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo, 
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 21:58:54 +00:00
Oscar Fuentes
45e11c7cc7 Fix CMake build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:10:57 +00:00
Bruno Cardoso Lopes
dca6cdd6a1 Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir 
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135678 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 16:28:51 +00:00
Evan Cheng
34ad6db8b9 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 07:51:56 +00:00
Akira Hatanaka
de9416e261 Change name of class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 00:53:09 +00:00
Akira Hatanaka
32b7ebb163 Define classes for definitions of atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 00:23:01 +00:00
Akira Hatanaka
db54826f20 Lower memory barriers to sync instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:30:50 +00:00
Akira Hatanaka
bdd83fe382 Change variable name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:56:53 +00:00
Akira Hatanaka
cc7ecc7290 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
4061da1403 Use descriptive variable names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:11:17 +00:00
Akira Hatanaka
29af0918ce Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135496 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
70564a9c19 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
81b441151f Separate code that modifies control flow from code that adds instruction to 
basic blocks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135490 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 17:09:53 +00:00
Evan Cheng
439661395f Introduce MCCodeGenInfo, which keeps information that can affect codegen 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 06:37:02 +00:00
Akira Hatanaka
939ece1b5c Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135465 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
a308c670b4 Do not insert instructions in reverse order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 03:14:58 +00:00
Evan Cheng
2d28617de2 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 
better location welcome).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 22:29:13 +00:00
Evan Cheng
0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 20:57:22 +00:00
Akira Hatanaka
a921164f39 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135418 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
0d7d0b5cb7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 18:52:12 +00:00
Akira Hatanaka
45473c1b15 Change destination register operands of SC instructions so that unique 
virtual registers are used. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 17:44:27 +00:00
Chris Lattner
db125cfaf5 land David Blaikie's patch to de-constify Type, with a few tweaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 04:54:35 +00:00
Evan Cheng
1be0e271a0 Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest 
solution but it is a small step towards removing the horror that is
TargetAsmInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 02:09:41 +00:00
Evan Cheng
1abf2cb59b Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 23:50:31 +00:00
Evan Cheng
c60f9b7523 Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 20:59:42 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo 
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 03:57:24 +00:00
Evan Cheng
ffc0e73046 Change createAsmParser to take a MCSubtargetInfo instead of triple, 
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-09 05:47:46 +00:00
Cameron Zwarich
33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent 
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 21:39:21 +00:00
Benjamin Kramer
70629abe31 Silence compiler warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:18:13 +00:00