Commit Graph

4690 Commits

Author SHA1 Message Date
Rafael Espindola
af5f6ba32d Fix PR4485.
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74534 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 16:40:03 +00:00
Rafael Espindola
f55715c5c7 Fix PR4484.
This was caused by me confounding FP0 and ST(0).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74523 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 12:18:16 +00:00
Evan Cheng
4784f1fc73 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 08:49:04 +00:00
Chris Lattner
e3821c79bc remove a bogus note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74509 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 05:22:31 +00:00
Chris Lattner
a05ec61684 add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 04:20:46 +00:00
David Greene
d94c101abb Add a 256-bit register class and YMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74469 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 22:50:51 +00:00
Rafael Espindola
63de5c3b7e FIX PR 4459.
Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74446 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 20:29:59 +00:00
Owen Anderson
9917700af4 Add a target-specific DAG combine on X86 to fold the common pattern of
fence-atomic-fence down to just the atomic op.  This is possible thanks to
X86's relatively strong memory model, which guarantees that locked instructions
(which are used to implement atomics) are implicit fences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74435 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 18:04:45 +00:00
David Greene
3016af5a1d Add processor descriptions for Istanbul and Shanghai.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74429 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 16:54:06 +00:00
David Greene
640a0c1477 Fix a subtarget feature bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 16:51:01 +00:00
David Greene
9b9838dbd4 Add more vector ValueTypes for AVX and other extended vector instruction
sets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 16:47:10 +00:00
Chris Lattner
f7789c72bd remove a bunch of fixmes (old checking code) and commonize all the
target-specific operand printing functionality.  Yay.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 05:46:24 +00:00
Chris Lattner
b1acd68fe4 pull @GOT, @GOTOFF, @GOTPCREL handling into isel from the asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74378 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 05:39:56 +00:00
Chris Lattner
4c1b606ecd simplify some code and eliminate the symbolicAddressesAreRIPRel() predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74377 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 05:24:12 +00:00
Chris Lattner
553e571b43 fix clang/test/CodeGenObjC/try.m, a basereg doesn't mean no global anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74375 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:50:14 +00:00
Chris Lattner
380135cc3e fix a bunch of failures in the X86-64 JIT by tolerating RIP as
a base register.  We just ignore it for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74374 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:46:33 +00:00
Chris Lattner
74d3f50a80 factor some logic out into a helper function, allow remat of loads from constant
globals.  This implements remat-constant.ll even without aggressive-remat.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74373 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:38:55 +00:00
Chris Lattner
18c5987fa3 Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
Chris Lattner
89da699092 Fix PR4466 by making fastisel set operand flags correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74366 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 01:31:51 +00:00
David Greene
343dadbb36 Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 22:46:54 +00:00
Evan Cheng
2c2fb823b9 Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 22:00:19 +00:00
Chris Lattner
d8220e5794 simplify printing of MO_ExternalSymbol in a non-pcrel context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74334 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 21:47:27 +00:00
Chris Lattner
c4233af200 add %rip to the GR64 register class. Lets avoid allocating it to anything though! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 21:25:00 +00:00
Chris Lattner
b903bed0fe Move all the TLS processing logic into isel, don't do it in asmprinter at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74327 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 21:20:29 +00:00
Chris Lattner
ba8ef45d12 make sure to propagate operand flags in SelectTLSADDRAddr properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74326 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 21:18:37 +00:00
Chris Lattner
03a597f2b7 minor cleanup/framework changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74316 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 20:00:05 +00:00
Chris Lattner
41621a2700 move magic for PIC constantpool references from asmprinter to isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74313 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 19:22:52 +00:00
Chris Lattner
89ca575c31 use jump table operand flags in asm printer instead of "magic predicates"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74310 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 18:55:01 +00:00
Chris Lattner
0b0deab464 fix a pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 05:56:49 +00:00
Chris Lattner
b8afeb99e9 propagate target operand flags through addressing mode selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74272 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 05:51:45 +00:00
Devang Patel
0f05d22a31 Let's ignore MDStrings also!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 02:26:12 +00:00
Chris Lattner
55e7c82730 start adding logic in isel to determine asm printer semantics, step N of M.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74246 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 00:43:52 +00:00
Chris Lattner
2b0de6a286 simplify shouldPrintPLT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74186 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 17:58:52 +00:00
Chris Lattner
ac5e887a6c Use target-specific machine operand flags to eliminate a gross hack
from the asmprinter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74184 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 17:38:33 +00:00
Chris Lattner
b1fb84dee9 just eliminate the code entirely!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74183 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 17:28:07 +00:00
Douglas Gregor
4b73893d82 Add missing dependencies to the CMake build system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74161 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 05:03:06 +00:00
Chris Lattner
4b950ec072 fix comments to be correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74154 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 01:15:47 +00:00
Devang Patel
e4c0c0fab8 No need to code gen MDNodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74150 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 00:47:42 +00:00
Chris Lattner
ab16299346 move some functions, add a FIXME, use PrintPICBaseSymbol to print the
picbase instead of inlining it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74111 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 19:44:36 +00:00
Chris Lattner
b5299dd06a reimplement getPICLabelString as PrintPICBaseSymbol to eliminate std::string heap thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 19:19:16 +00:00
Chris Lattner
0de1fc4f41 sink management of DwarfWriter & MachineModuleInfo into the AsmPrinter base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74101 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 19:09:55 +00:00
Chris Lattner
1f522feabf sink dwarf finalization out of each target into AsmPrinter::doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74097 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:54:37 +00:00
Chris Lattner
0a7befa8bd eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:52:01 +00:00
Chris Lattner
52cff83526 only emit one .align for all the hidden gv stubs instead of one for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74094 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:24:42 +00:00
Chris Lattner
8f61f984b0 inline print*Stub and rearrange function stub printing to more closely match
gv and hiddengv stub printing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74093 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:24:09 +00:00
Chris Lattner
3a03f74349 remove dead code now that personality functions don't print stubs directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74092 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:19:01 +00:00
Chris Lattner
9dd71749bc remove now-dead argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74091 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:17:56 +00:00
Chris Lattner
381d4fef6f simplify personality function stub printing to use the mangler and
decorateName like other stuff instead of special casing _.  Also, stick
it into GVStubs and let the normal stub printer print the stub instead 
of doing it manually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74090 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:17:00 +00:00
Chris Lattner
7af485e109 remove dead argument
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74089 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 18:00:11 +00:00
Chris Lattner
974469d7aa factor some code better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 05:47:59 +00:00
Chris Lattner
40e3c7acad wire up support for MCContext/MCStreamer in -experimental-asm-printer mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74066 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 05:46:28 +00:00
Bob Wilson
a96751fc8f Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings.  Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 23:59:40 +00:00
Sean Callanan
1c97ceb5e2 Test commit: fixed spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 23:25:37 +00:00
Bill Wendling
5c324d77d9 "The MMX_MASKMOVQ and MMX_MASKMOVQ64 instructions are labeled as MRMDestMem
instructions, which implies that there is an explicit memory operand.  There is
(however) no explicit memory operand; although this is a store, the only memory
operand is implicit, indicated by DS:EDI.  This causes the table-generation code
for the disassembler to report an error."

Patch by Sean Callanan!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73989 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 19:52:59 +00:00
Douglas Gregor
7e9e36a23e Eliminate object-relinking support from CMake. Fixes PR 4429 and
cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73969 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 17:57:35 +00:00
Bruno Cardoso Lopes
0d3193ef3c Add more methods to gather target specific elf stuff
Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 19:16:16 +00:00
Rafael Espindola
1c3329f707 Fix PR4185.
Handle FpSET_ST0_80 being used when ST0 is still alive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73850 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-21 12:02:51 +00:00
Chris Lattner
e372333597 simplify closing paren and (rip) printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73841 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-21 02:22:53 +00:00
Chris Lattner
4150c086d0 indentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73840 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-21 02:22:34 +00:00
Chris Lattner
2f429e5eb6 remove #if 0 code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73837 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-21 01:48:49 +00:00
Chris Lattner
aecaa1f143 cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-21 01:27:55 +00:00
Chris Lattner
5c0b16d0c4 change TLS_ADDR lowering to lower to a real mem operand, instead of matching as
a global with that gets printed with the :mem modifier.  All operands to lea's 
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this.  There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).

This also makes the use of EBX explicit in the operand list in the 32-bit, 
instead of implicit in the instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 20:38:48 +00:00
Chris Lattner
8cb65a5092 remove dead code, the main codepath never has to deal
with MBB's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73830 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 19:34:47 +00:00
Chris Lattner
7680e73341 eliminate the "call" operand modifier from the asm descriptions, modeling
it as a pcrel immediate instead.  This gets pc-rel weirdness out of the
main printoperand codepath.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73829 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 19:34:09 +00:00
Chris Lattner
7f8217f64b fix edit-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73824 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 08:13:12 +00:00
Chris Lattner
dc479f6ebf some comments and cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73818 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 07:59:10 +00:00
Chris Lattner
c12430644a implement support for lowering subregs when preparing to print
LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.

Implement support for printing mbb labels as operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 07:03:18 +00:00
Devang Patel
66b4d3ba52 Initialize MMI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 01:00:07 +00:00
Chris Lattner
ad48be0ea3 hook up printMemReference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73811 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 00:50:32 +00:00
Chris Lattner
f38c03af2a Start implementing translation of MachineInstr to MCInst. Next
step is to make tblgen generate something more appropriate for MCInst,
and generate calls to operand translation routines where needed.
This includes a bunch of #if 0 code which will slowly be refactored into
something sensible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73810 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 00:49:26 +00:00
Chris Lattner
d5fb790613 stub out some hacky code for wiring up the new asmprinter interfaces
on X86.  Not useful yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73799 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 23:59:57 +00:00
Devang Patel
5090f19f09 DwarfWriter is used to emit EH info also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73792 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 23:21:20 +00:00
Devang Patel
14a55d952c Move up dwarf writer initialization in common AsmPrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73784 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 21:54:26 +00:00
Eli Friedman
7e2242be71 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to
handle with an SSE2 instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73760 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 07:00:55 +00:00
Eli Friedman
aace4b1a2c Misc tweaks to Intel asm printing to make it more compatible with MASM.
Patch by Benedict Gaster.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73753 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 04:48:38 +00:00
Chris Lattner
fadc83c699 add a file I missed, this goes with r73743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73744 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 00:47:59 +00:00
Chris Lattner
475370b036 Add some scaffolding for a new experimental asmprinter
implementation.  The idea is that we want asmprinting to
work by converting MachineInstrs into a new MCInst class,
then the per-instruction asmprinter works on MCInst.  MCInst
and the new asmprinters will not depend on most of the 
llvm code generators.  This allows building diassemblers
that don't link in the whole llvm code generator.  This is
step #1 of many.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 00:47:33 +00:00
Chris Lattner
4e0f25b603 merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp.  The remaining differences should
be evaluated.  It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 00:08:39 +00:00
Chris Lattner
a93ca92379 move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:41:35 +00:00
Chris Lattner
7e816dc175 minor cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73737 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:33:13 +00:00
Chris Lattner
b839c3f577 simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:31:37 +00:00
Evan Cheng
b13bafe5c1 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 20:37:15 +00:00
Devang Patel
369de261e7 Do not use first actual instruction's location for prologue. The debug wants to skip prologue while setting a breakpoint for the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73592 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 00:48:26 +00:00
Douglas Gregor
1555a23335 Introduce new headers whose inclusion forces linking and
initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 20:12:29 +00:00
Evan Cheng
876eac9da5 CALL64pcrel32 immediate field is 32-bit. Patch by Abhinav Duggal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 19:44:27 +00:00
Eli Friedman
6314ac2bca Misc accumulated tweaks to legalization logic for various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73476 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 06:40:59 +00:00
Chris Lattner
b42e20be77 another xform that is target-independent (should be done in instcombine).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73472 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 06:15:56 +00:00
Chris Lattner
d23fffeb16 I think instcombine should unconditionally do this xform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73471 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 06:11:35 +00:00
Bill Wendling
fe7f294d5c There doesn't seem to be a reason to move the save FP stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 04:12:45 +00:00
Bill Wendling
d0446b08c4 The DWARF to compact encoding converter assumes that the DW_CFA_def_cfa_offset
comes after the DW_CFA_def_cfa_register, because the CFA is really ESP from the
start of the function and only gets an offset when the "subl $xxx,%esp"
instruction happens, not the other way around.

And reapply r72898:

The DWARF unwind info was incorrect. While compiling with
`-fomit-frame-pointer', we would lack the DW_CFA_advance_loc information for a
lot of function, and then they would be `0'. The linker (at least on Darwin)
needs to encode the stack size. In some cases, the stack size is too large to
directly encode. So the linker checks to see if there is a "subl $xxx,%esp"
instruction at the point where the `DW_CFA_def_cfa_offset' says the pc was. If
so, the compact encoding records the offset in the function to where the stack
size is embedded. But because the `DW_CFA_advance_loc' instructions are missing,
it looks before the function and dies.

So, instead of emitting the EH debug label before the stack adjustment
operations, emit it afterwards, right before the frame move stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73465 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 04:06:15 +00:00
Bill Wendling
927788c500 The Ls and Qs were mixed up. Patch by Sean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 20:59:31 +00:00
Bill Wendling
453eb26106 "The Intel instruction tables should include the 64-bit and 32-bit instructions
that push immediate operands of 1, 2, and 4 bytes (extended to the native
register size in each case).  The assembly mnemonics are "pushl" and "pushq."
One such instruction appears at the beginning of the "start" function , so this
is essential for accurate disassembly when unwinding."

Patch by Sean Callanan!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 19:39:04 +00:00
Chris Lattner
3771071dd8 remove extraneous const qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73373 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 04:42:32 +00:00
Chris Lattner
2e06dd2101 I got J and K backward, many thanks to Eli for spotting this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 04:39:05 +00:00
Chris Lattner
e4935150c7 implement support for the 'K' asm constraint, PR4347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73366 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 04:01:39 +00:00
Arnold Schwaighofer
bbd8c33ee6 Fix Bug 4278: X86-64 with -tailcallopt calling convention
out of sync with regular cc.

The only difference between the tail call cc and the normal
cc was that one parameter register - R9 - was reserved for
calling functions through a function pointer. After time the
tail call cc has gotten out of sync with the regular cc. 

We can use R11 which is also caller saved but not used as
parameter register for potential function pointers and
remove the special tail call cc on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73233 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 16:26:57 +00:00
Eli Friedman
7161cb1dad Misc x86 README updates: remove a couple of already-fixed issues,
add a few suggestions from looking at some assembly code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 23:07:04 +00:00
Bruno Cardoso Lopes
d00d4159d4 Use forward declarations and move TargetELFWriterInfo impl to a new file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 22:13:00 +00:00
Bruno Cardoso Lopes
c997d45ae5 Support for ELF Visibility
Emission for globals, using the correct data sections
Function alignment can be computed for each target using TargetELFWriterInfo
Some small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 19:16:03 +00:00
Anton Korobeynikov
b51b6cf1d0 Silence a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73152 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 23:00:39 +00:00
Bill Wendling
3ae67f5910 Simplified logic of this if-then statement to reduce nesting. No functionality
change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73143 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 20:08:51 +00:00
Anton Korobeynikov
0eebf653a7 The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:53:56 +00:00
Bill Wendling
faf2671776 Revert r72898. It does not solve the problem I want it to solve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73075 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 18:18:28 +00:00
Eli Friedman
5d28eb9e97 Get rid of some unnecessary code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73017 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 07:28:45 +00:00
Eli Friedman
7a5e55509b Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 06:52:44 +00:00
Eli Friedman
30e71eb61b Avoid crashing on a variable-index insertelement with element type i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 06:32:50 +00:00
Eli Friedman
1041553424 Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 06:05:10 +00:00
Eli Friedman
9d47b8d8ea Fix an obvious typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72987 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 05:55:37 +00:00
Bruno Cardoso Lopes
cf0a577033 x86_64 now uses the correct ELF e_machine type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 04:29:16 +00:00
Eli Friedman
1762c1439e Get rid of a bogus pattern that interferes with optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72985 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 04:17:04 +00:00
Eli Friedman
23ef105580 PR2598: make sure to expand illegal forms of integer/floating-point
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72983 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 03:57:58 +00:00
Dan Gohman
2392efef1b Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 23:05:51 +00:00
Devang Patel
578efa920a Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:57:13 +00:00
Nate Begeman
abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:37:30 +00:00
Devang Patel
6a784894b1 Evan thinks NoImplicitFloat check is not required here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 18:48:29 +00:00
Bill Wendling
e075a62746 The DWARF unwind info was incorrect. While compiling with
`-fomit-frame-pointer', we would lack the DW_CFA_advance_loc information for a
lot of function, and then they would be `0'. The linker (at least on Darwin)
needs to encode the stack size. In some cases, the stack size is too large to
directly encode. So the linker checks to see if there is a "subl $xxx,%esp"
instruction at the point where the `DW_CFA_def_cfa_offset' says the pc was. If
so, the compact encoding records the offset in the function to where the stack
size is embedded. But because the `DW_CFA_advance_loc' instructions are missing,
it looks before the function and dies.

So, instead of emitting the EH debug label before the stack adjustment
operations, emit it afterwards, right before the frame move stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72898 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:52:30 +00:00
Devang Patel
d18e31ae17 Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:05:33 +00:00
Eli Friedman
bccf4b3050 PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 02:32:04 +00:00
Eli Friedman
9a41712122 PR3739, part 1: Disable the red zone on Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72830 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 02:02:01 +00:00
Stuart Hastings
d58902a19b Evan says it's wrong; back out 72808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 22:59:34 +00:00
Stuart Hastings
77648cfd75 Recognize another euphemism for MOVDQ2Q.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72808 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 21:39:14 +00:00
Evan Cheng
424f8f339a For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
I view this as a temporary workaround until the assembler / linker changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72806 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 21:13:54 +00:00
Dan Gohman
c553462c29 Remove the redundant TM member from X86DAGToDAGISel; replace it
with an accessor method which simply casts the parent class
SelectionDAGISel's TM to the target-specific type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72801 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 20:20:00 +00:00
Dan Gohman
974d90bb70 Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72782 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 16:47:12 +00:00
Duncan Sands
12513889fd Avoid a warning "'U' might be used uninitialized in
this function" when using a not-too-smart compiler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72768 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 12:05:18 +00:00
Dan Gohman
6ecc2602a6 Revert r72734. The Darwin assembler doesn't support the static
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 00:37:20 +00:00
Evan Cheng
da9863fa41 On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 20:09:31 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
ca46fdd284 Add missing file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72709 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:48:58 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Bruno Cardoso Lopes
434dd4fd94 Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 19:57:37 +00:00
Dan Gohman
2d98f0664b Fix a grammaro and clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-31 17:52:18 +00:00
Bruno Cardoso Lopes
a3f99f9033 First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 20:51:52 +00:00
Evan Cheng
cf7895ff8b (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72618 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 08:43:27 +00:00
Bill Wendling
51b16f4737 Untabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 01:09:53 +00:00
Evan Cheng
cb219f0ef6 More h-registers tricks: folding zext nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 01:44:43 +00:00
Bill Wendling
2265ba0717 The MONITOR and MWAIT instructions have insufficient information for
decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.

Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72556 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 23:40:46 +00:00
Evan Cheng
8a0b2daac2 Fix MOVMSKPDrr encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 18:55:28 +00:00
Evan Cheng
ed7f56b555 Fix PSIGND encoding bug. Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72534 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 18:48:53 +00:00
Bill Wendling
3b1259bb9f "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but
the Intel manual (screenshot) says it should be 0b11110110 (f6).  The existing
encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be
0f e0."

Patch by Sean Callanan!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 02:04:00 +00:00
Evan Cheng
8b944d39b3 Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 00:35:15 +00:00
Eli Friedman
ba2352b066 Ger rid of some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 20:39:00 +00:00
Evan Cheng
bc9be219d6 Fix sfence jit encoding. Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72488 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 18:38:01 +00:00
Eli Friedman
36df499648 Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
FP_TO_XINT.  Necessary for some cleanups I'm working on.  Updated 
from the previous version (r72431) to fix a bug and make some things a 
bit clearer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72445 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 00:47:34 +00:00
Daniel Dunbar
82205570d1 Back out r72431, it is causing a number of compilation crashes with clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 21:27:02 +00:00
Stefanus Du Toit
8cf5ab153d Update CPU capabilities for AMD machines
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 21:04:35 +00:00
Eli Friedman
ecc23a5240 Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
FP_TO_XINT.  Necessary for some cleanups I'm working on. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 19:18:56 +00:00
Chris Lattner
d9b77159d6 add some late optimizations that GCC does. It thinks these are a win
even on Core2, not just AMD processors which was a surprise to me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72396 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-25 20:28:19 +00:00
Chris Lattner
f9dc644936 we should eventually add -march=atom and the new atom movbe instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72387 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-25 16:34:44 +00:00
Eli Friedman
108b519cc1 Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the
moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 22:44:52 +00:00
Anton Korobeynikov
41a024385f Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:50:50 +00:00
Eli Friedman
948e95a381 Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit
systems instead of attempting to promote them to a 64-bit SINT_TO_FP or 
FP_TO_SINT.  This is in preparation for removing the type legalization 
code from LegalizeDAG: once type legalization is gone from LegalizeDAG, 
it won't be able to handle the i64 operand/result correctly.

This isn't quite ideal, but I don't think any other operation for any 
target ends up in this situation, so treating this case specially seems 
reasonable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72324 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 09:59:16 +00:00
Evan Cheng
d7f666a869 Try again. Allow call to immediate address for ELF or when in static relocation mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 04:53:57 +00:00
Evan Cheng
65cdee3fd4 Cannot use immediate as call absolute target in PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72154 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 01:11:00 +00:00
Dale Johannesen
94c9cd17de Add OpSize to 16-bit ADC and SBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72045 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18 21:41:59 +00:00
Dale Johannesen
ca11dae4a4 Fill in the missing patterns for ADC and SBB.
Some comment cleanup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18 17:44:15 +00:00
Mike Stump
11adeed8b3 Reflow to fit 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-14 23:23:37 +00:00
Mike Stump
6726be6a67 Reflow to fit 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-14 23:22:47 +00:00
Evan Cheng
6ebf7bc740 Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:42:09 +00:00
Bill Wendling
587daedce2 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
Bill Wendling
b877a1f545 More MSVC fixes -- class/struct conflicts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71601 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 21:55:29 +00:00
Evan Cheng
0af934eb64 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71582 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 20:17:52 +00:00
Evan Cheng
6ed34918eb Avoid unneeded SIB byte encoding. Patch by Zoltan Varga.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 00:07:35 +00:00
Dan Gohman
3cd90a18bb Convert a subtract into a negate and an add when it helps x86
address folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71446 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 18:02:53 +00:00
Duncan Sands
777d2306b3 Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-09 07:06:46 +00:00
Anton Korobeynikov
c1c6ef8f74 Factor out cycle-finder code and make it generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71241 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-08 18:51:58 +00:00
Chris Lattner
4992196322 Fix PR4152: asm constraint validation happens before dag combine, so we
need to work a bit to combine things like (x+c1+c2) into x+c3.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71232 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-08 18:23:14 +00:00
Evan Cheng
45e0010e14 Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.
///       A:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       <fallthrough to B>                                                                                                                                                 
///                                                                                                                                                                          
///       B:  --> loop header                                                                                                                                                
///       ...                                                                                                                                                                
///       jcc <cond> C, [exit]                                                                                                                                               
///                                                                                                                                                                          
///       C:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jmp B                                                                                                                                                              
///                                                                                                                                                                          
/// ==>                                                                                                                                                                      
///                                                                                                                                                                          
///       A:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jmp B                                                                                                                                                              
///                                                                                                                                                                          
///       C:  --> new loop header                                                                                                                                            
///       ...                                                                                                                                                                
///       <fallthough to B>                                                                                                                                                  
///                                                                                                                                                                          
///       B:                                                                                                                                                                 
///       ...                                                                                                                                                                
///       jcc <cond> C, [exit] 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-08 06:34:09 +00:00
Dale Johannesen
43e91b9c2f Use X86AddrNumOperands instead of magic constant one
more place.  This fixes a bunch of x86-64 JIT regressions.
(Introduced when the value of the magic constant changed
in 68645.  At the time apparently nobody noticed; failures
were hidden in 70343-70439 by an unrelated bug, so showed
up again as "new" failures in 70440.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71106 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-06 19:04:30 +00:00
Chris Lattner
1777d0c6c5 Add basic support for code generation of
addrspace(257) -> FS relative on x86.  Patch by Zoltan Varga!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 18:52:19 +00:00
Evan Cheng
ef1840173c Revert part of 70929 that has to do with determining whether a SIB byte is needed. It causes a lot of x86_64 JIT failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 18:18:57 +00:00
Evan Cheng
b0030ddca4 - Avoid the longer SIB encoding on x86_64 when it's not needed.
- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp
Patch by Zoltan Varga.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70929 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-04 22:49:16 +00:00
Dan Gohman
7d04e4a7c0 X86FastISel doesn't support the -tailcallopt ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-04 19:50:33 +00:00
Argyrios Kyrtzidis
9eddfd3687 Fix compilation for some targets other than x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70522 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 23:50:26 +00:00
Argyrios Kyrtzidis
a26eae64dd Make DebugLoc independent of DwarfWriter.
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 23:22:31 +00:00
Dan Gohman
78e04d4aa0 Set mayLoad on MOVZX32_NOREXrm8 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70466 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 03:11:48 +00:00
Evan Cheng
8c1474050d Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70461 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 00:58:57 +00:00
Bill Wendling
98a366d547 Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 23:29:43 +00:00
Nate Begeman
ec8eee2d3a Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:47:44 +00:00
Nate Begeman
5a5ca1519e Implement review feedback for vector shuffle work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 05:20:52 +00:00
Bill Wendling
be8cc2a3de Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 00:15:41 +00:00
Anton Korobeynikov
573c92d8ba Properly print 'P' modifier on inline asm memory operands.
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 21:49:33 +00:00
Bill Wendling
c69d56f115 r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 01:04:53 +00:00
Bill Wendling
2e9d5f912a Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 00:21:31 +00:00
Nate Begeman
9008ca6b6b 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 18:41:29 +00:00
Dan Gohman
4af325d1b4 Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 16:41:36 +00:00
Dan Gohman
6241762c5a Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 16:33:14 +00:00
Dan Gohman
4d47b9bcb9 Break up long multi-mnemonic strings into separate lines for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 15:13:28 +00:00
Mon P Wang
a7e01d7efd Revised 68749 to allow matching of load/stores for address spaces < 256.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70197 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 07:22:10 +00:00
Chris Lattner
bc58322d6a add support for detecting process features on win64, patch by
Nicolas Capens!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-25 18:27:23 +00:00
Rafael Espindola
15f1b66d64 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
very elegant, but neither is the tls specification :-(



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69968 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:59:40 +00:00
Rafael Espindola
15684b2955 Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:40:33 +00:00
Nate Begeman
b706d29f9c PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 03:42:54 +00:00
Dan Gohman
146a310e66 Add support for printing MO_ExternalSymbol operands in
memory operand tuples. This doesn't ever come up in normal
code however.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 00:57:37 +00:00
Duncan Sands
005e7984cc Get rid of what looks like a copy-and-pasted typo.
Spotted by gcc-4.5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 09:44:39 +00:00
Rafael Espindola
7daa13c2a4 TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.
This fixes PR4002.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 08:22:09 +00:00
Dan Gohman
70bc17dbf5 Make X86's copyRegToReg able to handle copies to and from subclasses.
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69635 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-20 22:54:34 +00:00
Bob Wilson
998e125a87 Move duplicated AddLiveIn function from X86 and ARM backends to be a method
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock.  Thanks for Anton for suggesting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-20 18:36:57 +00:00
Mon P Wang
0bd07fc5dd Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 05:16:01 +00:00
Bill Wendling
1824773689 Recommit r69335 and r69336. These were not causing problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69394 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 22:40:38 +00:00
Rafael Espindola
2ee3db3003 For general dynamic TLS access we must use
leaq	foo@TLSGD(%rip), %rdi

as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 14:35:58 +00:00
Bill Wendling
c3a76ef955 Revert r69335 and r69336. They were causing build failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69347 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 04:19:22 +00:00
Dan Gohman
d10a4ce582 MOV8rr_NOREX is a "Move" instruction. This doesn't currently
matter, because this instruction isn't generated until after
things that care.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 00:45:17 +00:00
Dan Gohman
d51def353c Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at
present, but it's inconsistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 00:43:09 +00:00
Rafael Espindola
7c36683fa3 fix PR3995. A scale must be 1, 2, 4 or 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69284 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 12:34:53 +00:00
Dan Gohman
df7dfc7715 Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69204 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 19:48:57 +00:00
Dan Gohman
25174963f6 Add a folding table entry for MOV8rr_NOREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69203 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 19:48:28 +00:00
Dan Gohman
6288b93f00 Fix X86MachineFunctionInfo's doxygen comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 01:20:18 +00:00
Dan Gohman
aaa1fdb271 Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with
the local register allocator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69115 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 00:10:16 +00:00
Dan Gohman
6d9305c7fd Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when
either the source or destination is a physical h register.

This fixes sqlite3 with the post-RA scheduler enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69111 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 00:04:23 +00:00
Dan Gohman
a2f3703efd GR8_NOREX can contain the H registers, since they don't require
REX prefixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69108 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 00:00:48 +00:00
Dan Gohman
62ad138d70 For the h-register addressing-mode trick, use the correct value for
any non-address uses of the address value. This fixes 186.crafty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69094 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:45:05 +00:00
Evan Cheng
b3f5bfe37f Some of GR8_NOREX registers are only available in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 16:57:43 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Devang Patel
0f7fef3872 Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68964 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 17:02:03 +00:00
Dan Gohman
21e3dfbc86 Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
Dan Gohman
8433df36fb Remove x86's special-case handling for ISD::TRUNCATE and
ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68959 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:29:31 +00:00
Dan Gohman
3cf9b3e455 Fix copy+pastos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68958 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:28:29 +00:00
Dan Gohman
ee30047386 List the l registers before h registers, for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:18:42 +00:00
Dan Gohman
3cd0aa3260 Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68951 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:14:03 +00:00
Dan Gohman
04d19f0241 Add a comment about MOVSX64rr8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:13:28 +00:00
Dan Gohman
8cc632f705 Fix another hard-coded constant to use X86AddrNumOperands.
This unbreaks the JIT on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:04:25 +00:00
Rafael Espindola
7ff5bff45e X86-64 TLS support for local exec and initial exec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68947 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 13:02:49 +00:00
Rafael Espindola
b215776fa1 In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
only if symbolic addresses are RIP relatives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 23:00:38 +00:00
Rafael Espindola
49a168daae refactor some code into X86DAGToDAGISel::MatchWrapper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68915 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 21:55:03 +00:00
Chris Lattner
8d57b778b5 fix a cross-block fastisel crash handling overflow intrinsics.
See comment for details.  This fixes rdar://6772169


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68890 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 07:51:14 +00:00
Chris Lattner
a9a42259ed simplify code by using IntrinsicInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68887 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 07:36:01 +00:00
Chris Lattner
0461c0a8f5 Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
hasImplicitDefOfPhysReg methods.  Use them to remove a 
look in X86 fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 07:26:51 +00:00
Dan Gohman
c6fa3ff0bd Revert r68847. It breaks the build on non-Darwin targets, with this message
from the assembler:

Error: unknown pseudo-op: `.debug_inlined'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-11 15:57:04 +00:00
Devang Patel
2057532679 Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-11 00:16:47 +00:00
Rafael Espindola
dbcfb3080a Don't fold a load if the other operand is a TLS address.
With this we generate

movl    %gs:0, %eax
leal    i@NTPOFF(%eax), %eax

instead of

movl    $i@NTPOFF, %eax
addl    %gs:0, %eax



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-10 10:09:34 +00:00
Chris Lattner
c2406f2341 a few fixes to "addrspace(256) is reference offset of GS segment register".
It turns out that there are still several problems with this, will file a bugzilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68749 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-10 00:16:23 +00:00
Dan Gohman
fc1665793e Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
code that uses it by using SelectionDAG::getVTList instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68744 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 23:54:40 +00:00
Chris Lattner
a1cd83a258 Fix code size computation on x86-64, patch by Zoltan Varga!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 06:10:51 +00:00
Dan Gohman
349ba4951f Fix grammaros in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68666 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 02:06:09 +00:00
Rafael Espindola
094fad37b9 Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 21:14:34 +00:00
Rafael Espindola
8ef2b89131 Avoid a hard coded constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68603 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 08:09:33 +00:00
Dan Gohman
97121ba2af Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
Bill Wendling
044b5344c4 Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.

--- Reverse-merging (from foreign repository) r68552 into '.':
U    test/CodeGen/X86/tls8.ll
U    test/CodeGen/X86/tls10.ll
U    test/CodeGen/X86/tls2.ll
U    test/CodeGen/X86/tls6.ll
U    lib/Target/X86/X86Instr64bit.td
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86CodeEmitter.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86InstrInfo.h
U    lib/Target/X86/X86ISelDAGToDAG.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86ISelLowering.h
U    lib/Target/X86/X86InstrInfo.cpp
U    lib/Target/X86/X86InstrBuilder.h
U    lib/Target/X86/X86RegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07 22:35:25 +00:00
Rafael Espindola
2a6411bbbd Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07 21:37:46 +00:00
Mon P Wang
1e95580925 Added a x86 dag combine to increase the chances to use a
movq for v2i64 on x86-32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03 02:43:30 +00:00
Chris Lattner
5867de1243 silence warning in release-asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68253 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-01 22:14:45 +00:00
Evan Cheng
d54f2d571d i128 shift libcalls are not available on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68133 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 19:38:51 +00:00
Dan Gohman
968dc7a207 Reapply 68073, with fixes. EH Landing-pad basic blocks are not
entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68129 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 18:39:13 +00:00
Rafael Espindola
523249f856 remove unused arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68109 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 16:16:57 +00:00
Bill Wendling
df4881c68a Really temporarily revert r68073.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68100 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 08:42:40 +00:00
Bill Wendling
e67f5e4273 Oy! When reverting r68073, I added in experimental code. Sorry...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68099 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 08:41:31 +00:00
Bill Wendling
8fe00540fc Revert r68073. It's causing a failure in the Apple-style builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68092 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 08:26:26 +00:00
Evan Cheng
4d95232469 X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead.
This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68082 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 01:13:53 +00:00
Dan Gohman
80c93e7442 Except in asm-verbose mode, avoid printing labels for blocks that are
only reachable via fall-through edges. This dramatically reduces the
number of labels printed, and thus also the number of labels the
assembler must parse and remember.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68073 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 22:55:17 +00:00
Evan Cheng
73f24c9f0d When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 21:36:47 +00:00
Anton Korobeynikov
fca82deecb Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68032 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 15:27:43 +00:00
Anton Korobeynikov
71a7c6cde0 Add data.rel stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68031 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 15:27:03 +00:00
Rafael Espindola
a0a4f07fb6 Use array_lengthof
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 19:02:18 +00:00
Rafael Espindola
da945e3bb2 Have only one definition of X86AddrNumOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 18:55:31 +00:00
Rafael Espindola
b449a68146 Make code a bit less brittle by no hardcoding the number
of operands in an address in so many places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67945 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 17:03:24 +00:00
Evan Cheng
0b0cd9113a Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 05:57:29 +00:00
Rafael Espindola
705d800879 Avoid hardcoding that X86 addresses have 4 operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27 15:57:50 +00:00
Rafael Espindola
e4d5d34cfc Use less hard coded constants to make the code less brittle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67846 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27 15:45:05 +00:00
Rafael Espindola
a82dfca8c6 I am trying to add a segment to the X86 addresses matching to
improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html), but that code is VERY brittle.

This patch just makes it a bit more resistant.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27 15:26:30 +00:00
Evan Cheng
9272253381 -no-implicit-float means explicit fp operations are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67784 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 23:06:32 +00:00
Bill Wendling
a02a3dda56 Pull transform from target-dependent code into target-independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 06:14:09 +00:00
Bill Wendling
8b4b874cc6 Match this pattern so that we can generate simpler code:
%a = ...
  %b = and i32 %a, 2
  %c = srl i32 %b, 1
  %d = br i32 %c, 

into

  %a = ...
  %b = and %a, 2
  %c = X86ISD::CMP %b, 0
  %d = X86ISD::BRCOND %c ...

This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 01:47:50 +00:00
Bill Wendling
bddc442a00 Doxygen-ify comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 01:46:56 +00:00
Evan Cheng
42bf74be14 CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 01:47:28 +00:00
Evan Cheng
7db860d4de Don't print global names twice with -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67667 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 01:08:42 +00:00
Dan Gohman
a96dc14968 I was convinced that it's ok to allow a second i8 return value
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67588 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24 01:04:34 +00:00
Evan Cheng
f1c0ae9de5 Do not emit comments unless -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24 00:17:40 +00:00
Dan Gohman
2004eb6272 Correct some comments. Operand numbers start at 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 15:40:10 +00:00
Evan Cheng
fb11288109 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 08:01:15 +00:00
Dan Gohman
3aff0a63f9 Fix a grammaro in a comment that Bill noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 05:02:44 +00:00
Dan Gohman
82f84159e0 Add comments explaining why there's only one register for
i8 return values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 04:28:24 +00:00
Nick Lewycky
9c0f146d50 Remove strange extra semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67287 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 05:51:39 +00:00
Chris Lattner
ff81ebf758 Disable the "call to immediate" optimization on x86-64. It is
not safe in general because the immediate could be an arbitrary
value that does not fit in a 32-bit pcrel displacement.  
Conservatively fall back to loading the value into a register
and calling through it.

We still do the optzn on X86-32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-18 00:43:52 +00:00
Dan Gohman
9626447e70 Recognize bswapl as bswap too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67072 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 02:45:40 +00:00
Dan Gohman
d73566609e Recognize "bswapq" as an alternate spelling for the bswap instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67071 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 02:17:27 +00:00
Dan Gohman
72bb0a64af Use %rip-relative addressing on x86-64 whenever practical, as
it has a smaller encoding than absolute addressing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-14 02:33:41 +00:00
Dan Gohman
9a49d31b6f Don't forego folding of loads into 64-bit adds when the other
operand is a signed 32-bit immediate. Unlike with the 8-bit
signed immediate case, it isn't actually smaller to fold a
32-bit signed immediate instead of a load. In fact, it's
larger in the case of 32-bit unsigned immediates, because
they can be materialized with movl instead of movq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67001 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-14 02:07:16 +00:00
Dan Gohman
474d3b3f40 Improve FastISel's handling of truncates to i1, and implement
ptrtoint and inttoptr in X86FastISel. These casts aren't always
handled in the generic FastISel code because X86 sometimes needs
custom code to do truncation and zero-extension.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 23:53:06 +00:00
Dan Gohman
14ea1ec232 Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 20:42:20 +00:00
Rafael Espindola
520ebe6c2f add 8 and 16 bit TLS moves.
add a fixme note on how to remove code duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66932 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 19:39:55 +00:00
Rafael Espindola
9b922aa3b8 Improve sext and zext of TLS variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 18:37:06 +00:00
Chris Lattner
44ceb8a341 generalize this code so that fast isel handles integer truncates to i1, which
codegen to the same thing as integer truncates to i8 (the top bits are 
just undefined).  This implements rdar://6667338


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 16:36:42 +00:00
Bill Wendling
105be5ac99 These instructions have special lowering that may lower them to SSE
instructions. Prevent that if we don't want implicit uses of SSE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66877 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 08:41:47 +00:00
Evan Cheng
1606e8e4cd Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.


Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 07:51:59 +00:00
Chris Lattner
cee56e7d33 generalize the previous code to use the full generality of LEA
for i32/i64 expressions (we could also do i16 on cpus where
i16 lea is fast, but I didn't add this).  On the example, we now
generate:

_test:
	movl	4(%esp), %eax
	cmpl	$42, (%eax)
	setl	%al
	movzbl	%al, %eax
	leal	4(%eax,%eax,8), %eax
	ret

instead of:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	movl	$4, %ecx
	movl	$13, %eax
	cmovg	%ecx, %eax
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66869 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 05:53:31 +00:00
Chris Lattner
97a29a5fee optimize the case of cond ? 42 : 41 and friends. This compiles the
example to:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	setg	%al
	movzbl	%al, %eax
	orl	$4294967294, %eax
	ret

instead of:

        movl    4(%esp), %eax
        cmpl    $41, (%eax)
	movl	$4294967294, %ecx
	movl	$4294967295, %eax
	cmova	%ecx, %eax
	ret

which is smaller in code size and faster. rdar://6668608



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 05:22:11 +00:00
Dan Gohman
77502c9344 Enhance address-mode folding of ISD::ADD to handle cases where the
operands can't both be fully folded at the same time. For example,
in the included testcase, a global variable is being added with
an add of two values. The global variable wants RIP-relative
addressing, so it can't share the address with another base
register, but it's still possible to fold the initial add.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66865 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 02:25:09 +00:00
Evan Cheng
a065200eaf Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 18:15:39 +00:00
Chris Lattner
d1980a5acd Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend.  These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).

Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0  -> (zext(cond) << 3).  This happens frequently
with the recently added cp constant select optimization, but is a
very general xform.  For example, we now compile the second example
in const-select.ll to:

_test:
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        seta    %al
        movzbl  %al, %eax
        movl    4(%esp), %ecx
        movsbl  (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl    4(%esp), %eax
        leal    4(%eax), %ecx
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        cmovbe  %eax, %ecx
        movsbl  (%ecx), %eax
        ret

This passes multisource and dejagnu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 06:52:53 +00:00
Chris Lattner
2b9f434908 improve comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 06:46:02 +00:00
Evan Cheng
536e66764b On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66776 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 05:59:15 +00:00
Dan Gohman
30143763b9 Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the
assembly text output uses an indirect call ("call *") instead of a direct call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66735 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 23:01:47 +00:00
Rafael Espindola
b316f90e57 optimize i8 and i16 tls values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66725 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 22:40:04 +00:00
Bill Wendling
f9abd7e33e Add a -no-implicit-float flag. This acts like -soft-float, but may generate
floating point instructions that are explicitly specified by the user.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 22:30:01 +00:00
Duncan Sands
4dc2b39bf8 It makes no sense to have a ODR version of common
linkage, so remove it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 20:14:15 +00:00
Mon P Wang
6b3ef693d7 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66684 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 18:47:57 +00:00
Mon P Wang
37b9a19653 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66645 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 06:35:11 +00:00
Chris Lattner
47b4ce8529 formatting change, reduce indentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 05:48:52 +00:00
Dan Gohman
3328adda6b Add more information to the EFLAGS note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66515 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-10 00:26:23 +00:00
Dan Gohman
ad93e1e5fc Add a note about EFLAGS optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-09 23:47:02 +00:00
Chris Lattner
087fcf3e89 do not export all the X86FastISel symbols, ever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66382 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 18:44:31 +00:00
Chris Lattner
ff9dcee534 add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66360 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 03:04:26 +00:00
Chris Lattner
b34487dcba add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66359 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 01:54:43 +00:00
Duncan Sands
667d4b8de6 Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr.  These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global.  In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time.   This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function.  If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body.  The
code generators on the other hand map weak and weak_odr linkage
to the same thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-07 15:45:40 +00:00
Dan Gohman
3112581441 Arithmetic instructions don't set EFLAGS bits OF and CF bits
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-07 01:58:32 +00:00
Dan Gohman
1f4af262d5 Don't use plain INC32 and DEC32 on x86-64; it needs
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 21:32:23 +00:00
Dan Gohman
51bb47480e When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66206 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 21:29:28 +00:00
Dan Gohman
4bfcf2a2a6 Fix the "test" optimization to recognize "dec" as an add of
negative one, as subtracts of immediates are canonicalized
to adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66180 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 19:32:48 +00:00
Dan Gohman
076aee32e8 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 19:44:21 +00:00
Dan Gohman
fc53fc657e Correct this comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 19:24:25 +00:00
Dan Gohman
b37a8206b6 When using MachineInstr operand indices on SDNodes, the number
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 19:23:38 +00:00
Evan Cheng
ae3f2b6c77 Fix PR3666: isel calls to constant addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 06:48:53 +00:00
Dan Gohman
29582d1223 Revert r66004 for now; it's causing a variety of test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 03:54:19 +00:00
Dan Gohman
12bbc52aa7 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
result from add, sub, inc, and dec instructions in simple cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 02:33:24 +00:00
Evan Cheng
599a6a88ce Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04 01:41:49 +00:00
Dan Gohman
09a2609e20 Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC
instructions. These aren't used yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 19:53:46 +00:00
Dan Gohman
0f8b53f19d Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 02:55:14 +00:00
Mon P Wang
9feb5dd568 Added another darwin subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65662 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-28 00:25:30 +00:00
Rafael Espindola
9a58023c6c Refactor TLS code and add some tests. The tests and expected results are:
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 13:37:18 +00:00
Evan Cheng
236aa8a503 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:12:02 +00:00
Evan Cheng
a87008d90b Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-25 22:49:59 +00:00
Bill Wendling
57f0db833d Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-24 08:30:20 +00:00
Dan Gohman
e9865945ad Fast-isel can't do TLS yet, so it should fall back to SDISel
if it sees TLS addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65341 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 22:03:08 +00:00
Evan Cheng
242b38bae5 Only v1i16 (i.e. _m64) is returned via RAX / RDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65313 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 09:03:22 +00:00
Nate Begeman
b9a47b824f Generate better code for v8i16 shuffles on SSE2
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65311 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23 08:49:38 +00:00
Scott Michel
4214a5531c Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 23:36:09 +00:00
Evan Cheng
779aee1fea Add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:13:45 +00:00
Evan Cheng
6140a8b057 Be bug compatible with gcc by returning MMX values in RAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65274 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:05:12 +00:00
Evan Cheng
c94ebef1b1 Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:04:23 +00:00
Anton Korobeynikov
b5bd026a75 Drop bunch of half-working stuff in the ext_weak linkage support.
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65230 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 11:53:32 +00:00
Bill Wendling
5a45d76c25 Make sure this doesn't access .end() too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65213 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 01:11:36 +00:00
Bill Wendling
8aa374b629 Make sure we don't dereference the .end() of the container.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65211 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 01:07:26 +00:00
Bill Wendling
3d2445f5d9 Propagate more debug loc infos. This also includes some code cleaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 00:43:56 +00:00
Bill Wendling
2625f9b2e4 We need to propagate the debug location information even when dealing with the
prologue/epilogue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65206 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-21 00:32:08 +00:00
Evan Cheng
79fb3b434f Support return of MMX values in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65152 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-20 20:43:02 +00:00
Bill Wendling
cb819f13d7 Put code that generates debug labels into TableGen so that it can be used by
everyone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64978 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 23:12:06 +00:00
Nate Begeman
d6b7a242d3 Add support to the JIT for true non-lazy operation. When a call to a function
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 08:31:02 +00:00
Dan Gohman
97357614b5 Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 05:45:50 +00:00
Evan Cheng
caa0c2cadd GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 02:19:52 +00:00
Scott Michel
fdc40a0a69 Remove trailing whitespace to reduce later commit patch noise.
(Note: Eventually, commits like this will be handled via a pre-commit hook that
 does this automagically, as well as expand tabs to spaces and look for 80-col
 violations.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 22:15:04 +00:00
Chris Lattner
a66878b881 add a horrible note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 01:16:14 +00:00
Bill Wendling
86e6cb924b --- Merging (from foreign repository) r64714 into '.':
U    include/llvm/CodeGen/DebugLoc.h
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 01:04:54 +00:00
Dan Gohman
35188eb54d MachineLICM now handles these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-15 23:24:52 +00:00
Dan Gohman
b5aa3ad1e7 The x86-64 red zone is now being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-14 03:30:05 +00:00
Evan Cheng
c7ce29b04f Teach x86 target -soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64496 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 22:36:38 +00:00
Dale Johannesen
8d13f8f104 Remove non-DebugLoc versions of BuildMI from X86.
There were some that might even matter in X86FastISel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:33:27 +00:00
Bill Wendling
92c1e12647 Revert this. It was breaking stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:16:35 +00:00
Bill Wendling
54fc7d6714 Turn off the old way of handling debug information in the code generator. Use
the new way, where all of the information is passed on SDNodes and machine
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:01:04 +00:00
Dale Johannesen
21b5541814 Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 23:08:38 +00:00