Bruno Cardoso Lopes
ce8524c016
Cleanup Mips code and rename some variables. Patch by Jack Carter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes
3aa035fa0c
Improve Mips JIT.
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Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 21:04:30 +00:00
Craig Topper
7ba2725f5d
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 07:16:00 +00:00
Craig Topper
06f554d06a
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e
Add FMA4 instructions to disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 05:20:36 +00:00
Craig Topper
5d1a38cbfa
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 04:48:54 +00:00
Craig Topper
4d5c4423b9
Combine FMA4 SS/SD patterns with the instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 03:33:59 +00:00
Craig Topper
ca28590d8b
Combine FMA4 PS/PD patterns with the instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 03:17:15 +00:00
Craig Topper
2e9ed29449
Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 02:18:36 +00:00
Craig Topper
57d4b3315f
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 01:49:53 +00:00
Hal Finkel
2e95afa04c
Cleanup stack/frame register define/kill states. This fixes two bugs:
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1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 00:34:00 +00:00
Craig Topper
1604ccfc01
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:43:40 +00:00
Craig Topper
19f18be449
Expose FMA3 instructions to the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:03:14 +00:00
Craig Topper
c38fff4277
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 19:46:19 +00:00
Craig Topper
5ebee4494b
Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 19:25:56 +00:00
Craig Topper
8493e39014
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 18:47:31 +00:00
Craig Topper
b75f5f7d5d
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 18:08:36 +00:00
Craig Topper
78be212d1b
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 18:00:08 +00:00
Craig Topper
d65c7da5b0
Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 17:41:56 +00:00
Craig Topper
d4d3513d37
Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 15:51:45 +00:00
Craig Topper
19ec2a9db1
Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 03:34:54 +00:00
Craig Topper
d62c16e535
Remove some elses after returns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 03:20:51 +00:00
Craig Topper
3224e6b60a
Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 03:09:33 +00:00
Eli Friedman
da813f4209
Fix type-checking for load transformation which is not legal on floating-point types. PR11674.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-28 21:24:44 +00:00
Elena Demikhovsky
021c0a2ee7
Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.
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Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-28 08:14:01 +00:00
Benjamin Kramer
27baab62e7
Clean up some Release build warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-27 11:41:05 +00:00
Craig Topper
3738ccd7eb
Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-27 06:27:23 +00:00
Venkatraman Govindaraju
55caf9c60a
Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-25 18:50:24 +00:00
Rafael Espindola
ce618af3e8
Section relative fixups are a coff concept, not a x86 one. Replace the
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x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 14:47:52 +00:00
Chandler Carruth
7782102c70
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the
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LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type
We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 12:12:34 +00:00
Chandler Carruth
3d636ea8ed
Add systematic testing for cttz as well, and fix the bug I spotted by
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inspection earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 11:46:10 +00:00
Benjamin Kramer
32d720bb2f
Chandler fixed this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 11:23:32 +00:00
Chandler Carruth
d873a4b89b
Expand more when we have a nice 'tzcnt' instruction, to avoid generating
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'bsf' instructions here.
This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 11:11:38 +00:00
Chandler Carruth
acc068e873
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
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X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:
(sizeof(x)*8 - 1) ^ __builtin_clz(x)
Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.
The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.
Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.
These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 10:55:54 +00:00
Jakob Stoklund Olesen
43ea32ca04
Fix Comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 04:17:01 +00:00
Akira Hatanaka
fd1d9250b2
Add MachineMemOperands to instructions generated in storeRegToStackSlot or
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loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 03:11:18 +00:00
Akira Hatanaka
9dfd4399a9
Detect unaligned loads/stores that have been added for Mips64 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 03:07:37 +00:00
Akira Hatanaka
9dbeb0284d
If target ABI is N64, LEA should be daddiu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 02:59:27 +00:00
Rafael Espindola
df09270ae8
Move x86 specific bits of the COFF writer to lib/Target/X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147231 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 02:14:02 +00:00
Jakob Stoklund Olesen
f06f6f50e9
Experimental support for aligned NEON spills.
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ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.
Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.
This feature is off by default, controlled by an -align-neon-spills
command line option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-23 00:36:18 +00:00
Bob Wilson
f4aea8f349
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
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My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 23:39:48 +00:00
Chad Rosier
30450e89d9
Fix 80-column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:35:21 +00:00
Jim Grosbach
4050bc4cab
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:19:05 +00:00
Bob Wilson
d2355e72c5
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
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Noticed by inspection; I don't have a testcase for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:12:44 +00:00
Jim Grosbach
21bcca81f4
Tidy up. Use predicate function a bit more liberally.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:02:35 +00:00
Rafael Espindola
b975c27adc
Fix incorrect relocation generation. Patch by Kristof Beyls.
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Fixes PR11214.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 21:36:43 +00:00
Jim Grosbach
c7448f8d47
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
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The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:55:21 +00:00
Jim Grosbach
8c748113eb
Remove some bogus comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:45:01 +00:00
Jim Grosbach
1aa149f5ac
ARM pre-UAL aliases. fcmp[sd].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:20:45 +00:00
Rafael Espindola
f51e95a9f2
Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
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it. It does need some some tests...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 18:38:06 +00:00
Jim Grosbach
8d9550bde9
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 18:04:04 +00:00
Jim Grosbach
de626ad872
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:37:00 +00:00
Jim Grosbach
18c8d12dea
Tidy up. Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:17:10 +00:00
Jim Grosbach
f1a88fc474
Nuke invalid comment from copy/paste.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:04:50 +00:00
Rafael Espindola
090445967f
Move the Mips only bits of the ELF writer to lib/Target/Mips.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 03:03:17 +00:00
Rafael Espindola
6db2d92603
Make the virtual methods in ARMELFObjectWriter public.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 02:58:12 +00:00
Rafael Espindola
4982159b88
Move the MBlaze ELF writer bits to lib/Target/MBlaze.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 02:28:24 +00:00
Rafael Espindola
dcc557f146
Fix cmake.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 02:06:17 +00:00
Rafael Espindola
f3a86fb03d
Move PPC bits to lib/Target/PowerPC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:57:09 +00:00
Rafael Espindola
81fafde8a6
Hopefully fix the cmake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:11:01 +00:00
Rafael Espindola
7609785d2b
Fix name in comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:06:53 +00:00
Akira Hatanaka
bc24985c5f
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
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ELF relocations.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:05:17 +00:00
Richard Smith
74cab51aa5
Unbreak cmake build after r147115.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:03:35 +00:00
Rafael Espindola
69bbda0391
Move the ARM specific parts of the ELF writer to Target/ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 00:37:50 +00:00
Jim Grosbach
f7c66fa0de
ARM NEON mnemonic aliase for vrecpeq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:52:37 +00:00
Jim Grosbach
af33a0cfe0
ARM VFP optional data type on VMOV GPR<-->SPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:24:15 +00:00
Jim Grosbach
5f669fa8ba
ARM NEON optional data type on VSWP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:09:28 +00:00
Jim Grosbach
4553fa3128
ARM NEON mnemonic aliases for vzipq and vswpq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:04:33 +00:00
Jim Grosbach
de4d83943a
ARM asm parser should be more lenient w/ .thumb_func directive.
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Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 22:30:16 +00:00
Jim Grosbach
520dc78d92
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 21:04:19 +00:00
Chad Rosier
5c0d761d63
Fix 80-column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:59:09 +00:00
Jim Grosbach
2cc5cda464
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
a2a98fd0dd
Move common code into an MRI function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:50:05 +00:00
Jim Grosbach
e6949b1399
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:40:55 +00:00
Chad Rosier
649326ab15
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
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necessary. Please chime in if I'm mistaken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:14:52 +00:00
Chad Rosier
8d0447c506
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 18:56:22 +00:00
Rafael Espindola
edae8e1e4d
Move the X86 specific bits of the ELF writer to the Target/X86 directory.
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Other targets will follow shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 17:30:17 +00:00
Rafael Espindola
dc9a8a378d
Reduce the exposure of Triple::OSType in the ELF object writer. This will
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avoid including ADT/Triple.h in many places when the target specific bits are
moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 17:00:36 +00:00
Craig Topper
224c1b275d
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 08:06:52 +00:00
Craig Topper
e1a18a66df
Fix typo in a couple comments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 06:30:53 +00:00
Evan Cheng
1e33e8b715
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 03:04:10 +00:00
Jim Grosbach
c931325d99
ARM assembly parsing allows constant expressions for lane indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Akira Hatanaka
c7541c49a9
Fix bug in zero-store peephole pattern reported in pr11615.
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The patch and test case were originally written by Mans Rullgard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
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case for DCLO and DCLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:20:27 +00:00
Akira Hatanaka
7f162743fc
Expand 64-bit CTPOP and CTTZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:14:05 +00:00
Akira Hatanaka
9aed504c82
Expand 64-bit atomic load and store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:02:58 +00:00
Akira Hatanaka
c0ea04389c
Add definition of DSBH (Double Swap Bytes within Halfwords) and
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DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:56:43 +00:00
Akira Hatanaka
4d2b0f3ce7
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
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instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:47:44 +00:00
Akira Hatanaka
e1bcd6b5c6
64-bit uint-fp conversion nodes are expanded.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:40:56 +00:00
Akira Hatanaka
9388383b34
Enable custom lowering DYNAMIC_STACKALLOC nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:35:46 +00:00
Akira Hatanaka
056a1bc40f
Set the correct stack pointer register that should be saved or restored.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:28:36 +00:00
Jim Grosbach
aee718beac
ARM .req register name aliases are case insensitive, just like regnames.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:11:00 +00:00
Akira Hatanaka
2fd0475cdb
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
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nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:10:57 +00:00
Akira Hatanaka
49d534bb3d
Fix indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:58:01 +00:00
Akira Hatanaka
8dc684d2a2
64-bit data directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:52:19 +00:00
Akira Hatanaka
ef43c2de86
32-to-64-bit sext_inreg pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:40:40 +00:00
Akira Hatanaka
acb5a06f7a
Add 64-bit extload patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:36:08 +00:00
Akira Hatanaka
ab05b6c227
Add patterns for matching extloads with 64-bit address. The patterns are enabled
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only when the target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:33:53 +00:00
Jim Grosbach
3cbe43fe69
Move comment to appropriate place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:26:38 +00:00
Akira Hatanaka
990d639f55
Add code in MipsDAGToDAGISel for selecting constant +0.0.
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MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
52346e964f
Heed spill slot alignment on ARM.
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Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:15:04 +00:00
Akira Hatanaka
05c585319b
Revert part of r146995 that was accidentally commmitted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:09:36 +00:00
Akira Hatanaka
403992dc58
32-to-64-bit sign extension pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:06:20 +00:00
Akira Hatanaka
caace8abdf
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
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only when the target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 21:50:49 +00:00
Jim Grosbach
5b484312c6
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
Jim Grosbach
95fad1c603
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 18:26:50 +00:00
Jason W Kim
d7c9e08b6b
First steps in ARM AsmParser support for .eabi_attribute and .arch
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(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 17:38:12 +00:00
Elena Demikhovsky
ba4f83b4e9
This is the second fix related to VZEXT_MOVL node.
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The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 13:34:28 +00:00
Chandler Carruth
f2d7693fbb
Begin teaching the X86 target how to efficiently codegen patterns that
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use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 11:19:37 +00:00
Chandler Carruth
cfb75fba73
Fix up the CMake build for the new files added in r146960, they're
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likely to stay either way that discussion ends up resolving itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 08:42:11 +00:00
David Blaikie
2d24e2a396
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 02:50:00 +00:00
Bob Wilson
c0b0e57a87
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
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We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:29:27 +00:00
Jim Grosbach
04b5d93250
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:59:38 +00:00
Dan Gohman
e3376ecd50
Add basic generic CodeGen support for half.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:02:33 +00:00
Jim Grosbach
9b0878512f
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
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e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117 "
rdar://10603913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:51:07 +00:00
Jim Grosbach
2f196747f1
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:06:24 +00:00
Akira Hatanaka
f06cb2b207
Add patterns for matching immediates whose lower 16-bit is cleared. These
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patterns emit a single LUi instruction instead of a pair of LUi and ORi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 20:21:18 +00:00
Akira Hatanaka
8209968306
Tidy up. Simplify logic. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:52:25 +00:00
Jim Grosbach
d22170e16a
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:51:03 +00:00
Akira Hatanaka
ee973147ac
Remove definitions of double word shift plus 32 instructions. Assembler or
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direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:44:09 +00:00
Jim Grosbach
6849019079
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:43:50 +00:00
Akira Hatanaka
ed538b5271
Remove unused predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:32:20 +00:00
Akira Hatanaka
89dc8d790d
Remove the restriction on the first operand of the add node in SelectAddr.
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This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:28:37 +00:00
Jim Grosbach
9c39789c36
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:02:41 +00:00
Jim Grosbach
61b74b4247
ARM NEON implied destination aliases for VMAX/VMIN.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:31:43 +00:00
Jim Grosbach
3346dcef02
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
9897c622e0
Remove a register class that can just as well be synthesized.
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Add the new TableGen register class synthesizer feature to the release
notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 16:53:40 +00:00
Jakob Stoklund Olesen
570f9a972e
Emit a getMatchingSuperRegClass() implementation for every target.
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Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 16:53:34 +00:00
Benjamin Kramer
0581ed792b
Another variadics tweak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-18 20:51:31 +00:00
Benjamin Kramer
2ea4cdb81f
Use the fancy new VariadicFunction template instead of a plain variadic function.
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Some compilers were complaining about passing StringRef to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-18 19:59:20 +00:00
Benjamin Kramer
4c1ea552c5
Hexagon: Remove unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-18 12:00:09 +00:00
Craig Topper
ab44d3cf49
Remove an unused X86ISD node type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 19:16:44 +00:00
Benjamin Kramer
e6cddb77dc
X86: Factor the bswap asm matching to be slightly less horrible to read.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 14:36:05 +00:00
Evan Cheng
b16db81719
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:25:34 +00:00
Rafael Espindola
8f7d12ccfd
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
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asm parsing and testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:14:52 +00:00
Lang Hames
8b99c1e42c
Make sure that the lower bits on the VSELECT condition are properly set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:08:46 +00:00
Jakob Stoklund Olesen
2027379985
Preserve more memory operands in ARMExpandPseudo.
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I don't think this affects anything but verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 00:07:02 +00:00
Jakob Stoklund Olesen
b076fb7762
Fix off-by-one error in bucket sort.
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The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 23:00:05 +00:00
Jakob Stoklund Olesen
f9aabb8f32
Don't adjust for alignment padding in OffsetIsInRange.
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This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 19:10:00 +00:00
Benjamin Kramer
903456245b
Hexagon: Fix a nasty order-of-initialization bug.
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Reenable the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 19:08:59 +00:00
Jakob Stoklund Olesen
f5bb45f895
Note ARM constant island alignment in the release notes.
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The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 16:07:41 +00:00
Craig Topper
94438ba538
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
46209476e7
Target/Hexagon: Fix CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 06:21:02 +00:00
Jim Grosbach
ddecfe54a3
ARM NEON aliases for vmovq.f*
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 00:12:22 +00:00
Jim Grosbach
b6744db06f
Thumb2 ADR assembly parsing w/o the .w suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:52:17 +00:00
Eli Friedman
7e840efc23
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:46:18 +00:00
Nick Lewycky
028700f544
Move parts of lib/Target that use CodeGen into lib/CodeGen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146702 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:58:58 +00:00
Eli Friedman
2f21e8c5ba
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:53 +00:00
Jim Grosbach
a738da7bd3
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:33 +00:00
Tony Linthicum
d239ff67f2
Add MCTargetDesc library to Hexagon target
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:29:08 +00:00
Jim Grosbach
60d99a5278
ARM NEON VTBL/VTBX assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:27:11 +00:00
Jakob Stoklund Olesen
b6ff6ec85e
Enable proper constant island alignment by default.
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The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:14:45 +00:00
Chad Rosier
c8dd20170e
Add missing zmovl AVX patterns which were causing crashes.
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Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:11:31 +00:00
Jim Grosbach
276ed0344c
Silence warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:54:55 +00:00
Jim Grosbach
0aaf4cd9b3
ARM NEON two-register double spaced register list parsing support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:44:33 +00:00
Chad Rosier
0660cfe3c8
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
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Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 21:34:44 +00:00
Lang Hames
a0a251372f
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 18:57:27 +00:00
Hal Finkel
7f370b6155
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 17:54:01 +00:00
Richard Osborne
27a7859bf7
Pass optLevel to XCoreDAGToDAGISel.
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Patch by Kyriakos Georgiou.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 15:18:35 +00:00
Chad Rosier
01d426e0e1
Use SmallVector/assign(), rather than std::vector/push_back().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 01:16:09 +00:00
Chad Rosier
a860b189e4
Add support for lowering fneg when AVX is enabled.
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rdar://10566486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 01:02:25 +00:00
Bill Wendling
10e412ec6b
The saved registers weren't being processed in the correct order. This lead to
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the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:53:24 +00:00
Jakob Stoklund Olesen
299b059cd6
Consider CPE alignment in CreateNewWater().
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An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:48:54 +00:00
Jim Grosbach
799ca9d1b7
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:35:06 +00:00
Jim Grosbach
9b1b390288
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
Jim Grosbach
ec04a3f8db
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:49:24 +00:00
Jim Grosbach
2dbab5c33d
Nuke old code. Missed in last commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:41:32 +00:00
Jim Grosbach
bb3a2e4d0d
ARM NEON refactor VST2 w/ writeback instructions.
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In addition to improving the representation, this adds support for assembly
parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:32:11 +00:00
Jim Grosbach
20accfc6c7
ARM NEON improve factoring a bit. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 20:59:15 +00:00
Evan Cheng
020f4106f8
Model ARM predicated write as read-mod-write. e.g.
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r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 20:00:08 +00:00
Jim Grosbach
e90ac9bce9
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
Jakob Stoklund Olesen
5e46dcbb4b
Fix speling and 80-col.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 18:49:13 +00:00
Akira Hatanaka
3faac0a78c
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
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emission is not supported yet, but a patch that adds the support should follow
soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 18:26:41 +00:00
Jim Grosbach
5dca1c9f63
Fix copy/pasto that skipped the 'modify' step.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146571 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 18:12:37 +00:00
Jim Grosbach
4677708d4f
ARM/Thumb2 mov vs. mvn alias goes both ways.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:56:51 +00:00
Chad Rosier
6762f8f302
VFP2 is required for FP loads. Noticed by inspection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:55:03 +00:00
Chad Rosier
64ac91b4b6
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:32:02 +00:00
Jim Grosbach
8d11c6349f
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
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When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:30:24 +00:00
Chad Rosier
404ed3c223
Fix 80-column violation and extraneous brackets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:26:05 +00:00
Jim Grosbach
a39cda7aff
ARM assembler support for the target-specific .req directive.
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rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:16:11 +00:00
Evan Cheng
ddfd1377d2
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
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to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:11:42 +00:00
Jim Grosbach
863d2af947
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1
ARM LDM/STM system instruction variants.
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rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:48:29 +00:00
Jim Grosbach
b0659873e6
Thumb2 pre/post indexed stores can be from any non-PC GPR.
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rdar://10549786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:10:25 +00:00
Jim Grosbach
d7ea73a490
Thumb2 tweak for ccout handling in RSB parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:06:41 +00:00
Jim Grosbach
55b02f28c1
ARM thumb2 parsing of "rsb rd, rn, #0 ".
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rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207
ARM NEON two-operand aliases for VQDMULH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc
ARM pre-UAL NEG mnemonic for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:23:22 +00:00
Jim Grosbach
f10154010e
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:13:48 +00:00
Jim Grosbach
485d8bf7e5
ARM add more 'gas' compatibility aliases for NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:08:32 +00:00
Chad Rosier
8a9bce978f
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
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load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 19:22:14 +00:00
Akira Hatanaka
044a784fa5
Expand .cprestore directive to multiple instructions if the offset does not fit
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in a 16-bit field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 03:09:05 +00:00
Chandler Carruth
63974b2144
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
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undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 01:56:10 +00:00
Jakob Stoklund Olesen
2e29024d2e
Account for CPE alignment when searching for new water.
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Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 00:44:30 +00:00
NAKAMURA Takumi
e97b4990e1
Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 00:36:04 +00:00
Daniel Dunbar
b0c594fd42
LLVMBuild: Introduce a common section which currently has a list of the
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subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 22:45:54 +00:00
Akira Hatanaka
6e55ff56b8
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
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-relocation-model=static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 22:39:35 +00:00
Akira Hatanaka
bfcb83fa32
Fix indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 22:38:19 +00:00
Tony Linthicum
22614a02eb
fix warning
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:52:59 +00:00
Bob Wilson
9cd2b9562d
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
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These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:45:15 +00:00
Tony Linthicum
b4b54153ad
Hexagon backend support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:14:40 +00:00
Daniel Dunbar
4ab406d7fc
LLVMBuild: Remove trailing newline, which irked me.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:48:00 +00:00
Jan Sjödin
37e7ecf52b
XOP instructions and encoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:37:49 +00:00
Jakob Stoklund Olesen
8552821e57
Add a postOffset() alignment argument.
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This computes the offset of the layout sucessor block, considering its
alignment as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146401 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:25:54 +00:00
Jakob Stoklund Olesen
bd1ec17caf
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:25:51 +00:00
Jan Sjödin
ebebe35d1c
XOP encoding bits and logic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:12:26 +00:00
Jakob Stoklund Olesen
cca33a3f24
Also set the proper alignment on inner islands and the function itself.
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Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.
This is all gated by -arm-align-constant-islands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 18:45:45 +00:00
Jakob Stoklund Olesen
dbf350a5a8
Make MF a class member instead of passing it around everywhere.
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Also add an MCP member pointing to the machine constant pool.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 18:16:53 +00:00
Jakob Stoklund Olesen
b813f924a7
Add a -arm-align-constant-islands flag, default off.
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Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment. When the command line
flag is set, also align the basic block containing the constant pool
entries.
This is only a partial implementation of constant island alignment. More
to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 16:49:37 +00:00
Craig Topper
d93e4c3496
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 19:12:35 +00:00
Stepan Dyatkovskiy
3e0dc0606a
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 14:35:48 +00:00
Benjamin Kramer
5eccf67492
Mips: Don't create a dangling IR function just to get the address of a symbol.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 12:21:34 +00:00
Nick Lewycky
ead7448a85
Also remove unnecessary includes from this file, which was supposed to be part
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of r146334!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 00:45:13 +00:00
Nick Lewycky
531bb82556
Minimize #include's and forward-declares in Target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 22:35:47 +00:00
Nick Lewycky
b3ffe102fe
Refactor the implementation of the TargetOptions out of TargetMachine, taking
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the only parts of TM that depends on CodeGen headers with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 22:34:41 +00:00
Chad Rosier
d440f678fb
Revert r146322 to appease buildbots. Original commit message:
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Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 19:55:03 +00:00
Stepan Dyatkovskiy
8c0b807e8f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 08:42:24 +00:00
Hal Finkel
fed4d19edd
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 04:50:53 +00:00
Jakob Stoklund Olesen
77caaf0fc0
Try to align the point where a large basic block is split.
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The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:55:10 +00:00
Jakob Stoklund Olesen
2d5023bbcf
More debug output formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:55:06 +00:00
Rafael Espindola
f3aefb56de
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:28:43 +00:00
Jim Grosbach
48171e7fbe
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 00:01:02 +00:00
Eli Friedman
effab8fa24
Splats can contain undef's; make sure to handle them correctly. PR11526.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 23:54:42 +00:00
Jim Grosbach
21d7fb814a
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 23:34:09 +00:00
Jim Grosbach
8a12e3b5df
ARM allows '' syntax, not just '#imm' for assembly.
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Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:25:03 +00:00
Jim Grosbach
840bf7eda7
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Jim Grosbach
4332983e77
ARM NEON data type aliases for VBIC(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:46:04 +00:00
Jim Grosbach
a4e3c7fc4b
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
Jakob Stoklund Olesen
493ad6b95d
User a helper overload for a common pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:44:39 +00:00
Jim Grosbach
2af50d981d
Tidy up. Better base class factoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:07:20 +00:00
Jim Grosbach
1f94ec7b59
Tidy up. Better base class factoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:54:11 +00:00
Jakob Stoklund Olesen
3c4615eef2
Tweak debugging output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:20:35 +00:00
Benjamin Kramer
bf67a99c35
This is now implemented.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:45:57 +00:00
Benjamin Kramer
b653397dcd
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:44:03 +00:00
Benjamin Kramer
a73fb9adbb
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:43:55 +00:00
Evan Cheng
32f9763017
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:41:08 +00:00
Evan Cheng
85abb2700d
Remove hasSSE1orAVX(). It's the same as hasXMM().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:32:46 +00:00
Akira Hatanaka
6df7e23f0c
Rename WrapperPIC. It is now used for both pic and static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:53:17 +00:00
Akira Hatanaka
0dca9456c5
jalr should use t9 ($25) for indirect calls regardless of the relocation model
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specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:45:12 +00:00
Jim Grosbach
976c0da213
ARM convenience aliases for VSQRT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:51:25 +00:00
Evan Cheng
e955726a0e
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:30:45 +00:00
Jim Grosbach
8759c3f548
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:19:04 +00:00
Owen Anderson
243eb9ecbb
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:15:21 +00:00
Jim Grosbach
6b044c2609
ARM VSHR implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:06:06 +00:00
Evan Cheng
13d2ba34f2
Add various missing AVX patterns which was causing crashes. Sadly, the generated
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code looks pretty bad compared to SSE.
rdar://10538793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:05:28 +00:00
Jim Grosbach
a62d11ea94
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:34:20 +00:00
Akira Hatanaka
7a7194b529
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
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MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:05:38 +00:00
Jim Grosbach
120313435d
ARM VSUB implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:56:26 +00:00
Owen Anderson
587e34065f
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
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Fixes failures caused by r146171.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:51:38 +00:00
Jim Grosbach
9e7b42a40e
ARM VQADD implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389
ARM a few more VMUL implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:42:35 +00:00
Akira Hatanaka
ca0747917d
Implement 64-bit support for thread local storage handling.
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- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:34:32 +00:00
Owen Anderson
4a4fdf3476
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:32:14 +00:00
Jim Grosbach
40e2855547
ARM assembler support for register name aliases.
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rdar://10550084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:27:38 +00:00
Evan Cheng
2f435511e9
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
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if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:00:42 +00:00
Daniel Dunbar
3b0887e291
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
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sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 17:32:18 +00:00
Jan Sjödin
703420f50e
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 14:43:19 +00:00
Stepan Dyatkovskiy
72590c9738
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 07:55:03 +00:00
Hal Finkel
6772452644
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 04:36:44 +00:00
Jim Grosbach
730fe6c1b6
ARM NEON two-operand aliases for VSHL(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jakob Stoklund Olesen
e6f9e9d836
Drop the HasInlineAsm flag.
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It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:22:39 +00:00
Jim Grosbach
ff4cbb4c9a
ARM NEON two-operand aliases for VSHL(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
99486be8ba
Simplify offset verification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:10:05 +00:00
Jim Grosbach
517a013a4f
Fix copy/past-o.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:02:26 +00:00
Jim Grosbach
2b8810c500
ARM NEON two-operand aliases for VMUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
540c6d9d26
Don't include alignment padding in BBInfo.Size.
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Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:55:02 +00:00
Jim Grosbach
8254f02231
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:52:55 +00:00
Jim Grosbach
67ca1adf82
ARM VFP support 'flds/fldd' aliases for 'vldr'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:49:29 +00:00
Jim Grosbach
a44f2c4a28
ARM optional destination operand variants for VEXT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:43:47 +00:00
Jim Grosbach
3bc8a3d3af
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:40:58 +00:00
Akira Hatanaka
08a7d92da6
Modify class ReadHardware and add definition of 64-bit version of instruction
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RDHWR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:31:26 +00:00
Akira Hatanaka
f99c1e5a19
Add newline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:26:03 +00:00
Akira Hatanaka
be7b67368c
Add 64-bit HWR29 register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:23:52 +00:00
Akira Hatanaka
da86fa14f0
32 to 64-bit anyext pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:21:19 +00:00
Akira Hatanaka
0a18cdc372
32 to 64-bit zext pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:14:41 +00:00
Jim Grosbach
9fa0a743e6
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f
ARM two-operand aliases for VADDW instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13
ARM two-operand aliases for VADD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:52:54 +00:00
Bruno Cardoso Lopes
d1bcf0dbc1
Variable cleanup. Based on past patch submittals variable names have
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been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:35:30 +00:00
Akira Hatanaka
2c78be01f6
64-bit WrapperPICPat patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:11:43 +00:00
Akira Hatanaka
20aa12ae5c
Define base class for WrapperPICPat.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:54:54 +00:00
Akira Hatanaka
7398bf01c2
Modify LowerFCOPYSIGN to handle Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:48:50 +00:00
Akira Hatanaka
bd15090aa2
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:15:01 +00:00
Akira Hatanaka
3bdc03a592
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:13:53 +00:00
Akira Hatanaka
4d0eb637f0
Fix 64-bit immediate patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:10:24 +00:00
Jim Grosbach
4f66a050a2
Nuke inadvertant debugging commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:56:16 +00:00
Jim Grosbach
577b09155f
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:59 +00:00
Jim Grosbach
8524bca750
Thumb2 alias for long-form pop and friends.
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rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca
ARM support the .arm and .thumb directives for assembly mode switching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Craig Topper
d802326335
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 08:30:53 +00:00
Bill Wendling
b3ec329c14
Adjust the stack by one pointer size for all frameless stacks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:58:55 +00:00
Bill Wendling
c61751373a
Fix off-by-one error when encoding the stack size for a frameless stack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:49:49 +00:00
Evan Cheng
5a96b3dad2
Add bundle aware API for querying instruction properties and switch the code
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generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Hal Finkel
234bb38d6c
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:34:06 +00:00
Hal Finkel
6d0e014b1f
make base register selection used in eliminateFrameIndex 64-bit clean
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:34:02 +00:00
Hal Finkel
ae37cd0a37
set mayStore and mayLoad on CR pseudos
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:33:57 +00:00
Hal Finkel
7ad6b7d359
64-bit LR8 load should use X11 not R11
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2fe71c5ef4
Eliminate delta argument from AdjustBBOffsetsAfter.
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The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
a26811ec83
Compute some alignment information for each basic block.
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These fields are not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 04:17:35 +00:00
Jim Grosbach
1ceef1a491
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
5bb32530bc
Move common expression into a method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:22:52 +00:00
Jim Grosbach
9f3d220c63
ARM Implement ARM ARM Table A7-3 via TokenAlias.
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Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a3f331bd81
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
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No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:08:25 +00:00
Jim Grosbach
3b8991cc98
ARM: NEON SHLL instruction immediate operand range checking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:07:24 +00:00
Bruno Cardoso Lopes
e3d3572e28
Add a few moreLocal/Global R_MIPS_GOT related fixups and
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make the addend fixup code a bit more generic
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:28:57 +00:00
Jim Grosbach
4e4139588c
ARM: Parameterize the immediate operand type for NEON VSHLL.
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No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen
6fbea43b0b
Revert r145971: "Use conservative size estimate for tBR_JTr."
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This caused more offset errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:41:31 +00:00
Bill Wendling
84d518af19
Explicitly check for the different SUB instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:14:27 +00:00
Evan Cheng
7c2a4a30e0
First chunk of MachineInstr bundle support.
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1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
d25c27807e
Use conservative size estimate for tBR_JTr.
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This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen
305e5fe797
Remove alignment from deserted constant islands.
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ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:35 +00:00
Bill Wendling
581ac2723c
Encode the total stack if there isn't a frame.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:34:01 +00:00
Bill Wendling
57a3cd2f32
* Add a macro to remove a magic number.
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* Rename variables to reflect what they're actually used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:23:42 +00:00
Hal Finkel
d21e930eac
add RESTORE_CR and support CR unspills
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:55:36 +00:00
Hal Finkel
16588e794c
remove old FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:52:56 +00:00
Bill Wendling
5b2c4978ce
Check the correct value for small stack sizes. Also modify some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 19:16:17 +00:00
Bill Wendling
75e14e0ebd
For a small sized stack, we encode that value directly with no "stack adjust" value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 19:09:06 +00:00
Justin Holewinski
4c7ffb6a7e
PTX: Continue to fix up the register mess.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:39:48 +00:00
Justin Holewinski
e37a83f66b
PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:39:46 +00:00
Craig Topper
fe03315925
Add X86ISD::HADD/HSUB to getTargetNodeName
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 09:31:36 +00:00
Craig Topper
cb6bd11bd6
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 09:04:59 +00:00
Craig Topper
34671b812a
Merge floating point and integer UNPCK X86ISD node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 08:21:25 +00:00
Craig Topper
3d8c2ce3e4
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:31:16 +00:00
Jim Grosbach
23261af193
ARM mode 'mul' operand ordering tweak.
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Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2
Thumb2: MUL two-operand form encoding operand order fix.
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Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
ff452f5349
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
2bcc789a9d
Add register HWR29 numbering. Patch by Jack Carter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:34:36 +00:00
Bill Wendling
80caf9c273
Add a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:57:48 +00:00
Jim Grosbach
cb86509e7a
Tidy up value checking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
6482e91149
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:48:32 +00:00
Chad Rosier
ed42c5f778
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb
Align ARM constant pool islands via their basic block.
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Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
8c741b8064
Use logarithmic units for basic block alignment.
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This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:26:19 +00:00
Bill Wendling
79df986c60
The compact encoding of the registers are 3-bits each. Make sure we shift the
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value over that much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:26:14 +00:00
Jim Grosbach
d9a6e8978d
Fix ARM handling of tBcc branch relaxation.
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rdar://10069056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e80fba0e6c
Use an existing function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 00:51:12 +00:00
Jim Grosbach
370b78d795
Move target-specific logic out of generic MCAssembler.
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Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 00:47:03 +00:00
Jim Grosbach
f503ef6800
Simple branch relaxation for Thumb2 Bcc instructions.
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Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 23:45:46 +00:00
Jim Grosbach
713c70238c
Tweak ADDrr fix. Bad check for explicit .w
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6
Thumb2 prefer ADD register encoding T2 to T3 when possible.
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rdar://10529664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:16:39 +00:00
Akira Hatanaka
d6bc5237d8
Add definitions of 64-bit extract and insert instrucions and make
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PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:26:34 +00:00
Akira Hatanaka
cee46abc16
Split ExtIns into two base classes and have instructions EXT and INS derive from
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them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:14:28 +00:00
Jim Grosbach
da84786bee
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:06:26 +00:00