Chris Lattner
dfa3c9d982
add support for pushfd/popfd which are aliases for pushfl/popfl.
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This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:39:16 +00:00
Chris Lattner
ee211d0ed6
implement rdar://8407928 - support for in/out with a missing "a" register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:32:12 +00:00
Chris Lattner
cbf8a98c7c
fix the asmparser so that the target is responsible for skipping to
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the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:18:25 +00:00
Bill Wendling
a65568676d
Rename ConvertToSetZeroFlag to something more general.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 00:13:50 +00:00
Bill Wendling
3665661a57
No need to recompute the SrcReg and CmpValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:46:12 +00:00
Bill Wendling
92ad57f066
Move some of the decision logic for converting an instruction into one that sets
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the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:34:19 +00:00
Eric Christopher
d10cd7b314
Start sketching out ARM fast-isel calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:18:12 +00:00
Eric Christopher
44bff903e2
For consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:10:30 +00:00
Eric Christopher
09b2171d7e
Newline at end of file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 22:46:03 +00:00
Eric Christopher
6f2ccefdc0
Split out some of the calling convention bits so that they can be
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used for fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 22:42:06 +00:00
Bill Wendling
220e240bdf
Modify the comparison optimizations in the peephole optimizer to update the
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iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:55:43 +00:00
Jim Grosbach
51f5b67395
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:38:22 +00:00
Michael J. Spencer
4e9c939312
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:14:25 +00:00
Dale Johannesen
bb811a2445
Add X86 MMX type to bitcode and Type.
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(The Ada bindings probably need it too, but all the
obvious places to change say "do not edit this file".)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113618 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 20:55:01 +00:00
Bill Wendling
1ec2ee6526
Reapply r113585. The msvc machine is mercurial.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 20:20:28 +00:00
Bill Wendling
b28f579200
r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't
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understand (the log file was no help).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 19:20:47 +00:00
Bob Wilson
979927ab26
Calculate the number of VLDM/VSTM registers by subtracting the number of
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fixed operands from the total number of operands (including the variadic ones).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 18:25:35 +00:00
Bill Wendling
81781ed939
Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so
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that the memoperands are properly set after DAG building and general mucking
about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 10:34:22 +00:00
Bill Wendling
c8714bb144
Reword since this may not be a bug but intended behavior.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113584 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 10:31:11 +00:00
Bob Wilson
efe7d9a12f
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
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to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 05:15:04 +00:00
Evan Cheng
3ef1c8759a
Teach if-converter to be more careful with predicating instructions that would
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take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
Eric Christopher
920a2089d9
Fix build error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 00:35:09 +00:00
Eric Christopher
db12b2ba9c
Update comments, reorganize some code, rename variables to be
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more clear. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 00:34:35 +00:00
Eric Christopher
238bb16251
64-bit fp loads can come straight out of the constant pool, not as
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bad as I'd thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113561 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 23:50:00 +00:00
Eric Christopher
9ee4ce2f91
SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move
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some data around and implement a couple of move routines to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113546 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 21:44:45 +00:00
Eric Christopher
aa3ace10c1
New "move to fp reg" routine. Use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 20:49:25 +00:00
Eric Christopher
ef2fdd2141
"Strike that, reverse it." -- Mr. Wonka.
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Truncate when truncating, extend when extending.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 20:36:19 +00:00
Eric Christopher
ce07b5458d
Add FPTrunc, fix some bugs where I forgot to update the value map.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 20:26:31 +00:00
Eric Christopher
9a040492f7
Basic FP->Int, Int->FP conversions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:54:59 +00:00
Bruno Cardoso Lopes
ae4f7421c0
Add one more pattern to fallback movddup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:48:34 +00:00
Evan Cheng
5f54ce3473
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:18:55 +00:00
Roman Divacky
5baf79edc0
Make ELF OS ABI dependent on the OS from target triple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 17:57:50 +00:00
Dale Johannesen
f73c5587fa
Move remaining MMX instructions from SSE to MMX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 17:13:07 +00:00
Kalle Raiskila
bb7d33a253
Silence compiler warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 07:30:15 +00:00
Bob Wilson
0f1e9457a5
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
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the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 05:40:26 +00:00
Eric Christopher
ac1a19e18a
Nuke whitespace and fix some indenting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 01:06:51 +00:00
Dale Johannesen
4efb0feac8
Move most MMX instructions (defined as anything that
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uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX. No (intended) functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 01:02:39 +00:00
Eric Christopher
bd6bf0848e
Handle 64-bit floating point binops as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 01:02:03 +00:00
Eric Christopher
bc39b829f2
Basic 32-bit FP operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 00:53:57 +00:00
Bob Wilson
19d644d5a9
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
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operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 00:38:32 +00:00
Eric Christopher
4620360842
Handle float->double extension.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 00:26:48 +00:00
Eric Christopher
9ed58dff86
Rewrite TargetMaterializeConstant splitting it out into two functions
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for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 00:19:41 +00:00
Bob Wilson
63569c99ec
Simplify copying over operands from pseudo NEON load/store instructions.
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For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 00:15:32 +00:00
Bob Wilson
656edcf138
Clean up a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 23:39:54 +00:00
Eric Christopher
d43393ae34
Very basic compare support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 23:13:45 +00:00
Eric Christopher
a88d8577e6
Delete dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113436 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:58:35 +00:00
Evan Cheng
7602acbf3b
Fix LDM_RET schedule itinery.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:57:08 +00:00
Chris Lattner
90b54547d9
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:27:05 +00:00
Chris Lattner
a7f08b4970
fix wonky formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113426 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:22:10 +00:00
Chris Lattner
373c458850
fix bugs in push/pop segment support, rdar://8407242
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:13:08 +00:00
Dale Johannesen
52664c8efe
Add intrinsic-based patterns for MMX PINSRW and PEXTRW.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:08:40 +00:00
Eric Christopher
30b663339e
Make the loads/stores match the type we really want to store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113417 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 21:49:50 +00:00
Dale Johannesen
ab1deb998e
Check in forgotten file. Should fix build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 21:09:48 +00:00
Dale Johannesen
246658f158
Slight cleanup, use only one form of MMXI_binop_rm_int.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 20:54:00 +00:00
Jim Grosbach
d0bd76b0fb
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
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Re-running some nightly testers w/ it enabled to verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 20:12:02 +00:00
Jim Grosbach
951f699afb
Fix errant fall-throughs causing the base pointer to be used when the frame
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pointer was intended. rdar://8401980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 19:55:28 +00:00
Dale Johannesen
af4748168c
Add intrinsic forms of mmx<->sse conversions. Notes:
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Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 19:15:38 +00:00
Eric Christopher
845c5757ed
Rewrite TargetMaterializeConstant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 18:56:34 +00:00
Bruno Cardoso Lopes
0a7dd4fa40
Minor change. Fix comments and remove unused and redundant code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 18:12:31 +00:00
Bruno Cardoso Lopes
1485cc2bb3
x86 vector shuffle lowering now relies only on target specific
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nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 17:43:25 +00:00
Jim Grosbach
30c93e1cd3
Be more careful about when to do dynamic stack realignment. Since we have an
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option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 17:22:12 +00:00
Jim Grosbach
6b53834d5f
Add missing assert
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 17:05:45 +00:00
Kalle Raiskila
0b4ab0cfe0
Fix CellSPU vector shuffles, again.
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Some cases of lowering to rotate were miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 11:53:38 +00:00
Chris Lattner
c8ae35a8e8
add support for the commuted form of the test instruction, rdar://8018260.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:51:12 +00:00
Chris Lattner
ba8e81cca2
implement proper support for sysret{,l,q}, rdar://8403907
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:45:34 +00:00
Chris Lattner
ba8cea450f
implement the iret suite of instructions properly,
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fixing rdar://8403974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:38:31 +00:00
Chris Lattner
2544f42692
add support for instruction prefixes on the same line as the instruction,
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implementing rdar://8033482 and PR7254.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:17:37 +00:00
Chris Lattner
34e53140c2
change the MC "ParseInstruction" interface to make it the
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implementation's job to check for and lex the EndOfStatement
marker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:10:46 +00:00
Chris Lattner
9607c40601
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
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Add this to the mc assembler, fixing PR8061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 04:53:27 +00:00
NAKAMURA Takumi
186acea746
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 04:48:17 +00:00
Chris Lattner
a247685b30
fix the encoding of the "jump on *cx" family of instructions,
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rdar://8061602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 04:30:51 +00:00
Jim Grosbach
4725ca746a
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 03:54:02 +00:00
Jim Grosbach
707fb648d2
remove obsolete comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 03:51:44 +00:00
Jim Grosbach
e1e6d18786
disable for the moment while tracking down a few Thumb2-O0 failure that look
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related. (attempt deux, complete w/ test update this time)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 02:00:34 +00:00
Jim Grosbach
8b95dfe2b6
woops. need to update a test along with this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 01:49:09 +00:00
Jim Grosbach
8a076eb79d
disable temporarily while sorting out a few test failures in Thumb2-O0 tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 01:47:49 +00:00
Jim Grosbach
0cfcf93c95
correct spill code to properly determine if dynamic stack realignment is
...
present in the function and thus whether aligned load/store instructions can
be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 00:26:59 +00:00
Jim Grosbach
72db182438
VFP/NEON load/store multiple instructions are addrmode4, not 5.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 00:25:50 +00:00
Jim Grosbach
447e7ac913
To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base
...
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).
rdar://8394087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 22:30:53 +00:00
Jim Grosbach
e2f70d1724
grammar tweak
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 21:30:25 +00:00
Bruno Cardoso Lopes
90462b4ae1
Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113286 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 21:03:14 +00:00
Bruno Cardoso Lopes
0d1340b181
Move code around to prepare for moving some of the logic together to another function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 20:20:27 +00:00
Bill Wendling
d8dd5757e0
Add an MVT::x86mmx type. It will take the place of all current MMX vector types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 20:03:56 +00:00
Evan Cheng
dc0b06c815
Remove a dead comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 20:01:10 +00:00
Chris Lattner
6cd5db41f7
hopefully fix a problem building on cygwin-1.5
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113255 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 19:50:53 +00:00
Bruno Cardoso Lopes
58277b17c3
decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113247 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:41:45 +00:00
Bruno Cardoso Lopes
673bf78bb5
Remove now useless check, because the code can be matched below, no need to leave it for isel
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:29:03 +00:00
Bruno Cardoso Lopes
67fc1e76d4
Minor change. Since the checks are equivalent, use isMMX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113239 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:24:00 +00:00
Nick Lewycky
f7a3c50183
Create PTX backend. Patch by Che-Liang Chiou!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:14:24 +00:00
Dale Johannesen
86097c384f
Add patterns for MMX that use the new intrinsics.
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Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:10:56 +00:00
Bruno Cardoso Lopes
70e81f1517
Remove unused target specific node
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 17:38:55 +00:00
Benjamin Kramer
aceeb3a4e2
Don't leak the old operand when transforming "sldt" into "sldtw".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 14:40:58 +00:00
Chris Lattner
e9e0fc5eed
add missing cmov aliases, this resolves rdar://8208499
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 00:05:45 +00:00
Chris Lattner
7d284de955
remove duplicated entry
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:57:24 +00:00
Chris Lattner
c5cebeb3cb
"sldt <mem>" is ambiguous in 64-bit mode, but should
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always be disambiguated as sldtw. sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact. Force it to sldtw, resolving rdar://8017530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:51:44 +00:00
Chris Lattner
d68c474ec5
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)"
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:40:56 +00:00
Chris Lattner
9389b60a03
fix the operand constraints of the immediate form of in/out,
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allowing unsigned 8-bit operands. This fixes rdar://8208481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:29:05 +00:00
Chris Lattner
ce4a3355d9
in the case where an instruction only has one implementation
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of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 22:11:18 +00:00
Chris Lattner
a008e8ac73
Now that we know if we had a total fail on the instruction mnemonic,
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give a more detailed error. Before:
t.s:11:4: error: unrecognized instruction
addl $1, $1
^
t.s:12:4: error: unrecognized instruction
f2efqefa $1
^
After:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
f2efqefa $1
^
This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 21:54:15 +00:00
Chris Lattner
69c7249a6f
simplify the hacks around jrcxz.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 20:10:12 +00:00
Chris Lattner
ec6789f4f9
have tblgen detect when an instruction would have matched, but
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failed because a subtarget feature was not enabled. Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode. Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.
This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113166 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 20:08:02 +00:00
Chris Lattner
79ed3f77e8
change MatchInstructionImpl to return an enum instead of bool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 19:22:17 +00:00
Chris Lattner
0692ee676f
have AsmMatcherEmitter.cpp produce the hunk of code that gets included
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into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 19:11:01 +00:00
Roman Divacky
436c54a186
Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 18:43:14 +00:00
Chris Lattner
47ab90bfa8
random cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 18:32:06 +00:00
Chris Lattner
979b061819
remove some dead code. t2addrmode_imm8s4 is never used in a
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pattern, so there is no need to define a matching function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 22:51:11 +00:00
Chris Lattner
252b491875
cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 21:18:45 +00:00
Chris Lattner
f0f5780b39
update this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 20:22:09 +00:00
Chris Lattner
beac75da37
implement rdar://6653118 - fastisel should fold loads where possible.
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Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 02:18:34 +00:00
Chris Lattner
17aa68055b
zap dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 18:12:00 +00:00
Chris Lattner
89f87e8f5a
remove dead code, mblaze uses SelectAddrRegImm/SelectAddrRegReg,
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not SelectAddr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 18:02:47 +00:00
Bruno Cardoso Lopes
2eb63dfa0a
Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 02:58:56 +00:00
Bruno Cardoso Lopes
828f6ae03c
make explicit that we not handle several mmx shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 02:50:13 +00:00
Bruno Cardoso Lopes
aace0f295b
Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 02:36:07 +00:00
Bruno Cardoso Lopes
c800c0d25f
Emit target specific nodes to handle splats starting at zero indicies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 02:02:14 +00:00
Bruno Cardoso Lopes
bbfc31012b
Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 01:36:45 +00:00
Bruno Cardoso Lopes
4c827f5ae1
Emit target specific nodes for isSHUFPMask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113048 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 01:22:57 +00:00
Bruno Cardoso Lopes
d344f28b9d
Previous isMOVLMask matching already emits targets nodes, remove check
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 00:50:08 +00:00
Bruno Cardoso Lopes
e09abcd3c4
One more check from the original isShuffleMaskLegal goes away
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 00:46:16 +00:00
Bruno Cardoso Lopes
b733996110
Remove a duplicated but useless check that i've inserted in the previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 00:43:12 +00:00
Bruno Cardoso Lopes
a22c84571a
Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04 00:39:43 +00:00
Bruno Cardoso Lopes
43c05744b5
Remove check for unpckh mask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 23:32:47 +00:00
Bruno Cardoso Lopes
ef3adb3243
Remove check for unpckl mask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 23:31:50 +00:00
Bruno Cardoso Lopes
7256e22f77
Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start
...
checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 23:24:06 +00:00
Bruno Cardoso Lopes
e8f279cbd4
Reapply considered harmfull part of rr112934 and r112942.
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"Use target specific nodes instead of relying in unpckl and
unpckh pattern fragments during isel time. Also place a
depth limit in getShuffleScalarElt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 22:09:41 +00:00
Dale Johannesen
caa9ba228d
Remove the rest of the nonexistent 64-bit AVX instructions.
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Bruno, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 21:23:00 +00:00
Bruno Cardoso Lopes
190d0a54c1
Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 20:44:26 +00:00
Bruno Cardoso Lopes
2a4460606e
Reintroduce a simple function refactoring done in r112934, also without any functionality changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 20:20:02 +00:00
Bruno Cardoso Lopes
be8b084d8a
Reapply piecies of r112942 and r112934 which don't do
...
functional changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 20:10:35 +00:00
Bruno Cardoso Lopes
b3e0669b8e
Reapply Fix comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113006 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 19:55:05 +00:00
Daniel Dunbar
3139422058
Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced
...
some infinite loop and select failures.
- Apologies for eager reverting, but its branch day.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 19:38:11 +00:00
Daniel Dunbar
78541f258c
Revert r112938 "Fix comment", which depends on r112934, which introduced some
...
infinite loop and select failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 19:38:08 +00:00
Daniel Dunbar
a87ccce95b
Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh
...
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 19:38:05 +00:00
Jim Grosbach
65482b1bb8
Re-apply r112883:
...
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."
r112986 fixed a latent bug exposed by the above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 18:37:12 +00:00
Jim Grosbach
fc63300233
Check the local frame alignment for determining whether dynamic stack
...
alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 18:28:19 +00:00
Bob Wilson
f572191fe4
Finish converting the rest of the NEON VLD instructions to use pseudo-
...
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 18:16:02 +00:00
Daniel Dunbar
6a8700301c
Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.
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This reverts commit 8d6e29cfda270be483abf638850311670829ee65.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 15:26:42 +00:00
Benjamin Kramer
df3f25656d
Zap dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 12:13:18 +00:00
Bruno Cardoso Lopes
95f1e2d6b5
AVX doesn't support mm operations neither its instrinsics.
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The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 02:08:45 +00:00
Bruno Cardoso Lopes
4b0c9f3e73
Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:39:08 +00:00
Bob Wilson
eb0c3d3729
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
...
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:35:08 +00:00
Bruno Cardoso Lopes
01f0847ce8
Fix comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:28:51 +00:00
Bruno Cardoso Lopes
5e5342b0a8
- Use specific nodes to match unpckl masks.
...
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:24:00 +00:00
Eric Christopher
e5734105da
Simple branch instruction support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:47 +00:00
Jakob Stoklund Olesen
3061c4442e
Don't call Predicate_* from X86 target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:18 +00:00
Jakob Stoklund Olesen
7853cd0bea
Remove Predicate_* calls from MBlaze and XCore
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:16 +00:00
Jakob Stoklund Olesen
7fa846f7d9
Remove Predicate_* calls from Mips
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:13 +00:00
Eric Christopher
56d2b72884
Add basic support for materializing constants (including fp) and
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stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 23:43:26 +00:00
Anton Korobeynikov
ace53f2fbc
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
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Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
ed5c711a6e
Move insertps mask decoding to header file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:43:39 +00:00
Anton Korobeynikov
c7c62bb3ca
Revert win64 changes. They seem to be incomplete
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:31:32 +00:00
Jim Grosbach
1755b3964f
For ARM stack frames that utilize variable sized objects and have either
...
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.
rdar://7352504
rdar://8374540
rdar://8355680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:29:01 +00:00
Anton Korobeynikov
2f4fad99ea
Properly allocate win64 shadow reg area.
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Patch by Jan Sjodin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:16:28 +00:00
Bruno Cardoso Lopes
5594560766
Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 21:51:11 +00:00
Dan Gohman
24bde5bce1
Don't narrow the load and store in a load+twiddle+store sequence unless
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there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 21:18:42 +00:00
Jim Grosbach
5c33f5bf67
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 19:52:39 +00:00
Jim Grosbach
3e234e7579
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:44:51 +00:00
Bruno Cardoso Lopes
6b1d0a3b36
Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:40:13 +00:00
Jim Grosbach
bb5a039b76
handle case where a register class is specified
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:18:52 +00:00
Jim Grosbach
e7c1416263
Now that register allocation properly considers reserved regs, simplify the
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ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:14:29 +00:00
Jim Grosbach
5a0fabae5a
Mask out reserved registers when constructing the set of allocatable regs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112828 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:31:21 +00:00
Bob Wilson
82a9c8480e
Fill in a missing comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:17:29 +00:00
Bob Wilson
ffde080ae6
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
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after regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:00:54 +00:00
Bruno Cardoso Lopes
3722f007b6
Replace unpckl_undef and unpckh_undef matching with target specific opcodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 05:23:12 +00:00
Bruno Cardoso Lopes
dd69db858c
Move condition out to prepare for more matching
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 04:20:26 +00:00
Bruno Cardoso Lopes
ad10fb2b56
Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 03:57:58 +00:00
Bruno Cardoso Lopes
d00bfe1f8d
become more strict about when it's safe to use X86ISD::MOVLPS
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 02:35:51 +00:00
Eric Christopher
1f58741aab
Clang's -ccc-host-triple was ignoring the arch specifier on my triple,
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I don't need to implement this quite yet - and not for ConstantInt anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 02:30:46 +00:00
Eric Christopher
1b61ef4b22
This should be TargetMaterializeConstant instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 01:48:11 +00:00
Eric Christopher
eaa204b2f8
One definition of isThumb is plenty, thanks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 01:39:14 +00:00
Jim Grosbach
b0739b7833
Remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 01:02:06 +00:00
Eric Christopher
318b6eec8d
Rework arm fast-isel load and store handling. Move offset computation
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into the "address selection" routine and handle constant materialization
for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 00:53:56 +00:00
Jim Grosbach
7af3a345a9
trivial cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 00:02:26 +00:00
Jim Grosbach
352f23529c
Simplify the tGPR register class now that the register allocators know not
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to try to allocate reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 23:50:23 +00:00
Bob Wilson
d0b69cf119
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
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add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 23:50:19 +00:00
Bruno Cardoso Lopes
4783a3ee13
Revert r112689, avoid those kind of checks cause they mess up with mmx
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:59:03 +00:00
Bruno Cardoso Lopes
29c353b9c3
Using target specific nodes for shuffle nodes makes the mask
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check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:
movaps (%rdi), %xmm0
movaps (%rax), %xmm1
movaps %xmm0, %xmm2
movss %xmm1, %xmm2
shufps $36, %xmm2, %xmm0
now is generated as:
movaps (%rdi), %xmm0
movaps %xmm0, %xmm1
movlps (%rax), %xmm1
shufps $36, %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:33:20 +00:00
Eric Christopher
543cf05b9c
Some basic store support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:16:27 +00:00
Eric Christopher
4e68c7cca4
Add some more load types in.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 18:01:32 +00:00
Chris Lattner
14ab39e43f
zap dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 16:04:34 +00:00
Chris Lattner
5bcb8a6112
temporarily revert r112664, it is causing a decoding conflict, and
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the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 16:00:50 +00:00
Bruno Cardoso Lopes
56098f5d26
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 05:08:25 +00:00
Bruno Cardoso Lopes
9cfad89a68
minor change, simplify some logic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:57:08 +00:00
Bruno Cardoso Lopes
e654b56eb1
Move some functions around so they can be used for some other to come function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:51:36 +00:00
Bill Wendling
43a6c5e2fc
We have a chance for an optimization. Consider this code:
...
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:41:22 +00:00
Bruno Cardoso Lopes
013bb3dee9
Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:35:05 +00:00
Bruno Cardoso Lopes
5023ef281c
Use x86 specific MOVSHDUP node and add more patterns to match it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:22:11 +00:00
Bill Wendling
2d811d38d4
And ANDS pattern to match the t2ANDS pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:05:37 +00:00
Jakob Stoklund Olesen
63b1dbaadd
Make %EFLAGS unallocatable.
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No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:51:07 +00:00
Bruno Cardoso Lopes
7ff30bb1a5
Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:38:49 +00:00
Bruno Cardoso Lopes
f2db5b48d0
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:15:21 +00:00
Jim Grosbach
c1dc78de76
SP relative offsets need to be adjusted by the local allocation size when
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determining if they're likely to be in range of the SP when resolving
frame references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 18:52:31 +00:00
Jim Grosbach
d4511e947e
this assert should just be a condition, since this function is just asking if
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the offset is legally encodable, not actually trying to do the encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 18:49:31 +00:00
Bill Wendling
da2ae63206
- Cleanup some whitespaces.
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- Convert {0,1} and friends into 0b01, which is identical and more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 07:50:46 +00:00
Bruno Cardoso Lopes
20a07f422d
Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 02:26:40 +00:00
Eric Christopher
dc90804a40
Rewrite slightly so we can expand for floating point types easier.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112568 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 01:28:42 +00:00
Eric Christopher
548d1bb97e
If we have an unhandled type then assert, we shouldn't get here for
...
things we can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 23:48:26 +00:00
Anton Korobeynikov
6d1e29d2f2
Expand MOVi32imm in ARM mode after regalloc. This provides
...
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 22:50:36 +00:00
Bill Wendling
55c134a261
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
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is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 22:05:23 +00:00
Jakob Stoklund Olesen
2536279674
Remember to clear the shadow kill flag at the same time as clearing the real
...
kill flag.
This could cause duplicate kill flags when the same register was used twice in a
continuous sequence of STRs.
There is no small test case. <rdar://problem/8218046>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 21:52:40 +00:00