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1018 Commits

Author SHA1 Message Date
Chris Lattner
30483b0c84 Teach the X86 backend about unreachable and undef. Among other things, we 
now compile:

'foo() {}' into "ret" instead of "mov EAX, 0; ret"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17049 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-16 18:13:05 +00:00
Chris Lattner
358a9027a8 Instruction select globals with offsets better. For example, on this test 
case:

int C[100];
int foo() {
  return C[4];
}

We now codegen:

foo:
        mov %EAX, DWORD PTR [C + 16]
        ret

instead of:

foo:
        mov %EAX, OFFSET C
        mov %EAX, DWORD PTR [%EAX + 16]
        ret

Other impressive features may be coming later.

This patch is contributed by Jeff Cohen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17011 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-15 05:05:29 +00:00
Chris Lattner
8cce7cd0ae Give the X86 JIT the ability to encode global+disp constants. Patch 
contributed by Jeff Cohen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17010 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-15 04:53:13 +00:00
Chris Lattner
d416f086cc Give the X86 asm printer the ability to print out addressing modes that have 
constant displacements from global variables.  Patch by Jeff Cohen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17009 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-15 04:44:53 +00:00
Chris Lattner
fb3d844e50 Allow X86 addressing modes to represent globals with offsets. Patch contributed 
by Jeff Cohen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17008 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-15 04:43:20 +00:00
Reid Spencer
d96cb6eaa0 Update to reflect changes in Makefile rules. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16950 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-13 11:46:52 +00:00
Reid Spencer
81f76b324e Initial version of automake Makefile.am file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16893 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-10 22:20:40 +00:00
Chris Lattner
222b86f694 The person who was planning to add SSE support isn't anymore, so disable 
the -sse* options (to avoid misleading people).

Also, the stack alignment of the target doesn't depend on whether SSE is
eventually implemented, so remove a comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16860 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-08 22:41:46 +00:00
Chris Lattner
b0f4e389db Fix a major regression from the bugfix for 2004-10-08-SelectSetCCFold.llx, 
which prevented setcc's from being folded into branches.  It appears that
conditional branchinst's CC operand is actually operand(2), not operand(0)
as we might expect. :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16859 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-08 22:24:31 +00:00
Chris Lattner
d04cd55796 Fix bug: 2004-10-08-SelectSetCCFold.llx. Normally this is hidden by the 
instcombine xform, which is why we didn't notice it before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16840 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-08 16:34:13 +00:00
Chris Lattner
09c750f73d Remove debugging code, fix encoding problem. This fixes the problems 
the JIT had last night.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16766 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 14:31:50 +00:00
Chris Lattner
2483f67914 Codegen signed mod by 2 or -2 more efficiently. Instead of generating: 
t:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %ECX, 2
        mov %EAX, %EDX
        sar %EDX, 31
        idiv %ECX
        mov %EAX, %EDX
        ret

Generate:
t:
        mov %ECX, DWORD PTR [%ESP + 4]
***     mov %EAX, %ECX
        cdq
        and %ECX, 1
        xor %ECX, %EDX
        sub %ECX, %EDX
***     mov %EAX, %ECX
        ret

Note that the two marked moves are redundant, and should be eliminated by the
register allocator, but aren't.

Compare this to GCC, which generates:

t:
        mov     %eax, DWORD PTR [%esp+4]
        mov     %edx, %eax
        shr     %edx, 31
        lea     %ecx, [%edx+%eax]
        and     %ecx, -2
        sub     %eax, %ecx
        ret

or ICC 8.0, which generates:

t:
        movl      4(%esp), %ecx                                 #3.5
        movl      $-2147483647, %eax                            #3.25
        imull     %ecx                                          #3.25
        movl      %ecx, %eax                                    #3.25
        sarl      $31, %eax                                     #3.25
        addl      %ecx, %edx                                    #3.25
        subl      %edx, %eax                                    #3.25
        addl      %eax, %eax                                    #3.25
        negl      %eax                                          #3.25
        subl      %eax, %ecx                                    #3.25
        movl      %ecx, %eax                                    #3.25
        ret                                                     #3.25

We would be in great shape if not for the moves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16763 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 05:01:07 +00:00
Chris Lattner
3ffdff6448 Fix a scary bug with signed division by a power of two. We used to generate: 
s:   ;; X / 4
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 1
        shr %ECX, 30
        mov %EDX, %EAX
        add %EDX, %ECX
        sar %EAX, 2
        ret

When we really meant:

s:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 1
        shr %ECX, 30
        add %EAX, %ECX
        sar %EAX, 2
        ret

Hey, this also reduces register pressure too :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16761 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 04:19:43 +00:00
Chris Lattner
610f1e2785 Codegen signed divides by 2 and -2 more efficiently. In particular 
instead of:

s:   ;; X / 2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        ret

t:   ;; X / -2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        negl %eax
        ret

Emit:

s:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        ret

t:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        negl %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16760 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 04:02:39 +00:00
Chris Lattner
d93d3b047c Add some new instructions. Fix the asm string for sbb32rr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16759 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 04:01:02 +00:00
Chris Lattner
955f09666d * Prune #includes 
* Update comments
* Rearrange code a bit
* Finally ELIMINATE the GAS workaround emitter for Intel mode.  woot!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16647 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 07:31:08 +00:00
Chris Lattner
ac5701c562 Add support for emitting AT&T style .s files, and make it the default. Users 
may now choose their output format with the -x86-asm-syntax={intel|att} flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16646 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 07:24:48 +00:00
Chris Lattner
8f99eff156 Convert some missed patterns to support AT&T style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16645 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 07:23:07 +00:00
Chris Lattner
10f873b420 Apparently the GNU assembler has a HUGE hack to be compatible with really 
old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16644 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 07:08:46 +00:00
Chris Lattner
ac6a47588b Fix incorrect suffix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16642 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 05:20:16 +00:00
Chris Lattner
707c6fe3ad Fix some more missed suffixes and swapped operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16641 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 01:38:10 +00:00
Chris Lattner
60c715c9a2 Add missing suffixes to FP instructions for AT&T mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16640 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-04 00:43:31 +00:00
Chris Lattner
9a3e49a1b3 Add support for the -x86-asm-syntax flag, which can be used to choose between 
Intel and AT&T style assembly language.  The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-03 20:36:57 +00:00
Chris Lattner
3a173dfc72 Add support to the instruction patterns for AT&T style output, which will 
hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16638 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-03 20:35:00 +00:00
Alkis Evlogimenos
65cbfa0f37 The real x87 floating point registers should not be allocatable. They 
are only used by the stackifier when transforming FPn register
allocations to the real stack file x87 registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16472 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-21 21:22:11 +00:00
Misha Brukman
eae1bf10ea s/ISel/X86ISel/ to have unique class names for debugging via gdb because the C++ 
front-end in gcc does not mangle classes in anonymous namespaces correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16469 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-21 18:21:21 +00:00
Reid Spencer
2da5c3dda6 Convert code to compile with vc7.1. 
Patch contributed by Paolo Invernizzi. Thanks Paolo!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16368 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-15 17:06:42 +00:00
Misha Brukman
a2700194ae Fit long lines into 80 cols via creative space elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16353 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-15 01:40:18 +00:00
Chris Lattner
b228657acc Revamp the Register class, and allow the use of the RegisterGroup class to 
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-14 04:17:02 +00:00
Misha Brukman
fb0796e82e Fix filename: Printer.cpp has become X86AsmPrinter.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16299 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-12 21:26:04 +00:00
Alkis Evlogimenos
93c1ab2e15 Use a shorter form to express implicit use/defs in FpGETRESULT and 
FpSETRESULT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16247 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-08 18:29:31 +00:00
Alkis Evlogimenos
978f629ba9 A call instruction should implicitely define ST0 since the return 
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16246 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-08 16:54:54 +00:00
Reid Spencer
551ccae044 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-01 22:55:40 +00:00
Reid Spencer
fc989e1ee0 Reduce the number of arguments in the instruction builder and make some 
improvements on instruction selection that account for register and frame
index bases.

Patch contributed by Jeff Cohen. Thanks Jeff!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16110 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-30 00:13:26 +00:00
Chris Lattner
6f0161aac3 Add -sse[,2,3] arguments to LLC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16018 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-24 08:18:44 +00:00
Chris Lattner
47d2f2bb50 Nuke commented out stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16017 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-24 08:18:27 +00:00
Chris Lattner
ff0a6e6aac Switch from bytes to bits for alignment for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15974 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 20:14:13 +00:00
Chris Lattner
fae896999c Reduce uses of getRegClass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15973 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 20:13:52 +00:00
Chris Lattner
f746a7d09b Rename var 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15897 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-18 02:22:55 +00:00
Chris Lattner
c6393f82bf Start using alignment output routines from AsmPrinter. 
Changes to make this more similar to the ppc asmprinter


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15890 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-17 19:25:42 +00:00
Chris Lattner
8581ee85b4 Use the AsmPrinter emitGlobalConstant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15872 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-17 06:48:55 +00:00
Chris Lattner
055acae18c Start using the AsmPrinter to emit our first class constants. This also 
drops our half-assed support for cygwin, which noone uses and doesn't work
anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15839 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-16 23:16:06 +00:00
Chris Lattner
f60b91cbe3 Disable the pattern isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15787 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 23:02:17 +00:00
Chris Lattner
01d0efba39 Code insertion methods now return void instead of an int. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15780 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 22:15:11 +00:00
Chris Lattner
57f1b67c34 These methods no longer take a TargetRegisterClass* operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15774 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 21:56:44 +00:00
Nate Begeman
f8be5e94aa Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15739 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 22:05:10 +00:00
Chris Lattner
c96bb817aa Remove a bunch of ad-hoc target-specific flags that were only used by the 
old asmprinter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15660 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 07:12:04 +00:00
Chris Lattner
8e61d82528 Remove a dead method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15659 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 07:07:14 +00:00
Chris Lattner
2a998bdc7c Finally, the entire instruction asmprinter is now generated from tblgen, woo! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15658 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 07:02:04 +00:00
Chris Lattner
e4ead0ce62 Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15657 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 06:59:12 +00:00
Chris Lattner
8198fcfc5d This file is long dead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15656 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 06:55:12 +00:00
Chris Lattner
9795b3a0e7 Scrunch memoperands, add a few more for floating point memops 
Eliminate the FPI*m classes, converting them to use FPI instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15655 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 06:50:10 +00:00
Chris Lattner
8549429a78 Move hacks up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15654 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 06:09:55 +00:00
Chris Lattner
0f38e6ccca Make FPI take asm string and operand list 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15653 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 05:54:16 +00:00
Chris Lattner
f5d3a83f65 Nuke the Im*i* patterns, by asmprintergenifying all users. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15652 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 05:31:07 +00:00
Chris Lattner
f29ed0937f X86 instructions that read-modify-write memory are not LLVM two-address instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15651 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 05:07:25 +00:00
Chris Lattner
57a02306c5 Get rid of the Im8, Im16, Im32 classes, converting more instructions over to 
asmprintergeneration


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15650 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 04:31:00 +00:00
Chris Lattner
916f96ace0 Remove dead method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15647 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 02:26:39 +00:00
Chris Lattner
66fa1dcf90 Convert asmprinter to new style of instruction printer 
Start asmprintergen'ifying machine instrs with memory operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15646 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 02:25:00 +00:00
Chris Lattner
36b689009d This is purely a formatting patch that gets us closer to the mecca of fitting 
X86InstrInfo.td into 80 columns


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15629 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 21:21:30 +00:00
Chris Lattner
1b9e20e32f Drop the first argument of FPI, and asmprinterify fxch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15628 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 21:02:13 +00:00
Chris Lattner
30bf2d8951 This purely mechanical patch gives the "I" tblgen class operand list and asm 
string operands, and adjusts all users to pass them in instead of using II.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15624 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 20:17:41 +00:00
Chris Lattner
869f477f34 Convert Ii32 instructions over to use the asmprinter generator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15621 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 19:06:36 +00:00
Chris Lattner
7d620d57a4 Convert the Ii16 instructions over 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15606 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 16:22:02 +00:00
Chris Lattner
ab67067186 Convert all Ii8 instructions over to the autogenerated asmprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15605 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 16:09:54 +00:00
Alkis Evlogimenos
15876bb28c Stop using getValues(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15487 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-04 08:44:43 +00:00
Chris Lattner
bcdda01210 Fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15409 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 19:31:30 +00:00
Chris Lattner
fc752713d7 Convert all I<> instructions to asmformat. 
Delete the 'name' field of all instructions that have asmformats.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15403 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 09:52:59 +00:00
Chris Lattner
a35ce87e2e Eliminate 3 of the X86 printImplicit* flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15398 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 08:23:17 +00:00
Chris Lattner
1626c507e8 Get rid of 3 of the 4 'printimplicit' flags. Implicit operands are now 
explicitly listed in the asm string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15397 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 08:22:29 +00:00
Chris Lattner
0e967d4f48 Convert more instructions over to the asmprinter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15396 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 08:13:11 +00:00
Chris Lattner
25369cfa2b Handle registers a bit more efficiently 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15395 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 08:12:41 +00:00
Chris Lattner
068758e518 give FP stack registers names 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15394 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 08:12:13 +00:00
Chris Lattner
ffff70827c Switch more instructions over to using the asmprinter. Fix bugs in the emission 
of in/out instructions (missing %'s on registers).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15393 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 07:44:35 +00:00
Chris Lattner
b12ee503f7 The tblgen'erated asmparser wants a way to print operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15392 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 07:43:46 +00:00
Chris Lattner
3fa861ac6c Rename the Printer class -> X86AsmPrinter. 
Include the tablegenerated assembly writer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15389 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 06:02:08 +00:00
Chris Lattner
8f945d7756 Factor a bunch of the rules and add support for generating the asmwriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 06:01:32 +00:00
Chris Lattner
96563df090 Specify an asm string and operands lists for a bunch of instructions. 
This only really covers no-operand instructions so far.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15387 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 06:01:00 +00:00
Chris Lattner
1ab7c5b5e8 Completely disable the pattern isel until it is more substantial. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15380 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 03:28:02 +00:00
Chris Lattner
4ad25e432d Entirely eliminate all patterns and expanders from this file. We shall go 
with an incremental approach rather than a revolutionary approach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15379 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 03:25:01 +00:00
Chris Lattner
bb737edcc3 Remove obsolete file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15377 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-01 03:19:28 +00:00
Alkis Evlogimenos
31e155e610 Align breaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15371 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-31 10:05:44 +00:00
Chris Lattner
167cf33e1d Add breaks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15365 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-31 09:53:31 +00:00
Alkis Evlogimenos
6103c1703c Simplify code a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15364 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-31 09:44:32 +00:00
Alkis Evlogimenos
02a453074d Correctly spell 'unconditional'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15363 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-31 09:41:44 +00:00
Alkis Evlogimenos
36f506eddb Implement insertGoto and reverseBranchCondition for the X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15362 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-31 09:38:47 +00:00
Chris Lattner
62cce39515 Mark barrier instructions. Execution does not fall through uncond branches 
or return intructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15356 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-31 02:10:53 +00:00
Misha Brukman
8606aea117 Fix indentation: should be 2 spaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15240 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-26 18:48:58 +00:00
Misha Brukman
91b5ca838a Fix file header as it has been renamed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15239 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-26 18:45:48 +00:00
Misha Brukman
c6d398abbb Renamed files to have the `X86' prefix for uniqueness purposes. 
All CVS history was renamed, the *,v were copied over.  No worries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15238 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-26 18:43:11 +00:00
Chris Lattner
cc46c4fcee Remove some (LARGE) abandoned code for the release. If this is ever needed 
again in the future, it can be resurrected out of CVS


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15112 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-22 21:30:35 +00:00
Chris Lattner
3dbb504081 Fix cases where we generated horrible code like this: 
mov %EDI, 12
        add %EDI, %ECX
        mov %ECX, 12
        add %ECX, %EDX
        mov %EDX, 12
        add %EDX, %ESI

instead (really!) generate this:

        add %ECX, 12
        add %EDX, 12
        add %ESI, 12


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15090 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-21 21:28:26 +00:00
Chris Lattner
4771288fe3 While I'm at it, don't break codegen of mul by 3,5,9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15013 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-19 23:50:57 +00:00
Chris Lattner
596b97f1ab Generate better code for multiplies by negative constants like -4, -1, -9, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15012 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-19 23:47:21 +00:00
Reid Spencer
8863f1814b bug 122: 
- Replace ConstantPointerRef usage with GlobalValue usage
- Minimize redundant isa<GlobalValue> usage
- Correct isa<Constant> for GlobalValue subclass


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14950 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-18 00:38:32 +00:00
Chris Lattner
42df461c90 Make sure to emit the immediate byte for instructions like: 
shrd [mem], reg, imm

This fixes the jit-ls failure on 186.crafty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14914 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-17 20:26:14 +00:00
Chris Lattner
3b5e6e5f84 Reserve the correct amt of space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14913 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-17 20:24:05 +00:00
Chris Lattner
76e2df2645 Patches towards fixing PR341 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14841 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-15 02:14:30 +00:00
Chris Lattner
d2995df5b7 Improve codegen for the LLVM offsetof/sizeof "operator". Before we compiled 
this LLVM function:

int %foo() {
        ret int cast (int** getelementptr (int** null, int 1) to int)
}

into:

foo:
        mov %EAX, 0
        lea %EAX, DWORD PTR [%EAX + 4]
        ret

now we compile it into:

foo:
        mov %EAX, 4
        ret

This sequence is frequently generated by the MSIL front-end, and soon the malloc lowering pass and
Java front-ends as well..

-Chris


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14834 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-15 00:58:53 +00:00
Chris Lattner
0cf0c37469 Delete the allocate*TargetMachine function, which is now dead . 
The shared command line options are now in a header that makes sense.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14756 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-11 04:17:10 +00:00
Chris Lattner
71d24aab2d Make these format a bit nicer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14747 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-11 03:27:42 +00:00
Chris Lattner
d36c970a11 Auto-registrate target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14745 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-11 02:48:49 +00:00
Reid Spencer
954da37bb4 Add #include <iostream> since Value.h does not #include it any more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14622 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-04 12:19:56 +00:00
Chris Lattner
9a9ca0f06b Remove dead blocks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14564 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-02 05:46:41 +00:00
Misha Brukman
c1f901c589 Fix associativity of parameters to assert(): now it actually makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14483 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-29 19:43:20 +00:00
Misha Brukman
e8d8fb26a6 Convert tabs to spaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14482 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-29 19:28:53 +00:00
Chris Lattner
23a53aa9c4 I believe that the code generator now properly handles dead basic blocks. If not, 
this is a bug, and should be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14476 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-29 07:17:12 +00:00
Chris Lattner
8b486a114e Fix a regression from r1.224. In particular, codegen a cast from double -> 
float as a truncation by going through memory.  This truncation was being
skipped, which caused 175.vpr to fail after aggressive register promotion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14473 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-29 00:14:38 +00:00
Tanya Lattner
b140762a45 Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14389 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-25 00:13:11 +00:00
Misha Brukman
66d6ee4247 Spell out `NoFramePointerElim' for readability. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14299 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-21 21:17:44 +00:00
Misha Brukman
83eaa0b567 Use the common `NoFPElim' setting instead of our own. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14298 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-21 21:10:24 +00:00
Chris Lattner
3048373748 Move the IntrinsicLowering header into the CodeGen directory, as per PR346 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14266 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-20 07:49:54 +00:00
Chris Lattner
667ea024b5 Codegen sub C, X a little bit better for register pressure. Instead of 
mov REG, C
sub REG, X

generate:

neg X
add X, C

which uses one less reg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14213 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-18 00:50:37 +00:00
Chris Lattner
a6f9fe6dbc Fold setcc instructions into select and branches that are not in the same BB as 
the setcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14212 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-18 00:29:22 +00:00
Chris Lattner
ccd9796a46 Do not fold loads into instructions if it is used more than once. In particular 
we do not want to fold the load in cases like this:

  X = load
    = add A, X
    = add B, X


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14204 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-17 22:15:25 +00:00
Chris Lattner
f70c22b019 Rename Type::PrimitiveID to TypeId and ::getPrimitiveID() to ::getTypeID() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14201 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-17 18:19:28 +00:00
Chris Lattner
4adf066f99 Remove support for llvm.isnan. Alkis wins :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14189 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-15 21:48:07 +00:00
Chris Lattner
dc5724478e Add basic support for the isunordered intrinsic. The isnan stuff still needs to go 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14185 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-15 21:36:44 +00:00
Chris Lattner
01cdb1b367 By far, one of the most common uses of isnan is to make 'isunordered' 
comparisons.  In an 'isunordered' predicate, which looks like this at
the LLVM level:

        %a = call bool %llvm.isnan(double %X)
        %b = call bool %llvm.isnan(double %Y)
        %COM = or bool %a, %b

We used to generate this code:

        fxch %ST(1)
        fucomip %ST(0), %ST(0)
        setp %AL
        fucomip %ST(0), %ST(0)
        setp %AH
        or %AL, %AH

With this patch, we generate this code:

        fucomip %ST(0), %ST(1)
        fstp %ST(0)
        setp %AL

Which should make alkis happy.  Tested as X86/compare_folding.llx:test1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14148 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 05:33:49 +00:00
Chris Lattner
57790422ca Fix bug in previous checkin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14146 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 05:22:44 +00:00
Chris Lattner
899dbdcdb0 No really, these are dead now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14145 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 04:50:14 +00:00
Chris Lattner
0ca2c8e02c Now that compare instructions aren't lumped in with the other twoargfp instructions, 
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14144 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 04:49:02 +00:00
Chris Lattner
ab8deccb82 Introduce a new FP instruction type to separate the compare cases from the 
twoarg cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14143 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 04:41:24 +00:00
Chris Lattner
b4fe76cbb5 Add direct support for the isnan intrinsic, implementing test/Regression/CodeGen/X86/isnan.llx 
testcase


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14141 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 04:31:10 +00:00
Chris Lattner
665e661384 Add support for the setp instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14140 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 04:30:06 +00:00
Chris Lattner
d62d5d7e5b Split compare instruction handling OUT of handleTwoArgFP into handleCompareFP. 
This makes the code much simpler, and the two cases really do belong apart.
Once we do it, it's pretty obvious how flawed the logic was for A != A case,
so I fixed it (fixing PR369).

This also uses freeStackSlotAfter instead of inserting an fxchg then
popStackAfter'ing in the case where there is a dead result (unlikely, but
possible), producing better code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14139 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-11 04:25:06 +00:00
Chris Lattner
32305f7763 Fix the fixed stack offset, patch contributed by Vladimir Prus 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14110 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-10 06:19:25 +00:00
John Criswell
6b5bd5857d Fix for PR#366. We use getClassB() so that we can handle cast instructions 
that cast to bool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14096 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-09 15:18:51 +00:00
Chris Lattner
994d7ae649 This file is obsolete 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14005 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-04 00:15:21 +00:00
Chris Lattner
d029cd2d5a Convert to the new TargetMachine interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13952 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-02 05:55:25 +00:00
Chris Lattner
99c59e8e21 Add support for accurate garbage collection to the LLVM code generators 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13696 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-23 21:23:35 +00:00
Chris Lattner
df04097f87 Add some notes to myself, no functional changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13695 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-23 21:23:12 +00:00
Chris Lattner
bbdbf30238 minor wording change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13694 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-23 21:22:55 +00:00
Brian Gaeke
09015d9468 Don't keep track of references to LLVM BasicBlocks while emitting; use 
MachineBasicBlocks instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13568 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-14 06:54:58 +00:00
Brian Gaeke
3fb5d1a6cc Support MachineBasicBlock operands on RawFrm instructions. 
Get rid of separate numbering for LLVM BasicBlocks; use the automatically
generated MachineBasicBlock numbering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13567 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-14 06:54:57 +00:00
Brian Gaeke
9f088e481c Generate branch machine instructions with MachineBasicBlock operands instead of 
LLVM BasicBlock operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13566 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-14 06:54:56 +00:00
Chris Lattner
b7cb9ffd34 Two more improvements for null pointer handling: storing a null pointer 
and passing a null pointer into a function.

For this testcase:

void %test(int** %X) {
  store int* null, int** %X
  call void %test(int** null)
  ret void
}

we now generate this:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov DWORD PTR [%EAX], 0
        mov DWORD PTR [%ESP], 0
        call test
        add %ESP, 12
        ret

instead of this:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, 0
        mov DWORD PTR [%EAX], %ECX
        mov %EAX, 0
        mov DWORD PTR [%ESP], %EAX
        call test
        add %ESP, 12
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13558 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-13 15:26:48 +00:00
Chris Lattner
9f1b531090 Second half of my fixed-sized-alloca patch. This folds the LEA to compute 
the alloca address into common operations like loads/stores.

In a simple testcase like this (which is just designed to excersize the
alloca A, nothing more):

int %test(int %X, bool %C) {
        %A = alloca int
        store int %X, int* %A
        store int* %A, int** %G
        br bool %C, label %T, label %F
T:
        call int %test(int 1, bool false)
        %V = load int* %A
        ret int %V
F:
        call int %test(int 123, bool true)
        %V2 = load int* %A
        ret int %V2
}

We now generate:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %CL, BYTE PTR [%ESP + 20]
***     mov DWORD PTR [%ESP + 8], %EAX
        mov %EAX, OFFSET G
        lea %EDX, DWORD PTR [%ESP + 8]
        mov DWORD PTR [%EAX], %EDX
        test %CL, %CL
        je .LBB2 # PC rel: F
.LBB1:  # T
        mov DWORD PTR [%ESP], 1
        mov DWORD PTR [%ESP + 4], 0
        call test
***     mov %EAX, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret
.LBB2:  # F
        mov DWORD PTR [%ESP], 123
        mov DWORD PTR [%ESP + 4], 1
        call test
***     mov %EAX, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret

Instead of:

test:
        sub %ESP, 20
        mov %EAX, DWORD PTR [%ESP + 24]
        mov %CL, BYTE PTR [%ESP + 28]
***     lea %EDX, DWORD PTR [%ESP + 16]
***     mov DWORD PTR [%EDX], %EAX
        mov %EAX, OFFSET G
        mov DWORD PTR [%EAX], %EDX
        test %CL, %CL
***     mov DWORD PTR [%ESP + 12], %EDX
        je .LBB2 # PC rel: F
.LBB1:  # T
        mov DWORD PTR [%ESP], 1
        mov %EAX, 0
        mov DWORD PTR [%ESP + 4], %EAX
        call test
***     mov %EAX, DWORD PTR [%ESP + 12]
***     mov %EAX, DWORD PTR [%EAX]
        add %ESP, 20
        ret
.LBB2:  # F
        mov DWORD PTR [%ESP], 123
        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX
        call test
***     mov %EAX, DWORD PTR [%ESP + 12]
***     mov %EAX, DWORD PTR [%EAX]
        add %ESP, 20
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13557 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-13 15:12:43 +00:00
Chris Lattner
cb2fd557ee Substantially improve code generation for address exposed locals (aka fixed 
sized allocas in the entry block).  Instead of generating code like this:

entry:
  reg1024 = ESP+1234
... (much later)
  *reg1024 = 17


Generate code that looks like this:
entry:
  (no code generated)
... (much later)
  t = ESP+1234
  *t = 17

The advantage being that we DRAMATICALLY reduce the register pressure for these
silly temporaries (they were all being spilled to the stack, resulting in very
silly code).  This is actually a manual implementation of rematerialization :)

I have a patch to fold the alloca address computation into loads & stores, which
will make this much better still, but just getting this right took way too much time
and I'm sleepy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13554 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-13 07:40:27 +00:00
Chris Lattner
2b10b08ad6 Pass boolean constants into function calls more efficiently, generating: 
mov DWORD PTR [%ESP + 4], 1

instead of:

        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13494 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-12 16:35:04 +00:00
Chris Lattner
c81e6bae88 Fix a fairly serious pessimizaion that was preventing us from efficiently 
compiling things like 'add long %X, 1'.  The problem is that we were switching
the order of the operands for longs even though we can't fold them yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13451 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-10 15:15:55 +00:00
Chris Lattner
9984fd0df9 Fix some comments, avoid sign extending booleans when zero extend works fine 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13440 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-09 23:16:33 +00:00
Chris Lattner
96e3b426d5 Generate more efficient code for casting booleans to integers (no sign extension required) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13439 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-09 22:28:45 +00:00
Chris Lattner
e7a31c98db Codegen floating point stores of constants into integer instructions. This 
allows us to compile:

store float 10.0, float* %P

into:
        mov DWORD PTR [%EAX], 1092616192

instead of:

.CPItest_0:                                     # float 0x4024000000000000
.long   1092616192      # float 10
...
        fld DWORD PTR [.CPItest_0]
        fstp DWORD PTR [%EAX]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13409 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-07 21:18:15 +00:00
Chris Lattner
260195d2b1 Make comparisons against the null pointer as efficient as integer comparisons 
against zero.  In particular, don't emit:

        mov %ESI, 0
        cmp %ECX, %ESI

instead, emit:

       test %ECX, %ECX


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13407 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-07 19:55:55 +00:00
Chris Lattner
bbc130d110 Remove unneeded check 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13355 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-04 19:35:11 +00:00
Chris Lattner
c8af02c403 Improve signed division by power of 2 *dramatically* from this: 
div:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %ECX, 64
        mov %EAX, %EDX
        sar %EDX, 31
        idiv %ECX
        ret

to this:

div:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 5
        shr %ECX, 26
        mov %EDX, %EAX
        add %EDX, %ECX
        sar %EAX, 6
        ret

Note that the intel compiler is currently making this:

div:
        movl      4(%esp), %edx                                 #3.5
        movl      %edx, %eax                                    #4.14
        sarl      $5, %eax                                      #4.14
        shrl      $26, %eax                                     #4.14
        addl      %edx, %eax                                    #4.14
        sarl      $6, %eax                                      #4.14
        ret                                                     #4.14

Which has one less register->register copy.  (hint hint alkis :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13354 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-04 19:33:58 +00:00
Chris Lattner
9eb9b8ecb9 Improve code generated for integer multiplications by 2,3,5,9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13342 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-04 15:47:14 +00:00
Chris Lattner
77993632a1 Remove unused #include 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13304 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-01 21:29:16 +00:00
Chris Lattner
2268684f6f Iterate over the Machine CFG that Brian added instead of the LLVM CFG. 
Look at all of the pretty minuses. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13303 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-05-01 21:27:53 +00:00
Brian Gaeke
1afe7736ff Make RequiresFPRegKill() take a MachineBasicBlock arg. 
In InsertFPRegKills(), just check the MachineBasicBlock for successors
instead of its corresponding BasicBlock.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13213 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-28 04:45:55 +00:00
Brian Gaeke
235aa5eba7 In InsertFPRegKills(), use the machine-CFG itself rather than the 
LLVM CFG when trying to find the successors of BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13212 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-28 04:34:16 +00:00
Brian Gaeke
ea9ca67304 Update the machine-CFG edges whenever we see a branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13211 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-28 04:19:37 +00:00
Brian Gaeke
b61fc83ecb Use emitWordAt() to emit forward-branch fixups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13120 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-23 17:11:16 +00:00
John Criswell
53b54be5fc Remove code to adjust the iterator for llvm.readio and llvm.writeio. 
The iterator is pointing at the next instruction which should not disappear
when doing the load/store replacement.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12954 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-14 21:27:56 +00:00
Chris Lattner
098e945fbd This is the real fix for Codegen/X86/2004-04-13-FPCMOV-Crash.llx which works 
even when the "optimization" I added before is turned off.  It generates this
extremely pointless code:

test:
        fld QWORD PTR [%ESP + 4]
        mov %AL, 0
        test %AL, %AL
        fcmove %ST(0), %ST(0)
        ret

Good thing the optimizer will have removed this before code generation
anyway.  :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12939 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-14 02:42:32 +00:00
John Criswell
e5a4c15da6 Added support for the llvm.readio and llvm.writeio intrinsics. 
On x86, memory operations occur in-order, so these are just lowered into
volatile loads and stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12936 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-13 22:13:14 +00:00
Chris Lattner
82c5a9990f Implement a small optimization, which papers over the problem in 
X86/2004-04-13-FPCMOV-Crash.llx

A more robust fix is to follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12935 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-13 21:56:09 +00:00
Chris Lattner
87e18deabc Emit the immediate form of in/out when possible. 
Fix several bugs in the intrinsics:
  1. Make sure to copy the input registers before the instructions that use them
  2. Make sure to copy the value returned by 'in' out of EAX into the register
     it is supposed to be in.

This fixes assertions when using in/out and linear scan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12896 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-13 17:20:37 +00:00
Chris Lattner
440bbc257e Add immediate forms of in/out. Use let to shorten lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12895 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-13 17:19:31 +00:00
Chris Lattner
e47f4ff9f6 Add support for new instruction type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12894 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-13 17:18:51 +00:00
Chris Lattner
266538350a Add support for the printImplicitDefsBefore flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12893 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-13 17:18:39 +00:00
Chris Lattner
133dbb1285 Fix issues that the local allocator has dealing with instructions that implicitly use ST(0) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12855 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 03:02:48 +00:00
Chris Lattner
284b496aae No really, fix printing for LLC. I gotta get a way for CVS to whine at me if 
I have unsaved emacs buffers, geeze...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12854 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 01:52:04 +00:00
Chris Lattner
2fc83a5ba6 Correct printing for LLC and the encoding for the JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12853 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 01:50:04 +00:00
Chris Lattner
8d2822e7f1 Use the fucomi[p] instructions to perform floating point comparisons instead 
of the fucom[p][p] instructions.  This allows us to code generate this function

bool %test(double %X, double %Y) {
        %C = setlt double %Y, %X
        ret bool %C
}

... into:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucomip %ST(1)
        fstp %ST(0)
        setb %AL
        movsx %EAX, %AL
        ret

where before we generated:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucompp
**      fnstsw
**      sahf
        setb %AL
        movsx %EAX, %AL
        ret

The two marked instructions (which are the ones eliminated) are very bad,
because they serialize execution of the processor.  These instructions are
available on the PPRO and later, but since we already use cmov's we aren't
losing any portability.

I retained the old code for the day when we decide we want to support back
to the 386.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12852 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 01:43:36 +00:00
Chris Lattner
c040bca4b9 Add support for the FUCOMIr instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12851 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 01:39:15 +00:00
Chris Lattner
a1b5e160ed Add two new instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12850 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 01:38:55 +00:00
Chris Lattner
9938286325 Fix a bug in my load/cast folding patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12849 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 00:23:04 +00:00
Chris Lattner
13c07feb20 Adjust some comments, fix a bug in my previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12848 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-12 00:12:04 +00:00
Chris Lattner
feac3e18aa On X86, casting an integer to floating point requires going through memory. 
If the source of the cast is a load, we can just use the source memory location,
without having to create a temporary stack slot entry.

Before we code generated this:

double %int(int* %P) {
        %V = load int* %P
        %V2 = cast int %V to double
        ret double %V2
}

into:

int:
        sub %ESP, 4
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        mov DWORD PTR [%ESP], %EAX
        fild DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we produce this:

int:
        mov %EAX, DWORD PTR [%ESP + 4]
        fild DWORD PTR [%EAX]
        ret

... which is nicer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12846 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 23:21:26 +00:00
Chris Lattner
95157f7638 Implement folding of loads into floating point operations. This implements: 
test/Regression/CodeGen/X86/fp_load_fold.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12844 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 22:05:45 +00:00
Chris Lattner
6621ed94cc Unify all of the code for floating point +,-,*,/ into one function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12842 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 21:23:56 +00:00
Chris Lattner
8ebf1c35a1 This implements folding of constant operands into floating point operations 
for mul and div.

Instead of generating this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_divr_0]
        fdivrp %ST(1)
        ret

We now generate this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fdivr QWORD PTR [.CPItest_divr_0]
        ret

This code desperately needs refactoring, which will come in the next
patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12841 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 21:09:14 +00:00
Chris Lattner
462fa82270 Restructure the mul/div/rem handling code to follow the pattern the other 
instructions use.  This doesn't change any functionality except that long
constant expressions of these operations will now magically start working.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12840 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 20:56:28 +00:00
Chris Lattner
48b0c97e20 Codegen FP adds and subtracts with a constant more efficiently, generating: 
fld QWORD PTR [%ESP + 4]
        fadd QWORD PTR [.CPItest_add_0]

instead of:

        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_add_0]
        faddp %ST(1)

I also intend to do this for mul & div, but it appears that I have to
refactor a bit of code before I can do so.

This is tested by: test/Regression/CodeGen/X86/fp_constant_op.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12839 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 20:26:20 +00:00
Chris Lattner
490e86fed5 Add some new instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12838 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 20:24:15 +00:00
Chris Lattner
4cf15e7a3b Relax assertion to make this function work with a broader class of instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12836 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 20:21:06 +00:00
Chris Lattner
427aeb476f Two changes: 
1. If an incoming argument is dead, don't load it from the stack
  2. Do not code gen noop copies at all (ie, cast int -> uint), not even to
     a move.  This should reduce register pressure for allocators that are
     unable to coallesce away these copies in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12835 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-11 19:21:59 +00:00
Chris Lattner
85aa7097c2 Silence a spurious warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12815 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-10 18:32:01 +00:00
John Criswell
6d804f408a Reversed the order of the llvm.writeport() operands so that the value 
is listed first and the address is listed second.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12795 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-09 19:09:14 +00:00
John Criswell
aee0cf3fca Changed assertions to error messages. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12787 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-09 15:10:15 +00:00
John Criswell
ca6ea0f137 Changes recommended by Chris: 
InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12786 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-08 22:39:13 +00:00
John Criswell
4ffff9e2fa Added the llvm.readport and llvm.writeport intrinsics for x86. These do 
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12782 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-08 20:31:47 +00:00
Jakub Staszak
8ac0009979 file based off InstSelectSimple.cpp, slowly being replaced by generated code from the really simple X86 instruction selector tablegen backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12715 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 19:35:17 +00:00
Jakub Staszak
0a8fd30c1b Tablgen files for really simple instruction selector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 19:34:00 +00:00
Chris Lattner
7b92de1e7d Fix PR313: [x86] JIT miscompiles unsigned short to floating point 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12711 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 19:29:36 +00:00
Chris Lattner
43ab3a8f45 Fix incorrect encoding of some ADC and SBB instuctions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12710 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 19:20:32 +00:00
Chris Lattner
48c937e5c9 Fix a minor bug in previous checking 
Enable folding of long seteq/setne comparisons into branches and select instructions
Implement unfolded long relational comparisons against a constants a bit more efficiently

Folding comparisons changes code that looks like this:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

into code that looks like this:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        jne .LBB2 # PC rel: F

This speeds up 186.crafty by 6% with llc-ls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12702 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 17:34:50 +00:00
Chris Lattner
e80e637793 Improve codegen of long == and != comparisons against constants. Before, 
comparing a long against zero got us this:

        sub %ESP, 8
        mov DWORD PTR [%ESP + 4], %ESI
        mov DWORD PTR [%ESP], %EDI
        mov %EAX, DWORD PTR [%ESP + 12]
        mov %EDX, DWORD PTR [%ESP + 16]
        mov %ECX, 0
        mov %ESI, 0
        mov %EDI, %EAX
        xor %EDI, %ECX
        mov %ECX, %EDX
        xor %ECX, %ESI
        or %EDI, %ECX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

Now it gets us this:

        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12696 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 16:02:27 +00:00
Chris Lattner
6ab06d5d19 Handle various other important cases of multiplying a long constant immediate. For 
example, multiplying X*(1 + (1LL << 32)) now produces:

test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %ECX
        add %EDX, %ECX
        ret

[[[Note to Alkis: why isn't linear scan generating this code??  This might be a
 problem with your intervals being too conservative:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        add %EDX, %EAX
        ret

end note]]]

Whereas GCC produces this:

T:
        sub     %esp, 12
        mov     %edx, DWORD PTR [%esp+16]
        mov     DWORD PTR [%esp+8], %edi
        mov     %ecx, DWORD PTR [%esp+20]
        xor     %edi, %edi
        mov     DWORD PTR [%esp], %ebx
        mov     %ebx, %edi
        mov     %eax, %edx
        mov     DWORD PTR [%esp+4], %esi
        add     %ebx, %edx
        mov     %edi, DWORD PTR [%esp+8]
        lea     %edx, [%ecx+%ebx]
        mov     %esi, DWORD PTR [%esp+4]
        mov     %ebx, DWORD PTR [%esp]
        add     %esp, 12
        ret

I'm not sure example what GCC is smoking here, but it looks like it has just
confused itself with a bunch of stack slots or something.  The intel compiler
is better, but still not good:

T:
        movl      4(%esp), %edx                                 #2.11
        movl      8(%esp), %eax                                 #2.11
        lea       (%eax,%edx), %ecx                             #3.12
        movl      $1, %eax                                      #3.12
        mull      %edx                                          #3.12
        addl      %ecx, %edx                                    #3.12
        ret                                                     #3.12


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12693 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 04:55:43 +00:00
Chris Lattner
028adc422d Efficiently handle a long multiplication by a constant. For this testcase: 
long %test(long %X) {
        %Y = mul long %X, 123
        ret long %Y
}

we used to generate:

test:
        sub %ESP, 12
        mov DWORD PTR [%ESP + 8], %ESI
        mov DWORD PTR [%ESP + 4], %EDI
        mov DWORD PTR [%ESP], %EBX
        mov %ECX, DWORD PTR [%ESP + 16]
        mov %ESI, DWORD PTR [%ESP + 20]
        mov %EDI, 123
        mov %EBX, 0
        mov %EAX, %ECX
        mul %EDI
        imul %ESI, %EDI
        add %ESI, %EDX
        imul %ECX, %EBX
        add %ESI, %ECX
        mov %EDX, %ESI
        mov %EBX, DWORD PTR [%ESP]
        mov %EDI, DWORD PTR [%ESP + 4]
        mov %ESI, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret

Now we emit:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, 123
        mul %EDX
        imul %ECX, %ECX, 123
        add %ECX, %EDX
        mov %EDX, %ECX
        ret

Which, incidently, is substantially nicer than what GCC manages:
T:
        sub     %esp, 8
        mov     %eax, 123
        mov     DWORD PTR [%esp], %ebx
        mov     %ebx, DWORD PTR [%esp+16]
        mov     DWORD PTR [%esp+4], %esi
        mov     %esi, DWORD PTR [%esp+12]
        imul    %ecx, %ebx, 123
        mov     %ebx, DWORD PTR [%esp]
        mul     %esi
        mov     %esi, DWORD PTR [%esp+4]
        add     %esp, 8
        lea     %edx, [%ecx+%edx]
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12692 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 04:29:36 +00:00
Chris Lattner
722070e0ba Improve code generation of long shifts by 32. 
On this testcase:

long %test(long %X) {
        %Y = shr long %X, ubyte 32
        ret long %Y
}

instead of:
t:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        sar %EAX, 0
        mov %EDX, 0
        ret


we now emit:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EDX, 0
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12688 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 03:42:38 +00:00
Chris Lattner
0652167bea Bugfixes: inc/dec don't set the carry flag! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12687 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 03:36:57 +00:00
Chris Lattner
92900a65a3 Improve code for passing constant longs as arguments to function calls. 
For example, on this instruction:

        call void %test(long 1234)

Instead of this:
        mov %EAX, 1234
        mov %ECX, 0
        mov DWORD PTR [%ESP], %EAX
        mov DWORD PTR [%ESP + 4], %ECX
        call test

We now emit this:
        mov DWORD PTR [%ESP], 1234
        mov DWORD PTR [%ESP + 4], 0
        call test


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12686 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 03:23:00 +00:00
Chris Lattner
33f7fa317b Emit more efficient 64-bit operations when the RHS is a constant, and one 
of the words of the constant is zeros.  For example:
  Y = and long X, 1234

now generates:
  Yl = and Xl, 1234
  Yh = 0

instead of:
  Yl = and Xl, 1234
  Yh = and Xh, 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12685 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 03:15:53 +00:00
Chris Lattner
7ba92306db Fix typeo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12684 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 02:13:25 +00:00
Chris Lattner
ab1d0e0963 Add support for simple immediate handling to long instruction selection. 
This allows us to handle code like 'add long %X, 123456789012' more efficiently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12683 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 02:11:49 +00:00
Chris Lattner
ee98389808 The sbb instructions really ARE sbb's, not adc's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12682 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 02:02:11 +00:00
Chris Lattner
edd5e4957a Implement negation of longs efficiently. For this testcase: 
long %test(long %X) {
        %Y = sub long 0, %X
        ret long %Y
}

We used to generate:

test:
        sub %ESP, 4
        mov DWORD PTR [%ESP], %ESI
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %ESI, DWORD PTR [%ESP + 12]
        mov %EAX, 0
        mov %EDX, 0
        sub %EAX, %ECX
        sbb %EDX, %ESI
        mov %ESI, DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we generate:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        neg %EAX
        adc %EDX, 0
        neg %EDX
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12681 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 01:48:06 +00:00
Chris Lattner
502e36c3c9 Minor tweak to avoid an extra reg-reg copy that the register allocator has to eliminate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12680 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 01:25:33 +00:00
Chris Lattner
29bf0623e5 Two changes: 
* In promote32, if we can just promote a constant value, do so instead of
    promoting a constant dynamically.
  * In visitReturn inst, actually USE the promote32 argument that takes a
    Value*

The end result of this is that we now generate this:

test:
        mov %EAX, 0
        ret

instead of...

test:
        mov %AX, 0
        movzx %EAX, %AX
        ret

for:

ushort %test() {
        ret ushort 0
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12679 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-06 01:21:00 +00:00
Chris Lattner
28977af72a Support getelementptr instructions which use uint's to index into structure 
types and can have arbitrary 32- and 64-bit integer types indexing into
sequential types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12653 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-05 01:30:19 +00:00
Alkis Evlogimenos
bee8a094af Clean up code a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12615 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-02 18:11:32 +00:00
Alkis Evlogimenos
1a66731da8 Fix type in comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12611 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
13ce339442 Fix type in instruction builder instantiation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12610 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-02 15:51:03 +00:00
Alkis Evlogimenos
8b28b6d187 Add more ADC and SBB variants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12607 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-02 07:11:10 +00:00
Chris Lattner
0526f01fec Simplify code by using the more powerful BuildMI forms. 
Implement a small optimization.  In test/Regression/CodeGen/X86/select.ll,
we now generate this for foldSel3:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fstp %ST(1)
        ret

Instead of:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fxch %ST(1)
***     fstp %ST(0)
        ret

In practice, this only effects code size: performance should be basically
unaffected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12588 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-01 04:06:09 +00:00
Chris Lattner
f1ac50ec53 Wrap at 80 cols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12587 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-04-01 04:03:27 +00:00
Chris Lattner
68626c2b30 Generate slightly smaller code, "test R, R" instead of "cmp R, 0" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12579 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-31 22:22:36 +00:00
Chris Lattner
08bde1870a The X86 backend no longer needs the select lowering pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12578 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-31 22:03:46 +00:00
Chris Lattner
352eb48f8e Codegen FP select instructions into X86 conditional moves. Annoyingly enough 
the X86 does not support a full set of fp cmove instructions, so we can't always
fold the condition into the select.  :(  Yuck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12577 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-31 22:03:35 +00:00
Chris Lattner
c1bab32bc5 Add support for floating point conditional move instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12576 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-31 22:02:36 +00:00
Chris Lattner
30b2f72e7c Add support for FP cmoves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12575 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-31 22:02:21 +00:00
Chris Lattner
1c54a85447 Add FP conditional move instructions, which annoyingly have special properties 
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12574 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-31 22:02:13 +00:00
Chris Lattner
307ecbaddb Fold comparisons into select instructions, making much better code and 
using our broad selection of movcc instructions.  :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12560 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-30 22:39:09 +00:00
Chris Lattner
87d3bb5dfa Implement spill code folding for all of the conditional move instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12554 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-30 21:29:47 +00:00
Chris Lattner
12d96a0b4d Add direct support for integer select instructions, though we still don't support 
folding compares into the select yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12553 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-30 21:22:00 +00:00
Chris Lattner
a5cdab7101 Fix some serious bugs in the cmov descriptions, which didn't cause a problem because 
we never generated them

Make indentation a bit more consistent


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12549 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-30 20:18:02 +00:00
Chris Lattner
6f2ab04e91 Fix a fairly major performance problem. If a PHI node had a constant as 
an incoming value from a block, the selector would evaluate the constant
at the TOP of the block instead of at the end of the block.  This made the
live range for the constant span the entire block, increasing register
pressure needlessly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12542 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-30 19:10:12 +00:00
Chris Lattner
5abd61f6d9 Add the select lowering pass to get initial support for select instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12541 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-30 18:41:59 +00:00
Chris Lattner
ab18020cbd Malloc doesn't kill a load. This patch need not go into 1.2 though. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12500 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-18 17:01:26 +00:00
Chris Lattner
85c84e759e Fix a really nasty bug that was breaking ijpeg in LLC mode. We were incorrectly 
folding load instructions into other instructions across free instruction
boundaries.  Perhaps this will also fix the other strange failures?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12494 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-18 06:29:54 +00:00
Alkis Evlogimenos
63dd4ff809 Add LAHF instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12424 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
a1a7148c4d Another API change to MRegisterInfo::foldMemoryOperand. Instead of a 
MachineBasicBlock::iterator take a MachineInstr*.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12392 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-14 20:14:27 +00:00
Alkis Evlogimenos
39354c99a1 Change MRegisterInfo::foldMemoryOperand to return the folded 
instruction to make the API more flexible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12386 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-14 07:19:51 +00:00
Chris Lattner
5634b9f5e7 It helps if I save the file. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12357 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-13 00:24:52 +00:00
Chris Lattner
317201d773 Rename the intrinsic enum values for llvm.va_* from Intrinsic::va_* to 
Intrinsic::va*.  This avoid conflicting with macros in the stdlib.h file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12356 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-13 00:24:00 +00:00
Alkis Evlogimenos
a3f66842b2 Add support for a wider range of CMOV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12336 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-12 17:59:56 +00:00
Misha Brukman
db760d00c3 Fix compilation on Sparc: assert(0) => abort() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12289 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-11 19:08:24 +00:00
Alkis Evlogimenos
519f4e76b7 Check if printing of implicit uses is required for all types of shift 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12258 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-09 06:10:15 +00:00
Alkis Evlogimenos
cc2a2a530f Differentiate between extended precision floats (80-bit) and double precision floats (64-bit) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12254 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
0309066f6c Use newly added API to emit bytes for instructions that gas misassembles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12253 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-09 03:35:34 +00:00
Alkis Evlogimenos
39c2005b70 Add emitInstruction() API so that we can get the bytes of a simple instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12252 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-09 03:34:53 +00:00
Alkis Evlogimenos
f6e8156008 Constify things a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12251 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-09 03:30:12 +00:00
Chris Lattner
7dee5daf85 Implement folding explicit load instructions into binary operations. For a 
testcase like this:

int %test(int* %P, int %A) {
        %Pv = load int* %P
        %B = add int %A, %Pv
        ret int %B
}

We now generate:
test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        add %EAX, DWORD PTR [%ECX]
        ret

Instead of:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        add %EAX, %ECX
        ret

... saving one instruction, and often a register.  Note that there are a lot
of other instructions that could use this, but they aren't handled.  I'm not
really interested in adding them, but mul/div and all of the FP instructions
could be supported as well if someone wanted to add them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12204 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-08 01:58:35 +00:00
Chris Lattner
721d2d4a6e Rearrange and refactor some code. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12203 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-08 01:18:36 +00:00
Alkis Evlogimenos
13d362f310 Add memory operand version of conditional move. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12190 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-07 03:19:11 +00:00
Brian Gaeke
323819e4e1 make -print-machineinstrs work for both SparcV9 and X86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12122 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-04 19:16:23 +00:00
Alkis Evlogimenos
ce1e500e2f Add assertion for scale verification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12120 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-04 18:05:02 +00:00
Misha Brukman
538607fe45 Doxygenify some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12064 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-01 23:53:11 +00:00
Brian Gaeke
05b15fb075 TargetCacheInfo has been removed; its only uses were to propagate a constant 
(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12043 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-01 06:43:29 +00:00
Chris Lattner
21585221b6 Handle passing constant integers to functions much more efficiently. Instead 
of generating this code:

        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        call Y

we now generate:
        mov DWORD PTR [%ESP], 4
        mov DWORD PTR [%ESP + 4], 123
        call Y

Which hurts the eyes less.  :)

Considering that register pressure around call sites is already high (with all
of the callee clobber registers n stuff), this may help a lot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12028 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-01 02:42:43 +00:00
Chris Lattner
ce6096f49b Fix a minor code-quality issue. When passing 8 and 16-bit integer constants 
to function calls, we would emit dead code, like this:

int Y(int, short, double);
int X() {
  Y(4, 123, 4);
}

--- Old
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
***     mov %AX, 123
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Now we emit:
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Next up, eliminate the mov AX and movsx entirely!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12026 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-03-01 02:34:08 +00:00
Alkis Evlogimenos
96c9b8b496 Add instruction name description. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11998 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-02-29 18:44:03 +00:00
Alkis Evlogimenos
7f6124cfc2 Use correct template for SHLD and SHRD instructions so that the memory 
operand size is correctly specified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11997 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
9c22aeb0b2 Improve allocation order: 
1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11996 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-02-29 09:17:01 +00:00
Alkis Evlogimenos
8295f202d9 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-02-29 08:50:03 +00:00
Chris Lattner
ee352852e7 Eliminate the X86-specific BMI functions, using BuildMI instead. 
Replace uses of addZImm with addImm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11992 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-02-29 07:22:16 +00:00
Chris Lattner
168aa90bf6 Fix a miscompilation of 197.parser that occurs when you have single basic 
block loops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11990 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-02-29 07:10:16 +00:00