2005-01-07 07:47:53 +00:00
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//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
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2005-04-21 22:36:52 +00:00
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//
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2005-01-07 07:47:53 +00:00
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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2005-04-21 22:36:52 +00:00
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//
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2005-01-07 07:47:53 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This implements the SelectionDAGISel class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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2007-04-04 21:14:49 +00:00
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#include "llvm/ADT/BitVector.h"
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2006-10-16 20:52:31 +00:00
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#include "llvm/Analysis/AliasAnalysis.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2006-01-21 02:32:06 +00:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2007-04-04 21:14:49 +00:00
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#include "llvm/Constants.h"
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2005-05-13 18:50:42 +00:00
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#include "llvm/CallingConv.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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2005-11-29 06:21:05 +00:00
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#include "llvm/GlobalVariable.h"
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2006-01-26 22:24:51 +00:00
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#include "llvm/InlineAsm.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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2006-03-23 18:06:46 +00:00
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#include "llvm/IntrinsicInst.h"
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2007-04-09 06:17:21 +00:00
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#include "llvm/ParameterAttributes.h"
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2007-01-26 21:22:28 +00:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-04-22 18:53:45 +00:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2006-08-02 12:30:23 +00:00
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#include "llvm/CodeGen/SchedulerRegistry.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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2005-09-13 19:30:54 +00:00
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#include "llvm/Target/MRegisterInfo.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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2006-05-23 13:43:15 +00:00
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#include "llvm/Target/TargetOptions.h"
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2005-11-09 04:45:33 +00:00
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#include "llvm/Support/MathExtras.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Support/Debug.h"
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2006-08-27 12:54:02 +00:00
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#include "llvm/Support/Compiler.h"
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2006-02-24 02:52:40 +00:00
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#include <algorithm>
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2005-01-07 07:47:53 +00:00
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using namespace llvm;
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2005-09-01 18:44:10 +00:00
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#ifndef NDEBUG
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2005-01-12 03:41:21 +00:00
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static cl::opt<bool>
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2006-01-21 02:32:06 +00:00
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ViewISelDAGs("view-isel-dags", cl::Hidden,
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cl::desc("Pop up a window to show isel dags as they are selected"));
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static cl::opt<bool>
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ViewSchedDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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2005-01-12 03:41:21 +00:00
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#else
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2006-04-02 03:07:27 +00:00
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static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
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2005-01-12 03:41:21 +00:00
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#endif
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2006-08-02 12:30:23 +00:00
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//===---------------------------------------------------------------------===//
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///
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/// RegisterScheduler class - Track the registration of instruction schedulers.
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///
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//===---------------------------------------------------------------------===//
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MachinePassRegistry RegisterScheduler::Registry;
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//===---------------------------------------------------------------------===//
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///
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/// ISHeuristic command line option for instruction schedulers.
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///
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//===---------------------------------------------------------------------===//
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2006-01-23 07:01:07 +00:00
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namespace {
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2006-08-02 12:30:23 +00:00
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cl::opt<RegisterScheduler::FunctionPassCtor, false,
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RegisterPassParser<RegisterScheduler> >
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2006-08-01 14:21:23 +00:00
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ISHeuristic("sched",
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2006-08-03 00:18:59 +00:00
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cl::init(&createDefaultScheduler),
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2006-08-01 14:21:23 +00:00
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cl::desc("Instruction schedulers available:"));
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2006-08-01 18:29:48 +00:00
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static RegisterScheduler
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2006-08-01 19:14:14 +00:00
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defaultListDAGScheduler("default", " Best scheduler for the target",
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createDefaultScheduler);
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2006-01-23 07:01:07 +00:00
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} // namespace
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2006-02-22 22:37:12 +00:00
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namespace {
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/// RegsForValue - This struct represents the physical registers that a
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/// particular value is assigned and the type information about the value.
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/// This is needed because values can be promoted into larger registers and
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/// expanded into multiple smaller registers than the value.
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2006-06-28 23:17:24 +00:00
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struct VISIBILITY_HIDDEN RegsForValue {
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2006-02-22 22:37:12 +00:00
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/// Regs - This list hold the register (for legal and promoted values)
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/// or register set (for expanded values) that the value should be assigned
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/// to.
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std::vector<unsigned> Regs;
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/// RegVT - The value type of each register.
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///
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MVT::ValueType RegVT;
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/// ValueVT - The value type of the LLVM value, which may be promoted from
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/// RegVT or made from merging the two expanded parts.
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MVT::ValueType ValueVT;
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RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
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RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
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: RegVT(regvt), ValueVT(valuevt) {
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Regs.push_back(Reg);
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}
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RegsForValue(const std::vector<unsigned> ®s,
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MVT::ValueType regvt, MVT::ValueType valuevt)
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: Regs(regs), RegVT(regvt), ValueVT(valuevt) {
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}
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/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
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/// this value and returns the result as a ValueVT value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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SDOperand getCopyFromRegs(SelectionDAG &DAG,
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2006-02-23 20:06:57 +00:00
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SDOperand &Chain, SDOperand &Flag) const;
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2006-02-23 19:21:04 +00:00
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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2006-06-15 08:11:54 +00:00
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SDOperand &Chain, SDOperand &Flag,
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MVT::ValueType PtrVT) const;
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2006-02-23 19:21:04 +00:00
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker and includes the number of
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/// values added into it.
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void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
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2006-02-23 20:06:57 +00:00
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std::vector<SDOperand> &Ops) const;
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2006-02-22 22:37:12 +00:00
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};
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}
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2006-01-23 07:01:07 +00:00
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2005-01-07 07:47:53 +00:00
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namespace llvm {
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2006-08-01 19:14:14 +00:00
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//===--------------------------------------------------------------------===//
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB) {
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TargetLowering &TLI = IS->getTargetLowering();
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
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return createTDListDAGScheduler(IS, DAG, BB);
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} else {
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assert(TLI.getSchedulingPreference() ==
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TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
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return createBURRListDAGScheduler(IS, DAG, BB);
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}
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}
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2005-01-07 07:47:53 +00:00
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//===--------------------------------------------------------------------===//
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/// FunctionLoweringInfo - This contains information that is global to a
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/// function that is used when lowering a region of the function.
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2005-01-08 19:52:31 +00:00
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class FunctionLoweringInfo {
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public:
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2005-01-07 07:47:53 +00:00
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TargetLowering &TLI;
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Function &Fn;
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MachineFunction &MF;
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SSARegMap *RegMap;
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FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
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/// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
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std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
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/// ValueMap - Since we emit code for the function a basic block at a time,
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/// we must remember which virtual registers hold the values for
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/// cross-basic-block values.
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2007-02-04 01:35:11 +00:00
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DenseMap<const Value*, unsigned> ValueMap;
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2005-01-07 07:47:53 +00:00
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/// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
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/// the entry block. This allows the allocas to be efficiently referenced
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/// anywhere in the function.
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std::map<const AllocaInst*, int> StaticAllocaMap;
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unsigned MakeReg(MVT::ValueType VT) {
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return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
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}
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Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
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/// isExportedInst - Return true if the specified value is an instruction
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/// exported from its block.
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bool isExportedInst(const Value *V) {
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return ValueMap.count(V);
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}
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2005-04-21 22:36:52 +00:00
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2006-03-16 19:51:18 +00:00
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unsigned CreateRegForValue(const Value *V);
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2005-01-07 07:47:53 +00:00
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unsigned InitializeRegForValue(const Value *V) {
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unsigned &R = ValueMap[V];
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assert(R == 0 && "Already initialized this value register!");
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return R = CreateRegForValue(V);
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}
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};
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}
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/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
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2006-03-27 01:32:24 +00:00
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/// PHI nodes or outside of the basic block that defines it, or used by a
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/// switch instruction, which may expand to multiple basic blocks.
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2005-01-07 07:47:53 +00:00
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static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
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if (isa<PHINode>(I)) return true;
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BasicBlock *BB = I->getParent();
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for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
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2006-03-27 01:32:24 +00:00
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if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
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Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
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// FIXME: Remove switchinst special case.
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2006-03-27 01:32:24 +00:00
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isa<SwitchInst>(*UI))
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2005-01-07 07:47:53 +00:00
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return true;
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return false;
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}
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|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
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/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
|
2006-03-27 01:32:24 +00:00
|
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/// entry block, return true. This includes arguments used by switches, since
|
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/// the switch may expand into multiple basic blocks.
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
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static bool isOnlyUsedInEntryBlock(Argument *A) {
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BasicBlock *Entry = A->getParent()->begin();
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|
|
for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
|
2006-03-27 01:32:24 +00:00
|
|
|
if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
return false; // Use not in entry block.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
|
2005-04-21 22:36:52 +00:00
|
|
|
Function &fn, MachineFunction &mf)
|
2005-01-07 07:47:53 +00:00
|
|
|
: TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
|
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
// Create a vreg for each argument register that is not dead and is used
|
|
|
|
// outside of the entry block for the function.
|
2005-05-11 18:57:06 +00:00
|
|
|
for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
|
|
|
|
AI != E; ++AI)
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
if (!isOnlyUsedInEntryBlock(AI))
|
|
|
|
InitializeRegForValue(AI);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
// Initialize the mapping of values to registers. This is only set up for
|
|
|
|
// instruction values that are used outside of the block that defines
|
|
|
|
// them.
|
2005-10-01 03:57:14 +00:00
|
|
|
Function::iterator BB = Fn.begin(), EB = Fn.end();
|
2005-01-07 07:47:53 +00:00
|
|
|
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
|
|
|
|
if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
|
2006-10-20 07:07:24 +00:00
|
|
|
if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
|
2005-01-07 07:47:53 +00:00
|
|
|
const Type *Ty = AI->getAllocatedType();
|
2006-05-03 01:29:57 +00:00
|
|
|
uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
|
2005-11-06 09:00:38 +00:00
|
|
|
unsigned Align =
|
2007-02-14 05:52:17 +00:00
|
|
|
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
|
2005-11-06 09:00:38 +00:00
|
|
|
AI->getAlignment());
|
2005-05-13 23:14:17 +00:00
|
|
|
|
2006-10-20 07:07:24 +00:00
|
|
|
TySize *= CUI->getZExtValue(); // Get total allocated size.
|
2005-10-18 22:14:06 +00:00
|
|
|
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
|
2005-01-07 07:47:53 +00:00
|
|
|
StaticAllocaMap[AI] =
|
2005-01-08 19:52:31 +00:00
|
|
|
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-10-01 03:57:14 +00:00
|
|
|
for (; BB != EB; ++BB)
|
|
|
|
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
|
2005-01-07 07:47:53 +00:00
|
|
|
if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
|
|
|
|
if (!isa<AllocaInst>(I) ||
|
|
|
|
!StaticAllocaMap.count(cast<AllocaInst>(I)))
|
|
|
|
InitializeRegForValue(I);
|
|
|
|
|
|
|
|
// Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
|
|
|
|
// also creates the initial PHI MachineInstrs, though none of the input
|
|
|
|
// operands are populated.
|
2005-10-01 03:57:14 +00:00
|
|
|
for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
|
2005-01-07 07:47:53 +00:00
|
|
|
MachineBasicBlock *MBB = new MachineBasicBlock(BB);
|
|
|
|
MBBMap[BB] = MBB;
|
|
|
|
MF.getBasicBlockList().push_back(MBB);
|
|
|
|
|
|
|
|
// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
|
|
|
|
// appropriate.
|
|
|
|
PHINode *PN;
|
2006-10-27 23:50:33 +00:00
|
|
|
for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
|
|
|
|
if (PN->use_empty()) continue;
|
|
|
|
|
|
|
|
MVT::ValueType VT = TLI.getValueType(PN->getType());
|
|
|
|
unsigned NumElements;
|
|
|
|
if (VT != MVT::Vector)
|
|
|
|
NumElements = TLI.getNumElements(VT);
|
|
|
|
else {
|
|
|
|
MVT::ValueType VT1,VT2;
|
|
|
|
NumElements =
|
2007-02-15 02:26:10 +00:00
|
|
|
TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
|
2006-10-27 23:50:33 +00:00
|
|
|
VT1, VT2);
|
2005-01-07 21:34:19 +00:00
|
|
|
}
|
2006-10-27 23:50:33 +00:00
|
|
|
unsigned PHIReg = ValueMap[PN];
|
|
|
|
assert(PHIReg && "PHI node does not have an assigned virtual register!");
|
2006-11-27 23:37:22 +00:00
|
|
|
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
|
2006-10-27 23:50:33 +00:00
|
|
|
for (unsigned i = 0; i != NumElements; ++i)
|
2006-11-27 23:37:22 +00:00
|
|
|
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
|
2006-10-27 23:50:33 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-16 19:51:18 +00:00
|
|
|
/// CreateRegForValue - Allocate the appropriate number of virtual registers of
|
|
|
|
/// the correctly promoted or expanded types. Assign these registers
|
|
|
|
/// consecutive vreg numbers and return the first assigned number.
|
|
|
|
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
|
|
|
|
MVT::ValueType VT = TLI.getValueType(V->getType());
|
|
|
|
|
|
|
|
// The number of multiples of registers that we need, to, e.g., split up
|
|
|
|
// a <2 x int64> -> 4 x i32 registers.
|
|
|
|
unsigned NumVectorRegs = 1;
|
|
|
|
|
2007-02-15 03:39:18 +00:00
|
|
|
// If this is a vector type, figure out what type it will decompose into
|
2006-03-16 19:51:18 +00:00
|
|
|
// and how many of the elements it will use.
|
|
|
|
if (VT == MVT::Vector) {
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *PTy = cast<VectorType>(V->getType());
|
2006-03-16 19:51:18 +00:00
|
|
|
unsigned NumElts = PTy->getNumElements();
|
|
|
|
MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
|
|
|
|
|
|
|
|
// Divide the input until we get to a supported size. This will always
|
|
|
|
// end with a scalar if the target doesn't support vectors.
|
|
|
|
while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
|
|
|
|
NumElts >>= 1;
|
|
|
|
NumVectorRegs <<= 1;
|
|
|
|
}
|
2006-03-16 23:05:19 +00:00
|
|
|
if (NumElts == 1)
|
|
|
|
VT = EltTy;
|
|
|
|
else
|
|
|
|
VT = getVectorType(EltTy, NumElts);
|
2006-03-16 19:51:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// The common case is that we will only create one register for this
|
|
|
|
// value. If we have that case, create and return the virtual register.
|
|
|
|
unsigned NV = TLI.getNumElements(VT);
|
|
|
|
if (NV == 1) {
|
|
|
|
// If we are promoting this value, pick the next largest supported type.
|
|
|
|
MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
|
|
|
|
unsigned Reg = MakeReg(PromotedType);
|
|
|
|
// If this is a vector of supported or promoted types (e.g. 4 x i16),
|
|
|
|
// create all of the registers.
|
|
|
|
for (unsigned i = 1; i != NumVectorRegs; ++i)
|
|
|
|
MakeReg(PromotedType);
|
|
|
|
return Reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this value is represented with multiple target registers, make sure
|
|
|
|
// to create enough consecutive registers of the right (smaller) type.
|
2006-12-13 20:57:08 +00:00
|
|
|
VT = TLI.getTypeToExpandTo(VT);
|
|
|
|
unsigned R = MakeReg(VT);
|
2006-03-16 19:51:18 +00:00
|
|
|
for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
|
2006-12-13 20:57:08 +00:00
|
|
|
MakeReg(VT);
|
2006-03-16 19:51:18 +00:00
|
|
|
return R;
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// SelectionDAGLowering - This is the common target-independent lowering
|
|
|
|
/// implementation that is parameterized by a TargetLowering object.
|
|
|
|
/// Also, targets can overload any lowering method.
|
|
|
|
///
|
|
|
|
namespace llvm {
|
|
|
|
class SelectionDAGLowering {
|
|
|
|
MachineBasicBlock *CurMBB;
|
|
|
|
|
2007-02-04 01:31:47 +00:00
|
|
|
DenseMap<const Value*, SDOperand> NodeMap;
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2005-01-17 22:19:26 +00:00
|
|
|
/// PendingLoads - Loads are not emitted to the program immediately. We bunch
|
|
|
|
/// them up and then emit token factor nodes when possible. This allows us to
|
|
|
|
/// get simple disambiguation between loads without worrying about alias
|
|
|
|
/// analysis.
|
|
|
|
std::vector<SDOperand> PendingLoads;
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
/// Case - A struct to record the Value for a switch case, and the
|
|
|
|
/// case's target basic block.
|
|
|
|
struct Case {
|
|
|
|
Constant* Low;
|
|
|
|
Constant* High;
|
|
|
|
MachineBasicBlock* BB;
|
|
|
|
|
|
|
|
Case() : Low(0), High(0), BB(0) { }
|
|
|
|
Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
|
|
|
|
Low(low), High(high), BB(bb) { }
|
|
|
|
uint64_t size() const {
|
|
|
|
uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
|
|
|
|
uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
|
|
|
|
return (rHigh - rLow + 1ULL);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2007-04-09 12:31:58 +00:00
|
|
|
struct CaseBits {
|
|
|
|
uint64_t Mask;
|
|
|
|
MachineBasicBlock* BB;
|
|
|
|
unsigned Bits;
|
|
|
|
|
|
|
|
CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
|
|
|
|
Mask(mask), BB(bb), Bits(bits) { }
|
|
|
|
};
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
typedef std::vector<Case> CaseVector;
|
2007-04-09 12:31:58 +00:00
|
|
|
typedef std::vector<CaseBits> CaseBitsVector;
|
2007-04-04 21:14:49 +00:00
|
|
|
typedef CaseVector::iterator CaseItr;
|
|
|
|
typedef std::pair<CaseItr, CaseItr> CaseRange;
|
2006-03-27 01:32:24 +00:00
|
|
|
|
|
|
|
/// CaseRec - A struct with ctor used in lowering switches to a binary tree
|
|
|
|
/// of conditional branches.
|
|
|
|
struct CaseRec {
|
|
|
|
CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
|
|
|
|
CaseBB(bb), LT(lt), GE(ge), Range(r) {}
|
|
|
|
|
|
|
|
/// CaseBB - The MBB in which to emit the compare and branch
|
|
|
|
MachineBasicBlock *CaseBB;
|
|
|
|
/// LT, GE - If nonzero, we know the current case value must be less-than or
|
|
|
|
/// greater-than-or-equal-to these Constants.
|
|
|
|
Constant *LT;
|
|
|
|
Constant *GE;
|
|
|
|
/// Range - A pair of iterators representing the range of case values to be
|
|
|
|
/// processed at this point in the binary search tree.
|
|
|
|
CaseRange Range;
|
|
|
|
};
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
typedef std::vector<CaseRec> CaseRecVector;
|
2007-04-04 21:14:49 +00:00
|
|
|
|
|
|
|
/// The comparison function for sorting the switch case values in the vector.
|
|
|
|
/// WARNING: Case ranges should be disjoint!
|
2006-03-27 01:32:24 +00:00
|
|
|
struct CaseCmp {
|
2007-04-09 12:31:58 +00:00
|
|
|
bool operator () (const Case& C1, const Case& C2) {
|
2007-04-04 21:14:49 +00:00
|
|
|
assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
|
|
|
|
const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
|
|
|
|
const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
|
|
|
|
return CI1->getValue().slt(CI2->getValue());
|
2006-03-27 01:32:24 +00:00
|
|
|
}
|
|
|
|
};
|
2007-04-04 21:14:49 +00:00
|
|
|
|
2007-04-09 12:31:58 +00:00
|
|
|
struct CaseBitsCmp {
|
|
|
|
bool operator () (const CaseBits& C1, const CaseBits& C2) {
|
|
|
|
return C1.Bits > C2.Bits;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
public:
|
|
|
|
// TLI - This is information that describes the available target features we
|
|
|
|
// need for lowering. This indicates when operations are unavailable,
|
|
|
|
// implemented with a libcall, etc.
|
|
|
|
TargetLowering &TLI;
|
|
|
|
SelectionDAG &DAG;
|
2006-05-03 01:29:57 +00:00
|
|
|
const TargetData *TD;
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
/// SwitchCases - Vector of CaseBlock structures used to communicate
|
|
|
|
/// SwitchInst code generation information.
|
|
|
|
std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
|
2007-03-25 15:07:15 +00:00
|
|
|
/// JTCases - Vector of JumpTable structures used to communicate
|
|
|
|
/// SwitchInst code generation information.
|
|
|
|
std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
|
2007-04-09 12:31:58 +00:00
|
|
|
std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
/// FuncInfo - Information about the function as a whole.
|
|
|
|
///
|
|
|
|
FunctionLoweringInfo &FuncInfo;
|
|
|
|
|
|
|
|
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
|
2005-04-21 22:36:52 +00:00
|
|
|
FunctionLoweringInfo &funcinfo)
|
2005-01-07 07:47:53 +00:00
|
|
|
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
|
2007-03-25 15:07:15 +00:00
|
|
|
FuncInfo(funcinfo) {
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-01-17 19:43:36 +00:00
|
|
|
/// getRoot - Return the current virtual root of the Selection DAG.
|
|
|
|
///
|
|
|
|
SDOperand getRoot() {
|
2005-01-17 22:19:26 +00:00
|
|
|
if (PendingLoads.empty())
|
|
|
|
return DAG.getRoot();
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-17 22:19:26 +00:00
|
|
|
if (PendingLoads.size() == 1) {
|
|
|
|
SDOperand Root = PendingLoads[0];
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
PendingLoads.clear();
|
|
|
|
return Root;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we have to make a token factor node.
|
2006-08-08 02:23:42 +00:00
|
|
|
SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&PendingLoads[0], PendingLoads.size());
|
2005-01-17 22:19:26 +00:00
|
|
|
PendingLoads.clear();
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
return Root;
|
2005-01-17 19:43:36 +00:00
|
|
|
}
|
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void visit(Instruction &I) { visit(I.getOpcode(), I); }
|
|
|
|
|
|
|
|
void visit(unsigned Opcode, User &I) {
|
2006-11-10 04:41:34 +00:00
|
|
|
// Note: this doesn't use InstVisitor, because it has to work with
|
|
|
|
// ConstantExpr's in addition to instructions.
|
2005-01-07 07:47:53 +00:00
|
|
|
switch (Opcode) {
|
|
|
|
default: assert(0 && "Unknown instruction type encountered!");
|
|
|
|
abort();
|
|
|
|
// Build the switch statement using the Instruction.def file.
|
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
|
|
|
case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
|
|
|
|
#include "llvm/Instruction.def"
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
|
|
|
|
|
2006-03-15 22:19:46 +00:00
|
|
|
SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
|
2006-10-09 20:57:25 +00:00
|
|
|
const Value *SV, SDOperand Root,
|
2006-03-15 22:19:46 +00:00
|
|
|
bool isVolatile);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
SDOperand getIntPtrConstant(uint64_t Val) {
|
|
|
|
return DAG.getConstant(Val, TLI.getPointerTy());
|
|
|
|
}
|
|
|
|
|
2006-03-16 19:57:50 +00:00
|
|
|
SDOperand getValue(const Value *V);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2007-02-04 01:31:47 +00:00
|
|
|
void setValue(const Value *V, SDOperand NewN) {
|
2005-01-07 07:47:53 +00:00
|
|
|
SDOperand &N = NodeMap[V];
|
|
|
|
assert(N.Val == 0 && "Already set a value for this node!");
|
2007-02-04 01:31:47 +00:00
|
|
|
N = NewN;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
RegsForValue GetRegistersForValue(const std::string &ConstrCode,
|
|
|
|
MVT::ValueType VT,
|
|
|
|
bool OutReg, bool InReg,
|
|
|
|
std::set<unsigned> &OutputRegs,
|
|
|
|
std::set<unsigned> &InputRegs);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
|
|
|
unsigned Opc);
|
2006-10-27 23:50:33 +00:00
|
|
|
bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
void ExportFromCurrentBlock(Value *V);
|
2007-02-23 21:45:01 +00:00
|
|
|
void LowerCallTo(Instruction &I,
|
|
|
|
const Type *CalledValueTy, unsigned CallingConv,
|
|
|
|
bool IsTailCall, SDOperand Callee, unsigned OpIdx);
|
2007-02-22 15:38:06 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Terminator instructions.
|
|
|
|
void visitRet(ReturnInst &I);
|
|
|
|
void visitBr(BranchInst &I);
|
2006-03-27 01:32:24 +00:00
|
|
|
void visitSwitch(SwitchInst &I);
|
2005-01-07 07:47:53 +00:00
|
|
|
void visitUnreachable(UnreachableInst &I) { /* noop */ }
|
|
|
|
|
2007-03-27 11:29:11 +00:00
|
|
|
// Helpers for visitSwitch
|
2007-03-27 12:05:48 +00:00
|
|
|
bool handleSmallSwitchRange(CaseRec& CR,
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2007-03-27 12:05:48 +00:00
|
|
|
bool handleJTSwitchCase(CaseRec& CR,
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2007-03-27 12:05:48 +00:00
|
|
|
bool handleBTSplitSwitchCase(CaseRec& CR,
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2007-04-09 12:31:58 +00:00
|
|
|
bool handleBitTestsSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2006-03-27 01:32:24 +00:00
|
|
|
void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
|
2007-04-09 12:31:58 +00:00
|
|
|
void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
|
|
|
|
void visitBitTestCase(MachineBasicBlock* NextMBB,
|
|
|
|
unsigned Reg,
|
|
|
|
SelectionDAGISel::BitTestCase &B);
|
2006-04-22 18:53:45 +00:00
|
|
|
void visitJumpTable(SelectionDAGISel::JumpTable &JT);
|
2007-03-25 15:07:15 +00:00
|
|
|
void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
|
|
|
|
SelectionDAGISel::JumpTableHeader &JTH);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// These all get lowered before this pass.
|
2007-02-21 22:53:45 +00:00
|
|
|
void visitInvoke(InvokeInst &I);
|
2007-02-25 21:43:59 +00:00
|
|
|
void visitInvoke(InvokeInst &I, bool AsTerminator);
|
2007-02-21 22:53:45 +00:00
|
|
|
void visitUnwind(UnwindInst &I);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2007-01-21 00:29:26 +00:00
|
|
|
void visitScalarBinary(User &I, unsigned OpCode);
|
|
|
|
void visitVectorBinary(User &I, unsigned OpCode);
|
|
|
|
void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp);
|
2005-11-18 07:42:56 +00:00
|
|
|
void visitShift(User &I, unsigned Opcode);
|
2005-11-19 00:36:38 +00:00
|
|
|
void visitAdd(User &I) {
|
2007-02-15 02:26:10 +00:00
|
|
|
if (isa<VectorType>(I.getType()))
|
2007-01-21 00:29:26 +00:00
|
|
|
visitVectorBinary(I, ISD::VADD);
|
|
|
|
else if (I.getType()->isFloatingPoint())
|
|
|
|
visitScalarBinary(I, ISD::FADD);
|
2006-10-26 06:15:43 +00:00
|
|
|
else
|
2007-01-21 00:29:26 +00:00
|
|
|
visitScalarBinary(I, ISD::ADD);
|
2005-09-28 22:28:18 +00:00
|
|
|
}
|
2005-04-02 05:04:50 +00:00
|
|
|
void visitSub(User &I);
|
2006-10-26 06:15:43 +00:00
|
|
|
void visitMul(User &I) {
|
2007-02-15 02:26:10 +00:00
|
|
|
if (isa<VectorType>(I.getType()))
|
2007-01-21 00:29:26 +00:00
|
|
|
visitVectorBinary(I, ISD::VMUL);
|
|
|
|
else if (I.getType()->isFloatingPoint())
|
|
|
|
visitScalarBinary(I, ISD::FMUL);
|
2006-10-26 06:15:43 +00:00
|
|
|
else
|
2007-01-21 00:29:26 +00:00
|
|
|
visitScalarBinary(I, ISD::MUL);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2007-01-21 00:29:26 +00:00
|
|
|
void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); }
|
|
|
|
void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); }
|
|
|
|
void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); }
|
|
|
|
void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); }
|
|
|
|
void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); }
|
|
|
|
void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); }
|
|
|
|
void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); }
|
|
|
|
void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); }
|
|
|
|
void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); }
|
|
|
|
void visitShl (User &I) { visitShift(I, ISD::SHL); }
|
2006-11-08 06:47:33 +00:00
|
|
|
void visitLShr(User &I) { visitShift(I, ISD::SRL); }
|
|
|
|
void visitAShr(User &I) { visitShift(I, ISD::SRA); }
|
2006-11-20 01:22:35 +00:00
|
|
|
void visitICmp(User &I);
|
|
|
|
void visitFCmp(User &I);
|
2006-11-27 01:05:10 +00:00
|
|
|
// Visit the conversion instructions
|
|
|
|
void visitTrunc(User &I);
|
|
|
|
void visitZExt(User &I);
|
|
|
|
void visitSExt(User &I);
|
|
|
|
void visitFPTrunc(User &I);
|
|
|
|
void visitFPExt(User &I);
|
|
|
|
void visitFPToUI(User &I);
|
|
|
|
void visitFPToSI(User &I);
|
|
|
|
void visitUIToFP(User &I);
|
|
|
|
void visitSIToFP(User &I);
|
|
|
|
void visitPtrToInt(User &I);
|
|
|
|
void visitIntToPtr(User &I);
|
|
|
|
void visitBitCast(User &I);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-03-29 00:11:43 +00:00
|
|
|
void visitExtractElement(User &I);
|
|
|
|
void visitInsertElement(User &I);
|
2006-04-08 04:15:24 +00:00
|
|
|
void visitShuffleVector(User &I);
|
2006-03-18 01:44:44 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void visitGetElementPtr(User &I);
|
|
|
|
void visitSelect(User &I);
|
|
|
|
|
|
|
|
void visitMalloc(MallocInst &I);
|
|
|
|
void visitFree(FreeInst &I);
|
|
|
|
void visitAlloca(AllocaInst &I);
|
|
|
|
void visitLoad(LoadInst &I);
|
|
|
|
void visitStore(StoreInst &I);
|
|
|
|
void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
|
|
|
|
void visitCall(CallInst &I);
|
2006-01-26 22:24:51 +00:00
|
|
|
void visitInlineAsm(CallInst &I);
|
2005-11-09 19:44:01 +00:00
|
|
|
const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
|
2006-03-24 02:22:33 +00:00
|
|
|
void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
void visitVAStart(CallInst &I);
|
|
|
|
void visitVAArg(VAArgInst &I);
|
|
|
|
void visitVAEnd(CallInst &I);
|
|
|
|
void visitVACopy(CallInst &I);
|
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
void visitMemIntrinsic(CallInst &I, unsigned Op);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
void visitUserOp1(Instruction &I) {
|
|
|
|
assert(0 && "UserOp1 should not exist at instruction selection time!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
void visitUserOp2(Instruction &I) {
|
|
|
|
assert(0 && "UserOp2 should not exist at instruction selection time!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
|
2006-03-16 19:57:50 +00:00
|
|
|
SDOperand SelectionDAGLowering::getValue(const Value *V) {
|
|
|
|
SDOperand &N = NodeMap[V];
|
|
|
|
if (N.Val) return N;
|
|
|
|
|
|
|
|
const Type *VTy = V->getType();
|
|
|
|
MVT::ValueType VT = TLI.getValueType(VTy);
|
|
|
|
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
|
|
|
|
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
|
|
|
|
visit(CE->getOpcode(), *CE);
|
2007-02-04 01:31:47 +00:00
|
|
|
SDOperand N1 = NodeMap[V];
|
|
|
|
assert(N1.Val && "visit didn't populate the ValueMap!");
|
|
|
|
return N1;
|
2006-03-16 19:57:50 +00:00
|
|
|
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
|
|
|
|
return N = DAG.getGlobalAddress(GV, VT);
|
|
|
|
} else if (isa<ConstantPointerNull>(C)) {
|
|
|
|
return N = DAG.getConstant(0, TLI.getPointerTy());
|
|
|
|
} else if (isa<UndefValue>(C)) {
|
2007-02-15 02:26:10 +00:00
|
|
|
if (!isa<VectorType>(VTy))
|
2006-03-19 00:20:20 +00:00
|
|
|
return N = DAG.getNode(ISD::UNDEF, VT);
|
|
|
|
|
2006-03-19 00:52:58 +00:00
|
|
|
// Create a VBUILD_VECTOR of undef nodes.
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *PTy = cast<VectorType>(VTy);
|
2006-03-19 00:20:20 +00:00
|
|
|
unsigned NumElements = PTy->getNumElements();
|
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
|
|
|
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2006-03-19 00:20:20 +00:00
|
|
|
Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
|
|
|
|
|
|
|
|
// Create a VConstant node with generic Vector type.
|
|
|
|
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
|
|
|
|
Ops.push_back(DAG.getValueType(PVT));
|
2006-08-08 02:23:42 +00:00
|
|
|
return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-16 19:57:50 +00:00
|
|
|
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
|
|
|
|
return N = DAG.getConstantFP(CFP->getValue(), VT);
|
2007-02-15 02:26:10 +00:00
|
|
|
} else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
|
2006-03-16 19:57:50 +00:00
|
|
|
unsigned NumElements = PTy->getNumElements();
|
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
|
|
|
|
|
|
|
// Now that we know the number and type of the elements, push a
|
|
|
|
// Constant or ConstantFP node onto the ops list for each element of
|
|
|
|
// the packed constant.
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2007-02-15 02:26:10 +00:00
|
|
|
if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
|
2006-03-29 00:11:43 +00:00
|
|
|
for (unsigned i = 0; i != NumElements; ++i)
|
|
|
|
Ops.push_back(getValue(CP->getOperand(i)));
|
2006-03-16 19:57:50 +00:00
|
|
|
} else {
|
|
|
|
assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
|
|
|
|
SDOperand Op;
|
|
|
|
if (MVT::isFloatingPoint(PVT))
|
|
|
|
Op = DAG.getConstantFP(0, PVT);
|
|
|
|
else
|
|
|
|
Op = DAG.getConstant(0, PVT);
|
|
|
|
Ops.assign(NumElements, Op);
|
|
|
|
}
|
|
|
|
|
2006-03-19 00:52:58 +00:00
|
|
|
// Create a VBUILD_VECTOR node with generic Vector type.
|
2006-03-19 00:20:20 +00:00
|
|
|
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
|
|
|
|
Ops.push_back(DAG.getValueType(PVT));
|
2007-02-04 01:31:47 +00:00
|
|
|
return NodeMap[V] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0],
|
|
|
|
Ops.size());
|
2006-03-16 19:57:50 +00:00
|
|
|
} else {
|
|
|
|
// Canonicalize all constant ints to be unsigned.
|
2007-01-11 12:24:14 +00:00
|
|
|
return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
|
2006-03-16 19:57:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
|
|
|
|
std::map<const AllocaInst*, int>::iterator SI =
|
|
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end())
|
|
|
|
return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
|
|
|
|
}
|
|
|
|
|
2007-02-25 18:40:32 +00:00
|
|
|
unsigned InReg = FuncInfo.ValueMap[V];
|
|
|
|
assert(InReg && "Value not in map!");
|
2006-03-16 19:57:50 +00:00
|
|
|
|
|
|
|
// If this type is not legal, make it so now.
|
2006-03-31 02:06:56 +00:00
|
|
|
if (VT != MVT::Vector) {
|
2006-12-13 20:57:08 +00:00
|
|
|
if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
|
2006-03-31 02:06:56 +00:00
|
|
|
// Source must be expanded. This input value is actually coming from the
|
2007-02-25 18:40:32 +00:00
|
|
|
// register pair InReg and InReg+1.
|
2006-12-13 20:57:08 +00:00
|
|
|
MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
|
|
|
|
unsigned NumVals = TLI.getNumElements(VT);
|
|
|
|
N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
|
|
|
|
if (NumVals == 1)
|
|
|
|
N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
|
|
|
|
else {
|
|
|
|
assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
|
|
|
|
N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
|
|
|
|
DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
|
|
|
|
N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
|
|
|
|
if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
|
|
|
|
N = MVT::isFloatingPoint(VT)
|
|
|
|
? DAG.getNode(ISD::FP_ROUND, VT, N)
|
|
|
|
: DAG.getNode(ISD::TRUNCATE, VT, N);
|
2006-03-16 19:57:50 +00:00
|
|
|
}
|
2006-03-31 02:06:56 +00:00
|
|
|
} else {
|
|
|
|
// Otherwise, if this is a vector, make it available as a generic vector
|
|
|
|
// here.
|
|
|
|
MVT::ValueType PTyElementVT, PTyLegalElementVT;
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *PTy = cast<VectorType>(VTy);
|
|
|
|
unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT,
|
2006-03-31 02:06:56 +00:00
|
|
|
PTyLegalElementVT);
|
|
|
|
|
|
|
|
// Build a VBUILD_VECTOR with the input registers.
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2006-03-31 02:06:56 +00:00
|
|
|
if (PTyElementVT == PTyLegalElementVT) {
|
|
|
|
// If the value types are legal, just VBUILD the CopyFromReg nodes.
|
|
|
|
for (unsigned i = 0; i != NE; ++i)
|
|
|
|
Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
|
|
|
|
PTyElementVT));
|
|
|
|
} else if (PTyElementVT < PTyLegalElementVT) {
|
|
|
|
// If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
|
|
|
|
for (unsigned i = 0; i != NE; ++i) {
|
|
|
|
SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
|
|
|
|
PTyElementVT);
|
|
|
|
if (MVT::isFloatingPoint(PTyElementVT))
|
|
|
|
Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
|
|
|
|
else
|
|
|
|
Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
|
|
|
|
Ops.push_back(Op);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// If the register was expanded, use BUILD_PAIR.
|
|
|
|
assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
|
|
|
|
for (unsigned i = 0; i != NE/2; ++i) {
|
|
|
|
SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
|
|
|
|
PTyElementVT);
|
|
|
|
SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
|
|
|
|
PTyElementVT);
|
|
|
|
Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Ops.push_back(DAG.getConstant(NE, MVT::i32));
|
|
|
|
Ops.push_back(DAG.getValueType(PTyLegalElementVT));
|
2006-08-08 02:23:42 +00:00
|
|
|
N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
|
2006-04-05 06:54:42 +00:00
|
|
|
|
|
|
|
// Finally, use a VBIT_CONVERT to make this available as the appropriate
|
|
|
|
// vector type.
|
|
|
|
N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
|
|
|
|
DAG.getConstant(PTy->getNumElements(),
|
|
|
|
MVT::i32),
|
|
|
|
DAG.getValueType(TLI.getValueType(PTy->getElementType())));
|
2006-03-16 19:57:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return N;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitRet(ReturnInst &I) {
|
|
|
|
if (I.getNumOperands() == 0) {
|
2005-01-17 19:43:36 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
|
2005-01-07 07:47:53 +00:00
|
|
|
return;
|
|
|
|
}
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> NewValues;
|
2006-01-27 21:09:22 +00:00
|
|
|
NewValues.push_back(getRoot());
|
|
|
|
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
SDOperand RetOp = getValue(I.getOperand(i));
|
|
|
|
|
|
|
|
// If this is an integer return value, we need to promote it ourselves to
|
|
|
|
// the full width of a register, since LegalizeOp will use ANY_EXTEND rather
|
|
|
|
// than sign/zero.
|
2006-05-26 23:09:09 +00:00
|
|
|
// FIXME: C calling convention requires the return type to be promoted to
|
|
|
|
// at least 32-bit. But this is not necessary for non-C calling conventions.
|
2006-01-27 21:09:22 +00:00
|
|
|
if (MVT::isInteger(RetOp.getValueType()) &&
|
|
|
|
RetOp.getValueType() < MVT::i64) {
|
|
|
|
MVT::ValueType TmpVT;
|
|
|
|
if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
|
|
|
|
TmpVT = TLI.getTypeToTransformTo(MVT::i32);
|
|
|
|
else
|
|
|
|
TmpVT = MVT::i32;
|
2006-12-31 05:55:36 +00:00
|
|
|
const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
|
2007-04-09 06:17:21 +00:00
|
|
|
const ParamAttrsList *Attrs = FTy->getParamAttrs();
|
2007-01-03 16:49:33 +00:00
|
|
|
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(0, SExtAttribute))
|
2007-01-03 04:25:33 +00:00
|
|
|
ExtendKind = ISD::SIGN_EXTEND;
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(0, ZExtAttribute))
|
2006-12-31 05:55:36 +00:00
|
|
|
ExtendKind = ISD::ZERO_EXTEND;
|
2007-01-03 05:03:05 +00:00
|
|
|
RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
|
2006-01-27 21:09:22 +00:00
|
|
|
}
|
|
|
|
NewValues.push_back(RetOp);
|
2006-12-31 05:55:36 +00:00
|
|
|
NewValues.push_back(DAG.getConstant(false, MVT::i32));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-08-08 02:23:42 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
|
|
|
|
&NewValues[0], NewValues.size()));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
/// ExportFromCurrentBlock - If this condition isn't known to be exported from
|
|
|
|
/// the current basic block, add it to ValueMap now so that we'll get a
|
|
|
|
/// CopyTo/FromReg.
|
|
|
|
void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
|
|
|
|
// No need to export constants.
|
|
|
|
if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
|
|
|
|
|
|
|
|
// Already exported?
|
|
|
|
if (FuncInfo.isExportedInst(V)) return;
|
|
|
|
|
|
|
|
unsigned Reg = FuncInfo.InitializeRegForValue(V);
|
|
|
|
PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
|
|
|
|
}
|
|
|
|
|
2006-10-27 23:50:33 +00:00
|
|
|
bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
|
|
|
|
const BasicBlock *FromBB) {
|
|
|
|
// The operands of the setcc have to be in this block. We don't know
|
|
|
|
// how to export them from some other block.
|
|
|
|
if (Instruction *VI = dyn_cast<Instruction>(V)) {
|
|
|
|
// Can export from current BB.
|
|
|
|
if (VI->getParent() == FromBB)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Is already exported, noop.
|
|
|
|
return FuncInfo.isExportedInst(V);
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this is an argument, we can export it if the BB is the entry block or
|
|
|
|
// if it is already exported.
|
|
|
|
if (isa<Argument>(V)) {
|
|
|
|
if (FromBB == &FromBB->getParent()->getEntryBlock())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Otherwise, can only export this if it is already exported.
|
|
|
|
return FuncInfo.isExportedInst(V);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, constants can always be exported.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-10-29 21:01:20 +00:00
|
|
|
static bool InBlock(const Value *V, const BasicBlock *BB) {
|
|
|
|
if (const Instruction *I = dyn_cast<Instruction>(V))
|
|
|
|
return I->getParent() == BB;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
/// FindMergedConditions - If Cond is an expression like
|
|
|
|
void SelectionDAGLowering::FindMergedConditions(Value *Cond,
|
|
|
|
MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB,
|
|
|
|
MachineBasicBlock *CurBB,
|
|
|
|
unsigned Opc) {
|
|
|
|
// If this node is not part of the or/and tree, emit it as a branch.
|
2006-12-23 06:05:41 +00:00
|
|
|
Instruction *BOp = dyn_cast<Instruction>(Cond);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
|
2006-12-23 06:05:41 +00:00
|
|
|
if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
|
|
|
|
(unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
|
2006-10-29 21:01:20 +00:00
|
|
|
BOp->getParent() != CurBB->getBasicBlock() ||
|
|
|
|
!InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
|
|
|
|
!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
const BasicBlock *BB = CurBB->getBasicBlock();
|
|
|
|
|
2006-12-23 06:05:41 +00:00
|
|
|
// If the leaf of the tree is a comparison, merge the condition into
|
|
|
|
// the caseblock.
|
|
|
|
if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
|
|
|
|
// The operands of the cmp have to be in this block. We don't know
|
2006-10-29 18:23:37 +00:00
|
|
|
// how to export them from some other block. If this is the first block
|
|
|
|
// of the sequence, no exporting is needed.
|
|
|
|
(CurBB == CurMBB ||
|
|
|
|
(isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
|
|
|
|
isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
|
2006-12-23 06:05:41 +00:00
|
|
|
BOp = cast<Instruction>(Cond);
|
|
|
|
ISD::CondCode Condition;
|
|
|
|
if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
|
|
|
|
switch (IC->getPredicate()) {
|
|
|
|
default: assert(0 && "Unknown icmp predicate opcode!");
|
|
|
|
case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
|
|
|
|
case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
|
|
|
|
case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
|
|
|
|
case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
|
|
|
|
case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
|
|
|
|
case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
|
|
|
|
case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
|
|
|
|
case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
|
|
|
|
case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
|
|
|
|
case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
|
|
|
|
}
|
|
|
|
} else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
|
|
|
|
ISD::CondCode FPC, FOC;
|
|
|
|
switch (FC->getPredicate()) {
|
|
|
|
default: assert(0 && "Unknown fcmp predicate opcode!");
|
|
|
|
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
|
|
|
|
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
|
|
|
|
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
|
|
|
|
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
|
|
|
|
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
|
|
|
|
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
|
|
|
|
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
|
|
|
|
case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
|
|
|
|
case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
|
|
|
|
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
|
|
|
|
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
|
|
|
|
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
|
|
|
|
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
|
|
|
|
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
|
|
|
|
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
|
|
|
|
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
|
|
|
|
}
|
|
|
|
if (FiniteOnlyFPMath())
|
|
|
|
Condition = FOC;
|
|
|
|
else
|
|
|
|
Condition = FPC;
|
|
|
|
} else {
|
2007-02-04 01:31:47 +00:00
|
|
|
Condition = ISD::SETEQ; // silence warning.
|
2006-12-23 06:05:41 +00:00
|
|
|
assert(0 && "Unknown compare instruction");
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
|
2007-04-04 21:14:49 +00:00
|
|
|
BOp->getOperand(1), NULL, TBB, FBB, CurBB);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
SwitchCases.push_back(CB);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a CaseBlock record representing this branch.
|
2007-01-11 12:24:14 +00:00
|
|
|
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
|
2007-04-04 21:14:49 +00:00
|
|
|
NULL, TBB, FBB, CurBB);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
SwitchCases.push_back(CB);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:54:23 +00:00
|
|
|
|
|
|
|
// Create TmpBB after CurBB.
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
MachineFunction::iterator BBI = CurBB;
|
|
|
|
MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
|
|
|
|
CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
|
|
|
|
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:54:23 +00:00
|
|
|
if (Opc == Instruction::Or) {
|
|
|
|
// Codegen X | Y as:
|
|
|
|
// jmp_if_X TBB
|
|
|
|
// jmp TmpBB
|
|
|
|
// TmpBB:
|
|
|
|
// jmp_if_Y TBB
|
|
|
|
// jmp FBB
|
|
|
|
//
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:54:23 +00:00
|
|
|
// Emit the LHS condition.
|
|
|
|
FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
|
|
|
|
|
|
|
|
// Emit the RHS condition into TmpBB.
|
|
|
|
FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
|
|
|
|
} else {
|
|
|
|
assert(Opc == Instruction::And && "Unknown merge op!");
|
|
|
|
// Codegen X & Y as:
|
|
|
|
// jmp_if_X TmpBB
|
|
|
|
// jmp FBB
|
|
|
|
// TmpBB:
|
|
|
|
// jmp_if_Y TBB
|
|
|
|
// jmp FBB
|
|
|
|
//
|
|
|
|
// This requires creation of TmpBB after CurBB.
|
|
|
|
|
|
|
|
// Emit the LHS condition.
|
|
|
|
FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
|
|
|
|
|
|
|
|
// Emit the RHS condition into TmpBB.
|
|
|
|
FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
|
|
|
|
}
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
}
|
|
|
|
|
2006-10-31 22:37:42 +00:00
|
|
|
/// If the set of cases should be emitted as a series of branches, return true.
|
|
|
|
/// If we should emit this as a bunch of and/or'd together conditions, return
|
|
|
|
/// false.
|
|
|
|
static bool
|
|
|
|
ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
|
|
|
|
if (Cases.size() != 2) return true;
|
|
|
|
|
Compile CodeGen/PowerPC/fp-branch.ll to:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31330 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-31 23:06:00 +00:00
|
|
|
// If this is two comparisons of the same values or'd or and'd together, they
|
|
|
|
// will get folded into a single comparison, so don't emit two blocks.
|
|
|
|
if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
|
|
|
|
Cases[0].CmpRHS == Cases[1].CmpRHS) ||
|
|
|
|
(Cases[0].CmpRHS == Cases[1].CmpLHS &&
|
|
|
|
Cases[0].CmpLHS == Cases[1].CmpRHS)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-10-31 22:37:42 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitBr(BranchInst &I) {
|
|
|
|
// Update machine-CFG edges.
|
|
|
|
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
if (I.isUnconditional()) {
|
|
|
|
// If this is not a fall-through branch, emit the branch.
|
|
|
|
if (Succ0MBB != NextBlock)
|
2005-01-17 19:43:36 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
|
2005-04-22 04:01:18 +00:00
|
|
|
DAG.getBasicBlock(Succ0MBB)));
|
2006-10-24 17:57:59 +00:00
|
|
|
|
|
|
|
// Update machine-CFG edges.
|
|
|
|
CurMBB->addSuccessor(Succ0MBB);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this condition is one of the special cases we handle, do special stuff
|
|
|
|
// now.
|
|
|
|
Value *CondVal = I.getCondition();
|
|
|
|
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
|
|
|
|
// If this is a series of conditions that are or'd or and'd together, emit
|
|
|
|
// this as a sequence of branches instead of setcc's with and/or operations.
|
|
|
|
// For example, instead of something like:
|
|
|
|
// cmp A, B
|
|
|
|
// C = seteq
|
|
|
|
// cmp D, E
|
|
|
|
// F = setle
|
|
|
|
// or C, F
|
|
|
|
// jnz foo
|
|
|
|
// Emit:
|
|
|
|
// cmp A, B
|
|
|
|
// je foo
|
|
|
|
// cmp D, E
|
|
|
|
// jle foo
|
|
|
|
//
|
|
|
|
if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
|
|
|
|
if (BOp->hasOneUse() &&
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:54:23 +00:00
|
|
|
(BOp->getOpcode() == Instruction::And ||
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
BOp->getOpcode() == Instruction::Or)) {
|
|
|
|
FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
|
Compile CodeGen/PowerPC/fp-branch.ll to:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31330 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-31 23:06:00 +00:00
|
|
|
// If the compares in later blocks need to use values not currently
|
|
|
|
// exported from this block, export them now. This block should always
|
|
|
|
// be the first entry.
|
|
|
|
assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
|
|
|
|
|
2006-10-31 22:37:42 +00:00
|
|
|
// Allow some cases to be rejected.
|
|
|
|
if (ShouldEmitAsBranches(SwitchCases)) {
|
|
|
|
for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
|
|
|
|
ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
|
|
|
|
ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit the branch for this block.
|
|
|
|
visitSwitchCase(SwitchCases[0]);
|
|
|
|
SwitchCases.erase(SwitchCases.begin());
|
|
|
|
return;
|
2006-10-29 18:23:37 +00:00
|
|
|
}
|
|
|
|
|
Compile CodeGen/PowerPC/fp-branch.ll to:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31330 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-31 23:06:00 +00:00
|
|
|
// Okay, we decided not to do this, remove any inserted MBB's and clear
|
|
|
|
// SwitchCases.
|
|
|
|
for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
|
|
|
|
CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
|
|
|
|
|
2006-10-31 22:37:42 +00:00
|
|
|
SwitchCases.clear();
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
}
|
|
|
|
}
|
2006-10-24 18:07:37 +00:00
|
|
|
|
|
|
|
// Create a CaseBlock record representing this branch.
|
2007-01-11 12:24:14 +00:00
|
|
|
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
|
2007-04-04 21:14:49 +00:00
|
|
|
NULL, Succ0MBB, Succ1MBB, CurMBB);
|
2006-10-24 18:07:37 +00:00
|
|
|
// Use visitSwitchCase to actually insert the fast branch sequence for this
|
|
|
|
// cond branch.
|
|
|
|
visitSwitchCase(CB);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
/// visitSwitchCase - Emits the necessary code to represent a single node in
|
|
|
|
/// the binary search tree resulting from lowering a switch instruction.
|
|
|
|
void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
|
2006-10-24 17:57:59 +00:00
|
|
|
SDOperand Cond;
|
|
|
|
SDOperand CondLHS = getValue(CB.CmpLHS);
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
// Build the setcc now.
|
|
|
|
if (CB.CmpMHS == NULL) {
|
|
|
|
// Fold "(X == true)" to X and "(X == false)" to !X to
|
|
|
|
// handle common cases produced by branch lowering.
|
|
|
|
if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
|
|
|
|
Cond = CondLHS;
|
|
|
|
else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
|
|
|
|
SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
|
|
|
|
Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
|
|
|
|
} else
|
|
|
|
Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
|
|
|
|
} else {
|
|
|
|
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
|
|
|
|
|
|
|
|
uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
|
|
|
|
uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
|
|
|
|
|
|
|
|
SDOperand CmpOp = getValue(CB.CmpMHS);
|
|
|
|
MVT::ValueType VT = CmpOp.getValueType();
|
2007-03-25 15:07:15 +00:00
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
|
|
|
|
Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
|
|
|
|
} else {
|
|
|
|
SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
|
|
|
|
Cond = DAG.getSetCC(MVT::i1, SUB,
|
|
|
|
DAG.getConstant(High-Low, VT), ISD::SETULE);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
// If the lhs block is the next block, invert the condition so that we can
|
|
|
|
// fall through to the lhs instead of the rhs block.
|
2006-10-24 17:57:59 +00:00
|
|
|
if (CB.TrueBB == NextBlock) {
|
|
|
|
std::swap(CB.TrueBB, CB.FalseBB);
|
2006-03-27 01:32:24 +00:00
|
|
|
SDOperand True = DAG.getConstant(1, Cond.getValueType());
|
|
|
|
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
|
|
|
|
}
|
|
|
|
SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
|
2006-10-24 17:57:59 +00:00
|
|
|
DAG.getBasicBlock(CB.TrueBB));
|
|
|
|
if (CB.FalseBB == NextBlock)
|
2006-03-27 01:32:24 +00:00
|
|
|
DAG.setRoot(BrCond);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
|
2006-10-24 17:57:59 +00:00
|
|
|
DAG.getBasicBlock(CB.FalseBB)));
|
2006-03-27 01:32:24 +00:00
|
|
|
// Update successor info
|
2006-10-24 17:57:59 +00:00
|
|
|
CurMBB->addSuccessor(CB.TrueBB);
|
|
|
|
CurMBB->addSuccessor(CB.FalseBB);
|
2006-03-27 01:32:24 +00:00
|
|
|
}
|
|
|
|
|
2007-03-25 15:07:15 +00:00
|
|
|
/// visitJumpTable - Emit JumpTable node in the current MBB
|
2006-04-22 18:53:45 +00:00
|
|
|
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
|
|
|
|
// Emit the code for the jump table
|
2007-03-25 15:07:15 +00:00
|
|
|
assert(JT.Reg != -1UL && "Should lower JT Header first!");
|
2006-04-22 18:53:45 +00:00
|
|
|
MVT::ValueType PTy = TLI.getPointerTy();
|
2006-10-30 08:00:44 +00:00
|
|
|
SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
|
|
|
|
SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
|
|
|
|
Table, Index));
|
|
|
|
return;
|
2006-04-22 18:53:45 +00:00
|
|
|
}
|
|
|
|
|
2007-03-25 15:07:15 +00:00
|
|
|
/// visitJumpTableHeader - This function emits necessary code to produce index
|
|
|
|
/// in the JumpTable from switch case.
|
|
|
|
void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
|
|
|
|
SelectionDAGISel::JumpTableHeader &JTH) {
|
|
|
|
// Subtract the lowest switch case value from the value being switched on
|
|
|
|
// and conditional branch to default mbb if the result is greater than the
|
|
|
|
// difference between smallest and largest cases.
|
|
|
|
SDOperand SwitchOp = getValue(JTH.SValue);
|
|
|
|
MVT::ValueType VT = SwitchOp.getValueType();
|
|
|
|
SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
|
|
|
|
DAG.getConstant(JTH.First, VT));
|
|
|
|
|
|
|
|
// The SDNode we just created, which holds the value being switched on
|
|
|
|
// minus the the smallest case value, needs to be copied to a virtual
|
|
|
|
// register so it can be used as an index into the jump table in a
|
|
|
|
// subsequent basic block. This value may be smaller or larger than the
|
|
|
|
// target's pointer type, and therefore require extension or truncating.
|
|
|
|
if (VT > TLI.getPointerTy())
|
|
|
|
SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
|
|
|
|
else
|
|
|
|
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
|
|
|
|
|
|
|
|
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
|
|
|
|
SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
|
|
|
|
JT.Reg = JumpTableReg;
|
|
|
|
|
|
|
|
// Emit the range check for the jump table, and branch to the default
|
|
|
|
// block for the switch statement if the value being switched on exceeds
|
|
|
|
// the largest case in the switch.
|
|
|
|
SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
|
|
|
|
DAG.getConstant(JTH.Last-JTH.First,VT),
|
|
|
|
ISD::SETUGT);
|
|
|
|
|
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
|
|
|
|
DAG.getBasicBlock(JT.Default));
|
|
|
|
|
|
|
|
if (JT.MBB == NextBlock)
|
|
|
|
DAG.setRoot(BrCond);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
|
2007-04-09 12:31:58 +00:00
|
|
|
DAG.getBasicBlock(JT.MBB)));
|
|
|
|
|
|
|
|
return;
|
2007-03-25 15:07:15 +00:00
|
|
|
}
|
|
|
|
|
2007-04-09 12:31:58 +00:00
|
|
|
/// visitBitTestHeader - This function emits necessary code to produce value
|
|
|
|
/// suitable for "bit tests"
|
|
|
|
void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
|
|
|
|
// Subtract the minimum value
|
|
|
|
SDOperand SwitchOp = getValue(B.SValue);
|
|
|
|
MVT::ValueType VT = SwitchOp.getValueType();
|
|
|
|
SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
|
|
|
|
DAG.getConstant(B.First, VT));
|
|
|
|
|
|
|
|
// Check range
|
|
|
|
SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
|
|
|
|
DAG.getConstant(B.Range, VT),
|
|
|
|
ISD::SETUGT);
|
|
|
|
|
|
|
|
SDOperand ShiftOp;
|
|
|
|
if (VT > TLI.getShiftAmountTy())
|
|
|
|
ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
|
|
|
|
else
|
|
|
|
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
|
|
|
|
|
|
|
|
// Make desired shift
|
|
|
|
SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
|
|
|
|
DAG.getConstant(1, TLI.getPointerTy()),
|
|
|
|
ShiftOp);
|
|
|
|
|
|
|
|
unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
|
|
|
|
SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
|
|
|
|
B.Reg = SwitchReg;
|
|
|
|
|
|
|
|
SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
|
|
|
|
DAG.getBasicBlock(B.Default));
|
|
|
|
|
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
MachineBasicBlock* MBB = B.Cases[0].ThisBB;
|
|
|
|
if (MBB == NextBlock)
|
|
|
|
DAG.setRoot(BrRange);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
|
|
|
|
DAG.getBasicBlock(MBB)));
|
|
|
|
|
|
|
|
CurMBB->addSuccessor(B.Default);
|
|
|
|
CurMBB->addSuccessor(MBB);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// visitBitTestCase - this function produces one "bit test"
|
|
|
|
void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
|
|
|
|
unsigned Reg,
|
|
|
|
SelectionDAGISel::BitTestCase &B) {
|
|
|
|
// Emit bit tests and jumps
|
|
|
|
SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
|
|
|
|
|
|
|
|
SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
|
|
|
|
SwitchVal,
|
|
|
|
DAG.getConstant(B.Mask,
|
|
|
|
TLI.getPointerTy()));
|
|
|
|
SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
|
|
|
|
DAG.getConstant(0, TLI.getPointerTy()),
|
|
|
|
ISD::SETNE);
|
|
|
|
SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
|
|
|
|
AndCmp, DAG.getBasicBlock(B.TargetBB));
|
|
|
|
|
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
if (NextMBB == NextBlock)
|
|
|
|
DAG.setRoot(BrAnd);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
|
|
|
|
DAG.getBasicBlock(NextMBB)));
|
|
|
|
|
|
|
|
CurMBB->addSuccessor(B.TargetBB);
|
|
|
|
CurMBB->addSuccessor(NextMBB);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
2007-03-25 15:07:15 +00:00
|
|
|
|
2007-02-21 22:53:45 +00:00
|
|
|
void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
|
2007-02-25 21:43:59 +00:00
|
|
|
assert(0 && "Should never be visited directly");
|
|
|
|
}
|
|
|
|
void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) {
|
2007-02-21 22:53:45 +00:00
|
|
|
// Retrieve successors.
|
|
|
|
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
|
|
|
|
MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
|
|
|
|
|
2007-02-25 21:43:59 +00:00
|
|
|
if (!AsTerminator) {
|
|
|
|
// Mark landing pad so that it doesn't get deleted in branch folding.
|
|
|
|
LandingPad->setIsLandingPad();
|
|
|
|
|
|
|
|
// Insert a label before the invoke call to mark the try range.
|
|
|
|
// This can be used to detect deletion of the invoke via the
|
|
|
|
// MachineModuleInfo.
|
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
|
|
|
unsigned BeginLabel = MMI->NextLabelID();
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
|
|
|
|
DAG.getConstant(BeginLabel, MVT::i32)));
|
|
|
|
|
|
|
|
LowerCallTo(I, I.getCalledValue()->getType(),
|
|
|
|
I.getCallingConv(),
|
|
|
|
false,
|
|
|
|
getValue(I.getOperand(0)),
|
|
|
|
3);
|
|
|
|
|
|
|
|
// Insert a label before the invoke call to mark the try range.
|
|
|
|
// This can be used to detect deletion of the invoke via the
|
|
|
|
// MachineModuleInfo.
|
|
|
|
unsigned EndLabel = MMI->NextLabelID();
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
|
|
|
|
DAG.getConstant(EndLabel, MVT::i32)));
|
|
|
|
|
|
|
|
// Inform MachineModuleInfo of range.
|
|
|
|
MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
|
|
|
|
|
|
|
|
// Update successor info
|
|
|
|
CurMBB->addSuccessor(Return);
|
|
|
|
CurMBB->addSuccessor(LandingPad);
|
|
|
|
} else {
|
|
|
|
// Drop into normal successor.
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
|
|
|
|
DAG.getBasicBlock(Return)));
|
|
|
|
}
|
2007-02-21 22:53:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
|
|
|
|
}
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
|
2007-03-27 11:29:11 +00:00
|
|
|
/// small case ranges).
|
2007-03-27 12:05:48 +00:00
|
|
|
bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
2007-03-27 12:05:48 +00:00
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
|
|
|
|
// Size is the number of Cases represented by this range.
|
|
|
|
unsigned Size = CR.Range.second - CR.Range.first;
|
2007-04-09 12:31:58 +00:00
|
|
|
if (Size > 3)
|
2007-03-27 12:05:48 +00:00
|
|
|
return false;
|
2007-04-04 21:14:49 +00:00
|
|
|
|
2007-03-27 11:29:11 +00:00
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
// TODO: If any two of the cases has the same destination, and if one value
|
|
|
|
// is the same as the other, but has one bit unset that the other has set,
|
|
|
|
// use bit manipulation to do two compares at once. For example:
|
|
|
|
// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
|
|
|
|
|
|
|
|
// Rearrange the case blocks so that the last one falls through if possible.
|
2007-04-04 21:14:49 +00:00
|
|
|
if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
|
2007-03-27 11:29:11 +00:00
|
|
|
// The last case block won't fall through into 'NextBlock' if we emit the
|
|
|
|
// branches in this order. See if rearranging a case value would help.
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
|
2007-04-04 21:14:49 +00:00
|
|
|
if (I->BB == NextBlock) {
|
2007-03-27 11:29:11 +00:00
|
|
|
std::swap(*I, BackCase);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a CaseBlock record representing a conditional branch to
|
|
|
|
// the Case's target mbb if the value being switched on SV is equal
|
|
|
|
// to C.
|
|
|
|
MachineBasicBlock *CurBlock = CR.CaseBB;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
|
|
|
|
MachineBasicBlock *FallThrough;
|
|
|
|
if (I != E-1) {
|
|
|
|
FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, FallThrough);
|
|
|
|
} else {
|
|
|
|
// If the last case doesn't match, go to the default block.
|
|
|
|
FallThrough = Default;
|
|
|
|
}
|
2007-04-04 21:14:49 +00:00
|
|
|
|
|
|
|
Value *RHS, *LHS, *MHS;
|
|
|
|
ISD::CondCode CC;
|
|
|
|
if (I->High == I->Low) {
|
|
|
|
// This is just small small case range :) containing exactly 1 case
|
|
|
|
CC = ISD::SETEQ;
|
|
|
|
LHS = SV; RHS = I->High; MHS = NULL;
|
|
|
|
} else {
|
|
|
|
CC = ISD::SETLE;
|
|
|
|
LHS = I->Low; MHS = SV; RHS = I->High;
|
|
|
|
}
|
|
|
|
SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
|
|
|
|
I->BB, FallThrough, CurBlock);
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
// If emitting the first comparison, just call visitSwitchCase to emit the
|
|
|
|
// code into the current block. Otherwise, push the CaseBlock onto the
|
|
|
|
// vector to be later processed by SDISel, and insert the node's MBB
|
|
|
|
// before the next MBB.
|
|
|
|
if (CurBlock == CurMBB)
|
|
|
|
visitSwitchCase(CB);
|
|
|
|
else
|
|
|
|
SwitchCases.push_back(CB);
|
|
|
|
|
|
|
|
CurBlock = FallThrough;
|
|
|
|
}
|
2007-03-27 12:05:48 +00:00
|
|
|
|
|
|
|
return true;
|
2007-03-27 11:29:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// handleJTSwitchCase - Emit jumptable for current switch case range
|
2007-03-27 12:05:48 +00:00
|
|
|
bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
2007-03-27 12:05:48 +00:00
|
|
|
Case& FrontCase = *CR.Range.first;
|
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
|
|
|
|
int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
|
|
|
|
|
|
|
|
uint64_t TSize = 0;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second;
|
|
|
|
I!=E; ++I)
|
|
|
|
TSize += I->size();
|
2007-03-27 12:05:48 +00:00
|
|
|
|
|
|
|
if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) &&
|
|
|
|
!TLI.isOperationLegal(ISD::BRIND, MVT::Other)) ||
|
2007-04-09 12:31:58 +00:00
|
|
|
TSize <= 3)
|
2007-03-27 12:05:48 +00:00
|
|
|
return false;
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
double Density = (double)TSize / (double)((Last - First) + 1ULL);
|
|
|
|
if (Density < 0.4)
|
2007-03-27 12:05:48 +00:00
|
|
|
return false;
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
DOUT << "Lowering jump table\n"
|
|
|
|
<< "First entry: " << First << ". Last entry: " << Last << "\n"
|
2007-04-09 12:31:58 +00:00
|
|
|
<< "Size: " << TSize << ". Density: " << Density << "\n\n";
|
2007-04-04 21:14:49 +00:00
|
|
|
|
2007-03-27 11:29:11 +00:00
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
2007-03-27 12:05:48 +00:00
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
|
|
|
|
|
|
|
|
// Create a new basic block to hold the code for loading the address
|
|
|
|
// of the jump table, and jumping to it. Update successor information;
|
|
|
|
// we will either branch to the default case for the switch, or the jump
|
|
|
|
// table.
|
|
|
|
MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
|
|
|
|
CR.CaseBB->addSuccessor(Default);
|
|
|
|
CR.CaseBB->addSuccessor(JumpTableBB);
|
|
|
|
|
|
|
|
// Build a vector of destination BBs, corresponding to each target
|
2007-04-09 12:31:58 +00:00
|
|
|
// of the jump table. If the value of the jump table slot corresponds to
|
2007-03-27 11:29:11 +00:00
|
|
|
// a case statement, push the case's BB onto the vector, otherwise, push
|
|
|
|
// the default BB.
|
|
|
|
std::vector<MachineBasicBlock*> DestBBs;
|
|
|
|
int64_t TEI = First;
|
2007-04-04 21:14:49 +00:00
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
|
|
|
|
int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
|
|
|
|
int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
|
|
|
|
|
|
|
|
if ((Low <= TEI) && (TEI <= High)) {
|
|
|
|
DestBBs.push_back(I->BB);
|
|
|
|
if (TEI==High)
|
|
|
|
++I;
|
2007-03-27 11:29:11 +00:00
|
|
|
} else {
|
|
|
|
DestBBs.push_back(Default);
|
|
|
|
}
|
2007-04-04 21:14:49 +00:00
|
|
|
}
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
// Update successor info. Add one edge to each unique successor.
|
2007-04-04 21:14:49 +00:00
|
|
|
BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
|
2007-03-27 11:29:11 +00:00
|
|
|
for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
|
|
|
|
E = DestBBs.end(); I != E; ++I) {
|
|
|
|
if (!SuccsHandled[(*I)->getNumber()]) {
|
|
|
|
SuccsHandled[(*I)->getNumber()] = true;
|
|
|
|
JumpTableBB->addSuccessor(*I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a jump table index for this jump table, or return an existing
|
|
|
|
// one.
|
|
|
|
unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
|
|
|
|
|
|
|
|
// Set the jump table information so that we can codegen it as a second
|
|
|
|
// MachineBasicBlock
|
|
|
|
SelectionDAGISel::JumpTable JT(-1UL, JTI, JumpTableBB, Default);
|
|
|
|
SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
|
|
|
|
(CR.CaseBB == CurMBB));
|
|
|
|
if (CR.CaseBB == CurMBB)
|
|
|
|
visitJumpTableHeader(JT, JTH);
|
|
|
|
|
|
|
|
JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
|
|
|
|
|
2007-03-27 12:05:48 +00:00
|
|
|
return true;
|
2007-03-27 11:29:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
|
|
|
|
/// 2 subtrees.
|
2007-03-27 12:05:48 +00:00
|
|
|
bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
Case& FrontCase = *CR.Range.first;
|
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
|
|
|
|
|
|
|
|
// Size is the number of Cases represented by this range.
|
|
|
|
unsigned Size = CR.Range.second - CR.Range.first;
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
|
|
|
|
int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
|
2007-04-09 12:31:58 +00:00
|
|
|
double FMetric = 0;
|
2007-04-04 21:14:49 +00:00
|
|
|
CaseItr Pivot = CR.Range.first + Size/2;
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
// Select optimal pivot, maximizing sum density of LHS and RHS. This will
|
|
|
|
// (heuristically) allow us to emit JumpTable's later.
|
2007-04-04 21:14:49 +00:00
|
|
|
uint64_t TSize = 0;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second;
|
|
|
|
I!=E; ++I)
|
|
|
|
TSize += I->size();
|
|
|
|
|
|
|
|
uint64_t LSize = FrontCase.size();
|
|
|
|
uint64_t RSize = TSize-LSize;
|
2007-04-09 12:31:58 +00:00
|
|
|
DOUT << "Selecting best pivot: \n"
|
|
|
|
<< "First: " << First << ", Last: " << Last <<"\n"
|
|
|
|
<< "LSize: " << LSize << ", RSize: " << RSize << "\n";
|
2007-03-27 11:29:11 +00:00
|
|
|
for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
|
2007-04-04 21:14:49 +00:00
|
|
|
J!=E; ++I, ++J) {
|
|
|
|
int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
|
|
|
|
int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
|
2007-04-09 12:31:58 +00:00
|
|
|
assert((RBegin-LEnd>=1) && "Invalid case distance");
|
2007-03-27 11:29:11 +00:00
|
|
|
double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
|
|
|
|
double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
|
2007-04-09 21:57:03 +00:00
|
|
|
double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
|
2007-04-09 12:31:58 +00:00
|
|
|
// Should always split in some non-trivial place
|
|
|
|
DOUT <<"=>Step\n"
|
|
|
|
<< "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
|
|
|
|
<< "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
|
|
|
|
<< "Metric: " << Metric << "\n";
|
|
|
|
if (FMetric < Metric) {
|
2007-03-27 11:29:11 +00:00
|
|
|
Pivot = J;
|
2007-04-09 12:31:58 +00:00
|
|
|
FMetric = Metric;
|
|
|
|
DOUT << "Current metric set to: " << FMetric << "\n";
|
2007-03-27 11:29:11 +00:00
|
|
|
}
|
2007-04-04 21:14:49 +00:00
|
|
|
|
|
|
|
LSize += J->size();
|
|
|
|
RSize -= J->size();
|
2007-03-27 11:29:11 +00:00
|
|
|
}
|
2007-04-09 12:31:58 +00:00
|
|
|
// If our case is dense we *really* should handle it earlier!
|
2007-04-09 21:57:03 +00:00
|
|
|
assert((FMetric > 0) && "Should handle dense range earlier!");
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
CaseRange LHSR(CR.Range.first, Pivot);
|
|
|
|
CaseRange RHSR(Pivot, CR.Range.second);
|
2007-04-04 21:14:49 +00:00
|
|
|
Constant *C = Pivot->Low;
|
2007-03-27 11:29:11 +00:00
|
|
|
MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
|
|
|
|
|
|
|
|
// We know that we branch to the LHS if the Value being switched on is
|
|
|
|
// less than the Pivot value, C. We use this to optimize our binary
|
|
|
|
// tree a bit, by recognizing that if SV is greater than or equal to the
|
|
|
|
// LHS's Case Value, and that Case Value is exactly one less than the
|
|
|
|
// Pivot's Value, then we can branch directly to the LHS's Target,
|
|
|
|
// rather than creating a leaf node for it.
|
|
|
|
if ((LHSR.second - LHSR.first) == 1 &&
|
2007-04-04 21:14:49 +00:00
|
|
|
LHSR.first->High == CR.GE &&
|
|
|
|
cast<ConstantInt>(C)->getSExtValue() ==
|
|
|
|
(cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
|
|
|
|
TrueBB = LHSR.first->BB;
|
2007-03-27 11:29:11 +00:00
|
|
|
} else {
|
|
|
|
TrueBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, TrueBB);
|
|
|
|
WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Similar to the optimization above, if the Value being switched on is
|
|
|
|
// known to be less than the Constant CR.LT, and the current Case Value
|
|
|
|
// is CR.LT - 1, then we can branch directly to the target block for
|
|
|
|
// the current Case Value, rather than emitting a RHS leaf node for it.
|
|
|
|
if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
|
2007-04-04 21:14:49 +00:00
|
|
|
cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
|
|
|
|
(cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
|
|
|
|
FalseBB = RHSR.first->BB;
|
2007-03-27 11:29:11 +00:00
|
|
|
} else {
|
|
|
|
FalseBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, FalseBB);
|
|
|
|
WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a CaseBlock record representing a conditional branch to
|
|
|
|
// the LHS node if the value being switched on SV is less than C.
|
|
|
|
// Otherwise, branch to LHS.
|
2007-04-04 21:14:49 +00:00
|
|
|
SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
|
|
|
|
TrueBB, FalseBB, CR.CaseBB);
|
2007-03-27 11:29:11 +00:00
|
|
|
|
|
|
|
if (CR.CaseBB == CurMBB)
|
|
|
|
visitSwitchCase(CB);
|
|
|
|
else
|
|
|
|
SwitchCases.push_back(CB);
|
2007-03-27 12:05:48 +00:00
|
|
|
|
|
|
|
return true;
|
2007-03-27 11:29:11 +00:00
|
|
|
}
|
|
|
|
|
2007-04-09 12:31:58 +00:00
|
|
|
/// handleBitTestsSwitchCase - if current case range has few destination and
|
|
|
|
/// range span less, than machine word bitwidth, encode case range into series
|
|
|
|
/// of masks and emit bit tests with these masks.
|
|
|
|
bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
|
|
|
unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
|
|
|
|
|
|
|
|
Case& FrontCase = *CR.Range.first;
|
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
|
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
|
|
|
|
|
|
|
unsigned numCmps = 0;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second;
|
|
|
|
I!=E; ++I) {
|
|
|
|
// Single case counts one, case range - two.
|
|
|
|
if (I->Low == I->High)
|
|
|
|
numCmps +=1;
|
|
|
|
else
|
|
|
|
numCmps +=2;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Count unique destinations
|
|
|
|
SmallSet<MachineBasicBlock*, 4> Dests;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
|
|
|
|
Dests.insert(I->BB);
|
|
|
|
if (Dests.size() > 3)
|
|
|
|
// Don't bother the code below, if there are too much unique destinations
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
|
|
|
|
<< "Total number of comparisons: " << numCmps << "\n";
|
|
|
|
|
|
|
|
// Compute span of values.
|
|
|
|
Constant* minValue = FrontCase.Low;
|
|
|
|
Constant* maxValue = BackCase.High;
|
|
|
|
uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
|
|
|
|
cast<ConstantInt>(minValue)->getSExtValue();
|
|
|
|
DOUT << "Compare range: " << range << "\n"
|
|
|
|
<< "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
|
|
|
|
<< "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
|
|
|
|
|
|
|
|
if (range>IntPtrBits ||
|
|
|
|
(!(Dests.size() == 1 && numCmps >= 3) &&
|
|
|
|
!(Dests.size() == 2 && numCmps >= 5) &&
|
|
|
|
!(Dests.size() >= 3 && numCmps >= 6)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
DOUT << "Emitting bit tests\n";
|
|
|
|
int64_t lowBound = 0;
|
|
|
|
|
|
|
|
// Optimize the case where all the case values fit in a
|
|
|
|
// word without having to subtract minValue. In this case,
|
|
|
|
// we can optimize away the subtraction.
|
|
|
|
if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
|
|
|
|
cast<ConstantInt>(maxValue)->getSExtValue() <= IntPtrBits) {
|
|
|
|
range = cast<ConstantInt>(maxValue)->getSExtValue();
|
|
|
|
} else {
|
|
|
|
lowBound = cast<ConstantInt>(minValue)->getSExtValue();
|
|
|
|
}
|
|
|
|
|
|
|
|
CaseBitsVector CasesBits;
|
|
|
|
unsigned i, count = 0;
|
|
|
|
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
|
|
|
|
MachineBasicBlock* Dest = I->BB;
|
|
|
|
for (i = 0; i < count; ++i)
|
|
|
|
if (Dest == CasesBits[i].BB)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (i == count) {
|
|
|
|
assert((count < 3) && "Too much destinations to test!");
|
|
|
|
CasesBits.push_back(CaseBits(0, Dest, 0));
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
|
|
|
|
uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
|
|
|
|
|
|
|
|
for (uint64_t j = lo; j <= hi; j++) {
|
|
|
|
CasesBits[i].Mask |= 1 << j;
|
|
|
|
CasesBits[i].Bits++;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
|
|
|
|
|
|
|
|
SelectionDAGISel::BitTestInfo BTC;
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
++BBI;
|
|
|
|
|
|
|
|
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
|
|
|
|
|
|
|
|
DOUT << "Cases:\n";
|
|
|
|
for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
|
|
|
|
DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
|
|
|
|
<< ", BB: " << CasesBits[i].BB << "\n";
|
|
|
|
|
|
|
|
MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, CaseBB);
|
|
|
|
BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
|
|
|
|
CaseBB,
|
|
|
|
CasesBits[i].BB));
|
|
|
|
}
|
|
|
|
|
|
|
|
SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
|
2007-04-09 14:32:59 +00:00
|
|
|
-1U, (CR.CaseBB == CurMBB),
|
2007-04-09 12:31:58 +00:00
|
|
|
CR.CaseBB, Default, BTC);
|
|
|
|
|
|
|
|
if (CR.CaseBB == CurMBB)
|
|
|
|
visitBitTestHeader(BTB);
|
|
|
|
|
|
|
|
BitTestCases.push_back(BTB);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
// Clusterify - Transform simple list of Cases into list of CaseRange's
|
|
|
|
unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
|
|
|
|
const SwitchInst& SI) {
|
|
|
|
unsigned numCmps = 0;
|
|
|
|
|
|
|
|
// Start with "simple" cases
|
|
|
|
for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
|
|
|
|
MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
|
|
|
|
Cases.push_back(Case(SI.getSuccessorValue(i),
|
|
|
|
SI.getSuccessorValue(i),
|
|
|
|
SMBB));
|
|
|
|
}
|
|
|
|
sort(Cases.begin(), Cases.end(), CaseCmp());
|
|
|
|
|
|
|
|
// Merge case into clusters
|
|
|
|
if (Cases.size()>=2)
|
|
|
|
for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) {
|
|
|
|
int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
|
|
|
|
int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
|
|
|
|
MachineBasicBlock* nextBB = J->BB;
|
|
|
|
MachineBasicBlock* currentBB = I->BB;
|
|
|
|
|
|
|
|
// If the two neighboring cases go to the same destination, merge them
|
|
|
|
// into a single case.
|
|
|
|
if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
|
|
|
|
I->High = J->High;
|
|
|
|
J = Cases.erase(J);
|
|
|
|
} else {
|
|
|
|
I = J++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
|
|
|
|
if (I->Low != I->High)
|
|
|
|
// A range counts double, since it requires two compares.
|
|
|
|
++numCmps;
|
|
|
|
}
|
|
|
|
|
|
|
|
return numCmps;
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
|
2006-03-27 01:32:24 +00:00
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
2006-10-19 21:46:38 +00:00
|
|
|
|
2007-04-04 21:14:49 +00:00
|
|
|
MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
|
2006-10-22 21:36:53 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// If there is only the default destination, branch to it if it is not the
|
|
|
|
// next basic block. Otherwise, just fall through.
|
2007-04-04 21:14:49 +00:00
|
|
|
if (SI.getNumOperands() == 2) {
|
2006-03-27 01:32:24 +00:00
|
|
|
// Update machine-CFG edges.
|
2006-10-19 21:46:38 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// If this is not a fall-through branch, emit the branch.
|
2006-10-22 21:36:53 +00:00
|
|
|
if (Default != NextBlock)
|
2006-03-27 01:32:24 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
|
2006-10-22 21:36:53 +00:00
|
|
|
DAG.getBasicBlock(Default)));
|
2006-10-19 21:46:38 +00:00
|
|
|
|
2006-10-22 21:36:53 +00:00
|
|
|
CurMBB->addSuccessor(Default);
|
2006-03-27 01:32:24 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If there are any non-default case statements, create a vector of Cases
|
|
|
|
// representing each one, and sort the vector so that we can efficiently
|
|
|
|
// create a binary search tree from them.
|
2007-04-04 21:14:49 +00:00
|
|
|
CaseVector Cases;
|
|
|
|
unsigned numCmps = Clusterify(Cases, SI);
|
|
|
|
DOUT << "Clusterify finished. Total clusters: " << Cases.size()
|
|
|
|
<< ". Total compares: " << numCmps << "\n";
|
2006-10-19 21:46:38 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// Get the Value to be switched on and default basic blocks, which will be
|
|
|
|
// inserted into CaseBlock records, representing basic blocks in the binary
|
|
|
|
// search tree.
|
2007-04-04 21:14:49 +00:00
|
|
|
Value *SV = SI.getOperand(0);
|
2006-04-22 18:53:45 +00:00
|
|
|
|
2007-03-25 15:07:15 +00:00
|
|
|
// Push the initial CaseRec onto the worklist
|
2007-03-27 11:29:11 +00:00
|
|
|
CaseRecVector WorkList;
|
2007-03-25 15:07:15 +00:00
|
|
|
WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
|
|
|
|
|
|
|
|
while (!WorkList.empty()) {
|
|
|
|
// Grab a record representing a case range to process off the worklist
|
|
|
|
CaseRec CR = WorkList.back();
|
|
|
|
WorkList.pop_back();
|
|
|
|
|
2007-04-09 12:31:58 +00:00
|
|
|
if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
|
|
|
|
continue;
|
|
|
|
|
2007-03-25 15:07:15 +00:00
|
|
|
// If the range has few cases (two or less) emit a series of specific
|
|
|
|
// tests.
|
2007-03-27 12:05:48 +00:00
|
|
|
if (handleSmallSwitchRange(CR, WorkList, SV, Default))
|
|
|
|
continue;
|
|
|
|
|
2007-04-09 12:31:58 +00:00
|
|
|
// If the switch has more than 5 blocks, and at least 40% dense, and the
|
2007-03-25 15:07:15 +00:00
|
|
|
// target supports indirect branches, then emit a jump table rather than
|
|
|
|
// lowering the switch to a binary tree of conditional branches.
|
2007-03-27 12:05:48 +00:00
|
|
|
if (handleJTSwitchCase(CR, WorkList, SV, Default))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Emit binary tree. We need to pick a pivot, and push left and right ranges
|
|
|
|
// onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
|
|
|
|
handleBTSplitSwitchCase(CR, WorkList, SV, Default);
|
2006-03-27 01:32:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-25 15:07:15 +00:00
|
|
|
|
2005-04-02 05:04:50 +00:00
|
|
|
void SelectionDAGLowering::visitSub(User &I) {
|
|
|
|
// -0.0 - X --> fneg
|
2007-01-21 00:29:26 +00:00
|
|
|
const Type *Ty = I.getType();
|
2007-02-15 02:26:10 +00:00
|
|
|
if (isa<VectorType>(Ty)) {
|
2007-01-21 00:29:26 +00:00
|
|
|
visitVectorBinary(I, ISD::VSUB);
|
|
|
|
} else if (Ty->isFloatingPoint()) {
|
2005-09-28 22:28:18 +00:00
|
|
|
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
|
|
|
|
if (CFP->isExactlyValue(-0.0)) {
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
|
|
|
|
return;
|
|
|
|
}
|
2007-01-21 00:29:26 +00:00
|
|
|
visitScalarBinary(I, ISD::FSUB);
|
2006-10-26 06:15:43 +00:00
|
|
|
} else
|
2007-01-21 00:29:26 +00:00
|
|
|
visitScalarBinary(I, ISD::SUB);
|
2005-04-02 05:04:50 +00:00
|
|
|
}
|
|
|
|
|
2007-01-21 00:29:26 +00:00
|
|
|
void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) {
|
2005-01-07 07:47:53 +00:00
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
2007-01-21 00:29:26 +00:00
|
|
|
|
|
|
|
setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
|
2006-10-26 06:15:43 +00:00
|
|
|
}
|
|
|
|
|
2007-01-21 00:29:26 +00:00
|
|
|
void
|
|
|
|
SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) {
|
2007-02-15 02:26:10 +00:00
|
|
|
assert(isa<VectorType>(I.getType()));
|
|
|
|
const VectorType *Ty = cast<VectorType>(I.getType());
|
2007-01-21 00:29:26 +00:00
|
|
|
SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType()));
|
|
|
|
|
|
|
|
setValue(&I, DAG.getNode(OpCode, MVT::Vector,
|
|
|
|
getValue(I.getOperand(0)),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getConstant(Ty->getNumElements(), MVT::i32),
|
|
|
|
Typ));
|
|
|
|
}
|
2006-10-26 06:15:43 +00:00
|
|
|
|
2007-01-21 00:29:26 +00:00
|
|
|
void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp,
|
|
|
|
unsigned VectorOp) {
|
2007-02-15 02:26:10 +00:00
|
|
|
if (isa<VectorType>(I.getType()))
|
2007-01-21 00:29:26 +00:00
|
|
|
visitVectorBinary(I, VectorOp);
|
|
|
|
else
|
|
|
|
visitScalarBinary(I, ScalarOp);
|
2005-11-18 07:42:56 +00:00
|
|
|
}
|
2005-01-19 22:31:21 +00:00
|
|
|
|
2005-11-18 07:42:56 +00:00
|
|
|
void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
|
2007-02-02 02:16:23 +00:00
|
|
|
if (TLI.getShiftAmountTy() < Op2.getValueType())
|
|
|
|
Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
|
|
|
|
else if (TLI.getShiftAmountTy() > Op2.getValueType())
|
|
|
|
Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
|
2005-11-18 07:42:56 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
|
|
|
|
}
|
|
|
|
|
2006-11-20 01:22:35 +00:00
|
|
|
void SelectionDAGLowering::visitICmp(User &I) {
|
2006-12-23 06:05:41 +00:00
|
|
|
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
|
|
|
|
if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
|
|
|
|
predicate = IC->getPredicate();
|
|
|
|
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
|
|
|
|
predicate = ICmpInst::Predicate(IC->getPredicate());
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
2006-11-20 01:22:35 +00:00
|
|
|
ISD::CondCode Opcode;
|
2006-12-23 06:05:41 +00:00
|
|
|
switch (predicate) {
|
2006-11-20 01:22:35 +00:00
|
|
|
case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
|
|
|
|
case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
|
|
|
|
case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
|
|
|
|
case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
|
|
|
|
case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
|
|
|
|
case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
|
|
|
|
case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
|
|
|
|
case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
|
|
|
|
case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
|
|
|
|
case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
|
|
|
|
default:
|
|
|
|
assert(!"Invalid ICmp predicate value");
|
|
|
|
Opcode = ISD::SETEQ;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFCmp(User &I) {
|
2006-12-23 06:05:41 +00:00
|
|
|
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
|
|
|
|
if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
|
|
|
|
predicate = FC->getPredicate();
|
|
|
|
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
|
|
|
|
predicate = FCmpInst::Predicate(FC->getPredicate());
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
ISD::CondCode Condition, FOC, FPC;
|
|
|
|
switch (predicate) {
|
|
|
|
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
|
|
|
|
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
|
|
|
|
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
|
|
|
|
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
|
|
|
|
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
|
|
|
|
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
|
|
|
|
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
|
|
|
|
case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
|
|
|
|
case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
|
|
|
|
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
|
|
|
|
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
|
|
|
|
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
|
|
|
|
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
|
|
|
|
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
|
|
|
|
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
|
|
|
|
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
|
2006-11-20 01:22:35 +00:00
|
|
|
default:
|
|
|
|
assert(!"Invalid FCmp predicate value");
|
2006-12-23 06:05:41 +00:00
|
|
|
FOC = FPC = ISD::SETFALSE;
|
2006-11-20 01:22:35 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-12-23 06:05:41 +00:00
|
|
|
if (FiniteOnlyFPMath())
|
|
|
|
Condition = FOC;
|
|
|
|
else
|
|
|
|
Condition = FPC;
|
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSelect(User &I) {
|
|
|
|
SDOperand Cond = getValue(I.getOperand(0));
|
|
|
|
SDOperand TrueVal = getValue(I.getOperand(1));
|
|
|
|
SDOperand FalseVal = getValue(I.getOperand(2));
|
2007-02-15 02:26:10 +00:00
|
|
|
if (!isa<VectorType>(I.getType())) {
|
2006-04-08 22:22:57 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
|
|
|
|
TrueVal, FalseVal));
|
|
|
|
} else {
|
|
|
|
setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
|
|
|
|
*(TrueVal.Val->op_end()-2),
|
|
|
|
*(TrueVal.Val->op_end()-1)));
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-11-27 01:05:10 +00:00
|
|
|
|
|
|
|
void SelectionDAGLowering::visitTrunc(User &I) {
|
|
|
|
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitZExt(User &I) {
|
|
|
|
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
|
|
|
|
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSExt(User &I) {
|
|
|
|
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
|
|
|
|
// SExt also can't be a cast to bool for same reason. So, nothing much to do
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPTrunc(User &I) {
|
|
|
|
// FPTrunc is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPExt(User &I){
|
|
|
|
// FPTrunc is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPToUI(User &I) {
|
|
|
|
// FPToUI is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPToSI(User &I) {
|
|
|
|
// FPToSI is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitUIToFP(User &I) {
|
|
|
|
// UIToFP is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSIToFP(User &I){
|
|
|
|
// UIToFP is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitPtrToInt(User &I) {
|
|
|
|
// What to do depends on the size of the integer and the size of the pointer.
|
|
|
|
// We can either truncate, zero extend, or no-op, accordingly.
|
2005-01-07 07:47:53 +00:00
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2006-03-22 20:09:35 +00:00
|
|
|
MVT::ValueType SrcVT = N.getValueType();
|
2006-03-15 22:19:46 +00:00
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
2006-11-27 01:05:10 +00:00
|
|
|
SDOperand Result;
|
|
|
|
if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
|
|
|
|
Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
|
|
|
|
else
|
|
|
|
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
|
|
|
|
Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
|
|
|
|
setValue(&I, Result);
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-11-27 01:05:10 +00:00
|
|
|
void SelectionDAGLowering::visitIntToPtr(User &I) {
|
|
|
|
// What to do depends on the size of the integer and the size of the pointer.
|
|
|
|
// We can either truncate, zero extend, or no-op, accordingly.
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType SrcVT = N.getValueType();
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
|
|
|
if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
|
|
|
|
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
|
|
|
|
else
|
|
|
|
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
|
|
|
|
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitBitCast(User &I) {
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
2006-03-22 20:09:35 +00:00
|
|
|
if (DestVT == MVT::Vector) {
|
2006-11-27 01:05:10 +00:00
|
|
|
// This is a cast to a vector from something else.
|
|
|
|
// Get information about the output vector.
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *DestTy = cast<VectorType>(I.getType());
|
2006-03-22 20:09:35 +00:00
|
|
|
MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
|
|
|
|
setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
|
|
|
|
DAG.getConstant(DestTy->getNumElements(),MVT::i32),
|
|
|
|
DAG.getValueType(EltVT)));
|
2006-11-27 01:05:10 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
MVT::ValueType SrcVT = N.getValueType();
|
|
|
|
if (SrcVT == MVT::Vector) {
|
|
|
|
// This is a cast from a vctor to something else.
|
|
|
|
// Get information about the input vector.
|
2006-03-22 20:09:35 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
|
2006-11-27 01:05:10 +00:00
|
|
|
return;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-11-27 01:05:10 +00:00
|
|
|
|
|
|
|
// BitCast assures us that source and destination are the same size so this
|
|
|
|
// is either a BIT_CONVERT or a no-op.
|
|
|
|
if (DestVT != N.getValueType())
|
|
|
|
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
|
|
|
|
else
|
|
|
|
setValue(&I, N); // noop cast.
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-03-29 00:11:43 +00:00
|
|
|
void SelectionDAGLowering::visitInsertElement(User &I) {
|
2006-03-18 01:44:44 +00:00
|
|
|
SDOperand InVec = getValue(I.getOperand(0));
|
|
|
|
SDOperand InVal = getValue(I.getOperand(1));
|
|
|
|
SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(2)));
|
|
|
|
|
2006-03-19 01:17:20 +00:00
|
|
|
SDOperand Num = *(InVec.Val->op_end()-2);
|
|
|
|
SDOperand Typ = *(InVec.Val->op_end()-1);
|
|
|
|
setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
|
|
|
|
InVec, InVal, InIdx, Num, Typ));
|
2006-03-18 01:44:44 +00:00
|
|
|
}
|
|
|
|
|
2006-03-29 00:11:43 +00:00
|
|
|
void SelectionDAGLowering::visitExtractElement(User &I) {
|
2006-03-21 20:44:12 +00:00
|
|
|
SDOperand InVec = getValue(I.getOperand(0));
|
|
|
|
SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(1)));
|
|
|
|
SDOperand Typ = *(InVec.Val->op_end()-1);
|
|
|
|
setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
|
|
|
|
TLI.getValueType(I.getType()), InVec, InIdx));
|
|
|
|
}
|
2006-03-18 01:44:44 +00:00
|
|
|
|
2006-04-08 04:15:24 +00:00
|
|
|
void SelectionDAGLowering::visitShuffleVector(User &I) {
|
|
|
|
SDOperand V1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand V2 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Mask = getValue(I.getOperand(2));
|
|
|
|
|
|
|
|
SDOperand Num = *(V1.Val->op_end()-2);
|
|
|
|
SDOperand Typ = *(V2.Val->op_end()-1);
|
|
|
|
setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
|
|
|
|
V1, V2, Mask, Num, Typ));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
const Type *Ty = I.getOperand(0)->getType();
|
|
|
|
|
|
|
|
for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
|
|
|
|
OI != E; ++OI) {
|
|
|
|
Value *Idx = *OI;
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
|
2006-10-20 07:07:24 +00:00
|
|
|
unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
|
2005-01-07 07:47:53 +00:00
|
|
|
if (Field) {
|
|
|
|
// N = N + Offset
|
2007-02-10 19:55:17 +00:00
|
|
|
uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
|
2005-01-07 07:47:53 +00:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
2005-04-22 04:01:18 +00:00
|
|
|
getIntPtrConstant(Offset));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
Ty = StTy->getElementType(Field);
|
|
|
|
} else {
|
|
|
|
Ty = cast<SequentialType>(Ty)->getElementType();
|
2005-11-09 04:45:33 +00:00
|
|
|
|
|
|
|
// If this is a constant subscript, handle it quickly.
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
|
2006-10-20 07:07:24 +00:00
|
|
|
if (CI->getZExtValue() == 0) continue;
|
2006-12-31 05:55:36 +00:00
|
|
|
uint64_t Offs =
|
2007-01-05 01:46:20 +00:00
|
|
|
TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
|
2005-11-09 04:45:33 +00:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// N = N + Idx * ElementSize;
|
2006-05-03 01:29:57 +00:00
|
|
|
uint64_t ElementSize = TD->getTypeSize(Ty);
|
2005-11-09 04:45:33 +00:00
|
|
|
SDOperand IdxN = getValue(Idx);
|
|
|
|
|
|
|
|
// If the index is smaller or larger than intptr_t, truncate or extend
|
|
|
|
// it.
|
|
|
|
if (IdxN.getValueType() < N.getValueType()) {
|
2006-12-31 05:55:36 +00:00
|
|
|
IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
|
2005-11-09 04:45:33 +00:00
|
|
|
} else if (IdxN.getValueType() > N.getValueType())
|
|
|
|
IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
|
|
|
|
|
|
|
|
// If this is a multiply by a power of two, turn it into a shl
|
|
|
|
// immediately. This is a very common case.
|
|
|
|
if (isPowerOf2_64(ElementSize)) {
|
|
|
|
unsigned Amt = Log2_64(ElementSize);
|
|
|
|
IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
|
2005-11-09 16:50:40 +00:00
|
|
|
DAG.getConstant(Amt, TLI.getShiftAmountTy()));
|
2005-01-07 07:47:53 +00:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
2005-11-09 04:45:33 +00:00
|
|
|
continue;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2005-11-09 04:45:33 +00:00
|
|
|
|
|
|
|
SDOperand Scale = getIntPtrConstant(ElementSize);
|
|
|
|
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
|
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
setValue(&I, N);
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
|
|
|
// If this is a fixed sized alloca in the entry block of the function,
|
|
|
|
// allocate it statically on the stack.
|
|
|
|
if (FuncInfo.StaticAllocaMap.count(&I))
|
|
|
|
return; // getValue will auto-populate this.
|
|
|
|
|
|
|
|
const Type *Ty = I.getAllocatedType();
|
2006-05-03 01:29:57 +00:00
|
|
|
uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
|
2007-01-20 22:35:55 +00:00
|
|
|
unsigned Align =
|
2007-02-14 05:52:17 +00:00
|
|
|
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
|
2007-01-20 22:35:55 +00:00
|
|
|
I.getAlignment());
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
SDOperand AllocSize = getValue(I.getArraySize());
|
2005-01-22 23:04:37 +00:00
|
|
|
MVT::ValueType IntPtr = TLI.getPointerTy();
|
|
|
|
if (IntPtr < AllocSize.getValueType())
|
|
|
|
AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
|
|
|
|
else if (IntPtr > AllocSize.getValueType())
|
|
|
|
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2005-01-22 23:04:37 +00:00
|
|
|
AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
|
2005-01-07 07:47:53 +00:00
|
|
|
getIntPtrConstant(TySize));
|
|
|
|
|
|
|
|
// Handle alignment. If the requested alignment is less than or equal to the
|
|
|
|
// stack alignment, ignore it and round the size of the allocation up to the
|
|
|
|
// stack alignment size. If the size is greater than the stack alignment, we
|
|
|
|
// note this in the DYNAMIC_STACKALLOC node.
|
|
|
|
unsigned StackAlign =
|
|
|
|
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
|
|
|
|
if (Align <= StackAlign) {
|
|
|
|
Align = 0;
|
|
|
|
// Add SA-1 to the size.
|
|
|
|
AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
|
|
|
|
getIntPtrConstant(StackAlign-1));
|
|
|
|
// Mask out the low bits for alignment purposes.
|
|
|
|
AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
|
|
|
|
getIntPtrConstant(~(uint64_t)(StackAlign-1)));
|
|
|
|
}
|
|
|
|
|
2006-08-08 02:23:42 +00:00
|
|
|
SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
|
2006-08-14 23:53:35 +00:00
|
|
|
const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
|
|
|
|
MVT::Other);
|
|
|
|
SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
|
2007-02-04 01:31:47 +00:00
|
|
|
setValue(&I, DSA);
|
|
|
|
DAG.setRoot(DSA.getValue(1));
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
// Inform the Frame Information that we have just allocated a variable-sized
|
|
|
|
// object.
|
|
|
|
CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitLoad(LoadInst &I) {
|
|
|
|
SDOperand Ptr = getValue(I.getOperand(0));
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-17 22:19:26 +00:00
|
|
|
SDOperand Root;
|
|
|
|
if (I.isVolatile())
|
|
|
|
Root = getRoot();
|
|
|
|
else {
|
|
|
|
// Do not serialize non-volatile loads against each other.
|
|
|
|
Root = DAG.getRoot();
|
|
|
|
}
|
2006-03-15 22:19:46 +00:00
|
|
|
|
2006-10-09 20:57:25 +00:00
|
|
|
setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
|
2006-03-15 22:19:46 +00:00
|
|
|
Root, I.isVolatile()));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
|
2006-10-09 20:57:25 +00:00
|
|
|
const Value *SV, SDOperand Root,
|
2006-03-15 22:19:46 +00:00
|
|
|
bool isVolatile) {
|
2005-11-19 00:36:38 +00:00
|
|
|
SDOperand L;
|
2007-02-15 02:26:10 +00:00
|
|
|
if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) {
|
2005-11-22 01:29:36 +00:00
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
2006-10-09 20:57:25 +00:00
|
|
|
L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
|
|
|
|
DAG.getSrcValue(SV));
|
2005-11-19 00:36:38 +00:00
|
|
|
} else {
|
2006-12-20 01:27:29 +00:00
|
|
|
L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, isVolatile);
|
2005-11-19 00:36:38 +00:00
|
|
|
}
|
2005-01-17 22:19:26 +00:00
|
|
|
|
2006-03-15 22:19:46 +00:00
|
|
|
if (isVolatile)
|
2005-01-17 22:19:26 +00:00
|
|
|
DAG.setRoot(L.getValue(1));
|
|
|
|
else
|
|
|
|
PendingLoads.push_back(L.getValue(1));
|
2006-03-15 22:19:46 +00:00
|
|
|
|
|
|
|
return L;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitStore(StoreInst &I) {
|
|
|
|
Value *SrcV = I.getOperand(0);
|
|
|
|
SDOperand Src = getValue(SrcV);
|
|
|
|
SDOperand Ptr = getValue(I.getOperand(1));
|
2006-12-20 01:27:29 +00:00
|
|
|
DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
|
2006-10-13 21:14:26 +00:00
|
|
|
I.isVolatile()));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-03-24 02:22:33 +00:00
|
|
|
/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
|
|
|
|
/// access memory and has no other side effects at all.
|
|
|
|
static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
|
|
|
|
#define GET_NO_MEMORY_INTRINSICS
|
|
|
|
#include "llvm/Intrinsics.gen"
|
|
|
|
#undef GET_NO_MEMORY_INTRINSICS
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-04-02 03:41:14 +00:00
|
|
|
// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
|
|
|
|
// have any side-effects or if it only reads memory.
|
|
|
|
static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
|
|
|
|
#define GET_SIDE_EFFECT_INFO
|
|
|
|
#include "llvm/Intrinsics.gen"
|
|
|
|
#undef GET_SIDE_EFFECT_INFO
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-03-24 02:22:33 +00:00
|
|
|
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
|
|
|
|
/// node.
|
|
|
|
void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
|
|
|
|
unsigned Intrinsic) {
|
2006-03-24 22:49:42 +00:00
|
|
|
bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
|
2006-04-02 03:41:14 +00:00
|
|
|
bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
|
2006-03-24 02:22:33 +00:00
|
|
|
|
|
|
|
// Build the operand list.
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2006-04-02 03:41:14 +00:00
|
|
|
if (HasChain) { // If this intrinsic has side-effects, chainify it.
|
|
|
|
if (OnlyLoad) {
|
|
|
|
// We don't need to serialize loads against other loads.
|
|
|
|
Ops.push_back(DAG.getRoot());
|
|
|
|
} else {
|
|
|
|
Ops.push_back(getRoot());
|
|
|
|
}
|
|
|
|
}
|
2006-03-24 02:22:33 +00:00
|
|
|
|
|
|
|
// Add the intrinsic ID as an integer operand.
|
|
|
|
Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
|
|
|
|
|
|
|
|
// Add all operands of the call to the operand list.
|
|
|
|
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
SDOperand Op = getValue(I.getOperand(i));
|
|
|
|
|
2007-02-15 03:39:18 +00:00
|
|
|
// If this is a vector type, force it to the right vector type.
|
2006-03-24 02:22:33 +00:00
|
|
|
if (Op.getValueType() == MVT::Vector) {
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType());
|
2006-03-24 02:22:33 +00:00
|
|
|
MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
|
|
|
|
|
|
|
|
MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
|
|
|
|
assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
|
|
|
|
Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(TLI.isTypeLegal(Op.getValueType()) &&
|
|
|
|
"Intrinsic uses a non-legal type?");
|
|
|
|
Ops.push_back(Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
std::vector<MVT::ValueType> VTs;
|
|
|
|
if (I.getType() != Type::VoidTy) {
|
|
|
|
MVT::ValueType VT = TLI.getValueType(I.getType());
|
|
|
|
if (VT == MVT::Vector) {
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *DestTy = cast<VectorType>(I.getType());
|
2006-03-24 02:22:33 +00:00
|
|
|
MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
|
|
|
|
|
|
|
|
VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
|
|
|
|
assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
|
|
|
|
VTs.push_back(VT);
|
|
|
|
}
|
|
|
|
if (HasChain)
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
|
2006-08-14 23:53:35 +00:00
|
|
|
const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
|
|
|
|
|
2006-03-24 02:22:33 +00:00
|
|
|
// Create the node.
|
2006-03-28 00:40:33 +00:00
|
|
|
SDOperand Result;
|
|
|
|
if (!HasChain)
|
2006-08-14 23:53:35 +00:00
|
|
|
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-28 00:40:33 +00:00
|
|
|
else if (I.getType() != Type::VoidTy)
|
2006-08-14 23:53:35 +00:00
|
|
|
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-28 00:40:33 +00:00
|
|
|
else
|
2006-08-14 23:53:35 +00:00
|
|
|
Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-28 00:40:33 +00:00
|
|
|
|
2006-04-02 03:41:14 +00:00
|
|
|
if (HasChain) {
|
|
|
|
SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
|
|
|
|
if (OnlyLoad)
|
|
|
|
PendingLoads.push_back(Chain);
|
|
|
|
else
|
|
|
|
DAG.setRoot(Chain);
|
|
|
|
}
|
2006-03-24 02:22:33 +00:00
|
|
|
if (I.getType() != Type::VoidTy) {
|
2007-02-15 02:26:10 +00:00
|
|
|
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
|
2006-03-24 02:22:33 +00:00
|
|
|
MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
|
|
|
|
Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
|
|
|
|
DAG.getConstant(PTy->getNumElements(), MVT::i32),
|
|
|
|
DAG.getValueType(EVT));
|
|
|
|
}
|
|
|
|
setValue(&I, Result);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-11-09 19:44:01 +00:00
|
|
|
/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
|
|
|
|
/// we want to emit this as a call to a named external function, return the name
|
|
|
|
/// otherwise lower it and return null.
|
|
|
|
const char *
|
|
|
|
SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
|
|
|
switch (Intrinsic) {
|
2006-03-24 02:22:33 +00:00
|
|
|
default:
|
|
|
|
// By default, turn this into a target intrinsic node.
|
|
|
|
visitTargetIntrinsic(I, Intrinsic);
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
case Intrinsic::vastart: visitVAStart(I); return 0;
|
|
|
|
case Intrinsic::vaend: visitVAEnd(I); return 0;
|
|
|
|
case Intrinsic::vacopy: visitVACopy(I); return 0;
|
2007-01-29 22:58:52 +00:00
|
|
|
case Intrinsic::returnaddress:
|
|
|
|
setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::frameaddress:
|
|
|
|
setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
case Intrinsic::setjmp:
|
2006-12-10 23:12:42 +00:00
|
|
|
return "_setjmp"+!TLI.usesUnderscoreSetJmp();
|
2005-11-09 19:44:01 +00:00
|
|
|
break;
|
|
|
|
case Intrinsic::longjmp:
|
2006-12-10 23:12:42 +00:00
|
|
|
return "_longjmp"+!TLI.usesUnderscoreLongJmp();
|
2005-11-09 19:44:01 +00:00
|
|
|
break;
|
2006-03-03 00:00:25 +00:00
|
|
|
case Intrinsic::memcpy_i32:
|
|
|
|
case Intrinsic::memcpy_i64:
|
|
|
|
visitMemIntrinsic(I, ISD::MEMCPY);
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::memset_i32:
|
|
|
|
case Intrinsic::memset_i64:
|
|
|
|
visitMemIntrinsic(I, ISD::MEMSET);
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::memmove_i32:
|
|
|
|
case Intrinsic::memmove_i64:
|
|
|
|
visitMemIntrinsic(I, ISD::MEMMOVE);
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
|
2005-12-13 17:40:33 +00:00
|
|
|
case Intrinsic::dbg_stoppoint: {
|
2007-01-26 21:22:28 +00:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-23 18:06:46 +00:00
|
|
|
DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
|
2007-01-26 21:22:28 +00:00
|
|
|
if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
|
2006-08-08 02:23:42 +00:00
|
|
|
SDOperand Ops[5];
|
2005-11-29 06:21:05 +00:00
|
|
|
|
2006-08-08 02:23:42 +00:00
|
|
|
Ops[0] = getRoot();
|
|
|
|
Ops[1] = getValue(SPI.getLineValue());
|
|
|
|
Ops[2] = getValue(SPI.getColumnValue());
|
2006-02-11 01:01:30 +00:00
|
|
|
|
2007-01-26 21:22:28 +00:00
|
|
|
DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
|
2006-02-11 01:01:30 +00:00
|
|
|
assert(DD && "Not a debug information descriptor");
|
2006-03-23 18:06:46 +00:00
|
|
|
CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
|
|
|
|
|
2006-08-08 02:23:42 +00:00
|
|
|
Ops[3] = DAG.getString(CompileUnit->getFileName());
|
|
|
|
Ops[4] = DAG.getString(CompileUnit->getDirectory());
|
2006-02-11 01:01:30 +00:00
|
|
|
|
2006-08-08 02:23:42 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
|
2005-12-13 17:40:33 +00:00
|
|
|
}
|
2006-03-23 18:06:46 +00:00
|
|
|
|
2005-11-16 07:22:30 +00:00
|
|
|
return 0;
|
2005-11-29 06:21:05 +00:00
|
|
|
}
|
2006-03-23 18:06:46 +00:00
|
|
|
case Intrinsic::dbg_region_start: {
|
2007-01-26 21:22:28 +00:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-23 18:06:46 +00:00
|
|
|
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
|
2007-01-26 21:22:28 +00:00
|
|
|
if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
|
|
|
|
unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
|
2007-01-26 14:34:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
|
2006-08-08 02:23:42 +00:00
|
|
|
DAG.getConstant(LabelID, MVT::i32)));
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
|
2005-11-16 07:22:30 +00:00
|
|
|
return 0;
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
case Intrinsic::dbg_region_end: {
|
2007-01-26 21:22:28 +00:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-23 18:06:46 +00:00
|
|
|
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
|
2007-01-26 21:22:28 +00:00
|
|
|
if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
|
|
|
|
unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
|
2007-01-26 14:34:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
|
2006-08-08 02:23:42 +00:00
|
|
|
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
|
2005-11-16 07:22:30 +00:00
|
|
|
return 0;
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
case Intrinsic::dbg_func_start: {
|
2007-01-26 21:22:28 +00:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-23 18:06:46 +00:00
|
|
|
DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
|
2007-01-26 21:22:28 +00:00
|
|
|
if (MMI && FSI.getSubprogram() &&
|
|
|
|
MMI->Verify(FSI.getSubprogram())) {
|
|
|
|
unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
|
2007-01-26 14:34:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
|
2006-08-08 02:23:42 +00:00
|
|
|
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
|
2005-11-16 07:22:30 +00:00
|
|
|
return 0;
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
case Intrinsic::dbg_declare: {
|
2007-01-26 21:22:28 +00:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-23 18:06:46 +00:00
|
|
|
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
|
2007-01-26 21:22:28 +00:00
|
|
|
if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
|
2006-03-24 09:50:27 +00:00
|
|
|
SDOperand AddressOp = getValue(DI.getAddress());
|
2006-08-08 02:23:42 +00:00
|
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
|
2007-01-26 21:22:28 +00:00
|
|
|
MMI->RecordVariable(DI.getVariable(), FI->getIndex());
|
2006-03-23 18:06:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
|
2007-02-21 22:53:45 +00:00
|
|
|
case Intrinsic::eh_exception: {
|
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
|
|
|
|
2007-02-22 15:38:06 +00:00
|
|
|
if (MMI) {
|
|
|
|
// Add a label to mark the beginning of the landing pad. Deletion of the
|
|
|
|
// landing pad can thus be detected via the MachineModuleInfo.
|
|
|
|
unsigned LabelID = MMI->addLandingPad(CurMBB);
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
|
|
|
|
DAG.getConstant(LabelID, MVT::i32)));
|
|
|
|
|
|
|
|
// Mark exception register as live in.
|
|
|
|
unsigned Reg = TLI.getExceptionAddressRegister();
|
|
|
|
if (Reg) CurMBB->addLiveIn(Reg);
|
|
|
|
|
|
|
|
// Insert the EXCEPTIONADDR instruction.
|
|
|
|
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
|
|
|
|
SDOperand Ops[1];
|
|
|
|
Ops[0] = DAG.getRoot();
|
|
|
|
SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
|
|
|
|
setValue(&I, Op);
|
|
|
|
DAG.setRoot(Op.getValue(1));
|
2007-02-24 09:45:44 +00:00
|
|
|
} else {
|
2007-02-28 18:37:04 +00:00
|
|
|
setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
|
2007-02-22 15:38:06 +00:00
|
|
|
}
|
2007-02-21 22:53:45 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-03-01 20:24:30 +00:00
|
|
|
case Intrinsic::eh_selector:
|
|
|
|
case Intrinsic::eh_filter:{
|
2007-02-21 22:53:45 +00:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
|
|
|
|
2007-02-22 15:38:06 +00:00
|
|
|
if (MMI) {
|
|
|
|
// Inform the MachineModuleInfo of the personality for this landing pad.
|
2007-02-22 16:10:05 +00:00
|
|
|
ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(2));
|
|
|
|
assert(CE && CE->getOpcode() == Instruction::BitCast &&
|
|
|
|
isa<Function>(CE->getOperand(0)) &&
|
|
|
|
"Personality should be a function");
|
|
|
|
MMI->addPersonality(CurMBB, cast<Function>(CE->getOperand(0)));
|
2007-03-01 20:24:30 +00:00
|
|
|
if (Intrinsic == Intrinsic::eh_filter)
|
|
|
|
MMI->setIsFilterLandingPad(CurMBB);
|
2007-02-21 22:53:45 +00:00
|
|
|
|
2007-02-22 15:38:06 +00:00
|
|
|
// Gather all the type infos for this landing pad and pass them along to
|
|
|
|
// MachineModuleInfo.
|
|
|
|
std::vector<GlobalVariable *> TyInfo;
|
|
|
|
for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
|
2007-02-22 16:10:05 +00:00
|
|
|
ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(i));
|
|
|
|
if (CE && CE->getOpcode() == Instruction::BitCast &&
|
|
|
|
isa<GlobalVariable>(CE->getOperand(0))) {
|
|
|
|
TyInfo.push_back(cast<GlobalVariable>(CE->getOperand(0)));
|
|
|
|
} else {
|
|
|
|
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i));
|
|
|
|
assert(CI && CI->getZExtValue() == 0 &&
|
|
|
|
"TypeInfo must be a global variable typeinfo or NULL");
|
|
|
|
TyInfo.push_back(NULL);
|
2007-02-22 15:38:06 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
MMI->addCatchTypeInfo(CurMBB, TyInfo);
|
|
|
|
|
|
|
|
// Mark exception selector register as live in.
|
|
|
|
unsigned Reg = TLI.getExceptionSelectorRegister();
|
|
|
|
if (Reg) CurMBB->addLiveIn(Reg);
|
|
|
|
|
|
|
|
// Insert the EHSELECTION instruction.
|
2007-02-28 18:37:04 +00:00
|
|
|
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
|
2007-02-22 15:38:06 +00:00
|
|
|
SDOperand Ops[2];
|
|
|
|
Ops[0] = getValue(I.getOperand(1));
|
|
|
|
Ops[1] = getRoot();
|
|
|
|
SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
|
|
|
|
setValue(&I, Op);
|
|
|
|
DAG.setRoot(Op.getValue(1));
|
2007-02-24 09:45:44 +00:00
|
|
|
} else {
|
2007-02-28 18:37:04 +00:00
|
|
|
setValue(&I, DAG.getConstant(0, MVT::i32));
|
2007-02-21 22:53:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
case Intrinsic::eh_typeid_for: {
|
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2007-02-22 15:38:06 +00:00
|
|
|
|
|
|
|
if (MMI) {
|
|
|
|
// Find the type id for the given typeinfo.
|
|
|
|
GlobalVariable *GV = NULL;
|
2007-02-22 16:10:05 +00:00
|
|
|
ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(1));
|
|
|
|
if (CE && CE->getOpcode() == Instruction::BitCast &&
|
|
|
|
isa<GlobalVariable>(CE->getOperand(0))) {
|
|
|
|
GV = cast<GlobalVariable>(CE->getOperand(0));
|
|
|
|
} else {
|
|
|
|
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
|
|
|
|
assert(CI && CI->getZExtValue() == 0 &&
|
|
|
|
"TypeInfo must be a global variable typeinfo or NULL");
|
|
|
|
GV = NULL;
|
2007-02-21 22:53:45 +00:00
|
|
|
}
|
2007-02-22 15:38:06 +00:00
|
|
|
|
|
|
|
unsigned TypeID = MMI->getTypeIDFor(GV);
|
|
|
|
setValue(&I, DAG.getConstant(TypeID, MVT::i32));
|
2007-02-24 09:45:44 +00:00
|
|
|
} else {
|
|
|
|
setValue(&I, DAG.getConstant(0, MVT::i32));
|
2007-02-21 22:53:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:12:35 +00:00
|
|
|
case Intrinsic::sqrt_f32:
|
|
|
|
case Intrinsic::sqrt_f64:
|
2005-11-09 19:44:01 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FSQRT,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2006-09-09 06:03:30 +00:00
|
|
|
case Intrinsic::powi_f32:
|
|
|
|
case Intrinsic::powi_f64:
|
|
|
|
setValue(&I, DAG.getNode(ISD::FPOWI,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2))));
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
case Intrinsic::pcmarker: {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
|
|
|
|
return 0;
|
|
|
|
}
|
2005-11-11 22:48:54 +00:00
|
|
|
case Intrinsic::readcyclecounter: {
|
2006-08-08 02:23:42 +00:00
|
|
|
SDOperand Op = getRoot();
|
2006-08-14 23:53:35 +00:00
|
|
|
SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
|
|
|
|
DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
|
|
|
|
&Op, 1);
|
2005-11-11 22:48:54 +00:00
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
2005-11-11 16:47:30 +00:00
|
|
|
return 0;
|
2005-11-11 22:48:54 +00:00
|
|
|
}
|
2007-04-04 23:48:25 +00:00
|
|
|
case Intrinsic::bit_part_select: {
|
2007-04-05 01:20:18 +00:00
|
|
|
// Currently not implemented: just abort
|
|
|
|
assert(0 && "bit_part_select intrinsic not implemented");
|
|
|
|
abort();
|
2007-04-04 23:48:25 +00:00
|
|
|
}
|
2007-04-01 07:34:11 +00:00
|
|
|
case Intrinsic::bswap:
|
2006-01-14 03:14:10 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::BSWAP,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2007-04-01 07:34:11 +00:00
|
|
|
case Intrinsic::cttz: {
|
|
|
|
SDOperand Arg = getValue(I.getOperand(1));
|
|
|
|
MVT::ValueType Ty = Arg.getValueType();
|
|
|
|
SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
|
|
|
|
if (Ty < MVT::i32)
|
|
|
|
result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
|
|
|
|
else if (Ty > MVT::i32)
|
|
|
|
result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
|
|
|
|
setValue(&I, result);
|
2005-11-09 19:44:01 +00:00
|
|
|
return 0;
|
2007-04-01 07:34:11 +00:00
|
|
|
}
|
|
|
|
case Intrinsic::ctlz: {
|
|
|
|
SDOperand Arg = getValue(I.getOperand(1));
|
|
|
|
MVT::ValueType Ty = Arg.getValueType();
|
|
|
|
SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
|
|
|
|
if (Ty < MVT::i32)
|
|
|
|
result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
|
|
|
|
else if (Ty > MVT::i32)
|
|
|
|
result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
|
|
|
|
setValue(&I, result);
|
2005-11-09 19:44:01 +00:00
|
|
|
return 0;
|
2007-04-01 07:34:11 +00:00
|
|
|
}
|
|
|
|
case Intrinsic::ctpop: {
|
|
|
|
SDOperand Arg = getValue(I.getOperand(1));
|
|
|
|
MVT::ValueType Ty = Arg.getValueType();
|
|
|
|
SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
|
|
|
|
if (Ty < MVT::i32)
|
|
|
|
result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
|
|
|
|
else if (Ty > MVT::i32)
|
|
|
|
result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
|
|
|
|
setValue(&I, result);
|
2005-11-09 19:44:01 +00:00
|
|
|
return 0;
|
2007-04-01 07:34:11 +00:00
|
|
|
}
|
2006-01-13 02:50:02 +00:00
|
|
|
case Intrinsic::stacksave: {
|
2006-08-08 02:23:42 +00:00
|
|
|
SDOperand Op = getRoot();
|
2006-08-14 23:53:35 +00:00
|
|
|
SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
|
|
|
|
DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
|
2006-01-13 02:50:02 +00:00
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
|
|
|
return 0;
|
|
|
|
}
|
2006-01-23 05:22:07 +00:00
|
|
|
case Intrinsic::stackrestore: {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
|
2006-01-13 02:50:02 +00:00
|
|
|
return 0;
|
2006-01-23 05:22:07 +00:00
|
|
|
}
|
2005-12-12 22:51:16 +00:00
|
|
|
case Intrinsic::prefetch:
|
|
|
|
// FIXME: Currently discarding prefetches.
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-02-23 21:45:01 +00:00
|
|
|
void SelectionDAGLowering::LowerCallTo(Instruction &I,
|
|
|
|
const Type *CalledValueTy,
|
|
|
|
unsigned CallingConv,
|
|
|
|
bool IsTailCall,
|
2007-02-22 15:38:06 +00:00
|
|
|
SDOperand Callee, unsigned OpIdx) {
|
2007-02-23 21:45:01 +00:00
|
|
|
const PointerType *PT = cast<PointerType>(CalledValueTy);
|
2007-02-22 15:38:06 +00:00
|
|
|
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
2007-04-09 06:17:21 +00:00
|
|
|
const ParamAttrsList *Attrs = FTy->getParamAttrs();
|
2007-02-22 15:38:06 +00:00
|
|
|
|
|
|
|
TargetLowering::ArgListTy Args;
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
|
|
|
Args.reserve(I.getNumOperands());
|
|
|
|
for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
Value *Arg = I.getOperand(i);
|
|
|
|
SDOperand ArgNode = getValue(Arg);
|
|
|
|
Entry.Node = ArgNode; Entry.Ty = Arg->getType();
|
2007-04-09 06:17:21 +00:00
|
|
|
Entry.isSExt = Attrs && Attrs->paramHasAttr(i, SExtAttribute);
|
|
|
|
Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ZExtAttribute);
|
|
|
|
Entry.isInReg = Attrs && Attrs->paramHasAttr(i, InRegAttribute);
|
|
|
|
Entry.isSRet = Attrs && Attrs->paramHasAttr(i, StructRetAttribute);
|
2007-02-22 15:38:06 +00:00
|
|
|
Args.push_back(Entry);
|
|
|
|
}
|
|
|
|
|
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
|
|
|
TLI.LowerCallTo(getRoot(), I.getType(),
|
2007-04-09 06:17:21 +00:00
|
|
|
Attrs && Attrs->paramHasAttr(0, SExtAttribute),
|
2007-02-23 21:45:01 +00:00
|
|
|
FTy->isVarArg(), CallingConv, IsTailCall,
|
2007-02-22 15:38:06 +00:00
|
|
|
Callee, Args, DAG);
|
|
|
|
if (I.getType() != Type::VoidTy)
|
|
|
|
setValue(&I, Result.first);
|
|
|
|
DAG.setRoot(Result.second);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitCall(CallInst &I) {
|
2005-01-08 22:48:57 +00:00
|
|
|
const char *RenameFn = 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
if (Function *F = I.getCalledFunction()) {
|
2007-01-30 20:08:39 +00:00
|
|
|
if (F->isDeclaration())
|
2005-11-09 19:44:01 +00:00
|
|
|
if (unsigned IID = F->getIntrinsicID()) {
|
|
|
|
RenameFn = visitIntrinsicCall(I, IID);
|
|
|
|
if (!RenameFn)
|
|
|
|
return;
|
|
|
|
} else { // Not an LLVM intrinsic.
|
|
|
|
const std::string &Name = F->getName();
|
2006-03-05 05:09:38 +00:00
|
|
|
if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
|
|
|
|
if (I.getNumOperands() == 3 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType() &&
|
|
|
|
I.getType() == I.getOperand(2)->getType()) {
|
|
|
|
SDOperand LHS = getValue(I.getOperand(1));
|
|
|
|
SDOperand RHS = getValue(I.getOperand(2));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
|
|
|
|
LHS, RHS));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
|
2005-04-02 05:26:53 +00:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
2005-11-09 19:44:01 +00:00
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
2005-04-02 05:26:53 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
} else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
|
2005-04-30 04:43:14 +00:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
2006-02-14 05:39:35 +00:00
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
2005-11-09 19:44:01 +00:00
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
2005-04-30 04:43:14 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
} else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
|
2005-04-30 04:43:14 +00:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
2006-02-14 05:39:35 +00:00
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
2005-11-09 19:44:01 +00:00
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
2005-04-30 04:43:14 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2005-04-02 05:26:53 +00:00
|
|
|
}
|
2006-01-26 22:24:51 +00:00
|
|
|
} else if (isa<InlineAsm>(I.getOperand(0))) {
|
|
|
|
visitInlineAsm(I);
|
|
|
|
return;
|
2005-11-09 19:44:01 +00:00
|
|
|
}
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-08 22:48:57 +00:00
|
|
|
SDOperand Callee;
|
|
|
|
if (!RenameFn)
|
|
|
|
Callee = getValue(I.getOperand(0));
|
|
|
|
else
|
|
|
|
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
|
2007-02-22 15:38:06 +00:00
|
|
|
|
2007-02-23 21:45:01 +00:00
|
|
|
LowerCallTo(I, I.getCalledValue()->getType(),
|
|
|
|
I.getCallingConv(),
|
|
|
|
I.isTailCall(),
|
|
|
|
Callee,
|
|
|
|
1);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2007-02-22 15:38:06 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
|
2006-02-23 20:06:57 +00:00
|
|
|
SDOperand &Chain, SDOperand &Flag)const{
|
2006-02-22 22:37:12 +00:00
|
|
|
SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
|
|
|
|
Chain = Val.getValue(1);
|
|
|
|
Flag = Val.getValue(2);
|
|
|
|
|
|
|
|
// If the result was expanded, copy from the top part.
|
|
|
|
if (Regs.size() > 1) {
|
|
|
|
assert(Regs.size() == 2 &&
|
|
|
|
"Cannot expand to more than 2 elts yet!");
|
|
|
|
SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
|
2006-10-04 22:23:53 +00:00
|
|
|
Chain = Hi.getValue(1);
|
|
|
|
Flag = Hi.getValue(2);
|
2006-02-23 20:06:57 +00:00
|
|
|
if (DAG.getTargetLoweringInfo().isLittleEndian())
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
|
|
|
|
else
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
|
2006-02-22 22:37:12 +00:00
|
|
|
}
|
|
|
|
|
2006-06-08 18:22:48 +00:00
|
|
|
// Otherwise, if the return value was promoted or extended, truncate it to the
|
2006-02-22 22:37:12 +00:00
|
|
|
// appropriate type.
|
|
|
|
if (RegVT == ValueVT)
|
|
|
|
return Val;
|
|
|
|
|
2007-03-25 05:00:54 +00:00
|
|
|
if (MVT::isVector(RegVT)) {
|
|
|
|
assert(ValueVT == MVT::Vector && "Unknown vector conversion!");
|
|
|
|
return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
|
|
|
|
DAG.getConstant(MVT::getVectorNumElements(RegVT),
|
|
|
|
MVT::i32),
|
|
|
|
DAG.getValueType(MVT::getVectorBaseType(RegVT)));
|
|
|
|
}
|
|
|
|
|
2006-06-08 18:22:48 +00:00
|
|
|
if (MVT::isInteger(RegVT)) {
|
|
|
|
if (ValueVT < RegVT)
|
|
|
|
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
|
|
|
|
else
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
|
|
|
|
}
|
2007-03-25 05:00:54 +00:00
|
|
|
|
|
|
|
assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT));
|
|
|
|
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
|
2006-02-22 22:37:12 +00:00
|
|
|
}
|
|
|
|
|
2006-02-23 19:21:04 +00:00
|
|
|
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
|
|
|
|
/// specified value into the registers specified by this object. This uses
|
|
|
|
/// Chain/Flag as the input and updates them for the output Chain/Flag.
|
|
|
|
void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
|
2006-06-15 08:11:54 +00:00
|
|
|
SDOperand &Chain, SDOperand &Flag,
|
|
|
|
MVT::ValueType PtrVT) const {
|
2006-02-23 19:21:04 +00:00
|
|
|
if (Regs.size() == 1) {
|
|
|
|
// If there is a single register and the types differ, this must be
|
|
|
|
// a promotion.
|
|
|
|
if (RegVT != ValueVT) {
|
2007-03-25 05:00:54 +00:00
|
|
|
if (MVT::isVector(RegVT)) {
|
|
|
|
assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?");
|
|
|
|
Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
|
2007-04-09 05:31:20 +00:00
|
|
|
} else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) {
|
2006-06-08 18:27:11 +00:00
|
|
|
if (RegVT < ValueVT)
|
|
|
|
Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
|
|
|
|
else
|
|
|
|
Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
|
2007-04-09 05:31:20 +00:00
|
|
|
} else if (MVT::isFloatingPoint(RegVT) &&
|
|
|
|
MVT::isFloatingPoint(Val.getValueType())) {
|
2006-02-23 19:21:04 +00:00
|
|
|
Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
|
2007-04-09 05:31:20 +00:00
|
|
|
} else if (MVT::getSizeInBits(RegVT) ==
|
|
|
|
MVT::getSizeInBits(Val.getValueType())) {
|
|
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val);
|
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown mismatch!");
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
}
|
|
|
|
Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
} else {
|
2006-02-23 20:06:57 +00:00
|
|
|
std::vector<unsigned> R(Regs);
|
|
|
|
if (!DAG.getTargetLoweringInfo().isLittleEndian())
|
|
|
|
std::reverse(R.begin(), R.end());
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = R.size(); i != e; ++i) {
|
2006-02-23 19:21:04 +00:00
|
|
|
SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
|
2006-06-15 08:11:54 +00:00
|
|
|
DAG.getConstant(i, PtrVT));
|
2006-02-23 20:06:57 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
|
2006-02-23 19:21:04 +00:00
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
2006-02-23 19:21:04 +00:00
|
|
|
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
|
|
|
|
/// operand list. This adds the code marker and includes the number of
|
|
|
|
/// values added into it.
|
|
|
|
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
|
2006-02-23 20:06:57 +00:00
|
|
|
std::vector<SDOperand> &Ops) const {
|
2007-04-09 00:33:58 +00:00
|
|
|
MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
|
|
|
|
Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
|
2006-02-23 19:21:04 +00:00
|
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(Regs[i], RegVT));
|
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
|
|
|
/// isAllocatableRegister - If the specified register is safe to allocate,
|
|
|
|
/// i.e. it isn't a stack pointer or some other special register, return the
|
|
|
|
/// register class for the register. Otherwise, return null.
|
|
|
|
static const TargetRegisterClass *
|
2006-02-22 23:09:03 +00:00
|
|
|
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
|
|
|
|
const TargetLowering &TLI, const MRegisterInfo *MRI) {
|
2006-04-02 00:24:45 +00:00
|
|
|
MVT::ValueType FoundVT = MVT::Other;
|
|
|
|
const TargetRegisterClass *FoundRC = 0;
|
2006-02-22 23:09:03 +00:00
|
|
|
for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
|
|
|
|
E = MRI->regclass_end(); RCI != E; ++RCI) {
|
2006-04-02 00:24:45 +00:00
|
|
|
MVT::ValueType ThisVT = MVT::Other;
|
|
|
|
|
2006-02-22 23:09:03 +00:00
|
|
|
const TargetRegisterClass *RC = *RCI;
|
|
|
|
// If none of the the value types for this register class are valid, we
|
|
|
|
// can't use it. For example, 64-bit reg classes on 32-bit targets.
|
|
|
|
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (TLI.isTypeLegal(*I)) {
|
2006-04-02 00:24:45 +00:00
|
|
|
// If we have already found this register in a different register class,
|
|
|
|
// choose the one with the largest VT specified. For example, on
|
|
|
|
// PowerPC, we favor f64 register classes over f32.
|
|
|
|
if (FoundVT == MVT::Other ||
|
|
|
|
MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
|
|
|
|
ThisVT = *I;
|
|
|
|
break;
|
|
|
|
}
|
2006-02-22 23:09:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-02 00:24:45 +00:00
|
|
|
if (ThisVT == MVT::Other) continue;
|
2006-02-22 23:09:03 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// NOTE: This isn't ideal. In particular, this might allocate the
|
|
|
|
// frame pointer in functions that need it (due to them not being taken
|
|
|
|
// out of allocation, because a variable sized allocation hasn't been seen
|
|
|
|
// yet). This is a slight code pessimization, but should still work.
|
2006-02-22 23:09:03 +00:00
|
|
|
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
|
|
|
|
E = RC->allocation_order_end(MF); I != E; ++I)
|
2006-04-02 00:24:45 +00:00
|
|
|
if (*I == Reg) {
|
|
|
|
// We found a matching register class. Keep looking at others in case
|
|
|
|
// we find one with larger registers that this physreg is also in.
|
|
|
|
FoundRC = RC;
|
|
|
|
FoundVT = ThisVT;
|
|
|
|
break;
|
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
}
|
2006-04-02 00:24:45 +00:00
|
|
|
return FoundRC;
|
2006-02-22 22:37:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
RegsForValue SelectionDAGLowering::
|
|
|
|
GetRegistersForValue(const std::string &ConstrCode,
|
|
|
|
MVT::ValueType VT, bool isOutReg, bool isInReg,
|
|
|
|
std::set<unsigned> &OutputRegs,
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
std::set<unsigned> &InputRegs) {
|
2006-02-22 22:37:12 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> PhysReg =
|
|
|
|
TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
|
|
|
|
std::vector<unsigned> Regs;
|
|
|
|
|
|
|
|
unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
|
|
|
|
MVT::ValueType RegVT;
|
|
|
|
MVT::ValueType ValueVT = VT;
|
|
|
|
|
2006-11-02 01:41:49 +00:00
|
|
|
// If this is a constraint for a specific physical register, like {r17},
|
|
|
|
// assign it now.
|
2006-02-22 22:37:12 +00:00
|
|
|
if (PhysReg.first) {
|
|
|
|
if (VT == MVT::Other)
|
|
|
|
ValueVT = *PhysReg.second->vt_begin();
|
2006-06-08 18:22:48 +00:00
|
|
|
|
|
|
|
// Get the actual register value type. This is important, because the user
|
|
|
|
// may have asked for (e.g.) the AX register in i32 type. We need to
|
|
|
|
// remember that AX is actually i16 to get the right extension.
|
|
|
|
RegVT = *PhysReg.second->vt_begin();
|
2006-02-22 22:37:12 +00:00
|
|
|
|
|
|
|
// This is a explicit reference to a physical register.
|
|
|
|
Regs.push_back(PhysReg.first);
|
|
|
|
|
|
|
|
// If this is an expanded reference, add the rest of the regs to Regs.
|
|
|
|
if (NumRegs != 1) {
|
|
|
|
TargetRegisterClass::iterator I = PhysReg.second->begin();
|
|
|
|
TargetRegisterClass::iterator E = PhysReg.second->end();
|
|
|
|
for (; *I != PhysReg.first; ++I)
|
|
|
|
assert(I != E && "Didn't find reg!");
|
|
|
|
|
|
|
|
// Already added the first reg.
|
|
|
|
--NumRegs; ++I;
|
|
|
|
for (; NumRegs; --NumRegs, ++I) {
|
|
|
|
assert(I != E && "Ran out of registers to allocate!");
|
|
|
|
Regs.push_back(*I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return RegsForValue(Regs, RegVT, ValueVT);
|
|
|
|
}
|
|
|
|
|
2006-11-02 01:41:49 +00:00
|
|
|
// Otherwise, if this was a reference to an LLVM register class, create vregs
|
|
|
|
// for this reference.
|
|
|
|
std::vector<unsigned> RegClassRegs;
|
|
|
|
if (PhysReg.second) {
|
|
|
|
// If this is an early clobber or tied register, our regalloc doesn't know
|
|
|
|
// how to maintain the constraint. If it isn't, go ahead and create vreg
|
|
|
|
// and let the regalloc do the right thing.
|
|
|
|
if (!isOutReg || !isInReg) {
|
|
|
|
if (VT == MVT::Other)
|
|
|
|
ValueVT = *PhysReg.second->vt_begin();
|
|
|
|
RegVT = *PhysReg.second->vt_begin();
|
|
|
|
|
|
|
|
// Create the appropriate number of virtual registers.
|
|
|
|
SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
|
|
|
|
for (; NumRegs; --NumRegs)
|
|
|
|
Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
|
|
|
|
|
|
|
|
return RegsForValue(Regs, RegVT, ValueVT);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we can't allocate it. Let the code below figure out how to
|
|
|
|
// maintain these constraints.
|
|
|
|
RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
|
|
|
|
|
|
|
|
} else {
|
|
|
|
// This is a reference to a register class that doesn't directly correspond
|
|
|
|
// to an LLVM register class. Allocate NumRegs consecutive, available,
|
|
|
|
// registers from the class.
|
|
|
|
RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
|
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
|
|
|
|
MachineFunction &MF = *CurMBB->getParent();
|
2006-02-22 22:37:12 +00:00
|
|
|
unsigned NumAllocated = 0;
|
|
|
|
for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
|
|
|
|
unsigned Reg = RegClassRegs[i];
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// See if this register is available.
|
2006-02-22 22:37:12 +00:00
|
|
|
if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
|
|
|
|
(isInReg && InputRegs.count(Reg))) { // Already used.
|
|
|
|
// Make sure we find consecutive registers.
|
|
|
|
NumAllocated = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// Check to see if this register is allocatable (i.e. don't give out the
|
|
|
|
// stack pointer).
|
2006-02-22 23:09:03 +00:00
|
|
|
const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
|
2006-02-22 22:37:12 +00:00
|
|
|
if (!RC) {
|
|
|
|
// Make sure we find consecutive registers.
|
|
|
|
NumAllocated = 0;
|
|
|
|
continue;
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
}
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// Okay, this register is good, we can use it.
|
|
|
|
++NumAllocated;
|
|
|
|
|
2007-04-06 17:47:14 +00:00
|
|
|
// If we allocated enough consecutive registers, succeed.
|
2006-02-22 22:37:12 +00:00
|
|
|
if (NumAllocated == NumRegs) {
|
|
|
|
unsigned RegStart = (i-NumAllocated)+1;
|
|
|
|
unsigned RegEnd = i+1;
|
|
|
|
// Mark all of the allocated registers used.
|
|
|
|
for (unsigned i = RegStart; i != RegEnd; ++i) {
|
|
|
|
unsigned Reg = RegClassRegs[i];
|
|
|
|
Regs.push_back(Reg);
|
|
|
|
if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
|
|
|
|
if (isInReg) InputRegs.insert(Reg); // Mark reg used.
|
|
|
|
}
|
|
|
|
|
|
|
|
return RegsForValue(Regs, *RC->vt_begin(), VT);
|
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
|
|
|
// Otherwise, we couldn't allocate enough registers for this.
|
|
|
|
return RegsForValue();
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
}
|
|
|
|
|
2007-01-29 23:45:14 +00:00
|
|
|
/// getConstraintGenerality - Return an integer indicating how general CT is.
|
|
|
|
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
|
|
|
|
switch (CT) {
|
|
|
|
default: assert(0 && "Unknown constraint type!");
|
|
|
|
case TargetLowering::C_Other:
|
|
|
|
case TargetLowering::C_Unknown:
|
|
|
|
return 0;
|
|
|
|
case TargetLowering::C_Register:
|
|
|
|
return 1;
|
|
|
|
case TargetLowering::C_RegisterClass:
|
|
|
|
return 2;
|
|
|
|
case TargetLowering::C_Memory:
|
|
|
|
return 3;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static std::string GetMostGeneralConstraint(std::vector<std::string> &C,
|
|
|
|
const TargetLowering &TLI) {
|
|
|
|
assert(!C.empty() && "Must have at least one constraint");
|
|
|
|
if (C.size() == 1) return C[0];
|
|
|
|
|
|
|
|
std::string *Current = &C[0];
|
|
|
|
// If we have multiple constraints, try to pick the most general one ahead
|
|
|
|
// of time. This isn't a wonderful solution, but handles common cases.
|
2007-03-25 02:14:49 +00:00
|
|
|
TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
|
2007-01-29 23:45:14 +00:00
|
|
|
for (unsigned j = 1, e = C.size(); j != e; ++j) {
|
2007-03-25 02:14:49 +00:00
|
|
|
TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
|
2007-01-29 23:45:14 +00:00
|
|
|
if (getConstraintGenerality(ThisFlavor) >
|
|
|
|
getConstraintGenerality(Flavor)) {
|
|
|
|
// This constraint letter is more general than the previous one,
|
|
|
|
// use it.
|
|
|
|
Flavor = ThisFlavor;
|
|
|
|
Current = &C[j];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return *Current;
|
|
|
|
}
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
|
2006-01-26 22:24:51 +00:00
|
|
|
/// visitInlineAsm - Handle a call to an InlineAsm object.
|
|
|
|
///
|
|
|
|
void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
|
|
|
|
InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
|
|
|
|
|
|
|
|
SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
|
|
|
|
MVT::Other);
|
|
|
|
|
2006-02-01 01:28:23 +00:00
|
|
|
std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
|
2006-02-22 00:56:39 +00:00
|
|
|
std::vector<MVT::ValueType> ConstraintVTs;
|
2006-01-26 22:24:51 +00:00
|
|
|
|
|
|
|
/// AsmNodeOperands - A list of pairs. The first element is a register, the
|
|
|
|
/// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
|
|
|
|
/// if it is a def of that register.
|
|
|
|
std::vector<SDOperand> AsmNodeOperands;
|
|
|
|
AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
|
|
|
|
AsmNodeOperands.push_back(AsmStr);
|
|
|
|
|
|
|
|
SDOperand Chain = getRoot();
|
|
|
|
SDOperand Flag;
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// We fully assign registers here at isel time. This is not optimal, but
|
|
|
|
// should work. For register classes that correspond to LLVM classes, we
|
|
|
|
// could let the LLVM RA do its thing, but we currently don't. Do a prepass
|
|
|
|
// over the constraints, collecting fixed registers that we know we can't use.
|
|
|
|
std::set<unsigned> OutputRegs, InputRegs;
|
2006-02-22 00:56:39 +00:00
|
|
|
unsigned OpNum = 1;
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
|
2007-01-29 23:45:14 +00:00
|
|
|
std::string ConstraintCode =
|
|
|
|
GetMostGeneralConstraint(Constraints[i].Codes, TLI);
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
|
2006-02-22 00:56:39 +00:00
|
|
|
MVT::ValueType OpVT;
|
|
|
|
|
|
|
|
// Compute the value type for each operand and add it to ConstraintVTs.
|
|
|
|
switch (Constraints[i].Type) {
|
|
|
|
case InlineAsm::isOutput:
|
|
|
|
if (!Constraints[i].isIndirectOutput) {
|
|
|
|
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
|
|
|
|
OpVT = TLI.getValueType(I.getType());
|
|
|
|
} else {
|
2006-02-27 23:45:39 +00:00
|
|
|
const Type *OpTy = I.getOperand(OpNum)->getType();
|
2006-02-22 00:56:39 +00:00
|
|
|
OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
|
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case InlineAsm::isInput:
|
|
|
|
OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
|
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
break;
|
|
|
|
case InlineAsm::isClobber:
|
|
|
|
OpVT = MVT::Other;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ConstraintVTs.push_back(OpVT);
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
|
|
|
|
continue; // Not assigned a fixed reg.
|
2006-02-22 00:56:39 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// Build a list of regs that this operand uses. This always has a single
|
|
|
|
// element for promoted/expanded operands.
|
|
|
|
RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
|
|
|
|
false, false,
|
|
|
|
OutputRegs, InputRegs);
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
|
|
|
|
switch (Constraints[i].Type) {
|
|
|
|
case InlineAsm::isOutput:
|
|
|
|
// We can't assign any other output to this register.
|
2006-02-22 22:37:12 +00:00
|
|
|
OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// If this is an early-clobber output, it cannot be assigned to the same
|
|
|
|
// value as the input reg.
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
|
2006-02-22 22:37:12 +00:00
|
|
|
InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
break;
|
2006-02-22 00:56:39 +00:00
|
|
|
case InlineAsm::isInput:
|
|
|
|
// We can't assign any other input to this register.
|
2006-02-22 22:37:12 +00:00
|
|
|
InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
2006-02-22 00:56:39 +00:00
|
|
|
break;
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
case InlineAsm::isClobber:
|
|
|
|
// Clobbered regs cannot be used as inputs or outputs.
|
2006-02-22 22:37:12 +00:00
|
|
|
InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
|
|
|
OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-02-01 01:28:23 +00:00
|
|
|
|
2006-02-21 23:12:12 +00:00
|
|
|
// Loop over all of the inputs, copying the operand values into the
|
|
|
|
// appropriate registers and processing the output regs.
|
2006-02-22 22:37:12 +00:00
|
|
|
RegsForValue RetValRegs;
|
|
|
|
std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
|
2006-02-22 00:56:39 +00:00
|
|
|
OpNum = 1;
|
2006-02-21 23:12:12 +00:00
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
|
2007-01-29 23:45:14 +00:00
|
|
|
std::string ConstraintCode =
|
|
|
|
GetMostGeneralConstraint(Constraints[i].Codes, TLI);
|
2006-02-22 00:56:39 +00:00
|
|
|
|
2006-02-01 01:28:23 +00:00
|
|
|
switch (Constraints[i].Type) {
|
|
|
|
case InlineAsm::isOutput: {
|
2006-02-27 23:45:39 +00:00
|
|
|
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
|
|
|
|
if (ConstraintCode.size() == 1) // not a physreg name.
|
2007-03-25 02:14:49 +00:00
|
|
|
CTy = TLI.getConstraintType(ConstraintCode);
|
2006-02-27 23:45:39 +00:00
|
|
|
|
|
|
|
if (CTy == TargetLowering::C_Memory) {
|
|
|
|
// Memory output.
|
|
|
|
SDOperand InOperandVal = getValue(I.getOperand(OpNum));
|
|
|
|
|
|
|
|
// Check that the operand (the address to store to) isn't a float.
|
|
|
|
if (!MVT::isInteger(InOperandVal.getValueType()))
|
|
|
|
assert(0 && "MATCH FAIL!");
|
|
|
|
|
|
|
|
if (!Constraints[i].isIndirectOutput)
|
|
|
|
assert(0 && "MATCH FAIL!");
|
|
|
|
|
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
|
|
|
|
// Extend/truncate to the right pointer type if needed.
|
|
|
|
MVT::ValueType PtrType = TLI.getPointerTy();
|
|
|
|
if (InOperandVal.getValueType() < PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
|
|
|
|
else if (InOperandVal.getValueType() > PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
|
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know about this output.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
|
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, this is a register output.
|
|
|
|
assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// If this is an early-clobber output, or if there is an input
|
|
|
|
// constraint that matches this, we need to reserve the input register
|
|
|
|
// so no other inputs allocate to it.
|
|
|
|
bool UsesInputRegister = false;
|
|
|
|
if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
|
|
|
|
UsesInputRegister = true;
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// Copy the output from the appropriate register. Find a register that
|
|
|
|
// we can use.
|
|
|
|
RegsForValue Regs =
|
|
|
|
GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
|
|
|
|
true, UsesInputRegister,
|
|
|
|
OutputRegs, InputRegs);
|
2006-10-31 07:33:13 +00:00
|
|
|
if (Regs.Regs.empty()) {
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "Couldn't allocate output reg for contraint '"
|
|
|
|
<< ConstraintCode << "'!\n";
|
2006-10-31 07:33:13 +00:00
|
|
|
exit(1);
|
|
|
|
}
|
2006-02-01 01:28:23 +00:00
|
|
|
|
|
|
|
if (!Constraints[i].isIndirectOutput) {
|
2006-02-22 22:37:12 +00:00
|
|
|
assert(RetValRegs.Regs.empty() &&
|
2006-02-01 01:28:23 +00:00
|
|
|
"Cannot have multiple output constraints yet!");
|
|
|
|
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
|
2006-02-22 22:37:12 +00:00
|
|
|
RetValRegs = Regs;
|
2006-02-01 01:28:23 +00:00
|
|
|
} else {
|
2006-02-27 23:45:39 +00:00
|
|
|
IndirectStoresToEmit.push_back(std::make_pair(Regs,
|
|
|
|
I.getOperand(OpNum)));
|
2006-02-01 01:28:23 +00:00
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know that this register is
|
|
|
|
// set.
|
2006-02-23 19:21:04 +00:00
|
|
|
Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case InlineAsm::isInput: {
|
2006-02-27 23:45:39 +00:00
|
|
|
SDOperand InOperandVal = getValue(I.getOperand(OpNum));
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
OpNum++; // Consumes a call operand.
|
2006-02-04 02:16:44 +00:00
|
|
|
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
if (isdigit(ConstraintCode[0])) { // Matching constraint?
|
|
|
|
// If this is required to match an output register we have already set,
|
|
|
|
// just use its register.
|
|
|
|
unsigned OperandNo = atoi(ConstraintCode.c_str());
|
2006-02-04 02:16:44 +00:00
|
|
|
|
2006-02-23 19:21:04 +00:00
|
|
|
// Scan until we find the definition we already emitted of this operand.
|
|
|
|
// When we find it, create a RegsForValue operand.
|
|
|
|
unsigned CurOp = 2; // The first operand.
|
|
|
|
for (; OperandNo; --OperandNo) {
|
|
|
|
// Advance to the next operand.
|
|
|
|
unsigned NumOps =
|
|
|
|
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
|
2006-07-20 19:02:21 +00:00
|
|
|
assert(((NumOps & 7) == 2 /*REGDEF*/ ||
|
|
|
|
(NumOps & 7) == 4 /*MEM*/) &&
|
2006-02-23 19:21:04 +00:00
|
|
|
"Skipped past definitions?");
|
|
|
|
CurOp += (NumOps>>3)+1;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned NumOps =
|
|
|
|
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
|
2007-02-01 01:21:12 +00:00
|
|
|
if ((NumOps & 7) == 2 /*REGDEF*/) {
|
|
|
|
// Add NumOps>>3 registers to MatchedRegs.
|
|
|
|
RegsForValue MatchedRegs;
|
|
|
|
MatchedRegs.ValueVT = InOperandVal.getValueType();
|
|
|
|
MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
|
|
|
|
for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
|
|
|
|
unsigned Reg =
|
|
|
|
cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
|
|
|
|
MatchedRegs.Regs.push_back(Reg);
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
|
2007-02-01 01:21:12 +00:00
|
|
|
// Use the produced MatchedRegs object to
|
|
|
|
MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
|
|
|
|
TLI.getPointerTy());
|
|
|
|
MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
|
|
|
|
break;
|
|
|
|
} else {
|
|
|
|
assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
|
|
|
|
assert(0 && "matching constraints for memory operands unimp");
|
2006-02-23 19:21:04 +00:00
|
|
|
}
|
2006-02-24 01:11:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
|
|
|
|
if (ConstraintCode.size() == 1) // not a physreg name.
|
2007-03-25 02:14:49 +00:00
|
|
|
CTy = TLI.getConstraintType(ConstraintCode);
|
2006-02-04 02:16:44 +00:00
|
|
|
|
2006-02-24 01:11:24 +00:00
|
|
|
if (CTy == TargetLowering::C_Other) {
|
2006-10-31 19:41:18 +00:00
|
|
|
InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
|
|
|
|
ConstraintCode[0], DAG);
|
|
|
|
if (!InOperandVal.Val) {
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "Invalid operand for inline asm constraint '"
|
|
|
|
<< ConstraintCode << "'!\n";
|
2006-10-31 19:41:18 +00:00
|
|
|
exit(1);
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
|
2006-02-24 01:11:24 +00:00
|
|
|
// Add information to the INLINEASM node to know about this input.
|
|
|
|
unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
|
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
|
|
|
break;
|
|
|
|
} else if (CTy == TargetLowering::C_Memory) {
|
|
|
|
// Memory input.
|
|
|
|
|
2007-03-08 22:29:47 +00:00
|
|
|
// If the operand is a float, spill to a constant pool entry to get its
|
|
|
|
// address.
|
|
|
|
if (ConstantFP *Val = dyn_cast<ConstantFP>(I.getOperand(OpNum-1)))
|
|
|
|
InOperandVal = DAG.getConstantPool(Val, TLI.getPointerTy());
|
|
|
|
|
2007-03-08 07:07:03 +00:00
|
|
|
if (!MVT::isInteger(InOperandVal.getValueType())) {
|
2007-03-08 22:29:47 +00:00
|
|
|
cerr << "Match failed, cannot handle this yet!\n";
|
|
|
|
InOperandVal.Val->dump();
|
2007-03-08 07:07:03 +00:00
|
|
|
exit(1);
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
|
2006-02-24 01:11:24 +00:00
|
|
|
// Extend/truncate to the right pointer type if needed.
|
|
|
|
MVT::ValueType PtrType = TLI.getPointerTy();
|
|
|
|
if (InOperandVal.getValueType() < PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
|
|
|
|
else if (InOperandVal.getValueType() > PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
|
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know about this input.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
|
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
2006-02-23 19:21:04 +00:00
|
|
|
break;
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
}
|
2006-02-24 01:11:24 +00:00
|
|
|
|
|
|
|
assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
|
|
|
|
|
|
|
|
// Copy the input into the appropriate registers.
|
|
|
|
RegsForValue InRegs =
|
|
|
|
GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
|
|
|
|
false, true, OutputRegs, InputRegs);
|
|
|
|
// FIXME: should be match fail.
|
|
|
|
assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
|
|
|
|
|
2006-06-15 08:11:54 +00:00
|
|
|
InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
|
2006-02-24 01:11:24 +00:00
|
|
|
|
|
|
|
InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
case InlineAsm::isClobber: {
|
|
|
|
RegsForValue ClobberedRegs =
|
|
|
|
GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
|
|
|
|
OutputRegs, InputRegs);
|
|
|
|
// Add the clobbered value to the operand list, so that the register
|
|
|
|
// allocator is aware that the physreg got clobbered.
|
|
|
|
if (!ClobberedRegs.Regs.empty())
|
|
|
|
ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
}
|
2006-01-26 22:24:51 +00:00
|
|
|
|
|
|
|
// Finish up input operands.
|
|
|
|
AsmNodeOperands[0] = Chain;
|
|
|
|
if (Flag.Val) AsmNodeOperands.push_back(Flag);
|
|
|
|
|
2006-08-14 23:53:35 +00:00
|
|
|
Chain = DAG.getNode(ISD::INLINEASM,
|
|
|
|
DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
|
2006-08-08 02:23:42 +00:00
|
|
|
&AsmNodeOperands[0], AsmNodeOperands.size());
|
2006-01-26 22:24:51 +00:00
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
// If this asm returns a register value, copy the result from that register
|
|
|
|
// and set it as the value of the call.
|
2006-02-22 22:37:12 +00:00
|
|
|
if (!RetValRegs.Regs.empty())
|
|
|
|
setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
|
|
|
|
std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
|
|
|
|
|
|
|
|
// Process indirect outputs, first output all of the flagged copies out of
|
|
|
|
// physregs.
|
|
|
|
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
|
2006-02-22 22:37:12 +00:00
|
|
|
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
Value *Ptr = IndirectStoresToEmit[i].second;
|
2006-02-22 22:37:12 +00:00
|
|
|
SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
|
|
|
|
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
}
|
2006-01-26 22:24:51 +00:00
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
// Emit the non-flagged stores from the physregs.
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> OutChains;
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
|
2006-10-05 23:01:46 +00:00
|
|
|
OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
getValue(StoresToEmit[i].second),
|
2006-10-13 21:14:26 +00:00
|
|
|
StoresToEmit[i].second, 0));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
if (!OutChains.empty())
|
2006-08-08 02:23:42 +00:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&OutChains[0], OutChains.size());
|
2006-01-26 22:24:51 +00:00
|
|
|
DAG.setRoot(Chain);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitMalloc(MallocInst &I) {
|
|
|
|
SDOperand Src = getValue(I.getOperand(0));
|
|
|
|
|
|
|
|
MVT::ValueType IntPtr = TLI.getPointerTy();
|
2005-01-22 23:04:37 +00:00
|
|
|
|
|
|
|
if (IntPtr < Src.getValueType())
|
|
|
|
Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
|
|
|
|
else if (IntPtr > Src.getValueType())
|
|
|
|
Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
// Scale the source by the type size.
|
2006-05-03 01:29:57 +00:00
|
|
|
uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
|
2005-01-07 07:47:53 +00:00
|
|
|
Src = DAG.getNode(ISD::MUL, Src.getValueType(),
|
|
|
|
Src, getIntPtrConstant(ElementSize));
|
|
|
|
|
2006-12-31 05:55:36 +00:00
|
|
|
TargetLowering::ArgListTy Args;
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
|
|
|
Entry.Node = Src;
|
|
|
|
Entry.Ty = TLI.getTargetData()->getIntPtrType();
|
|
|
|
Args.push_back(Entry);
|
2005-01-08 19:26:18 +00:00
|
|
|
|
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2006-12-31 05:55:36 +00:00
|
|
|
TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
|
2005-01-08 19:26:18 +00:00
|
|
|
DAG.getExternalSymbol("malloc", IntPtr),
|
|
|
|
Args, DAG);
|
|
|
|
setValue(&I, Result.first); // Pointers always fit in registers
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFree(FreeInst &I) {
|
2006-12-31 05:55:36 +00:00
|
|
|
TargetLowering::ArgListTy Args;
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
|
|
|
Entry.Node = getValue(I.getOperand(0));
|
|
|
|
Entry.Ty = TLI.getTargetData()->getIntPtrType();
|
|
|
|
Args.push_back(Entry);
|
2005-01-07 07:47:53 +00:00
|
|
|
MVT::ValueType IntPtr = TLI.getPointerTy();
|
2005-01-08 19:26:18 +00:00
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2006-12-31 05:55:36 +00:00
|
|
|
TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
|
2005-01-08 19:26:18 +00:00
|
|
|
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-08-26 20:54:47 +00:00
|
|
|
// InsertAtEndOfBasicBlock - This method should be implemented by targets that
|
|
|
|
// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
|
|
|
|
// instructions are special in various ways, which require special support to
|
|
|
|
// insert. The specified MachineInstr is created but not inserted into any
|
|
|
|
// basic blocks, and the scheduler passes ownership of it to this method.
|
|
|
|
MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) {
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "If a target marks an instruction with "
|
|
|
|
<< "'usesCustomDAGSchedInserter', it must implement "
|
|
|
|
<< "TargetLowering::InsertAtEndOfBasicBlock!\n";
|
2005-08-26 20:54:47 +00:00
|
|
|
abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-01-09 00:00:49 +00:00
|
|
|
void SelectionDAGLowering::visitVAStart(CallInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-09 00:00:49 +00:00
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
|
|
|
|
getValue(I.getOperand(0)),
|
|
|
|
DAG.getSrcValue(I.getOperand(0)));
|
|
|
|
setValue(&I, V);
|
|
|
|
DAG.setRoot(V.getValue(1));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVACopy(CallInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(2))));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-12-12 07:27:38 +00:00
|
|
|
/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either
|
|
|
|
/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate.
|
|
|
|
static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg,
|
|
|
|
unsigned &i, SelectionDAG &DAG,
|
|
|
|
TargetLowering &TLI) {
|
|
|
|
if (TLI.getTypeAction(VT) != TargetLowering::Expand)
|
|
|
|
return SDOperand(Arg, i++);
|
|
|
|
|
|
|
|
MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
|
|
|
|
unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
|
|
|
|
if (NumVals == 1) {
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, VT,
|
|
|
|
ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI));
|
|
|
|
} else if (NumVals == 2) {
|
|
|
|
SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
|
|
|
|
SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
|
|
|
|
if (!TLI.isLittleEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
|
|
|
|
} else {
|
|
|
|
// Value scalarized into many values. Unimp for now.
|
|
|
|
assert(0 && "Cannot expand i64 -> i16 yet!");
|
|
|
|
}
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-04-12 16:20:43 +00:00
|
|
|
/// TargetLowering::LowerArguments - This is the default LowerArguments
|
|
|
|
/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
|
2006-05-16 22:53:20 +00:00
|
|
|
/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
|
|
|
|
/// integrated into SDISel.
|
2006-04-12 16:20:43 +00:00
|
|
|
std::vector<SDOperand>
|
|
|
|
TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
|
2007-01-28 13:31:35 +00:00
|
|
|
const FunctionType *FTy = F.getFunctionType();
|
2007-04-09 06:17:21 +00:00
|
|
|
const ParamAttrsList *Attrs = FTy->getParamAttrs();
|
2006-04-12 16:20:43 +00:00
|
|
|
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
|
|
|
|
std::vector<SDOperand> Ops;
|
2006-05-16 06:45:34 +00:00
|
|
|
Ops.push_back(DAG.getRoot());
|
2006-04-12 16:20:43 +00:00
|
|
|
Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
|
|
|
|
Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
|
|
|
|
|
|
|
|
// Add one result value for each formal argument.
|
|
|
|
std::vector<MVT::ValueType> RetVals;
|
2007-01-28 18:01:49 +00:00
|
|
|
unsigned j = 1;
|
2007-01-28 16:04:40 +00:00
|
|
|
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
|
|
|
|
I != E; ++I, ++j) {
|
2006-04-12 16:20:43 +00:00
|
|
|
MVT::ValueType VT = getValueType(I->getType());
|
2007-03-07 16:25:09 +00:00
|
|
|
unsigned Flags = ISD::ParamFlags::NoFlagSet;
|
2007-02-13 13:50:08 +00:00
|
|
|
unsigned OriginalAlignment =
|
2007-02-14 05:52:17 +00:00
|
|
|
getTargetData()->getABITypeAlignment(I->getType());
|
2007-02-13 13:50:08 +00:00
|
|
|
|
2007-02-26 02:56:58 +00:00
|
|
|
// FIXME: Distinguish between a formal with no [sz]ext attribute from one
|
|
|
|
// that is zero extended!
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(j, ZExtAttribute))
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags &= ~(ISD::ParamFlags::SExt);
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(j, SExtAttribute))
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags |= ISD::ParamFlags::SExt;
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(j, InRegAttribute))
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags |= ISD::ParamFlags::InReg;
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(j, StructRetAttribute))
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags |= ISD::ParamFlags::StructReturn;
|
|
|
|
Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
|
2007-02-26 02:56:58 +00:00
|
|
|
|
2006-04-12 16:20:43 +00:00
|
|
|
switch (getTypeAction(VT)) {
|
|
|
|
default: assert(0 && "Unknown type action!");
|
|
|
|
case Legal:
|
|
|
|
RetVals.push_back(VT);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-04-12 16:20:43 +00:00
|
|
|
break;
|
|
|
|
case Promote:
|
|
|
|
RetVals.push_back(getTypeToTransformTo(VT));
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-04-12 16:20:43 +00:00
|
|
|
break;
|
|
|
|
case Expand:
|
|
|
|
if (VT != MVT::Vector) {
|
|
|
|
// If this is a large integer, it needs to be broken up into small
|
|
|
|
// integers. Figure out what the destination type is and how many small
|
|
|
|
// integers it turns into.
|
2006-12-13 20:57:08 +00:00
|
|
|
MVT::ValueType NVT = getTypeToExpandTo(VT);
|
|
|
|
unsigned NumVals = getNumElements(VT);
|
2007-01-28 13:31:35 +00:00
|
|
|
for (unsigned i = 0; i != NumVals; ++i) {
|
2006-04-12 16:20:43 +00:00
|
|
|
RetVals.push_back(NVT);
|
2007-02-13 18:10:13 +00:00
|
|
|
// if it isn't first piece, alignment must be 1
|
2007-03-06 06:10:33 +00:00
|
|
|
if (i > 0)
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
|
|
|
|
(1 << ISD::ParamFlags::OrigAlignmentOffs);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
|
|
|
}
|
2006-04-12 16:20:43 +00:00
|
|
|
} else {
|
|
|
|
// Otherwise, this is a vector type. We only support legal vectors
|
|
|
|
// right now.
|
2007-02-15 02:26:10 +00:00
|
|
|
unsigned NumElems = cast<VectorType>(I->getType())->getNumElements();
|
|
|
|
const Type *EltTy = cast<VectorType>(I->getType())->getElementType();
|
2006-04-27 08:29:42 +00:00
|
|
|
|
2006-04-12 16:20:43 +00:00
|
|
|
// Figure out if there is a Packed type corresponding to this Vector
|
2007-02-15 03:39:18 +00:00
|
|
|
// type. If so, convert to the vector type.
|
2006-04-12 16:20:43 +00:00
|
|
|
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
|
|
|
|
if (TVT != MVT::Other && isTypeLegal(TVT)) {
|
|
|
|
RetVals.push_back(TVT);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-04-12 16:20:43 +00:00
|
|
|
} else {
|
|
|
|
assert(0 && "Don't support illegal by-val vector arguments yet!");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-04-25 23:03:35 +00:00
|
|
|
|
2006-05-16 06:45:34 +00:00
|
|
|
RetVals.push_back(MVT::Other);
|
2006-04-12 16:20:43 +00:00
|
|
|
|
|
|
|
// Create the node.
|
2006-08-14 23:53:35 +00:00
|
|
|
SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
|
|
|
|
DAG.getNodeValueTypes(RetVals), RetVals.size(),
|
2006-08-08 02:23:42 +00:00
|
|
|
&Ops[0], Ops.size()).Val;
|
2006-05-16 06:45:34 +00:00
|
|
|
|
|
|
|
DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
|
2006-04-12 16:20:43 +00:00
|
|
|
|
|
|
|
// Set up the return result vector.
|
|
|
|
Ops.clear();
|
|
|
|
unsigned i = 0;
|
2006-12-31 05:55:36 +00:00
|
|
|
unsigned Idx = 1;
|
|
|
|
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
|
|
|
|
++I, ++Idx) {
|
2006-04-12 16:20:43 +00:00
|
|
|
MVT::ValueType VT = getValueType(I->getType());
|
|
|
|
|
|
|
|
switch (getTypeAction(VT)) {
|
|
|
|
default: assert(0 && "Unknown type action!");
|
|
|
|
case Legal:
|
|
|
|
Ops.push_back(SDOperand(Result, i++));
|
|
|
|
break;
|
|
|
|
case Promote: {
|
|
|
|
SDOperand Op(Result, i++);
|
|
|
|
if (MVT::isInteger(VT)) {
|
2007-04-09 06:17:21 +00:00
|
|
|
if (Attrs && Attrs->paramHasAttr(Idx, SExtAttribute))
|
2007-01-04 22:22:37 +00:00
|
|
|
Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
|
|
|
|
DAG.getValueType(VT));
|
2007-04-09 06:17:21 +00:00
|
|
|
else if (Attrs && Attrs->paramHasAttr(Idx, ZExtAttribute))
|
2007-01-04 22:22:37 +00:00
|
|
|
Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
|
|
|
|
DAG.getValueType(VT));
|
2006-04-12 16:20:43 +00:00
|
|
|
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
|
|
|
|
} else {
|
|
|
|
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
|
|
|
|
Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
|
|
|
|
}
|
|
|
|
Ops.push_back(Op);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Expand:
|
|
|
|
if (VT != MVT::Vector) {
|
2006-12-12 07:27:38 +00:00
|
|
|
// If this is a large integer or a floating point node that needs to be
|
|
|
|
// expanded, it needs to be reassembled from small integers. Figure out
|
|
|
|
// what the source elt type is and how many small integers it is.
|
|
|
|
Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this));
|
2006-04-12 16:20:43 +00:00
|
|
|
} else {
|
|
|
|
// Otherwise, this is a vector type. We only support legal vectors
|
|
|
|
// right now.
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *PTy = cast<VectorType>(I->getType());
|
2006-04-28 05:25:15 +00:00
|
|
|
unsigned NumElems = PTy->getNumElements();
|
|
|
|
const Type *EltTy = PTy->getElementType();
|
2006-04-27 08:29:42 +00:00
|
|
|
|
2006-04-12 16:20:43 +00:00
|
|
|
// Figure out if there is a Packed type corresponding to this Vector
|
2007-02-15 03:39:18 +00:00
|
|
|
// type. If so, convert to the vector type.
|
2006-04-12 16:20:43 +00:00
|
|
|
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
|
2006-05-17 20:49:36 +00:00
|
|
|
if (TVT != MVT::Other && isTypeLegal(TVT)) {
|
2006-04-28 05:25:15 +00:00
|
|
|
SDOperand N = SDOperand(Result, i++);
|
|
|
|
// Handle copies from generic vectors to registers.
|
2006-05-17 20:49:36 +00:00
|
|
|
N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
|
|
|
|
DAG.getConstant(NumElems, MVT::i32),
|
|
|
|
DAG.getValueType(getValueType(EltTy)));
|
|
|
|
Ops.push_back(N);
|
|
|
|
} else {
|
2006-04-12 16:20:43 +00:00
|
|
|
assert(0 && "Don't support illegal by-val vector arguments yet!");
|
2006-05-16 23:39:44 +00:00
|
|
|
abort();
|
2006-04-12 16:20:43 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return Ops;
|
|
|
|
}
|
|
|
|
|
2006-05-16 22:53:20 +00:00
|
|
|
|
2006-12-12 07:27:38 +00:00
|
|
|
/// ExpandScalarCallArgs - Recursively expand call argument node by
|
|
|
|
/// bit_converting it or extract a pair of elements from the larger node.
|
|
|
|
static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg,
|
2007-02-13 13:50:08 +00:00
|
|
|
unsigned Flags,
|
2006-12-12 07:27:38 +00:00
|
|
|
SmallVector<SDOperand, 32> &Ops,
|
|
|
|
SelectionDAG &DAG,
|
2007-02-13 13:50:08 +00:00
|
|
|
TargetLowering &TLI,
|
|
|
|
bool isFirst = true) {
|
|
|
|
|
2006-12-12 07:27:38 +00:00
|
|
|
if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
|
2007-02-13 18:10:13 +00:00
|
|
|
// if it isn't first piece, alignment must be 1
|
2007-02-13 13:50:08 +00:00
|
|
|
if (!isFirst)
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
|
|
|
|
(1 << ISD::ParamFlags::OrigAlignmentOffs);
|
2006-12-12 07:27:38 +00:00
|
|
|
Ops.push_back(Arg);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-12-12 07:27:38 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
|
|
|
|
unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
|
|
|
|
if (NumVals == 1) {
|
|
|
|
Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg);
|
2007-02-13 13:50:08 +00:00
|
|
|
ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst);
|
2006-12-12 07:27:38 +00:00
|
|
|
} else if (NumVals == 2) {
|
|
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
|
|
|
|
DAG.getConstant(0, TLI.getPointerTy()));
|
|
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
|
|
|
|
DAG.getConstant(1, TLI.getPointerTy()));
|
|
|
|
if (!TLI.isLittleEndian())
|
|
|
|
std::swap(Lo, Hi);
|
2007-02-13 13:50:08 +00:00
|
|
|
ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst);
|
|
|
|
ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false);
|
2006-12-12 07:27:38 +00:00
|
|
|
} else {
|
|
|
|
// Value scalarized into many values. Unimp for now.
|
|
|
|
assert(0 && "Cannot expand i64 -> i16 yet!");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-16 22:53:20 +00:00
|
|
|
/// TargetLowering::LowerCallTo - This is the default LowerCallTo
|
|
|
|
/// implementation, which just inserts an ISD::CALL node, which is later custom
|
|
|
|
/// lowered by the target to something concrete. FIXME: When all targets are
|
|
|
|
/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
|
|
|
|
std::pair<SDOperand, SDOperand>
|
2006-12-31 05:55:36 +00:00
|
|
|
TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
|
|
|
|
bool RetTyIsSigned, bool isVarArg,
|
2006-05-16 22:53:20 +00:00
|
|
|
unsigned CallingConv, bool isTailCall,
|
|
|
|
SDOperand Callee,
|
|
|
|
ArgListTy &Args, SelectionDAG &DAG) {
|
2006-08-16 22:57:46 +00:00
|
|
|
SmallVector<SDOperand, 32> Ops;
|
2006-05-16 22:53:20 +00:00
|
|
|
Ops.push_back(Chain); // Op#0 - Chain
|
|
|
|
Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
|
|
|
|
Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
|
|
|
|
Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
|
|
|
// Handle all of the outgoing arguments.
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
2006-12-31 05:55:36 +00:00
|
|
|
MVT::ValueType VT = getValueType(Args[i].Ty);
|
|
|
|
SDOperand Op = Args[i].Node;
|
2007-03-07 16:25:09 +00:00
|
|
|
unsigned Flags = ISD::ParamFlags::NoFlagSet;
|
2007-02-13 13:50:08 +00:00
|
|
|
unsigned OriginalAlignment =
|
2007-02-14 05:52:17 +00:00
|
|
|
getTargetData()->getABITypeAlignment(Args[i].Ty);
|
2007-03-06 06:10:33 +00:00
|
|
|
|
2007-03-07 16:25:09 +00:00
|
|
|
if (Args[i].isSExt)
|
|
|
|
Flags |= ISD::ParamFlags::SExt;
|
|
|
|
if (Args[i].isZExt)
|
|
|
|
Flags |= ISD::ParamFlags::ZExt;
|
2007-03-06 06:10:33 +00:00
|
|
|
if (Args[i].isInReg)
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags |= ISD::ParamFlags::InReg;
|
2007-03-06 06:10:33 +00:00
|
|
|
if (Args[i].isSRet)
|
2007-03-07 16:25:09 +00:00
|
|
|
Flags |= ISD::ParamFlags::StructReturn;
|
|
|
|
Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
|
2007-03-06 06:10:33 +00:00
|
|
|
|
2006-05-16 22:53:20 +00:00
|
|
|
switch (getTypeAction(VT)) {
|
|
|
|
default: assert(0 && "Unknown type action!");
|
2007-02-13 13:50:08 +00:00
|
|
|
case Legal:
|
2006-05-16 22:53:20 +00:00
|
|
|
Ops.push_back(Op);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-05-16 22:53:20 +00:00
|
|
|
break;
|
|
|
|
case Promote:
|
|
|
|
if (MVT::isInteger(VT)) {
|
2007-03-07 16:25:09 +00:00
|
|
|
unsigned ExtOp;
|
|
|
|
if (Args[i].isSExt)
|
|
|
|
ExtOp = ISD::SIGN_EXTEND;
|
|
|
|
else if (Args[i].isZExt)
|
|
|
|
ExtOp = ISD::ZERO_EXTEND;
|
|
|
|
else
|
|
|
|
ExtOp = ISD::ANY_EXTEND;
|
2006-05-16 22:53:20 +00:00
|
|
|
Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
|
|
|
|
} else {
|
|
|
|
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
|
|
|
|
Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
|
|
|
|
}
|
|
|
|
Ops.push_back(Op);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-05-16 22:53:20 +00:00
|
|
|
break;
|
|
|
|
case Expand:
|
|
|
|
if (VT != MVT::Vector) {
|
|
|
|
// If this is a large integer, it needs to be broken down into small
|
|
|
|
// integers. Figure out what the source elt type is and how many small
|
|
|
|
// integers it is.
|
2007-01-28 13:31:35 +00:00
|
|
|
ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this);
|
2006-05-16 22:53:20 +00:00
|
|
|
} else {
|
2006-05-16 23:39:44 +00:00
|
|
|
// Otherwise, this is a vector type. We only support legal vectors
|
|
|
|
// right now.
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *PTy = cast<VectorType>(Args[i].Ty);
|
2006-05-16 23:39:44 +00:00
|
|
|
unsigned NumElems = PTy->getNumElements();
|
|
|
|
const Type *EltTy = PTy->getElementType();
|
|
|
|
|
|
|
|
// Figure out if there is a Packed type corresponding to this Vector
|
2007-02-15 03:39:18 +00:00
|
|
|
// type. If so, convert to the vector type.
|
2006-05-16 23:39:44 +00:00
|
|
|
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
|
2006-05-17 20:43:21 +00:00
|
|
|
if (TVT != MVT::Other && isTypeLegal(TVT)) {
|
2007-02-15 03:39:18 +00:00
|
|
|
// Insert a VBIT_CONVERT of the MVT::Vector type to the vector type.
|
2006-05-17 20:43:21 +00:00
|
|
|
Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
|
|
|
|
Ops.push_back(Op);
|
2007-01-28 13:31:35 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
|
2006-05-17 20:43:21 +00:00
|
|
|
} else {
|
2006-05-16 23:39:44 +00:00
|
|
|
assert(0 && "Don't support illegal by-val vector call args yet!");
|
|
|
|
abort();
|
|
|
|
}
|
2006-05-16 22:53:20 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Figure out the result value types.
|
2006-08-16 22:57:46 +00:00
|
|
|
SmallVector<MVT::ValueType, 4> RetTys;
|
2006-05-16 22:53:20 +00:00
|
|
|
|
|
|
|
if (RetTy != Type::VoidTy) {
|
|
|
|
MVT::ValueType VT = getValueType(RetTy);
|
|
|
|
switch (getTypeAction(VT)) {
|
|
|
|
default: assert(0 && "Unknown type action!");
|
|
|
|
case Legal:
|
|
|
|
RetTys.push_back(VT);
|
|
|
|
break;
|
|
|
|
case Promote:
|
|
|
|
RetTys.push_back(getTypeToTransformTo(VT));
|
|
|
|
break;
|
|
|
|
case Expand:
|
|
|
|
if (VT != MVT::Vector) {
|
|
|
|
// If this is a large integer, it needs to be reassembled from small
|
|
|
|
// integers. Figure out what the source elt type is and how many small
|
|
|
|
// integers it is.
|
2006-12-13 20:57:08 +00:00
|
|
|
MVT::ValueType NVT = getTypeToExpandTo(VT);
|
|
|
|
unsigned NumVals = getNumElements(VT);
|
2006-05-16 22:53:20 +00:00
|
|
|
for (unsigned i = 0; i != NumVals; ++i)
|
|
|
|
RetTys.push_back(NVT);
|
|
|
|
} else {
|
2006-05-16 23:39:44 +00:00
|
|
|
// Otherwise, this is a vector type. We only support legal vectors
|
|
|
|
// right now.
|
2007-02-15 02:26:10 +00:00
|
|
|
const VectorType *PTy = cast<VectorType>(RetTy);
|
2006-05-16 23:39:44 +00:00
|
|
|
unsigned NumElems = PTy->getNumElements();
|
|
|
|
const Type *EltTy = PTy->getElementType();
|
|
|
|
|
|
|
|
// Figure out if there is a Packed type corresponding to this Vector
|
2007-02-15 03:39:18 +00:00
|
|
|
// type. If so, convert to the vector type.
|
2006-05-16 23:39:44 +00:00
|
|
|
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
|
|
|
|
if (TVT != MVT::Other && isTypeLegal(TVT)) {
|
|
|
|
RetTys.push_back(TVT);
|
|
|
|
} else {
|
|
|
|
assert(0 && "Don't support illegal by-val vector call results yet!");
|
|
|
|
abort();
|
|
|
|
}
|
2006-05-16 22:53:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
RetTys.push_back(MVT::Other); // Always has a chain.
|
|
|
|
|
|
|
|
// Finally, create the CALL node.
|
2006-08-16 22:57:46 +00:00
|
|
|
SDOperand Res = DAG.getNode(ISD::CALL,
|
|
|
|
DAG.getVTList(&RetTys[0], RetTys.size()),
|
|
|
|
&Ops[0], Ops.size());
|
2006-05-16 22:53:20 +00:00
|
|
|
|
|
|
|
// This returns a pair of operands. The first element is the
|
|
|
|
// return value for the function (if RetTy is not VoidTy). The second
|
|
|
|
// element is the outgoing token chain.
|
|
|
|
SDOperand ResVal;
|
|
|
|
if (RetTys.size() != 1) {
|
|
|
|
MVT::ValueType VT = getValueType(RetTy);
|
|
|
|
if (RetTys.size() == 2) {
|
|
|
|
ResVal = Res;
|
|
|
|
|
|
|
|
// If this value was promoted, truncate it down.
|
|
|
|
if (ResVal.getValueType() != VT) {
|
2006-05-16 23:39:44 +00:00
|
|
|
if (VT == MVT::Vector) {
|
2007-03-25 05:00:54 +00:00
|
|
|
// Insert a VBIT_CONVERT to convert from the packed result type to the
|
2006-05-16 23:39:44 +00:00
|
|
|
// MVT::Vector type.
|
2007-02-15 02:26:10 +00:00
|
|
|
unsigned NumElems = cast<VectorType>(RetTy)->getNumElements();
|
|
|
|
const Type *EltTy = cast<VectorType>(RetTy)->getElementType();
|
2006-05-16 23:39:44 +00:00
|
|
|
|
|
|
|
// Figure out if there is a Packed type corresponding to this Vector
|
2007-02-15 03:39:18 +00:00
|
|
|
// type. If so, convert to the vector type.
|
2007-02-01 04:55:59 +00:00
|
|
|
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems);
|
2006-05-16 23:39:44 +00:00
|
|
|
if (TVT != MVT::Other && isTypeLegal(TVT)) {
|
|
|
|
// Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
|
|
|
|
// "N x PTyElementVT" MVT::Vector type.
|
|
|
|
ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
|
2006-05-17 20:49:36 +00:00
|
|
|
DAG.getConstant(NumElems, MVT::i32),
|
|
|
|
DAG.getValueType(getValueType(EltTy)));
|
2006-05-16 23:39:44 +00:00
|
|
|
} else {
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
} else if (MVT::isInteger(VT)) {
|
2006-12-31 05:55:36 +00:00
|
|
|
unsigned AssertOp = ISD::AssertSext;
|
|
|
|
if (!RetTyIsSigned)
|
|
|
|
AssertOp = ISD::AssertZext;
|
2006-05-16 22:53:20 +00:00
|
|
|
ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
|
|
|
|
DAG.getValueType(VT));
|
|
|
|
ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
|
|
|
|
} else {
|
|
|
|
assert(MVT::isFloatingPoint(VT));
|
2006-12-09 02:42:38 +00:00
|
|
|
if (getTypeAction(VT) == Expand)
|
|
|
|
ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
|
|
|
|
else
|
|
|
|
ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
|
2006-05-16 22:53:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (RetTys.size() == 3) {
|
|
|
|
ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
|
|
|
|
Res.getValue(0), Res.getValue(1));
|
|
|
|
|
|
|
|
} else {
|
|
|
|
assert(0 && "Case not handled yet!");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
|
|
|
|
}
|
|
|
|
|
2005-05-14 05:50:48 +00:00
|
|
|
SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
2005-01-16 07:28:41 +00:00
|
|
|
assert(0 && "LowerOperation not implemented for this target!");
|
|
|
|
abort();
|
2005-02-17 21:39:27 +00:00
|
|
|
return SDOperand();
|
2005-01-16 07:28:41 +00:00
|
|
|
}
|
|
|
|
|
2006-01-28 03:14:31 +00:00
|
|
|
SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
assert(0 && "CustomPromoteOperation not implemented for this target!");
|
|
|
|
abort();
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-02-15 21:59:04 +00:00
|
|
|
/// getMemsetValue - Vectorized representation of the memset value
|
2006-02-14 08:22:34 +00:00
|
|
|
/// operand.
|
|
|
|
static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
|
2006-02-15 22:12:35 +00:00
|
|
|
SelectionDAG &DAG) {
|
2006-02-14 08:22:34 +00:00
|
|
|
MVT::ValueType CurVT = VT;
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
|
|
|
|
uint64_t Val = C->getValue() & 255;
|
|
|
|
unsigned Shift = 8;
|
|
|
|
while (CurVT != MVT::i8) {
|
|
|
|
Val = (Val << Shift) | Val;
|
|
|
|
Shift <<= 1;
|
|
|
|
CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
|
|
|
|
}
|
|
|
|
return DAG.getConstant(Val, VT);
|
|
|
|
} else {
|
|
|
|
Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
|
|
|
|
unsigned Shift = 8;
|
|
|
|
while (CurVT != MVT::i8) {
|
|
|
|
Value =
|
|
|
|
DAG.getNode(ISD::OR, VT,
|
|
|
|
DAG.getNode(ISD::SHL, VT, Value,
|
|
|
|
DAG.getConstant(Shift, MVT::i8)), Value);
|
|
|
|
Shift <<= 1;
|
|
|
|
CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-15 21:59:04 +00:00
|
|
|
/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
|
|
|
|
/// used when a memcpy is turned into a memset when the source is a constant
|
|
|
|
/// string ptr.
|
|
|
|
static SDOperand getMemsetStringVal(MVT::ValueType VT,
|
|
|
|
SelectionDAG &DAG, TargetLowering &TLI,
|
|
|
|
std::string &Str, unsigned Offset) {
|
|
|
|
uint64_t Val = 0;
|
|
|
|
unsigned MSB = getSizeInBits(VT) / 8;
|
|
|
|
if (TLI.isLittleEndian())
|
|
|
|
Offset = Offset + MSB - 1;
|
|
|
|
for (unsigned i = 0; i != MSB; ++i) {
|
2006-11-29 01:38:07 +00:00
|
|
|
Val = (Val << 8) | (unsigned char)Str[Offset];
|
2006-02-15 21:59:04 +00:00
|
|
|
Offset += TLI.isLittleEndian() ? -1 : 1;
|
|
|
|
}
|
|
|
|
return DAG.getConstant(Val, VT);
|
|
|
|
}
|
|
|
|
|
2006-02-14 08:22:34 +00:00
|
|
|
/// getMemBasePlusOffset - Returns base and offset node for the
|
|
|
|
static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
|
|
|
|
SelectionDAG &DAG, TargetLowering &TLI) {
|
|
|
|
MVT::ValueType VT = Base.getValueType();
|
|
|
|
return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
|
|
|
|
}
|
|
|
|
|
2006-02-14 20:12:38 +00:00
|
|
|
/// MeetsMaxMemopRequirement - Determines if the number of memory ops required
|
2006-02-14 09:11:59 +00:00
|
|
|
/// to replace the memset / memcpy is below the threshold. It also returns the
|
|
|
|
/// types of the sequence of memory ops to perform memset / memcpy.
|
2006-02-14 20:12:38 +00:00
|
|
|
static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
|
|
|
|
unsigned Limit, uint64_t Size,
|
|
|
|
unsigned Align, TargetLowering &TLI) {
|
2006-02-14 08:22:34 +00:00
|
|
|
MVT::ValueType VT;
|
|
|
|
|
|
|
|
if (TLI.allowsUnalignedMemoryAccesses()) {
|
|
|
|
VT = MVT::i64;
|
|
|
|
} else {
|
|
|
|
switch (Align & 7) {
|
|
|
|
case 0:
|
|
|
|
VT = MVT::i64;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
VT = MVT::i32;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
VT = MVT::i16;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
VT = MVT::i8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-14 09:11:59 +00:00
|
|
|
MVT::ValueType LVT = MVT::i64;
|
|
|
|
while (!TLI.isTypeLegal(LVT))
|
|
|
|
LVT = (MVT::ValueType)((unsigned)LVT - 1);
|
|
|
|
assert(MVT::isInteger(LVT));
|
2006-02-14 08:22:34 +00:00
|
|
|
|
2006-02-14 09:11:59 +00:00
|
|
|
if (VT > LVT)
|
|
|
|
VT = LVT;
|
|
|
|
|
2006-02-14 23:05:54 +00:00
|
|
|
unsigned NumMemOps = 0;
|
2006-02-14 08:22:34 +00:00
|
|
|
while (Size != 0) {
|
|
|
|
unsigned VTSize = getSizeInBits(VT) / 8;
|
|
|
|
while (VTSize > Size) {
|
|
|
|
VT = (MVT::ValueType)((unsigned)VT - 1);
|
|
|
|
VTSize >>= 1;
|
|
|
|
}
|
2006-02-14 09:11:59 +00:00
|
|
|
assert(MVT::isInteger(VT));
|
|
|
|
|
|
|
|
if (++NumMemOps > Limit)
|
|
|
|
return false;
|
2006-02-14 08:22:34 +00:00
|
|
|
MemOps.push_back(VT);
|
|
|
|
Size -= VTSize;
|
|
|
|
}
|
2006-02-14 09:11:59 +00:00
|
|
|
|
|
|
|
return true;
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
|
2006-02-14 08:22:34 +00:00
|
|
|
SDOperand Op1 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(2));
|
|
|
|
SDOperand Op3 = getValue(I.getOperand(3));
|
|
|
|
SDOperand Op4 = getValue(I.getOperand(4));
|
|
|
|
unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
|
|
|
|
if (Align == 0) Align = 1;
|
|
|
|
|
|
|
|
if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
|
|
|
|
std::vector<MVT::ValueType> MemOps;
|
|
|
|
|
|
|
|
// Expand memset / memcpy to a series of load / store ops
|
|
|
|
// if the size operand falls below a certain threshold.
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> OutChains;
|
2006-02-14 08:22:34 +00:00
|
|
|
switch (Op) {
|
2006-02-14 19:45:56 +00:00
|
|
|
default: break; // Do nothing for now.
|
2006-02-14 08:22:34 +00:00
|
|
|
case ISD::MEMSET: {
|
2006-02-14 20:12:38 +00:00
|
|
|
if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
|
|
|
|
Size->getValue(), Align, TLI)) {
|
2006-02-14 09:11:59 +00:00
|
|
|
unsigned NumMemOps = MemOps.size();
|
2006-02-14 08:22:34 +00:00
|
|
|
unsigned Offset = 0;
|
|
|
|
for (unsigned i = 0; i < NumMemOps; i++) {
|
|
|
|
MVT::ValueType VT = MemOps[i];
|
|
|
|
unsigned VTSize = getSizeInBits(VT) / 8;
|
2006-02-15 22:12:35 +00:00
|
|
|
SDOperand Value = getMemsetValue(Op2, VT, DAG);
|
2006-10-05 23:01:46 +00:00
|
|
|
SDOperand Store = DAG.getStore(getRoot(), Value,
|
2006-02-22 22:37:12 +00:00
|
|
|
getMemBasePlusOffset(Op1, Offset, DAG, TLI),
|
2006-10-13 21:14:26 +00:00
|
|
|
I.getOperand(1), Offset);
|
2006-02-15 01:54:51 +00:00
|
|
|
OutChains.push_back(Store);
|
|
|
|
Offset += VTSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::MEMCPY: {
|
|
|
|
if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
|
|
|
|
Size->getValue(), Align, TLI)) {
|
|
|
|
unsigned NumMemOps = MemOps.size();
|
2006-02-16 23:11:42 +00:00
|
|
|
unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
|
2006-02-15 21:59:04 +00:00
|
|
|
GlobalAddressSDNode *G = NULL;
|
|
|
|
std::string Str;
|
2006-02-16 23:11:42 +00:00
|
|
|
bool CopyFromStr = false;
|
2006-02-15 21:59:04 +00:00
|
|
|
|
|
|
|
if (Op2.getOpcode() == ISD::GlobalAddress)
|
|
|
|
G = cast<GlobalAddressSDNode>(Op2);
|
|
|
|
else if (Op2.getOpcode() == ISD::ADD &&
|
|
|
|
Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
|
|
|
|
Op2.getOperand(1).getOpcode() == ISD::Constant) {
|
|
|
|
G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
|
2006-02-16 23:11:42 +00:00
|
|
|
SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
|
2006-02-15 21:59:04 +00:00
|
|
|
}
|
|
|
|
if (G) {
|
|
|
|
GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
|
2006-11-29 01:58:12 +00:00
|
|
|
if (GV && GV->isConstant()) {
|
2006-03-10 23:52:03 +00:00
|
|
|
Str = GV->getStringValue(false);
|
2006-02-16 23:11:42 +00:00
|
|
|
if (!Str.empty()) {
|
|
|
|
CopyFromStr = true;
|
|
|
|
SrcOff += SrcDelta;
|
|
|
|
}
|
|
|
|
}
|
2006-02-15 21:59:04 +00:00
|
|
|
}
|
|
|
|
|
2006-02-15 01:54:51 +00:00
|
|
|
for (unsigned i = 0; i < NumMemOps; i++) {
|
|
|
|
MVT::ValueType VT = MemOps[i];
|
|
|
|
unsigned VTSize = getSizeInBits(VT) / 8;
|
2006-02-15 21:59:04 +00:00
|
|
|
SDOperand Value, Chain, Store;
|
|
|
|
|
2006-02-16 23:11:42 +00:00
|
|
|
if (CopyFromStr) {
|
2006-02-15 21:59:04 +00:00
|
|
|
Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
|
|
|
|
Chain = getRoot();
|
|
|
|
Store =
|
2006-10-05 23:01:46 +00:00
|
|
|
DAG.getStore(Chain, Value,
|
|
|
|
getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
|
2006-10-13 21:14:26 +00:00
|
|
|
I.getOperand(1), DstOff);
|
2006-02-15 21:59:04 +00:00
|
|
|
} else {
|
|
|
|
Value = DAG.getLoad(VT, getRoot(),
|
|
|
|
getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
|
2006-10-09 20:57:25 +00:00
|
|
|
I.getOperand(2), SrcOff);
|
2006-02-15 21:59:04 +00:00
|
|
|
Chain = Value.getValue(1);
|
|
|
|
Store =
|
2006-10-05 23:01:46 +00:00
|
|
|
DAG.getStore(Chain, Value,
|
|
|
|
getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
|
2006-10-13 21:14:26 +00:00
|
|
|
I.getOperand(1), DstOff);
|
2006-02-15 21:59:04 +00:00
|
|
|
}
|
2006-02-15 01:54:51 +00:00
|
|
|
OutChains.push_back(Store);
|
2006-02-15 21:59:04 +00:00
|
|
|
SrcOff += VTSize;
|
|
|
|
DstOff += VTSize;
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
}
|
2006-02-15 01:54:51 +00:00
|
|
|
break;
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
}
|
2006-02-15 01:54:51 +00:00
|
|
|
|
|
|
|
if (!OutChains.empty()) {
|
2006-08-08 02:23:42 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&OutChains[0], OutChains.size()));
|
2006-02-15 01:54:51 +00:00
|
|
|
return;
|
|
|
|
}
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
|
2006-08-08 02:23:42 +00:00
|
|
|
DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SelectionDAGISel code
|
|
|
|
//===----------------------------------------------------------------------===//
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
|
|
|
|
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
|
|
|
|
}
|
|
|
|
|
2005-08-17 06:37:43 +00:00
|
|
|
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
|
2006-10-16 20:52:31 +00:00
|
|
|
AU.addRequired<AliasAnalysis>();
|
2007-03-31 04:18:03 +00:00
|
|
|
AU.setPreservesAll();
|
2005-08-17 06:37:43 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
|
2006-10-28 19:22:10 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
bool SelectionDAGISel::runOnFunction(Function &Fn) {
|
|
|
|
MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
|
|
|
|
RegMap = MF.getSSARegMap();
|
2006-12-07 20:04:42 +00:00
|
|
|
DOUT << "\n\n\n=== " << Fn.getName() << "\n";
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
|
|
|
|
|
|
|
|
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
|
|
|
|
SelectBasicBlock(I, MF, FuncInfo);
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2007-02-10 02:43:39 +00:00
|
|
|
// Add function live-ins to entry block live-in set.
|
|
|
|
BasicBlock *EntryBB = &Fn.getEntryBlock();
|
|
|
|
BB = FuncInfo.MBBMap[EntryBB];
|
|
|
|
if (!MF.livein_empty())
|
|
|
|
for (MachineFunction::livein_iterator I = MF.livein_begin(),
|
|
|
|
E = MF.livein_end(); I != E; ++I)
|
|
|
|
BB->addLiveIn(I->first);
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
|
|
|
|
unsigned Reg) {
|
|
|
|
SDOperand Op = getValue(V);
|
2005-01-13 20:50:02 +00:00
|
|
|
assert((Op.getOpcode() != ISD::CopyFromReg ||
|
2005-08-16 21:55:35 +00:00
|
|
|
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
|
2005-01-13 20:50:02 +00:00
|
|
|
"Copy from a reg to the same reg!");
|
2005-08-16 21:55:35 +00:00
|
|
|
|
|
|
|
// If this type is not legal, we must make sure to not create an invalid
|
|
|
|
// register use.
|
|
|
|
MVT::ValueType SrcVT = Op.getValueType();
|
|
|
|
MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
|
|
|
|
if (SrcVT == DestVT) {
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
return DAG.getCopyToReg(getRoot(), Reg, Op);
|
2006-03-21 19:20:37 +00:00
|
|
|
} else if (SrcVT == MVT::Vector) {
|
2006-03-31 02:06:56 +00:00
|
|
|
// Handle copies from generic vectors to registers.
|
|
|
|
MVT::ValueType PTyElementVT, PTyLegalElementVT;
|
2007-02-15 02:26:10 +00:00
|
|
|
unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()),
|
2006-03-31 02:06:56 +00:00
|
|
|
PTyElementVT, PTyLegalElementVT);
|
2006-03-21 19:20:37 +00:00
|
|
|
|
2006-03-31 02:06:56 +00:00
|
|
|
// Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
|
|
|
|
// MVT::Vector type.
|
|
|
|
Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
|
|
|
|
DAG.getConstant(NE, MVT::i32),
|
|
|
|
DAG.getValueType(PTyElementVT));
|
|
|
|
|
|
|
|
// Loop over all of the elements of the resultant vector,
|
|
|
|
// VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
|
|
|
|
// copying them into output registers.
|
2006-08-08 02:23:42 +00:00
|
|
|
SmallVector<SDOperand, 8> OutChains;
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
SDOperand Root = getRoot();
|
2006-03-31 02:06:56 +00:00
|
|
|
for (unsigned i = 0; i != NE; ++i) {
|
|
|
|
SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
|
2006-06-15 08:11:54 +00:00
|
|
|
Op, DAG.getConstant(i, TLI.getPointerTy()));
|
2006-03-31 02:06:56 +00:00
|
|
|
if (PTyElementVT == PTyLegalElementVT) {
|
|
|
|
// Elements are legal.
|
|
|
|
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
|
|
|
|
} else if (PTyLegalElementVT > PTyElementVT) {
|
|
|
|
// Elements are promoted.
|
|
|
|
if (MVT::isFloatingPoint(PTyLegalElementVT))
|
|
|
|
Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
|
|
|
|
else
|
|
|
|
Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
|
|
|
|
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
|
|
|
|
} else {
|
|
|
|
// Elements are expanded.
|
|
|
|
// The src value is expanded into multiple registers.
|
|
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
|
2006-06-15 08:11:54 +00:00
|
|
|
Elt, DAG.getConstant(0, TLI.getPointerTy()));
|
2006-03-31 02:06:56 +00:00
|
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
|
2006-06-15 08:11:54 +00:00
|
|
|
Elt, DAG.getConstant(1, TLI.getPointerTy()));
|
2006-03-31 02:06:56 +00:00
|
|
|
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
|
|
|
|
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
|
|
|
|
}
|
2006-03-21 19:20:37 +00:00
|
|
|
}
|
2006-08-08 02:23:42 +00:00
|
|
|
return DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&OutChains[0], OutChains.size());
|
2006-12-13 20:57:08 +00:00
|
|
|
} else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
|
2005-08-16 21:55:35 +00:00
|
|
|
// The src value is promoted to the register.
|
2005-08-17 06:06:25 +00:00
|
|
|
if (MVT::isFloatingPoint(SrcVT))
|
|
|
|
Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
|
|
|
|
else
|
2005-09-02 00:19:37 +00:00
|
|
|
Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
return DAG.getCopyToReg(getRoot(), Reg, Op);
|
2005-08-16 21:55:35 +00:00
|
|
|
} else {
|
2006-12-13 20:57:08 +00:00
|
|
|
DestVT = TLI.getTypeToExpandTo(SrcVT);
|
|
|
|
unsigned NumVals = TLI.getNumElements(SrcVT);
|
|
|
|
if (NumVals == 1)
|
|
|
|
return DAG.getCopyToReg(getRoot(), Reg,
|
|
|
|
DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
|
|
|
|
assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
|
2005-08-16 21:55:35 +00:00
|
|
|
// The src value is expanded into multiple registers.
|
|
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
|
2006-06-15 08:11:54 +00:00
|
|
|
Op, DAG.getConstant(0, TLI.getPointerTy()));
|
2005-08-16 21:55:35 +00:00
|
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
|
2006-06-15 08:11:54 +00:00
|
|
|
Op, DAG.getConstant(1, TLI.getPointerTy()));
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
|
2005-08-16 21:55:35 +00:00
|
|
|
return DAG.getCopyToReg(Op, Reg+1, Hi);
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-01-17 17:15:02 +00:00
|
|
|
void SelectionDAGISel::
|
2007-02-10 01:08:18 +00:00
|
|
|
LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
|
2005-01-17 17:15:02 +00:00
|
|
|
std::vector<SDOperand> &UnorderedChains) {
|
2005-01-07 07:47:53 +00:00
|
|
|
// If this is the entry block, emit arguments.
|
2007-02-10 01:08:18 +00:00
|
|
|
Function &F = *LLVMBB->getParent();
|
Implement a target independent optimization to codegen arguments only into
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19639 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-17 17:55:19 +00:00
|
|
|
FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
SDOperand OldRoot = SDL.DAG.getRoot();
|
|
|
|
std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
|
|
|
|
|
|
|
|
unsigned a = 0;
|
|
|
|
for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
|
|
|
|
AI != E; ++AI, ++a)
|
|
|
|
if (!AI->use_empty()) {
|
|
|
|
SDL.setValue(AI, Args[a]);
|
2006-04-27 08:29:42 +00:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
// If this argument is live outside of the entry block, insert a copy from
|
|
|
|
// whereever we got it to the vreg that other BB's will reference it as.
|
2007-02-25 18:40:32 +00:00
|
|
|
DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
|
|
|
|
if (VMI != FuncInfo.ValueMap.end()) {
|
|
|
|
SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
UnorderedChains.push_back(Copy);
|
|
|
|
}
|
Implement a target independent optimization to codegen arguments only into
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19639 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-17 17:55:19 +00:00
|
|
|
}
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
|
|
|
|
// Finally, if the target has anything special to do, allow it to do so.
|
2006-05-16 06:10:58 +00:00
|
|
|
// FIXME: this should insert code into the DAG!
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
|
2005-01-17 17:15:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
|
|
|
|
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
|
2006-03-27 01:32:24 +00:00
|
|
|
FunctionLoweringInfo &FuncInfo) {
|
2005-01-17 17:15:02 +00:00
|
|
|
SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
|
|
|
|
|
|
|
|
std::vector<SDOperand> UnorderedChains;
|
2005-04-21 22:36:52 +00:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
// Lower any arguments needed in this block if this is the entry block.
|
2007-03-22 16:38:57 +00:00
|
|
|
if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
LowerArguments(LLVMBB, SDL, UnorderedChains);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
BB = FuncInfo.MBBMap[LLVMBB];
|
|
|
|
SDL.setCurrentBasicBlock(BB);
|
|
|
|
|
|
|
|
// Lower all of the non-terminator instructions.
|
|
|
|
for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
|
|
|
|
I != E; ++I)
|
|
|
|
SDL.visit(*I);
|
2007-02-25 21:43:59 +00:00
|
|
|
|
|
|
|
// Lower call part of invoke.
|
|
|
|
InvokeInst *Invoke = dyn_cast<InvokeInst>(LLVMBB->getTerminator());
|
|
|
|
if (Invoke) SDL.visitInvoke(*Invoke, false);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Ensure that all instructions which are used outside of their defining
|
|
|
|
// blocks are available as virtual registers.
|
|
|
|
for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
|
2005-01-11 22:03:46 +00:00
|
|
|
if (!I->use_empty() && !isa<PHINode>(I)) {
|
2007-02-04 01:35:11 +00:00
|
|
|
DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
|
2005-01-07 07:47:53 +00:00
|
|
|
if (VMI != FuncInfo.ValueMap.end())
|
2005-01-13 17:59:43 +00:00
|
|
|
UnorderedChains.push_back(
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:36:01 +00:00
|
|
|
SDL.CopyValueToVirtualRegister(I, VMI->second));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
|
|
|
|
// ensure constants are generated when needed. Remember the virtual registers
|
|
|
|
// that need to be added to the Machine PHI nodes as input. We cannot just
|
|
|
|
// directly add them, because expansion might result in multiple MBB's for one
|
|
|
|
// BB. As such, the start of the BB might correspond to a different MBB than
|
|
|
|
// the end.
|
2005-04-21 22:36:52 +00:00
|
|
|
//
|
2006-10-27 23:50:33 +00:00
|
|
|
TerminatorInst *TI = LLVMBB->getTerminator();
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
// Emit constants only once even if used by multiple PHI nodes.
|
|
|
|
std::map<Constant*, unsigned> ConstantsOut;
|
2006-09-07 01:59:34 +00:00
|
|
|
|
2006-10-27 23:50:33 +00:00
|
|
|
// Vector bool would be better, but vector<bool> is really slow.
|
|
|
|
std::vector<unsigned char> SuccsHandled;
|
|
|
|
if (TI->getNumSuccessors())
|
|
|
|
SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Check successor nodes PHI nodes that expect a constant to be available from
|
|
|
|
// this block.
|
|
|
|
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
|
|
|
|
BasicBlock *SuccBB = TI->getSuccessor(succ);
|
2006-09-07 01:59:34 +00:00
|
|
|
if (!isa<PHINode>(SuccBB->begin())) continue;
|
2006-10-27 23:50:33 +00:00
|
|
|
MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
|
2006-09-07 01:59:34 +00:00
|
|
|
|
2006-10-27 23:50:33 +00:00
|
|
|
// If this terminator has multiple identical successors (common for
|
|
|
|
// switches), only handle each succ once.
|
|
|
|
unsigned SuccMBBNo = SuccMBB->getNumber();
|
|
|
|
if (SuccsHandled[SuccMBBNo]) continue;
|
|
|
|
SuccsHandled[SuccMBBNo] = true;
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator MBBI = SuccMBB->begin();
|
2005-01-07 07:47:53 +00:00
|
|
|
PHINode *PN;
|
|
|
|
|
|
|
|
// At this point we know that there is a 1-1 correspondence between LLVM PHI
|
|
|
|
// nodes and Machine PHI nodes, but the incoming operands have not been
|
|
|
|
// emitted yet.
|
|
|
|
for (BasicBlock::iterator I = SuccBB->begin();
|
2006-10-27 23:50:33 +00:00
|
|
|
(PN = dyn_cast<PHINode>(I)); ++I) {
|
|
|
|
// Ignore dead phi's.
|
|
|
|
if (PN->use_empty()) continue;
|
|
|
|
|
|
|
|
unsigned Reg;
|
|
|
|
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
|
2006-11-29 01:12:32 +00:00
|
|
|
|
2006-10-27 23:50:33 +00:00
|
|
|
if (Constant *C = dyn_cast<Constant>(PHIOp)) {
|
|
|
|
unsigned &RegOut = ConstantsOut[C];
|
|
|
|
if (RegOut == 0) {
|
|
|
|
RegOut = FuncInfo.CreateRegForValue(C);
|
|
|
|
UnorderedChains.push_back(
|
|
|
|
SDL.CopyValueToVirtualRegister(C, RegOut));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-10-27 23:50:33 +00:00
|
|
|
Reg = RegOut;
|
|
|
|
} else {
|
|
|
|
Reg = FuncInfo.ValueMap[PHIOp];
|
|
|
|
if (Reg == 0) {
|
|
|
|
assert(isa<AllocaInst>(PHIOp) &&
|
|
|
|
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
|
|
|
|
"Didn't codegen value into a register!??");
|
|
|
|
Reg = FuncInfo.CreateRegForValue(PHIOp);
|
|
|
|
UnorderedChains.push_back(
|
|
|
|
SDL.CopyValueToVirtualRegister(PHIOp, Reg));
|
2006-03-31 02:12:18 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-10-27 23:50:33 +00:00
|
|
|
|
|
|
|
// Remember that this register needs to added to the machine PHI node as
|
|
|
|
// the input for this MBB.
|
|
|
|
MVT::ValueType VT = TLI.getValueType(PN->getType());
|
|
|
|
unsigned NumElements;
|
|
|
|
if (VT != MVT::Vector)
|
|
|
|
NumElements = TLI.getNumElements(VT);
|
|
|
|
else {
|
|
|
|
MVT::ValueType VT1,VT2;
|
|
|
|
NumElements =
|
2007-02-15 02:26:10 +00:00
|
|
|
TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
|
2006-10-27 23:50:33 +00:00
|
|
|
VT1, VT2);
|
|
|
|
}
|
|
|
|
for (unsigned i = 0, e = NumElements; i != e; ++i)
|
|
|
|
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
ConstantsOut.clear();
|
|
|
|
|
2005-01-13 17:59:43 +00:00
|
|
|
// Turn all of the unordered chains into one factored node.
|
2005-01-13 19:53:14 +00:00
|
|
|
if (!UnorderedChains.empty()) {
|
2005-11-09 05:03:03 +00:00
|
|
|
SDOperand Root = SDL.getRoot();
|
|
|
|
if (Root.getOpcode() != ISD::EntryToken) {
|
|
|
|
unsigned i = 0, e = UnorderedChains.size();
|
|
|
|
for (; i != e; ++i) {
|
|
|
|
assert(UnorderedChains[i].Val->getNumOperands() > 1);
|
|
|
|
if (UnorderedChains[i].Val->getOperand(0) == Root)
|
|
|
|
break; // Don't add the root if we already indirectly depend on it.
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == e)
|
|
|
|
UnorderedChains.push_back(Root);
|
|
|
|
}
|
2006-08-08 02:23:42 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&UnorderedChains[0], UnorderedChains.size()));
|
2005-01-13 17:59:43 +00:00
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Lower the terminator after the copies are emitted.
|
2007-02-25 21:43:59 +00:00
|
|
|
if (Invoke) {
|
|
|
|
// Just the branch part of invoke.
|
|
|
|
SDL.visitInvoke(*Invoke, true);
|
|
|
|
} else {
|
|
|
|
SDL.visit(*LLVMBB->getTerminator());
|
|
|
|
}
|
2005-01-17 19:43:36 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// Copy over any CaseBlock records that may now exist due to SwitchInst
|
2006-04-22 18:53:45 +00:00
|
|
|
// lowering, as well as any jump table information.
|
2006-03-27 01:32:24 +00:00
|
|
|
SwitchCases.clear();
|
|
|
|
SwitchCases = SDL.SwitchCases;
|
2007-03-25 15:07:15 +00:00
|
|
|
JTCases.clear();
|
|
|
|
JTCases = SDL.JTCases;
|
2007-04-09 12:31:58 +00:00
|
|
|
BitTestCases.clear();
|
|
|
|
BitTestCases = SDL.BitTestCases;
|
|
|
|
|
2005-01-17 19:43:36 +00:00
|
|
|
// Make sure the root of the DAG is up-to-date.
|
|
|
|
DAG.setRoot(SDL.getRoot());
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
|
2006-10-16 20:52:31 +00:00
|
|
|
// Get alias analysis for load/store combining.
|
|
|
|
AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
|
|
|
|
|
2005-10-10 16:47:10 +00:00
|
|
|
// Run the DAG combiner in pre-legalize mode.
|
2006-10-16 20:52:31 +00:00
|
|
|
DAG.Combine(false, AA);
|
2005-09-07 00:15:36 +00:00
|
|
|
|
2006-12-07 20:04:42 +00:00
|
|
|
DOUT << "Lowered selection DAG:\n";
|
2005-01-07 07:47:53 +00:00
|
|
|
DEBUG(DAG.dump());
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Second step, hack on the DAG until it only uses operations and types that
|
|
|
|
// the target supports.
|
2005-01-23 04:36:26 +00:00
|
|
|
DAG.Legalize();
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2006-12-07 20:04:42 +00:00
|
|
|
DOUT << "Legalized selection DAG:\n";
|
2005-01-07 07:47:53 +00:00
|
|
|
DEBUG(DAG.dump());
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-10-10 16:47:10 +00:00
|
|
|
// Run the DAG combiner in post-legalize mode.
|
2006-10-16 20:52:31 +00:00
|
|
|
DAG.Combine(true, AA);
|
2005-09-07 00:15:36 +00:00
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
if (ViewISelDAGs) DAG.viewGraph();
|
2006-04-28 02:09:19 +00:00
|
|
|
|
2005-03-30 01:10:47 +00:00
|
|
|
// Third, instruction select all of the operations to machine code, adding the
|
|
|
|
// code to the MachineBasicBlock.
|
2005-01-07 07:47:53 +00:00
|
|
|
InstructionSelectBasicBlock(DAG);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2006-12-07 20:04:42 +00:00
|
|
|
DOUT << "Selected machine code:\n";
|
2005-01-07 07:47:53 +00:00
|
|
|
DEBUG(BB->dump());
|
2006-03-27 01:32:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
|
|
|
|
FunctionLoweringInfo &FuncInfo) {
|
|
|
|
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
|
|
|
|
{
|
2007-01-26 21:22:28 +00:00
|
|
|
SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
2006-03-27 01:32:24 +00:00
|
|
|
CurDAG = &DAG;
|
|
|
|
|
|
|
|
// First step, lower LLVM code to some DAG. This DAG may use operations and
|
|
|
|
// types that are not supported by the target.
|
|
|
|
BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// Second step, emit the lowered DAG as machine code.
|
|
|
|
CodeGenAndEmitDAG(DAG);
|
|
|
|
}
|
2007-04-09 12:31:58 +00:00
|
|
|
|
|
|
|
DOUT << "Total amount of phi nodes to update: "
|
|
|
|
<< PHINodesToUpdate.size() << "\n";
|
|
|
|
DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
|
|
|
|
DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
|
|
|
|
<< ", " << PHINodesToUpdate[i].second << ")\n";);
|
2006-03-27 01:32:24 +00:00
|
|
|
|
2005-03-30 01:10:47 +00:00
|
|
|
// Next, now that we know what the last MBB the LLVM BB expanded is, update
|
2005-01-07 07:47:53 +00:00
|
|
|
// PHI nodes in successors.
|
2007-04-09 12:31:58 +00:00
|
|
|
if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
|
2006-03-27 01:32:24 +00:00
|
|
|
for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[i].first;
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
2006-09-05 02:31:13 +00:00
|
|
|
PHI->addRegOperand(PHINodesToUpdate[i].second, false);
|
2006-03-27 01:32:24 +00:00
|
|
|
PHI->addMachineBasicBlockOperand(BB);
|
|
|
|
}
|
|
|
|
return;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2007-04-09 12:31:58 +00:00
|
|
|
|
|
|
|
for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
|
|
|
|
// Lower header first, if it wasn't already lowered
|
|
|
|
if (!BitTestCases[i].Emitted) {
|
|
|
|
SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &HSDAG;
|
|
|
|
SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
|
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = BitTestCases[i].Parent;
|
|
|
|
HSDL.setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
|
|
HSDL.visitBitTestHeader(BitTestCases[i]);
|
|
|
|
HSDAG.setRoot(HSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(HSDAG);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
|
|
|
|
SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &BSDAG;
|
|
|
|
SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo);
|
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = BitTestCases[i].Cases[j].ThisBB;
|
|
|
|
BSDL.setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
|
|
if (j+1 != ej)
|
|
|
|
BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
|
|
|
|
BitTestCases[i].Reg,
|
|
|
|
BitTestCases[i].Cases[j]);
|
|
|
|
else
|
|
|
|
BSDL.visitBitTestCase(BitTestCases[i].Default,
|
|
|
|
BitTestCases[i].Reg,
|
|
|
|
BitTestCases[i].Cases[j]);
|
|
|
|
|
|
|
|
|
|
|
|
BSDAG.setRoot(BSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(BSDAG);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update PHI Nodes
|
|
|
|
for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[pi].first;
|
|
|
|
MachineBasicBlock *PHIBB = PHI->getParent();
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
|
|
|
// This is "default" BB. We have two jumps to it. From "header" BB and
|
|
|
|
// from last "case" BB.
|
|
|
|
if (PHIBB == BitTestCases[i].Default) {
|
|
|
|
PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
|
|
|
|
PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
|
|
|
|
PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
|
|
|
|
}
|
|
|
|
// One of "cases" BB.
|
|
|
|
for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
|
|
|
|
MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
|
|
|
|
if (cBB->succ_end() !=
|
|
|
|
std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
|
|
|
|
PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
|
|
|
|
PHI->addMachineBasicBlockOperand(cBB);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-23 06:26:20 +00:00
|
|
|
// If the JumpTable record is filled in, then we need to emit a jump table.
|
|
|
|
// Updating the PHI nodes is tricky in this case, since we need to determine
|
|
|
|
// whether the PHI is a successor of the range check MBB or the jump table MBB
|
2007-03-25 15:07:15 +00:00
|
|
|
for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
|
|
|
|
// Lower header first, if it wasn't already lowered
|
|
|
|
if (!JTCases[i].first.Emitted) {
|
|
|
|
SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &HSDAG;
|
|
|
|
SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
|
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = JTCases[i].first.HeaderBB;
|
|
|
|
HSDL.setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
|
|
HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
|
|
|
|
HSDAG.setRoot(HSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(HSDAG);
|
2007-04-09 12:31:58 +00:00
|
|
|
}
|
2007-03-25 15:07:15 +00:00
|
|
|
|
|
|
|
SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &JSDAG;
|
|
|
|
SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo);
|
2006-04-22 18:53:45 +00:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
2007-03-25 15:07:15 +00:00
|
|
|
BB = JTCases[i].second.MBB;
|
|
|
|
JSDL.setCurrentBasicBlock(BB);
|
2006-04-22 18:53:45 +00:00
|
|
|
// Emit the code
|
2007-03-25 15:07:15 +00:00
|
|
|
JSDL.visitJumpTable(JTCases[i].second);
|
|
|
|
JSDAG.setRoot(JSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(JSDAG);
|
|
|
|
|
2006-04-22 18:53:45 +00:00
|
|
|
// Update PHI Nodes
|
|
|
|
for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[pi].first;
|
|
|
|
MachineBasicBlock *PHIBB = PHI->getParent();
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
2007-04-09 12:31:58 +00:00
|
|
|
// "default" BB. We can go there only from header BB.
|
2007-03-25 15:07:15 +00:00
|
|
|
if (PHIBB == JTCases[i].second.Default) {
|
2006-09-05 02:31:13 +00:00
|
|
|
PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
|
2007-03-25 15:07:15 +00:00
|
|
|
PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
|
2006-05-03 03:48:02 +00:00
|
|
|
}
|
2007-04-09 12:31:58 +00:00
|
|
|
// JT BB. Just iterate over successors here
|
2006-05-03 03:48:02 +00:00
|
|
|
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
|
2006-09-05 02:31:13 +00:00
|
|
|
PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
|
2006-05-03 03:48:02 +00:00
|
|
|
PHI->addMachineBasicBlockOperand(BB);
|
2006-04-22 18:53:45 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-22 23:00:53 +00:00
|
|
|
// If the switch block involved a branch to one of the actual successors, we
|
|
|
|
// need to update PHI nodes in that block.
|
|
|
|
for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[i].first;
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
|
|
|
if (BB->isSuccessor(PHI->getParent())) {
|
|
|
|
PHI->addRegOperand(PHINodesToUpdate[i].second, false);
|
|
|
|
PHI->addMachineBasicBlockOperand(BB);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// If we generated any switch lowering information, build and codegen any
|
|
|
|
// additional DAGs necessary.
|
2006-09-07 01:59:34 +00:00
|
|
|
for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
|
2007-01-26 21:22:28 +00:00
|
|
|
SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
2006-03-27 01:32:24 +00:00
|
|
|
CurDAG = &SDAG;
|
|
|
|
SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
|
2006-09-07 01:59:34 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = SwitchCases[i].ThisBB;
|
|
|
|
SDL.setCurrentBasicBlock(BB);
|
2006-09-07 01:59:34 +00:00
|
|
|
|
2006-03-27 01:32:24 +00:00
|
|
|
// Emit the code
|
|
|
|
SDL.visitSwitchCase(SwitchCases[i]);
|
|
|
|
SDAG.setRoot(SDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(SDAG);
|
2006-09-07 01:59:34 +00:00
|
|
|
|
|
|
|
// Handle any PHI nodes in successors of this chunk, as if we were coming
|
|
|
|
// from the original BB before switch expansion. Note that PHI nodes can
|
|
|
|
// occur multiple times in PHINodesToUpdate. We have to be very careful to
|
|
|
|
// handle them the right number of times.
|
2006-10-24 17:57:59 +00:00
|
|
|
while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
|
2006-09-07 01:59:34 +00:00
|
|
|
for (MachineBasicBlock::iterator Phi = BB->begin();
|
|
|
|
Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
|
|
|
|
// This value for this PHI node is recorded in PHINodesToUpdate, get it.
|
|
|
|
for (unsigned pn = 0; ; ++pn) {
|
|
|
|
assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
|
|
|
|
if (PHINodesToUpdate[pn].first == Phi) {
|
|
|
|
Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
|
|
|
|
Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-03-27 01:32:24 +00:00
|
|
|
}
|
2006-09-07 01:59:34 +00:00
|
|
|
|
|
|
|
// Don't process RHS if same block as LHS.
|
2006-10-24 17:57:59 +00:00
|
|
|
if (BB == SwitchCases[i].FalseBB)
|
|
|
|
SwitchCases[i].FalseBB = 0;
|
2006-09-07 01:59:34 +00:00
|
|
|
|
|
|
|
// If we haven't handled the RHS, do so now. Otherwise, we're done.
|
2006-10-24 18:07:37 +00:00
|
|
|
SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
|
2006-10-24 17:57:59 +00:00
|
|
|
SwitchCases[i].FalseBB = 0;
|
2006-03-27 01:32:24 +00:00
|
|
|
}
|
2006-10-24 17:57:59 +00:00
|
|
|
assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
|
2005-03-30 01:10:47 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-01-21 02:32:06 +00:00
|
|
|
|
2006-08-01 14:21:23 +00:00
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
|
|
|
|
/// target node in the graph.
|
|
|
|
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
|
|
|
|
if (ViewSchedDAGs) DAG.viewGraph();
|
2006-08-01 14:21:23 +00:00
|
|
|
|
2006-08-02 12:30:23 +00:00
|
|
|
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
|
2006-08-01 14:21:23 +00:00
|
|
|
|
|
|
|
if (!Ctor) {
|
2006-08-02 12:30:23 +00:00
|
|
|
Ctor = ISHeuristic;
|
2006-08-01 19:14:14 +00:00
|
|
|
RegisterScheduler::setDefault(Ctor);
|
2006-01-23 07:01:07 +00:00
|
|
|
}
|
2006-08-01 14:21:23 +00:00
|
|
|
|
2006-08-01 18:29:48 +00:00
|
|
|
ScheduleDAG *SL = Ctor(this, &DAG, BB);
|
2006-01-21 19:12:11 +00:00
|
|
|
BB = SL->Run();
|
2006-02-04 06:49:00 +00:00
|
|
|
delete SL;
|
2006-01-21 02:32:06 +00:00
|
|
|
}
|
2006-02-24 02:13:54 +00:00
|
|
|
|
2006-03-06 00:22:00 +00:00
|
|
|
|
2006-08-01 18:29:48 +00:00
|
|
|
HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
|
|
|
|
return new HazardRecognizer();
|
|
|
|
}
|
|
|
|
|
2006-10-11 03:58:02 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Helper functions used by the generated instruction selector.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Calls to these methods are generated by tblgen.
|
|
|
|
|
|
|
|
/// CheckAndMask - The isel is trying to match something like (and X, 255). If
|
|
|
|
/// the dag combiner simplified the 255, we still want to match. RHS is the
|
|
|
|
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
|
|
|
|
/// specified in the .td file (e.g. 255).
|
|
|
|
bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
|
|
|
|
int64_t DesiredMaskS) {
|
|
|
|
uint64_t ActualMask = RHS->getValue();
|
|
|
|
uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
|
|
|
|
|
|
|
|
// If the actual mask exactly matches, success!
|
|
|
|
if (ActualMask == DesiredMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the actual AND mask is allowing unallowed bits, this doesn't match.
|
|
|
|
if (ActualMask & ~DesiredMask)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Otherwise, the DAG Combiner may have proven that the value coming in is
|
|
|
|
// either already zero or is not demanded. Check for known zero input bits.
|
|
|
|
uint64_t NeededMask = DesiredMask & ~ActualMask;
|
|
|
|
if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// TODO: check to see if missing bits are just not demanded.
|
|
|
|
|
|
|
|
// Otherwise, this pattern doesn't match.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// CheckOrMask - The isel is trying to match something like (or X, 255). If
|
|
|
|
/// the dag combiner simplified the 255, we still want to match. RHS is the
|
|
|
|
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
|
|
|
|
/// specified in the .td file (e.g. 255).
|
|
|
|
bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
|
|
|
|
int64_t DesiredMaskS) {
|
|
|
|
uint64_t ActualMask = RHS->getValue();
|
|
|
|
uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
|
|
|
|
|
|
|
|
// If the actual mask exactly matches, success!
|
|
|
|
if (ActualMask == DesiredMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the actual AND mask is allowing unallowed bits, this doesn't match.
|
|
|
|
if (ActualMask & ~DesiredMask)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Otherwise, the DAG Combiner may have proven that the value coming in is
|
|
|
|
// either already zero or is not demanded. Check for known zero input bits.
|
|
|
|
uint64_t NeededMask = DesiredMask & ~ActualMask;
|
|
|
|
|
|
|
|
uint64_t KnownZero, KnownOne;
|
|
|
|
getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
|
|
|
|
|
|
|
|
// If all the missing bits in the or are already known to be set, match!
|
|
|
|
if ((NeededMask & KnownOne) == NeededMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// TODO: check to see if missing bits are just not demanded.
|
|
|
|
|
|
|
|
// Otherwise, this pattern doesn't match.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-08-01 18:29:48 +00:00
|
|
|
|
2006-02-24 02:13:54 +00:00
|
|
|
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
|
|
|
|
/// by tblgen. Others should not call it.
|
|
|
|
void SelectionDAGISel::
|
|
|
|
SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
|
|
|
|
std::vector<SDOperand> InOps;
|
|
|
|
std::swap(InOps, Ops);
|
|
|
|
|
|
|
|
Ops.push_back(InOps[0]); // input chain.
|
|
|
|
Ops.push_back(InOps[1]); // input asm string.
|
|
|
|
|
|
|
|
unsigned i = 2, e = InOps.size();
|
|
|
|
if (InOps[e-1].getValueType() == MVT::Flag)
|
|
|
|
--e; // Don't process a flag operand if it is here.
|
|
|
|
|
|
|
|
while (i != e) {
|
|
|
|
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
|
|
|
|
if ((Flags & 7) != 4 /*MEM*/) {
|
|
|
|
// Just skip over this operand, copying the operands verbatim.
|
|
|
|
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
|
|
|
|
i += (Flags >> 3) + 1;
|
|
|
|
} else {
|
|
|
|
assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
|
|
|
|
// Otherwise, this is a memory operand. Ask the target to select it.
|
|
|
|
std::vector<SDOperand> SelOps;
|
|
|
|
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
|
2006-12-07 20:04:42 +00:00
|
|
|
cerr << "Could not match memory address. Inline asm failure!\n";
|
2006-02-24 02:13:54 +00:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add this to the output node.
|
2007-04-09 00:33:58 +00:00
|
|
|
MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-12-16 21:14:48 +00:00
|
|
|
Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
|
2007-04-09 00:33:58 +00:00
|
|
|
IntPtrTy));
|
2006-02-24 02:13:54 +00:00
|
|
|
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
|
|
|
|
i += 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add the flag input back if present.
|
|
|
|
if (e != InOps.size())
|
|
|
|
Ops.push_back(InOps.back());
|
|
|
|
}
|