2012-02-28 07:46:26 +00:00
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//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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2012-12-03 16:50:05 +00:00
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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2007-08-28 05:08:16 +00:00
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#include "MipsMachineFunction.h"
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2012-12-03 16:50:05 +00:00
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#include "MipsSubtarget.h"
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2007-06-06 07:42:06 +00:00
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#include "MipsTargetMachine.h"
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2009-08-13 06:28:06 +00:00
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#include "MipsTargetObjectFile.h"
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2012-10-19 21:47:33 +00:00
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#include "llvm/ADT/Statistic.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/GlobalVariable.h"
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2012-10-19 21:47:33 +00:00
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#include "llvm/Support/CommandLine.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/Support/Debug.h"
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2009-07-11 20:10:48 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2012-04-21 15:31:45 +00:00
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#include "llvm/Support/raw_ostream.h"
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2013-08-14 00:21:25 +00:00
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#include <cctype>
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2012-04-21 15:31:45 +00:00
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2012-10-19 21:47:33 +00:00
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STATISTIC(NumTailCalls, "Number of tail calls");
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2012-11-21 20:21:11 +00:00
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static cl::opt<bool>
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LargeGOT("mxgot", cl::Hidden,
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cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
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2013-05-20 18:07:43 +00:00
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static cl::opt<bool>
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2013-05-21 17:17:59 +00:00
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NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
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2013-05-20 18:07:43 +00:00
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cl::desc("MIPS: Don't trap on integer division by zero."),
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cl::init(false));
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2012-10-27 00:29:43 +00:00
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static const uint16_t O32IntRegs[4] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const uint16_t Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
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};
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static const uint16_t Mips64DPRegs[8] = {
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Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
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Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
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};
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2012-02-28 07:46:26 +00:00
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// If I is a shifted mask, set the size (Size) and the first bit of the
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2011-08-18 20:07:42 +00:00
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// mask (Pos), and return true.
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2012-02-28 07:46:26 +00:00
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// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
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2013-03-12 00:16:36 +00:00
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static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
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2011-12-05 21:26:34 +00:00
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if (!isShiftedMask_64(I))
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2011-08-19 22:59:00 +00:00
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return false;
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2011-08-17 02:05:42 +00:00
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2011-12-05 21:26:34 +00:00
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Size = CountPopulation_64(I);
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2013-05-24 22:23:49 +00:00
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Pos = countTrailingZeros(I);
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2011-08-18 20:07:42 +00:00
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return true;
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2011-08-17 02:05:42 +00:00
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}
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2013-03-13 00:54:29 +00:00
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SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
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2012-02-24 22:34:47 +00:00
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MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
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return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
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}
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2012-11-21 20:26:38 +00:00
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static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
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EVT Ty = Op.getValueType();
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if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
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2013-05-25 02:42:55 +00:00
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return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0,
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2012-11-21 20:26:38 +00:00
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Flag);
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if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
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return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
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if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
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return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
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if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
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return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
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if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
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return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
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N->getOffset(), Flag);
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llvm_unreachable("Unexpected node type.");
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return SDValue();
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}
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static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
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2013-05-25 02:42:55 +00:00
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SDLoc DL(Op);
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2012-11-21 20:26:38 +00:00
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EVT Ty = Op.getValueType();
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SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
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SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
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return DAG.getNode(ISD::ADD, DL, Ty,
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DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
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DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
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}
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2013-03-13 00:54:29 +00:00
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SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG,
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bool HasMips64) const {
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2013-05-25 02:42:55 +00:00
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SDLoc DL(Op);
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2012-11-21 20:26:38 +00:00
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EVT Ty = Op.getValueType();
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unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
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2013-03-12 00:16:36 +00:00
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SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
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2012-11-21 20:26:38 +00:00
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getTargetNode(Op, DAG, GOTFlag));
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SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
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MachinePointerInfo::getGOT(), false, false, false,
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0);
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unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
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SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
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return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
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}
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2013-03-13 00:54:29 +00:00
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SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG,
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unsigned Flag) const {
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2013-05-25 02:42:55 +00:00
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SDLoc DL(Op);
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2012-11-21 20:26:38 +00:00
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EVT Ty = Op.getValueType();
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2013-03-12 00:16:36 +00:00
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SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
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2012-11-21 20:26:38 +00:00
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getTargetNode(Op, DAG, Flag));
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return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
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MachinePointerInfo::getGOT(), false, false, false, 0);
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}
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2013-03-13 00:54:29 +00:00
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SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
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unsigned HiFlag,
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unsigned LoFlag) const {
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2013-05-25 02:42:55 +00:00
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SDLoc DL(Op);
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2012-11-21 20:26:38 +00:00
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EVT Ty = Op.getValueType();
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SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
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2013-03-12 00:16:36 +00:00
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Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
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2012-11-21 20:26:38 +00:00
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SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
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getTargetNode(Op, DAG, LoFlag));
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return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
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MachinePointerInfo::getGOT(), false, false, false, 0);
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}
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2009-07-28 03:13:23 +00:00
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const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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2011-05-23 21:13:59 +00:00
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case MipsISD::JmpLink: return "MipsISD::JmpLink";
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2012-10-19 20:59:39 +00:00
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case MipsISD::TailCall: return "MipsISD::TailCall";
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2011-05-23 21:13:59 +00:00
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case MipsISD::Hi: return "MipsISD::Hi";
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case MipsISD::Lo: return "MipsISD::Lo";
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case MipsISD::GPRel: return "MipsISD::GPRel";
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2011-05-31 02:53:58 +00:00
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case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
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2011-05-23 21:13:59 +00:00
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case MipsISD::Ret: return "MipsISD::Ret";
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2013-01-30 00:26:49 +00:00
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case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
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2011-05-23 21:13:59 +00:00
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case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
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case MipsISD::FPCmp: return "MipsISD::FPCmp";
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case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
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case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
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2013-05-16 21:17:15 +00:00
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case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
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2013-03-30 01:14:04 +00:00
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case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI";
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case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI";
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case MipsISD::Mult: return "MipsISD::Mult";
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case MipsISD::Multu: return "MipsISD::Multu";
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2011-05-23 21:13:59 +00:00
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case MipsISD::MAdd: return "MipsISD::MAdd";
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case MipsISD::MAddu: return "MipsISD::MAddu";
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case MipsISD::MSub: return "MipsISD::MSub";
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case MipsISD::MSubu: return "MipsISD::MSubu";
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case MipsISD::DivRem: return "MipsISD::DivRem";
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case MipsISD::DivRemU: return "MipsISD::DivRemU";
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2013-03-30 01:14:04 +00:00
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case MipsISD::DivRem16: return "MipsISD::DivRem16";
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case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
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2011-05-23 21:13:59 +00:00
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case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
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case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
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2011-12-12 22:38:19 +00:00
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case MipsISD::Wrapper: return "MipsISD::Wrapper";
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2011-07-19 23:30:50 +00:00
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case MipsISD::Sync: return "MipsISD::Sync";
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2011-08-17 02:05:42 +00:00
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case MipsISD::Ext: return "MipsISD::Ext";
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case MipsISD::Ins: return "MipsISD::Ins";
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2012-06-02 00:03:12 +00:00
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case MipsISD::LWL: return "MipsISD::LWL";
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case MipsISD::LWR: return "MipsISD::LWR";
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case MipsISD::SWL: return "MipsISD::SWL";
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case MipsISD::SWR: return "MipsISD::SWR";
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case MipsISD::LDL: return "MipsISD::LDL";
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case MipsISD::LDR: return "MipsISD::LDR";
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case MipsISD::SDL: return "MipsISD::SDL";
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case MipsISD::SDR: return "MipsISD::SDR";
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2012-09-21 23:52:47 +00:00
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case MipsISD::EXTP: return "MipsISD::EXTP";
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case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
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case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
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case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
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case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
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case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
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case MipsISD::SHILO: return "MipsISD::SHILO";
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case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
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case MipsISD::MULT: return "MipsISD::MULT";
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case MipsISD::MULTU: return "MipsISD::MULTU";
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2013-03-04 01:06:54 +00:00
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case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
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2012-09-21 23:52:47 +00:00
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case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
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case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
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case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
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2013-04-19 23:21:32 +00:00
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case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
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case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
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case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
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2013-04-30 22:37:26 +00:00
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case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
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case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
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2013-08-28 12:14:50 +00:00
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case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
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case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
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case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
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case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
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2013-09-24 10:46:19 +00:00
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case MipsISD::VCEQ: return "MipsISD::VCEQ";
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case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
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case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
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case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
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case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
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2013-09-24 12:18:31 +00:00
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case MipsISD::VSMAX: return "MipsISD::VSMAX";
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case MipsISD::VSMIN: return "MipsISD::VSMIN";
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case MipsISD::VUMAX: return "MipsISD::VUMAX";
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case MipsISD::VUMIN: return "MipsISD::VUMIN";
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2013-09-23 14:03:12 +00:00
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case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
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case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
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2013-09-23 13:22:24 +00:00
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case MipsISD::VNOR: return "MipsISD::VNOR";
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2013-09-24 14:02:15 +00:00
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case MipsISD::VSHF: return "MipsISD::VSHF";
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2013-09-24 14:20:00 +00:00
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case MipsISD::SHF: return "MipsISD::SHF";
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2013-09-24 14:36:12 +00:00
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|
|
case MipsISD::ILVEV: return "MipsISD::ILVEV";
|
|
|
|
case MipsISD::ILVOD: return "MipsISD::ILVOD";
|
|
|
|
case MipsISD::ILVL: return "MipsISD::ILVL";
|
|
|
|
case MipsISD::ILVR: return "MipsISD::ILVR";
|
2013-09-24 14:53:25 +00:00
|
|
|
case MipsISD::PCKEV: return "MipsISD::PCKEV";
|
|
|
|
case MipsISD::PCKOD: return "MipsISD::PCKOD";
|
2011-06-07 18:58:42 +00:00
|
|
|
default: return NULL;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
MipsTargetLowering::
|
2009-07-28 03:13:23 +00:00
|
|
|
MipsTargetLowering(MipsTargetMachine &TM)
|
2011-09-26 21:47:02 +00:00
|
|
|
: TargetLowering(TM, new MipsTargetObjectFile()),
|
|
|
|
Subtarget(&TM.getSubtarget<MipsSubtarget>()),
|
2011-10-28 18:47:24 +00:00
|
|
|
HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
|
|
|
|
IsO32(Subtarget->isABI_O32()) {
|
2007-06-06 07:42:06 +00:00
|
|
|
// Mips does not have i1 type, so use i32 for
|
2010-11-23 03:31:01 +00:00
|
|
|
// setcc operations results (slt, sgt, ...).
|
2008-11-23 15:47:28 +00:00
|
|
|
setBooleanContents(ZeroOrOneBooleanContent);
|
2013-04-30 22:37:26 +00:00
|
|
|
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// Load extented operations for i1 types must be promoted
|
2009-08-11 20:47:22 +00:00
|
|
|
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
|
|
|
|
setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
|
|
|
|
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2009-07-17 04:07:24 +00:00
|
|
|
// MIPS doesn't have extending float->double load/store
|
2009-08-11 20:47:22 +00:00
|
|
|
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
|
|
|
|
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
|
2009-07-17 02:28:12 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// Used by legalize types to correctly generate the setcc result.
|
|
|
|
// Without this, every float setcc comes with a AND/OR with the result,
|
|
|
|
// we don't want this, since the fpcmp result goes to a flag register,
|
2008-07-31 18:31:28 +00:00
|
|
|
// which is used implicitly by brcond and select operations.
|
2009-08-11 20:47:22 +00:00
|
|
|
AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
|
2008-07-31 18:31:28 +00:00
|
|
|
|
2008-07-09 04:15:08 +00:00
|
|
|
// Mips Custom Operations
|
2013-03-06 21:32:03 +00:00
|
|
|
setOperationAction(ISD::BR_JT, MVT::Other, Custom);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
|
2011-03-04 20:01:52 +00:00
|
|
|
setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::SELECT, MVT::f32, Custom);
|
|
|
|
setOperationAction(ISD::SELECT, MVT::f64, Custom);
|
|
|
|
setOperationAction(ISD::SELECT, MVT::i32, Custom);
|
2012-07-11 19:32:27 +00:00
|
|
|
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
|
|
|
|
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
|
2012-03-09 23:46:03 +00:00
|
|
|
setOperationAction(ISD::SETCC, MVT::f32, Custom);
|
|
|
|
setOperationAction(ISD::SETCC, MVT::f64, Custom);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
|
2010-02-06 21:00:02 +00:00
|
|
|
setOperationAction(ISD::VASTART, MVT::Other, Custom);
|
2012-03-10 00:03:50 +00:00
|
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
|
|
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
|
2013-05-16 21:17:15 +00:00
|
|
|
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
|
2012-03-10 00:03:50 +00:00
|
|
|
|
2012-04-11 22:49:04 +00:00
|
|
|
if (!TM.Options.NoNaNsFPMath) {
|
|
|
|
setOperationAction(ISD::FABS, MVT::f32, Custom);
|
|
|
|
setOperationAction(ISD::FABS, MVT::f64, Custom);
|
|
|
|
}
|
|
|
|
|
2012-03-10 00:03:50 +00:00
|
|
|
if (HasMips64) {
|
|
|
|
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::SELECT, MVT::i64, Custom);
|
2012-06-02 00:04:42 +00:00
|
|
|
setOperationAction(ISD::LOAD, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::STORE, MVT::i64, Custom);
|
2013-05-16 21:17:15 +00:00
|
|
|
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
|
2012-03-10 00:03:50 +00:00
|
|
|
}
|
2010-02-06 21:00:02 +00:00
|
|
|
|
2012-05-09 00:55:21 +00:00
|
|
|
if (!HasMips64) {
|
|
|
|
setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
|
|
|
|
}
|
|
|
|
|
2012-11-07 19:10:58 +00:00
|
|
|
setOperationAction(ISD::ADD, MVT::i32, Custom);
|
|
|
|
if (HasMips64)
|
|
|
|
setOperationAction(ISD::ADD, MVT::i64, Custom);
|
|
|
|
|
2011-03-04 21:03:24 +00:00
|
|
|
setOperationAction(ISD::SDIV, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::SREM, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::UDIV, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::UREM, MVT::i32, Expand);
|
2011-10-03 21:06:13 +00:00
|
|
|
setOperationAction(ISD::SDIV, MVT::i64, Expand);
|
|
|
|
setOperationAction(ISD::SREM, MVT::i64, Expand);
|
|
|
|
setOperationAction(ISD::UDIV, MVT::i64, Expand);
|
|
|
|
setOperationAction(ISD::UREM, MVT::i64, Expand);
|
2011-03-04 21:03:24 +00:00
|
|
|
|
2008-07-09 04:15:08 +00:00
|
|
|
// Operations not directly supported by Mips.
|
2013-03-08 15:36:57 +00:00
|
|
|
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::BR_CC, MVT::f64, Expand);
|
|
|
|
setOperationAction(ISD::BR_CC, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::BR_CC, MVT::i64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
|
2011-12-20 23:40:56 +00:00
|
|
|
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
|
2011-12-20 23:40:56 +00:00
|
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
|
|
|
|
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
|
2011-12-21 00:14:05 +00:00
|
|
|
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
|
2011-12-21 00:14:05 +00:00
|
|
|
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
|
2011-12-13 01:56:10 +00:00
|
|
|
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
|
|
|
|
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::ROTL, MVT::i32, Expand);
|
2011-09-30 18:51:46 +00:00
|
|
|
setOperationAction(ISD::ROTL, MVT::i64, Expand);
|
2012-07-31 20:54:48 +00:00
|
|
|
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
|
2010-12-09 17:32:30 +00:00
|
|
|
|
2011-09-20 23:53:09 +00:00
|
|
|
if (!Subtarget->hasMips32r2())
|
2010-12-09 17:32:30 +00:00
|
|
|
setOperationAction(ISD::ROTR, MVT::i32, Expand);
|
|
|
|
|
2011-09-30 18:51:46 +00:00
|
|
|
if (!Subtarget->hasMips64r2())
|
|
|
|
setOperationAction(ISD::ROTR, MVT::i64, Expand);
|
|
|
|
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::FSIN, MVT::f32, Expand);
|
2011-03-04 18:54:14 +00:00
|
|
|
setOperationAction(ISD::FSIN, MVT::f64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::FCOS, MVT::f32, Expand);
|
2011-03-04 18:54:14 +00:00
|
|
|
setOperationAction(ISD::FCOS, MVT::f64, Expand);
|
2013-01-29 02:32:37 +00:00
|
|
|
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::FPOWI, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FPOW, MVT::f32, Expand);
|
2011-05-23 22:23:58 +00:00
|
|
|
setOperationAction(ISD::FPOW, MVT::f64, Expand);
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::FLOG, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FEXP, MVT::f32, Expand);
|
2011-07-08 21:39:21 +00:00
|
|
|
setOperationAction(ISD::FMA, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FMA, MVT::f64, Expand);
|
2012-03-29 18:43:11 +00:00
|
|
|
setOperationAction(ISD::FREM, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FREM, MVT::f64, Expand);
|
2008-07-09 04:15:08 +00:00
|
|
|
|
2012-04-11 22:59:08 +00:00
|
|
|
if (!TM.Options.NoNaNsFPMath) {
|
|
|
|
setOperationAction(ISD::FNEG, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FNEG, MVT::f64, Expand);
|
|
|
|
}
|
|
|
|
|
2013-01-30 00:26:49 +00:00
|
|
|
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
|
|
|
|
|
2011-03-09 19:22:22 +00:00
|
|
|
setOperationAction(ISD::VAARG, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::VAEND, MVT::Other, Expand);
|
|
|
|
|
2008-07-09 04:15:08 +00:00
|
|
|
// Use the default for now
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
|
2011-07-27 22:21:52 +00:00
|
|
|
|
2012-02-28 07:46:26 +00:00
|
|
|
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
|
|
|
|
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
|
2011-08-29 18:23:02 +00:00
|
|
|
|
2011-08-03 21:06:02 +00:00
|
|
|
setInsertFencesForAtomic(true);
|
|
|
|
|
2008-07-09 05:32:22 +00:00
|
|
|
if (!Subtarget->hasSEInReg()) {
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
|
|
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2011-12-21 00:20:27 +00:00
|
|
|
if (!Subtarget->hasBitCount()) {
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
|
2011-12-21 00:20:27 +00:00
|
|
|
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
|
|
|
|
}
|
2008-08-08 06:16:31 +00:00
|
|
|
|
2011-12-20 23:56:43 +00:00
|
|
|
if (!Subtarget->hasSwap()) {
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
|
2011-12-20 23:56:43 +00:00
|
|
|
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
|
|
|
|
}
|
2008-08-13 07:13:40 +00:00
|
|
|
|
2012-06-02 00:04:42 +00:00
|
|
|
if (HasMips64) {
|
|
|
|
setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
|
|
|
|
setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
|
|
|
|
setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
|
|
|
|
setTruncStoreAction(MVT::i64, MVT::i32, Custom);
|
|
|
|
}
|
|
|
|
|
2013-07-26 20:58:55 +00:00
|
|
|
setOperationAction(ISD::TRAP, MVT::Other, Legal);
|
|
|
|
|
2011-03-04 21:03:24 +00:00
|
|
|
setTargetDAGCombine(ISD::SDIVREM);
|
|
|
|
setTargetDAGCombine(ISD::UDIVREM);
|
2012-03-08 03:26:37 +00:00
|
|
|
setTargetDAGCombine(ISD::SELECT);
|
2011-08-17 17:45:08 +00:00
|
|
|
setTargetDAGCombine(ISD::AND);
|
|
|
|
setTargetDAGCombine(ISD::OR);
|
2012-06-13 20:33:18 +00:00
|
|
|
setTargetDAGCombine(ISD::ADD);
|
2011-01-18 19:29:17 +00:00
|
|
|
|
2012-03-08 01:59:33 +00:00
|
|
|
setMinFunctionAlignment(HasMips64 ? 3 : 2);
|
2011-05-06 20:34:06 +00:00
|
|
|
|
2012-02-02 03:17:04 +00:00
|
|
|
setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
|
2011-05-26 18:59:03 +00:00
|
|
|
|
2012-02-02 03:13:40 +00:00
|
|
|
setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
|
|
|
|
setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
|
2012-06-13 19:33:32 +00:00
|
|
|
|
2013-02-20 21:13:59 +00:00
|
|
|
MaxStoresPerMemcpy = 16;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
|
|
|
|
if (TM.getSubtargetImpl()->inMips16Mode())
|
|
|
|
return llvm::createMips16TargetLowering(TM);
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
return llvm::createMipsSETargetLowering(TM);
|
2011-08-12 21:30:06 +00:00
|
|
|
}
|
|
|
|
|
2013-05-18 00:21:46 +00:00
|
|
|
EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
2013-01-04 20:06:01 +00:00
|
|
|
if (!VT.isVector())
|
|
|
|
return MVT::i32;
|
|
|
|
return VT.changeVectorElementTypeToInteger();
|
2008-03-10 15:42:14 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
|
2011-03-04 21:03:24 +00:00
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
2012-06-14 21:10:56 +00:00
|
|
|
const MipsSubtarget *Subtarget) {
|
2011-03-04 21:03:24 +00:00
|
|
|
if (DCI.isBeforeLegalizeOps())
|
|
|
|
return SDValue();
|
|
|
|
|
2011-10-03 21:06:13 +00:00
|
|
|
EVT Ty = N->getValueType(0);
|
2013-08-14 00:47:08 +00:00
|
|
|
unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
|
|
|
|
unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
|
2013-03-30 01:36:35 +00:00
|
|
|
unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
|
|
|
|
MipsISD::DivRemU16;
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(N);
|
2011-03-04 21:03:24 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
|
2011-03-04 21:03:24 +00:00
|
|
|
N->getOperand(0), N->getOperand(1));
|
|
|
|
SDValue InChain = DAG.getEntryNode();
|
|
|
|
SDValue InGlue = DivRem;
|
|
|
|
|
|
|
|
// insert MFLO
|
|
|
|
if (N->hasAnyUseOfValue(0)) {
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
|
2011-03-04 21:03:24 +00:00
|
|
|
InGlue);
|
|
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
|
|
|
|
InChain = CopyFromLo.getValue(1);
|
|
|
|
InGlue = CopyFromLo.getValue(2);
|
|
|
|
}
|
|
|
|
|
|
|
|
// insert MFHI
|
|
|
|
if (N->hasAnyUseOfValue(1)) {
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
|
2011-10-03 21:06:13 +00:00
|
|
|
HI, Ty, InGlue);
|
2011-03-04 21:03:24 +00:00
|
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2013-04-18 01:00:46 +00:00
|
|
|
static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
|
2011-03-31 18:26:17 +00:00
|
|
|
switch (CC) {
|
|
|
|
default: llvm_unreachable("Unknown fp condition code!");
|
|
|
|
case ISD::SETEQ:
|
|
|
|
case ISD::SETOEQ: return Mips::FCOND_OEQ;
|
|
|
|
case ISD::SETUNE: return Mips::FCOND_UNE;
|
|
|
|
case ISD::SETLT:
|
|
|
|
case ISD::SETOLT: return Mips::FCOND_OLT;
|
|
|
|
case ISD::SETGT:
|
|
|
|
case ISD::SETOGT: return Mips::FCOND_OGT;
|
|
|
|
case ISD::SETLE:
|
|
|
|
case ISD::SETOLE: return Mips::FCOND_OLE;
|
|
|
|
case ISD::SETGE:
|
|
|
|
case ISD::SETOGE: return Mips::FCOND_OGE;
|
|
|
|
case ISD::SETULT: return Mips::FCOND_ULT;
|
|
|
|
case ISD::SETULE: return Mips::FCOND_ULE;
|
|
|
|
case ISD::SETUGT: return Mips::FCOND_UGT;
|
|
|
|
case ISD::SETUGE: return Mips::FCOND_UGE;
|
|
|
|
case ISD::SETUO: return Mips::FCOND_UN;
|
|
|
|
case ISD::SETO: return Mips::FCOND_OR;
|
|
|
|
case ISD::SETNE:
|
|
|
|
case ISD::SETONE: return Mips::FCOND_ONE;
|
|
|
|
case ISD::SETUEQ: return Mips::FCOND_UEQ;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-03-30 01:16:38 +00:00
|
|
|
/// This function returns true if the floating point conditional branches and
|
|
|
|
/// conditional moves which use condition code CC should be inverted.
|
|
|
|
static bool invertFPCondCodeUser(Mips::CondCode CC) {
|
2011-03-31 18:26:17 +00:00
|
|
|
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
|
|
|
|
return false;
|
|
|
|
|
2011-12-19 19:52:25 +00:00
|
|
|
assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
|
|
|
|
"Illegal Condition Code");
|
2011-03-31 18:26:17 +00:00
|
|
|
|
2011-12-19 19:52:25 +00:00
|
|
|
return true;
|
2011-03-31 18:26:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Creates and returns an FPCmp node from a setcc node.
|
|
|
|
// Returns Op if setcc is not a floating point comparison.
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
|
2011-03-31 18:26:17 +00:00
|
|
|
// must be a SETCC node
|
|
|
|
if (Op.getOpcode() != ISD::SETCC)
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
SDValue LHS = Op.getOperand(0);
|
|
|
|
|
|
|
|
if (!LHS.getValueType().isFloatingPoint())
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
SDValue RHS = Op.getOperand(1);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2011-03-31 18:26:17 +00:00
|
|
|
|
2011-04-15 21:00:26 +00:00
|
|
|
// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
|
|
|
|
// node if necessary.
|
2011-03-31 18:26:17 +00:00
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
|
2013-04-18 01:00:46 +00:00
|
|
|
DAG.getConstant(condCodeToFCC(CC), MVT::i32));
|
2011-03-31 18:26:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Creates and returns a CMovFPT/F node.
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDValue False, SDLoc DL) {
|
2013-03-30 01:16:38 +00:00
|
|
|
ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
|
|
|
|
bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
|
2013-07-26 20:51:20 +00:00
|
|
|
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
|
2011-03-31 18:26:17 +00:00
|
|
|
|
|
|
|
return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
|
2013-07-26 20:51:20 +00:00
|
|
|
True.getValueType(), True, FCC0, False, Cond);
|
2011-03-31 18:26:17 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
|
2012-03-08 02:14:24 +00:00
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
2012-06-14 21:10:56 +00:00
|
|
|
const MipsSubtarget *Subtarget) {
|
2012-03-08 02:14:24 +00:00
|
|
|
if (DCI.isBeforeLegalizeOps())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue SetCC = N->getOperand(0);
|
|
|
|
|
|
|
|
if ((SetCC.getOpcode() != ISD::SETCC) ||
|
|
|
|
!SetCC.getOperand(0).getValueType().isInteger())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue False = N->getOperand(2);
|
|
|
|
EVT FalseTy = False.getValueType();
|
|
|
|
|
|
|
|
if (!FalseTy.isInteger())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
|
|
|
|
|
|
|
|
if (!CN || CN->getZExtValue())
|
|
|
|
return SDValue();
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
const SDLoc DL(N);
|
2012-03-08 02:14:24 +00:00
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
|
|
|
|
SDValue True = N->getOperand(1);
|
2012-06-14 21:10:56 +00:00
|
|
|
|
2012-03-08 02:14:24 +00:00
|
|
|
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
|
|
|
|
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
|
2012-06-14 21:10:56 +00:00
|
|
|
|
2012-03-08 02:14:24 +00:00
|
|
|
return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
|
2011-08-17 17:45:08 +00:00
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
2012-06-14 21:10:56 +00:00
|
|
|
const MipsSubtarget *Subtarget) {
|
2011-08-17 17:45:08 +00:00
|
|
|
// Pattern match EXT.
|
|
|
|
// $dst = and ((sra or srl) $src , pos), (2**size - 1)
|
|
|
|
// => ext $dst, $src, size, pos
|
2011-09-20 23:53:09 +00:00
|
|
|
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
|
2011-12-05 21:26:34 +00:00
|
|
|
unsigned ShiftRightOpc = ShiftRight.getOpcode();
|
|
|
|
|
2011-08-17 17:45:08 +00:00
|
|
|
// Op's first operand must be a shift right.
|
2011-12-05 21:26:34 +00:00
|
|
|
if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// The second operand of the shift must be an immediate.
|
|
|
|
ConstantSDNode *CN;
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
|
|
|
|
return SDValue();
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-12-05 21:26:34 +00:00
|
|
|
uint64_t Pos = CN->getZExtValue();
|
2011-08-17 17:45:08 +00:00
|
|
|
uint64_t SMPos, SMSize;
|
2011-12-05 21:26:34 +00:00
|
|
|
|
2011-08-17 17:45:08 +00:00
|
|
|
// Op's second operand must be a shifted mask.
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
|
2013-03-12 00:16:36 +00:00
|
|
|
!isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// Return if the shifted mask does not start at bit 0 or the sum of its size
|
|
|
|
// and Pos exceeds the word's size.
|
2011-12-05 21:26:34 +00:00
|
|
|
EVT ValTy = N->getValueType(0);
|
|
|
|
if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
|
2011-12-19 19:52:25 +00:00
|
|
|
ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
|
2011-08-17 22:59:46 +00:00
|
|
|
DAG.getConstant(SMSize, MVT::i32));
|
2011-08-17 17:45:08 +00:00
|
|
|
}
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
|
2011-08-17 17:45:08 +00:00
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
2012-06-14 21:10:56 +00:00
|
|
|
const MipsSubtarget *Subtarget) {
|
2011-08-17 17:45:08 +00:00
|
|
|
// Pattern match INS.
|
|
|
|
// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
|
2012-02-28 07:46:26 +00:00
|
|
|
// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
|
2011-08-17 17:45:08 +00:00
|
|
|
// => ins $dst, $src, size, pos, $src1
|
2011-09-20 23:53:09 +00:00
|
|
|
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
|
|
|
|
uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
|
|
|
|
ConstantSDNode *CN;
|
|
|
|
|
|
|
|
// See if Op's first operand matches (and $src1 , mask0).
|
|
|
|
if (And0.getOpcode() != ISD::AND)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
|
2013-03-12 00:16:36 +00:00
|
|
|
!isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// See if Op's second operand matches (and (shl $src, pos), mask1).
|
|
|
|
if (And1.getOpcode() != ISD::AND)
|
|
|
|
return SDValue();
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2011-08-17 17:45:08 +00:00
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
|
2013-03-12 00:16:36 +00:00
|
|
|
!isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// The shift masks must have the same position and size.
|
|
|
|
if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue Shl = And1.getOperand(0);
|
|
|
|
if (Shl.getOpcode() != ISD::SHL)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
unsigned Shamt = CN->getZExtValue();
|
|
|
|
|
|
|
|
// Return if the shift amount and the first bit position of mask are not the
|
2012-02-28 07:46:26 +00:00
|
|
|
// same.
|
2011-12-05 21:26:34 +00:00
|
|
|
EVT ValTy = N->getValueType(0);
|
|
|
|
if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
|
2011-08-17 17:45:08 +00:00
|
|
|
DAG.getConstant(SMPos0, MVT::i32),
|
2011-12-19 19:52:25 +00:00
|
|
|
DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
|
2011-08-17 17:45:08 +00:00
|
|
|
}
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
|
2012-06-13 20:33:18 +00:00
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
2012-06-14 21:10:56 +00:00
|
|
|
const MipsSubtarget *Subtarget) {
|
2012-06-13 20:33:18 +00:00
|
|
|
// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
|
|
|
|
|
|
|
|
if (DCI.isBeforeLegalizeOps())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue Add = N->getOperand(1);
|
|
|
|
|
|
|
|
if (Add.getOpcode() != ISD::ADD)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue Lo = Add.getOperand(1);
|
|
|
|
|
|
|
|
if ((Lo.getOpcode() != MipsISD::Lo) ||
|
|
|
|
(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
EVT ValTy = N->getValueType(0);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(N);
|
2012-06-13 20:33:18 +00:00
|
|
|
|
|
|
|
SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
|
|
|
|
Add.getOperand(0));
|
|
|
|
return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
|
|
|
|
}
|
|
|
|
|
2011-02-10 18:05:10 +00:00
|
|
|
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
|
2011-01-18 19:29:17 +00:00
|
|
|
const {
|
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
2013-03-12 00:16:36 +00:00
|
|
|
unsigned Opc = N->getOpcode();
|
2011-01-18 19:29:17 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
switch (Opc) {
|
2011-01-18 19:29:17 +00:00
|
|
|
default: break;
|
2011-03-04 21:03:24 +00:00
|
|
|
case ISD::SDIVREM:
|
|
|
|
case ISD::UDIVREM:
|
2013-03-12 00:16:36 +00:00
|
|
|
return performDivRemCombine(N, DAG, DCI, Subtarget);
|
2012-03-08 02:14:24 +00:00
|
|
|
case ISD::SELECT:
|
2013-03-12 00:16:36 +00:00
|
|
|
return performSELECTCombine(N, DAG, DCI, Subtarget);
|
2011-08-17 17:45:08 +00:00
|
|
|
case ISD::AND:
|
2013-03-12 00:16:36 +00:00
|
|
|
return performANDCombine(N, DAG, DCI, Subtarget);
|
2011-08-17 17:45:08 +00:00
|
|
|
case ISD::OR:
|
2013-03-12 00:16:36 +00:00
|
|
|
return performORCombine(N, DAG, DCI, Subtarget);
|
2012-06-13 20:33:18 +00:00
|
|
|
case ISD::ADD:
|
2013-03-12 00:16:36 +00:00
|
|
|
return performADDCombine(N, DAG, DCI, Subtarget);
|
2011-01-18 19:29:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2012-09-21 23:58:31 +00:00
|
|
|
void
|
|
|
|
MipsTargetLowering::LowerOperationWrapper(SDNode *N,
|
|
|
|
SmallVectorImpl<SDValue> &Results,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
SDValue Res = LowerOperation(SDValue(N, 0), DAG);
|
|
|
|
|
|
|
|
for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
|
|
|
|
Results.push_back(Res.getValue(I));
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
MipsTargetLowering::ReplaceNodeResults(SDNode *N,
|
|
|
|
SmallVectorImpl<SDValue> &Results,
|
|
|
|
SelectionDAG &DAG) const {
|
2013-04-30 21:17:07 +00:00
|
|
|
return LowerOperationWrapper(N, Results, DAG);
|
2012-09-21 23:58:31 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
2010-11-23 03:31:01 +00:00
|
|
|
switch (Op.getOpcode())
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
2013-03-30 01:15:17 +00:00
|
|
|
case ISD::BR_JT: return lowerBR_JT(Op, DAG);
|
|
|
|
case ISD::BRCOND: return lowerBRCOND(Op, DAG);
|
|
|
|
case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
|
|
|
|
case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
|
|
|
|
case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
|
|
|
|
case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
|
|
|
|
case ISD::JumpTable: return lowerJumpTable(Op, DAG);
|
|
|
|
case ISD::SELECT: return lowerSELECT(Op, DAG);
|
|
|
|
case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
|
|
|
|
case ISD::SETCC: return lowerSETCC(Op, DAG);
|
|
|
|
case ISD::VASTART: return lowerVASTART(Op, DAG);
|
|
|
|
case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
|
|
|
|
case ISD::FABS: return lowerFABS(Op, DAG);
|
|
|
|
case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
|
|
|
|
case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
|
|
|
|
case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
|
|
|
|
case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
|
|
|
|
case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
|
|
|
|
case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
|
|
|
|
case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
|
|
|
|
case ISD::LOAD: return lowerLOAD(Op, DAG);
|
|
|
|
case ISD::STORE: return lowerSTORE(Op, DAG);
|
|
|
|
case ISD::ADD: return lowerADD(Op, DAG);
|
2013-05-16 21:17:15 +00:00
|
|
|
case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
return SDValue();
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Lower helper functions
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
// addLiveIn - This helper function adds the specified physical register to the
|
2007-06-06 07:42:06 +00:00
|
|
|
// MachineFunction as a live in value. It also creates a corresponding
|
|
|
|
// virtual register for it.
|
|
|
|
static unsigned
|
2013-03-12 00:16:36 +00:00
|
|
|
addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
2007-12-31 04:13:23 +00:00
|
|
|
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
MF.getRegInfo().addLiveIn(PReg, VReg);
|
2007-06-06 07:42:06 +00:00
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
|
2013-05-20 18:07:43 +00:00
|
|
|
static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
const TargetInstrInfo &TII,
|
|
|
|
bool Is64Bit) {
|
|
|
|
if (NoZeroDivCheck)
|
|
|
|
return &MBB;
|
|
|
|
|
|
|
|
// Insert instruction "teq $divisor_reg, $zero, 7".
|
|
|
|
MachineBasicBlock::iterator I(MI);
|
|
|
|
MachineInstrBuilder MIB;
|
|
|
|
MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
|
|
|
|
.addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
|
|
|
|
|
|
|
|
// Use the 32-bit sub-register if this is a 64-bit division.
|
|
|
|
if (Is64Bit)
|
|
|
|
MIB->getOperand(0).setSubReg(Mips::sub_32);
|
|
|
|
|
|
|
|
return &MBB;
|
|
|
|
}
|
|
|
|
|
2011-06-07 19:28:39 +00:00
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) const {
|
|
|
|
switch (MI->getOpcode()) {
|
2013-02-21 04:22:38 +00:00
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected instr type to insert");
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_AND_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, Mips::AND);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, Mips::AND64);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_OR_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, Mips::OR);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, Mips::OR64);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_XOR_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, Mips::XOR);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_NAND_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, 0, true);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, 0, true);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_SUB_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_SWAP_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 1, 0);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinaryPartword(MI, BB, 2, 0);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 4, 0);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicBinary(MI, BB, 8, 0);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_CMP_SWAP_I8:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicCmpSwapPartword(MI, BB, 1);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I16:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicCmpSwapPartword(MI, BB, 2);
|
2011-06-07 19:28:39 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I32:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicCmpSwap(MI, BB, 4);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I64:
|
2013-03-12 00:16:36 +00:00
|
|
|
return emitAtomicCmpSwap(MI, BB, 8);
|
2013-05-20 18:07:43 +00:00
|
|
|
case Mips::PseudoSDIV:
|
|
|
|
case Mips::PseudoUDIV:
|
|
|
|
return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
|
|
|
|
case Mips::PseudoDSDIV:
|
|
|
|
case Mips::PseudoDUDIV:
|
|
|
|
return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
|
2011-06-07 19:28:39 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
|
|
|
|
// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
|
|
|
|
MachineBasicBlock *
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
|
2011-06-08 23:55:35 +00:00
|
|
|
unsigned Size, unsigned BinOpcode,
|
2011-06-07 18:58:42 +00:00
|
|
|
bool Nand) const {
|
2011-11-11 04:14:30 +00:00
|
|
|
assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
2011-11-11 04:14:30 +00:00
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
|
2011-05-31 02:54:07 +00:00
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
2013-03-12 00:16:36 +00:00
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
2011-11-11 04:14:30 +00:00
|
|
|
unsigned LL, SC, AND, NOR, ZERO, BEQ;
|
|
|
|
|
|
|
|
if (Size == 4) {
|
2013-08-20 21:08:22 +00:00
|
|
|
LL = Mips::LL;
|
|
|
|
SC = Mips::SC;
|
2011-11-11 04:14:30 +00:00
|
|
|
AND = Mips::AND;
|
|
|
|
NOR = Mips::NOR;
|
|
|
|
ZERO = Mips::ZERO;
|
|
|
|
BEQ = Mips::BEQ;
|
|
|
|
}
|
|
|
|
else {
|
2013-08-20 21:08:22 +00:00
|
|
|
LL = Mips::LLD;
|
|
|
|
SC = Mips::SCD;
|
2011-11-11 04:14:30 +00:00
|
|
|
AND = Mips::AND64;
|
|
|
|
NOR = Mips::NOR64;
|
|
|
|
ZERO = Mips::ZERO_64;
|
|
|
|
BEQ = Mips::BEQ64;
|
|
|
|
}
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned OldVal = MI->getOperand(0).getReg();
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
|
|
|
unsigned Incr = MI->getOperand(2).getReg();
|
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned AndRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loopMBB);
|
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loopMBB
|
|
|
|
BB->addSuccessor(loopMBB);
|
2011-07-19 17:09:53 +00:00
|
|
|
loopMBB->addSuccessor(loopMBB);
|
|
|
|
loopMBB->addSuccessor(exitMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loopMBB:
|
|
|
|
// ll oldval, 0(ptr)
|
2011-07-19 20:11:17 +00:00
|
|
|
// <binop> storeval, oldval, incr
|
|
|
|
// sc success, storeval, 0(ptr)
|
|
|
|
// beq success, $0, loopMBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loopMBB;
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
|
2011-05-31 02:54:07 +00:00
|
|
|
if (Nand) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// and andres, oldval, incr
|
|
|
|
// nor storeval, $0, andres
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
|
|
|
|
BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
|
2011-05-31 02:54:07 +00:00
|
|
|
} else if (BinOpcode) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// <binop> storeval, oldval, incr
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
|
2011-05-31 02:54:07 +00:00
|
|
|
} else {
|
2011-07-19 20:11:17 +00:00
|
|
|
StoreVal = Incr;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
|
|
|
|
BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
|
2011-06-07 18:58:42 +00:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size, unsigned BinOpcode,
|
|
|
|
bool Nand) const {
|
2011-05-31 02:54:07 +00:00
|
|
|
assert((Size == 1 || Size == 2) &&
|
|
|
|
"Unsupported size for EmitAtomicBinaryPartial.");
|
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
|
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
2013-03-12 00:16:36 +00:00
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
|
|
|
unsigned Incr = MI->getOperand(2).getReg();
|
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Mask = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned NewVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned OldVal = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Incr2 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned AndRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:56:53 +00:00
|
|
|
unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SllRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loopMBB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MF->insert(It, sinkMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
2011-12-19 19:52:25 +00:00
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
|
2011-05-31 02:54:07 +00:00
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
2011-07-19 17:09:53 +00:00
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
loopMBB->addSuccessor(loopMBB);
|
|
|
|
loopMBB->addSuccessor(sinkMBB);
|
|
|
|
sinkMBB->addSuccessor(exitMBB);
|
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
// thisMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// addiu masklsb2,$0,-4 # 0xfffffffc
|
|
|
|
// and alignedaddr,ptr,masklsb2
|
|
|
|
// andi ptrlsb2,ptr,3
|
|
|
|
// sll shiftamt,ptrlsb2,3
|
|
|
|
// ori maskupper,$0,255 # 0xff
|
|
|
|
// sll mask,maskupper,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
// nor mask2,$0,mask
|
2011-07-19 20:11:17 +00:00
|
|
|
// sll incr2,incr,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
int64_t MaskImm = (Size == 1) ? 255 : 65535;
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Mips::ZERO).addImm(-4);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Ptr).addReg(MaskLSB2);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
|
2013-05-31 03:25:44 +00:00
|
|
|
if (Subtarget->isLittle()) {
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
|
|
|
|
} else {
|
|
|
|
unsigned Off = RegInfo.createVirtualRegister(RC);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::XORi), Off)
|
|
|
|
.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
|
|
|
|
}
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Mips::ZERO).addImm(MaskImm);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
|
2013-07-01 20:39:53 +00:00
|
|
|
.addReg(MaskUpper).addReg(ShiftAmt);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
|
2013-07-01 20:39:53 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
|
2011-05-31 20:25:26 +00:00
|
|
|
|
2011-07-18 18:52:12 +00:00
|
|
|
// atomic.load.binop
|
2011-05-31 02:54:07 +00:00
|
|
|
// loopMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// ll oldval,0(alignedaddr)
|
|
|
|
// binop binopres,oldval,incr2
|
|
|
|
// and newval,binopres,mask
|
|
|
|
// and maskedoldval0,oldval,mask2
|
|
|
|
// or storeval,maskedoldval0,newval
|
|
|
|
// sc success,storeval,0(alignedaddr)
|
|
|
|
// beq success,$0,loopMBB
|
|
|
|
|
2011-07-18 18:52:12 +00:00
|
|
|
// atomic.swap
|
|
|
|
// loopMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// ll oldval,0(alignedaddr)
|
2011-07-19 18:14:26 +00:00
|
|
|
// and newval,incr2,mask
|
2011-07-19 20:11:17 +00:00
|
|
|
// and maskedoldval0,oldval,mask2
|
|
|
|
// or storeval,maskedoldval0,newval
|
|
|
|
// sc success,storeval,0(alignedaddr)
|
|
|
|
// beq success,$0,loopMBB
|
2011-07-18 18:52:12 +00:00
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loopMBB;
|
2013-08-20 21:08:22 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
|
2011-05-31 02:54:07 +00:00
|
|
|
if (Nand) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// and andres, oldval, incr2
|
|
|
|
// nor binopres, $0, andres
|
|
|
|
// and newval, binopres, mask
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Mips::ZERO).addReg(AndRes);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
|
2011-05-31 02:54:07 +00:00
|
|
|
} else if (BinOpcode) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// <binop> binopres, oldval, incr2
|
|
|
|
// and newval, binopres, mask
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
|
2011-07-19 18:14:26 +00:00
|
|
|
} else {// atomic.swap
|
2011-07-19 20:11:17 +00:00
|
|
|
// and newval, incr2, mask
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
|
2011-07-19 18:14:26 +00:00
|
|
|
}
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(OldVal).addReg(Mask2);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
|
2011-07-19 20:56:53 +00:00
|
|
|
.addReg(MaskedOldVal0).addReg(NewVal);
|
2013-08-20 21:08:22 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SC), Success)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::BEQ))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
// sinkMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// and maskedoldval1,oldval,mask
|
|
|
|
// srl srlres,maskedoldval1,shiftamt
|
|
|
|
// sll sllres,srlres,24
|
|
|
|
// sra dest,sllres,24
|
2011-07-19 03:42:13 +00:00
|
|
|
BB = sinkMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
int64_t ShiftImm = (Size == 1) ? 24 : 16;
|
2011-07-19 03:14:58 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(OldVal).addReg(Mask);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
|
2013-07-01 20:39:53 +00:00
|
|
|
.addReg(MaskedOldVal1).addReg(ShiftAmt);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(SrlRes).addImm(ShiftImm);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(SllRes).addImm(ShiftImm);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
|
2011-06-07 18:58:42 +00:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size) const {
|
2011-11-11 04:14:30 +00:00
|
|
|
assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
2011-11-11 04:14:30 +00:00
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
|
2011-05-31 02:54:07 +00:00
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
2013-03-12 00:16:36 +00:00
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
2011-11-11 04:14:30 +00:00
|
|
|
unsigned LL, SC, ZERO, BNE, BEQ;
|
|
|
|
|
|
|
|
if (Size == 4) {
|
2013-08-20 21:08:22 +00:00
|
|
|
LL = Mips::LL;
|
|
|
|
SC = Mips::SC;
|
2011-11-11 04:14:30 +00:00
|
|
|
ZERO = Mips::ZERO;
|
|
|
|
BNE = Mips::BNE;
|
|
|
|
BEQ = Mips::BEQ;
|
|
|
|
}
|
|
|
|
else {
|
2013-08-20 21:08:22 +00:00
|
|
|
LL = Mips::LLD;
|
|
|
|
SC = Mips::SCD;
|
2011-11-11 04:14:30 +00:00
|
|
|
ZERO = Mips::ZERO_64;
|
|
|
|
BNE = Mips::BNE64;
|
|
|
|
BEQ = Mips::BEQ64;
|
|
|
|
}
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned OldVal = MI->getOperand(2).getReg();
|
|
|
|
unsigned NewVal = MI->getOperand(3).getReg();
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loop1MBB);
|
|
|
|
MF->insert(It, loop2MBB);
|
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
2011-12-19 19:52:25 +00:00
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
|
2011-05-31 02:54:07 +00:00
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loop1MBB
|
|
|
|
BB->addSuccessor(loop1MBB);
|
2011-07-19 17:09:53 +00:00
|
|
|
loop1MBB->addSuccessor(exitMBB);
|
|
|
|
loop1MBB->addSuccessor(loop2MBB);
|
|
|
|
loop2MBB->addSuccessor(loop1MBB);
|
|
|
|
loop2MBB->addSuccessor(exitMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop1MBB:
|
|
|
|
// ll dest, 0(ptr)
|
|
|
|
// bne dest, oldval, exitMBB
|
|
|
|
BB = loop1MBB;
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
|
|
|
|
BuildMI(BB, DL, TII->get(BNE))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop2MBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// sc success, newval, 0(ptr)
|
|
|
|
// beq success, $0, loop1MBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loop2MBB;
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(SC), Success)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(NewVal).addReg(Ptr).addImm(0);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(BEQ))
|
2011-11-11 04:14:30 +00:00
|
|
|
.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
|
2011-06-07 18:58:42 +00:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size) const {
|
2011-05-31 02:54:07 +00:00
|
|
|
assert((Size == 1 || Size == 2) &&
|
|
|
|
"Unsupported size for EmitAtomicCmpSwapPartial.");
|
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
|
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
2013-03-12 00:16:36 +00:00
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned CmpVal = MI->getOperand(2).getReg();
|
|
|
|
unsigned NewVal = MI->getOperand(3).getReg();
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Mask = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned OldVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SllRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loop1MBB);
|
|
|
|
MF->insert(It, loop2MBB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MF->insert(It, sinkMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
2011-12-19 19:52:25 +00:00
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
|
2011-05-31 02:54:07 +00:00
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
2011-07-19 17:09:53 +00:00
|
|
|
BB->addSuccessor(loop1MBB);
|
|
|
|
loop1MBB->addSuccessor(sinkMBB);
|
|
|
|
loop1MBB->addSuccessor(loop2MBB);
|
|
|
|
loop2MBB->addSuccessor(loop1MBB);
|
|
|
|
loop2MBB->addSuccessor(sinkMBB);
|
|
|
|
sinkMBB->addSuccessor(exitMBB);
|
|
|
|
|
2011-07-19 18:14:26 +00:00
|
|
|
// FIXME: computation of newval2 can be moved to loop2MBB.
|
2011-05-31 02:54:07 +00:00
|
|
|
// thisMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// addiu masklsb2,$0,-4 # 0xfffffffc
|
|
|
|
// and alignedaddr,ptr,masklsb2
|
|
|
|
// andi ptrlsb2,ptr,3
|
|
|
|
// sll shiftamt,ptrlsb2,3
|
|
|
|
// ori maskupper,$0,255 # 0xff
|
|
|
|
// sll mask,maskupper,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
// nor mask2,$0,mask
|
2011-07-19 20:11:17 +00:00
|
|
|
// andi maskedcmpval,cmpval,255
|
|
|
|
// sll shiftedcmpval,maskedcmpval,shiftamt
|
|
|
|
// andi maskednewval,newval,255
|
|
|
|
// sll shiftednewval,maskednewval,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
int64_t MaskImm = (Size == 1) ? 255 : 65535;
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Mips::ZERO).addImm(-4);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Ptr).addReg(MaskLSB2);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
|
2013-05-31 03:25:44 +00:00
|
|
|
if (Subtarget->isLittle()) {
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
|
|
|
|
} else {
|
|
|
|
unsigned Off = RegInfo.createVirtualRegister(RC);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::XORi), Off)
|
|
|
|
.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
|
|
|
|
}
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Mips::ZERO).addImm(MaskImm);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
|
2013-07-01 20:39:53 +00:00
|
|
|
.addReg(MaskUpper).addReg(ShiftAmt);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(CmpVal).addImm(MaskImm);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
|
2013-07-01 20:39:53 +00:00
|
|
|
.addReg(MaskedCmpVal).addReg(ShiftAmt);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(NewVal).addImm(MaskImm);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
|
2013-07-01 20:39:53 +00:00
|
|
|
.addReg(MaskedNewVal).addReg(ShiftAmt);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop1MBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// ll oldval,0(alginedaddr)
|
|
|
|
// and maskedoldval0,oldval,mask
|
|
|
|
// bne maskedoldval0,shiftedcmpval,sinkMBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loop1MBB;
|
2013-08-20 21:08:22 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(OldVal).addReg(Mask);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::BNE))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop2MBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// and maskedoldval1,oldval,mask2
|
|
|
|
// or storeval,maskedoldval1,shiftednewval
|
|
|
|
// sc success,storeval,0(alignedaddr)
|
|
|
|
// beq success,$0,loop1MBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loop2MBB;
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(OldVal).addReg(Mask2);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
|
2013-08-20 21:08:22 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SC), Success)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::BEQ))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
// sinkMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// srl srlres,maskedoldval0,shiftamt
|
|
|
|
// sll sllres,srlres,24
|
|
|
|
// sra dest,sllres,24
|
2011-07-19 03:42:13 +00:00
|
|
|
BB = sinkMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
int64_t ShiftImm = (Size == 1) ? 24 : 16;
|
2011-07-19 03:14:58 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
|
2013-07-01 20:39:53 +00:00
|
|
|
.addReg(MaskedOldVal0).addReg(ShiftAmt);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(SrlRes).addImm(ShiftImm);
|
2013-03-12 00:16:36 +00:00
|
|
|
BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(SllRes).addImm(ShiftImm);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Misc Lower Operation implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
|
2013-03-06 21:32:03 +00:00
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Table = Op.getOperand(1);
|
|
|
|
SDValue Index = Op.getOperand(2);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2013-03-06 21:32:03 +00:00
|
|
|
EVT PTy = getPointerTy();
|
|
|
|
unsigned EntrySize =
|
|
|
|
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
|
|
|
|
|
|
|
|
Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
|
|
|
|
DAG.getConstant(EntrySize, PTy));
|
|
|
|
SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
|
|
|
|
|
|
|
|
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
|
|
|
|
Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
|
|
|
|
MachinePointerInfo::getJumpTable(), MemVT, false, false,
|
|
|
|
0);
|
|
|
|
Chain = Addr.getValue(1);
|
|
|
|
|
|
|
|
if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
|
|
|
|
// For PIC, the sequence is:
|
|
|
|
// BRIND(load(Jumptable + index) + RelocBase)
|
|
|
|
// RelocBase can be JumpTable, GOT or some sort of global base.
|
|
|
|
Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
|
|
|
|
getPICJumpTableRelocBase(Table, DAG));
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
|
|
|
|
}
|
|
|
|
|
2008-07-28 19:11:24 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
|
2008-07-28 19:11:24 +00:00
|
|
|
{
|
2010-11-23 03:31:01 +00:00
|
|
|
// The first operand is the chain, the second is the condition, the third is
|
2008-07-28 19:11:24 +00:00
|
|
|
// the block to branch to if the condition is true.
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Dest = Op.getOperand(2);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2008-07-31 18:31:28 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
|
2011-03-31 18:26:17 +00:00
|
|
|
|
2011-04-15 05:18:47 +00:00
|
|
|
// Return if flag is not set by a floating point comparison.
|
2011-03-31 18:26:17 +00:00
|
|
|
if (CondRes.getOpcode() != MipsISD::FPCmp)
|
2008-07-30 17:06:13 +00:00
|
|
|
return Op;
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2008-07-31 18:31:28 +00:00
|
|
|
SDValue CCNode = CondRes.getOperand(2);
|
2008-09-12 16:56:44 +00:00
|
|
|
Mips::CondCode CC =
|
|
|
|
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
|
2013-03-30 01:16:38 +00:00
|
|
|
unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
|
|
|
|
SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
|
2013-07-26 20:13:47 +00:00
|
|
|
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
|
2013-03-12 00:16:36 +00:00
|
|
|
return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
|
2013-07-26 20:13:47 +00:00
|
|
|
FCC0, Dest, CondRes);
|
2008-07-28 19:11:24 +00:00
|
|
|
}
|
|
|
|
|
2008-07-29 19:05:28 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerSELECT(SDValue Op, SelectionDAG &DAG) const
|
2008-07-29 19:05:28 +00:00
|
|
|
{
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
|
2008-07-29 19:05:28 +00:00
|
|
|
|
2011-04-15 05:18:47 +00:00
|
|
|
// Return if flag is not set by a floating point comparison.
|
2011-03-31 18:26:17 +00:00
|
|
|
if (Cond.getOpcode() != MipsISD::FPCmp)
|
|
|
|
return Op;
|
2008-08-13 07:13:40 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc(Op));
|
2008-07-29 19:05:28 +00:00
|
|
|
}
|
|
|
|
|
2012-07-11 19:32:27 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
|
2012-07-11 19:32:27 +00:00
|
|
|
{
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-07-11 19:32:27 +00:00
|
|
|
EVT Ty = Op.getOperand(0).getValueType();
|
2013-05-18 00:21:46 +00:00
|
|
|
SDValue Cond = DAG.getNode(ISD::SETCC, DL,
|
|
|
|
getSetCCResultType(*DAG.getContext(), Ty),
|
2012-07-11 19:32:27 +00:00
|
|
|
Op.getOperand(0), Op.getOperand(1),
|
|
|
|
Op.getOperand(4));
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
|
|
|
|
Op.getOperand(3));
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
|
|
|
SDValue Cond = createFPCmp(DAG, Op);
|
2012-03-09 23:46:03 +00:00
|
|
|
|
|
|
|
assert(Cond.getOpcode() == MipsISD::FPCmp &&
|
|
|
|
"Floating point operand expected.");
|
|
|
|
|
|
|
|
SDValue True = DAG.getConstant(1, MVT::i32);
|
|
|
|
SDValue False = DAG.getConstant(0, MVT::i32);
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
|
2012-03-09 23:46:03 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
|
2010-04-17 15:26:15 +00:00
|
|
|
SelectionDAG &DAG) const {
|
2009-02-06 21:50:26 +00:00
|
|
|
// FIXME there isn't actually debug info here
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-02-28 07:46:26 +00:00
|
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
2008-07-29 19:29:50 +00:00
|
|
|
|
2011-10-11 00:55:05 +00:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
|
2012-09-12 23:27:55 +00:00
|
|
|
const MipsTargetObjectFile &TLOF =
|
|
|
|
(const MipsTargetObjectFile&)getObjFileLowering();
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2009-08-13 05:41:27 +00:00
|
|
|
// %gp_rel relocation
|
2010-11-23 03:31:01 +00:00
|
|
|
if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
|
2009-09-01 17:27:58 +00:00
|
|
|
MipsII::MO_GPREL);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
|
2012-11-21 20:30:40 +00:00
|
|
|
DAG.getVTList(MVT::i32), &GA, 1);
|
2012-08-22 03:18:13 +00:00
|
|
|
SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
|
2013-03-12 00:16:36 +00:00
|
|
|
return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
|
2009-08-13 05:41:27 +00:00
|
|
|
}
|
2012-11-21 20:30:40 +00:00
|
|
|
|
2008-07-29 19:29:50 +00:00
|
|
|
// %hi/%lo relocation
|
2012-11-21 20:30:40 +00:00
|
|
|
return getAddrNonPIC(Op, DAG);
|
2008-07-29 19:29:50 +00:00
|
|
|
}
|
|
|
|
|
2012-11-21 20:30:40 +00:00
|
|
|
if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
|
|
|
|
return getAddrLocal(Op, DAG, HasMips64);
|
|
|
|
|
2012-11-21 20:40:38 +00:00
|
|
|
if (LargeGOT)
|
|
|
|
return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
|
|
|
|
MipsII::MO_GOT_LO16);
|
|
|
|
|
2012-11-21 20:30:40 +00:00
|
|
|
return getAddrGlobal(Op, DAG,
|
|
|
|
HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
|
2008-07-29 19:29:50 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
|
2011-03-04 20:01:52 +00:00
|
|
|
SelectionDAG &DAG) const {
|
2012-11-21 20:30:40 +00:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
|
|
|
|
return getAddrNonPIC(Op, DAG);
|
2011-04-25 17:10:45 +00:00
|
|
|
|
2012-11-21 20:30:40 +00:00
|
|
|
return getAddrLocal(Op, DAG, HasMips64);
|
2011-03-04 20:01:52 +00:00
|
|
|
}
|
|
|
|
|
2008-07-29 19:29:50 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
|
2008-07-29 19:29:50 +00:00
|
|
|
{
|
2011-12-14 18:26:41 +00:00
|
|
|
// If the relocation model is PIC, use the General Dynamic TLS Model or
|
|
|
|
// Local Dynamic TLS model, otherwise use the Initial Exec or
|
|
|
|
// Local Exec TLS Model.
|
2011-05-31 02:53:58 +00:00
|
|
|
|
|
|
|
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(GA);
|
2011-05-31 02:53:58 +00:00
|
|
|
const GlobalValue *GV = GA->getGlobal();
|
|
|
|
EVT PtrVT = getPointerTy();
|
|
|
|
|
2012-05-04 09:40:39 +00:00
|
|
|
TLSModel::Model model = getTargetMachine().getTLSModel(GV);
|
|
|
|
|
|
|
|
if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
|
2012-06-04 14:02:08 +00:00
|
|
|
// General Dynamic and Local Dynamic TLS Model.
|
|
|
|
unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
|
|
|
|
: MipsII::MO_TLSGD;
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
|
|
|
|
SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
|
|
|
|
getGlobalReg(DAG, PtrVT), TGA);
|
2011-12-08 21:05:38 +00:00
|
|
|
unsigned PtrSize = PtrVT.getSizeInBits();
|
|
|
|
IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
|
|
|
|
|
2011-12-11 12:21:34 +00:00
|
|
|
SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
|
2011-05-31 02:53:58 +00:00
|
|
|
|
|
|
|
ArgListTy Args;
|
|
|
|
ArgListEntry Entry;
|
|
|
|
Entry.Node = Argument;
|
2011-12-08 20:34:32 +00:00
|
|
|
Entry.Ty = PtrTy;
|
2011-05-31 02:53:58 +00:00
|
|
|
Args.push_back(Entry);
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2012-05-25 16:35:28 +00:00
|
|
|
TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
|
2012-02-28 18:51:51 +00:00
|
|
|
false, false, false, false, 0, CallingConv::C,
|
2013-03-12 00:16:36 +00:00
|
|
|
/*IsTailCall=*/false, /*doesNotRet=*/false,
|
2012-02-28 18:51:51 +00:00
|
|
|
/*isReturnValueUsed=*/true,
|
2013-03-12 00:16:36 +00:00
|
|
|
TlsGetAddr, Args, DAG, DL);
|
2012-05-25 16:35:28 +00:00
|
|
|
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
|
2011-05-31 02:53:58 +00:00
|
|
|
|
2011-12-14 18:26:41 +00:00
|
|
|
SDValue Ret = CallResult.first;
|
|
|
|
|
2012-05-04 09:40:39 +00:00
|
|
|
if (model != TLSModel::LocalDynamic)
|
2011-12-14 18:26:41 +00:00
|
|
|
return Ret;
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
|
2011-12-14 18:26:41 +00:00
|
|
|
MipsII::MO_DTPREL_HI);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
|
|
|
|
SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
|
2011-12-14 18:26:41 +00:00
|
|
|
MipsII::MO_DTPREL_LO);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
|
|
|
|
SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
|
|
|
|
return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
|
2011-06-21 01:02:03 +00:00
|
|
|
}
|
2011-05-31 02:53:58 +00:00
|
|
|
|
2011-06-21 01:02:03 +00:00
|
|
|
SDValue Offset;
|
2012-05-04 09:40:39 +00:00
|
|
|
if (model == TLSModel::InitialExec) {
|
2011-06-21 01:02:03 +00:00
|
|
|
// Initial Exec TLS Model
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
|
2011-06-21 01:02:03 +00:00
|
|
|
MipsII::MO_GOTTPREL);
|
2013-03-12 00:16:36 +00:00
|
|
|
TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
|
2012-02-24 22:34:47 +00:00
|
|
|
TGA);
|
2013-03-12 00:16:36 +00:00
|
|
|
Offset = DAG.getLoad(PtrVT, DL,
|
2011-06-21 01:02:03 +00:00
|
|
|
DAG.getEntryNode(), TGA, MachinePointerInfo(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0);
|
2011-06-21 01:02:03 +00:00
|
|
|
} else {
|
|
|
|
// Local Exec TLS Model
|
2012-05-04 09:40:39 +00:00
|
|
|
assert(model == TLSModel::LocalExec);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
|
2011-06-21 01:02:03 +00:00
|
|
|
MipsII::MO_TPREL_HI);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
|
2011-06-21 01:02:03 +00:00
|
|
|
MipsII::MO_TPREL_LO);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
|
|
|
|
Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
|
2011-05-31 02:53:58 +00:00
|
|
|
}
|
2011-06-21 01:02:03 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
|
|
|
|
return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
|
2008-07-29 19:29:50 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
|
2007-11-12 19:49:57 +00:00
|
|
|
{
|
2012-11-21 20:30:40 +00:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
|
|
|
|
return getAddrNonPIC(Op, DAG);
|
2007-11-12 19:49:57 +00:00
|
|
|
|
2012-11-21 20:30:40 +00:00
|
|
|
return getAddrLocal(Op, DAG, HasMips64);
|
2007-11-12 19:49:57 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
|
2008-07-09 04:15:08 +00:00
|
|
|
{
|
2008-07-23 16:01:50 +00:00
|
|
|
// gp_rel relocation
|
2010-11-23 03:31:01 +00:00
|
|
|
// FIXME: we should reference the constant pool using small data sections,
|
2011-04-15 05:18:47 +00:00
|
|
|
// but the asm printer currently doesn't support this feature without
|
2010-11-23 03:31:01 +00:00
|
|
|
// hacking it. This feature should come soon so we can uncomment the
|
2008-07-28 19:26:25 +00:00
|
|
|
// stuff below.
|
2009-08-03 02:22:28 +00:00
|
|
|
//if (IsInSmallSection(C->getType())) {
|
2009-08-11 20:47:22 +00:00
|
|
|
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
|
|
|
|
// SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
|
2010-11-23 03:31:01 +00:00
|
|
|
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
|
2009-11-25 12:17:58 +00:00
|
|
|
|
2012-11-21 20:30:40 +00:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
|
|
|
|
return getAddrNonPIC(Op, DAG);
|
2008-07-23 16:01:50 +00:00
|
|
|
|
2012-11-21 20:30:40 +00:00
|
|
|
return getAddrLocal(Op, DAG, HasMips64);
|
2008-07-09 04:15:08 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
2010-04-17 14:41:14 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2010-04-17 14:41:14 +00:00
|
|
|
SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
|
|
|
|
getPointerTy());
|
2010-02-06 21:00:02 +00:00
|
|
|
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
|
|
// memory location argument.
|
|
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
2013-03-12 00:16:36 +00:00
|
|
|
return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
|
2011-12-19 19:52:25 +00:00
|
|
|
MachinePointerInfo(SV), false, false, 0);
|
2010-02-06 21:00:02 +00:00
|
|
|
}
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
|
2012-04-11 22:13:04 +00:00
|
|
|
EVT TyX = Op.getOperand(0).getValueType();
|
|
|
|
EVT TyY = Op.getOperand(1).getValueType();
|
|
|
|
SDValue Const1 = DAG.getConstant(1, MVT::i32);
|
|
|
|
SDValue Const31 = DAG.getConstant(31, MVT::i32);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-04-11 22:13:04 +00:00
|
|
|
SDValue Res;
|
|
|
|
|
|
|
|
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
|
|
|
|
// to i32.
|
|
|
|
SDValue X = (TyX == MVT::f32) ?
|
|
|
|
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
|
|
|
|
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
|
|
|
|
Const1);
|
|
|
|
SDValue Y = (TyY == MVT::f32) ?
|
|
|
|
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
|
|
|
|
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
|
|
|
|
Const1);
|
|
|
|
|
|
|
|
if (HasR2) {
|
|
|
|
// ext E, Y, 31, 1 ; extract bit31 of Y
|
|
|
|
// ins X, E, 31, 1 ; insert extracted bit at bit31 of X
|
|
|
|
SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
|
|
|
|
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
|
|
|
|
} else {
|
|
|
|
// sll SllX, X, 1
|
|
|
|
// srl SrlX, SllX, 1
|
|
|
|
// srl SrlY, Y, 31
|
|
|
|
// sll SllY, SrlX, 31
|
|
|
|
// or Or, SrlX, SllY
|
|
|
|
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
|
|
|
|
SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
|
|
|
|
SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
|
|
|
|
SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
|
|
|
|
Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
|
|
|
|
}
|
2011-05-25 19:32:07 +00:00
|
|
|
|
2012-04-11 22:13:04 +00:00
|
|
|
if (TyX == MVT::f32)
|
|
|
|
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
|
2011-06-08 23:55:35 +00:00
|
|
|
|
2012-04-11 22:13:04 +00:00
|
|
|
SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
|
|
|
|
Op.getOperand(0), DAG.getConstant(0, MVT::i32));
|
|
|
|
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
|
|
|
|
}
|
2011-05-25 19:32:07 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
|
2012-04-11 22:13:04 +00:00
|
|
|
unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
|
|
|
|
unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
|
|
|
|
EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
|
|
|
|
SDValue Const1 = DAG.getConstant(1, MVT::i32);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-04-11 22:13:04 +00:00
|
|
|
|
|
|
|
// Bitcast to integer nodes.
|
|
|
|
SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
|
|
|
|
SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
|
|
|
|
|
|
|
|
if (HasR2) {
|
|
|
|
// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
|
|
|
|
// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
|
|
|
|
SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
|
|
|
|
DAG.getConstant(WidthY - 1, MVT::i32), Const1);
|
|
|
|
|
|
|
|
if (WidthX > WidthY)
|
|
|
|
E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
|
|
|
|
else if (WidthY > WidthX)
|
|
|
|
E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
|
|
|
|
|
|
|
|
SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
|
|
|
|
DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
|
|
|
|
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
|
|
|
|
}
|
|
|
|
|
|
|
|
// (d)sll SllX, X, 1
|
|
|
|
// (d)srl SrlX, SllX, 1
|
|
|
|
// (d)srl SrlY, Y, width(Y)-1
|
|
|
|
// (d)sll SllY, SrlX, width(Y)-1
|
|
|
|
// or Or, SrlX, SllY
|
|
|
|
SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
|
|
|
|
SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
|
|
|
|
SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
|
|
|
|
DAG.getConstant(WidthY - 1, MVT::i32));
|
|
|
|
|
|
|
|
if (WidthX > WidthY)
|
|
|
|
SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
|
|
|
|
else if (WidthY > WidthX)
|
|
|
|
SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
|
|
|
|
|
|
|
|
SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
|
|
|
|
DAG.getConstant(WidthX - 1, MVT::i32));
|
|
|
|
SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
|
|
|
|
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
|
2011-05-25 19:32:07 +00:00
|
|
|
}
|
|
|
|
|
2011-12-19 19:52:25 +00:00
|
|
|
SDValue
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
|
2012-04-11 22:13:04 +00:00
|
|
|
if (Subtarget->hasMips64())
|
2013-03-12 00:16:36 +00:00
|
|
|
return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
|
2011-05-25 19:32:07 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
|
2012-04-11 22:49:04 +00:00
|
|
|
SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-04-11 22:49:04 +00:00
|
|
|
|
|
|
|
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
|
|
|
|
// to i32.
|
|
|
|
SDValue X = (Op.getValueType() == MVT::f32) ?
|
|
|
|
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
|
|
|
|
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
|
|
|
|
Const1);
|
|
|
|
|
|
|
|
// Clear MSB.
|
|
|
|
if (HasR2)
|
|
|
|
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
|
|
|
|
DAG.getRegister(Mips::ZERO, MVT::i32),
|
|
|
|
DAG.getConstant(31, MVT::i32), Const1, X);
|
|
|
|
else {
|
|
|
|
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
|
|
|
|
Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op.getValueType() == MVT::f32)
|
|
|
|
return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
|
|
|
|
|
|
|
|
SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
|
|
|
|
Op.getOperand(0), DAG.getConstant(0, MVT::i32));
|
|
|
|
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
|
2012-04-11 22:49:04 +00:00
|
|
|
SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-04-11 22:49:04 +00:00
|
|
|
|
|
|
|
// Bitcast to integer node.
|
|
|
|
SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
|
|
|
|
|
|
|
|
// Clear MSB.
|
|
|
|
if (HasR2)
|
|
|
|
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
|
|
|
|
DAG.getRegister(Mips::ZERO_64, MVT::i64),
|
|
|
|
DAG.getConstant(63, MVT::i32), Const1, X);
|
|
|
|
else {
|
|
|
|
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
|
|
|
|
Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
|
2012-04-11 22:49:04 +00:00
|
|
|
if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
|
2013-03-12 00:16:36 +00:00
|
|
|
return lowerFABS64(Op, DAG, Subtarget->hasMips32r2());
|
2012-04-11 22:49:04 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
return lowerFABS32(Op, DAG, Subtarget->hasMips32r2());
|
2012-04-11 22:49:04 +00:00
|
|
|
}
|
|
|
|
|
2011-06-02 00:24:44 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2013-03-12 00:16:36 +00:00
|
|
|
lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
|
2011-06-16 00:40:02 +00:00
|
|
|
// check the depth
|
|
|
|
assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
|
2011-06-07 18:58:42 +00:00
|
|
|
"Frame address can only be determined for current frame.");
|
2011-06-02 00:24:44 +00:00
|
|
|
|
|
|
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
MFI->setFrameAddressIsTaken(true);
|
|
|
|
EVT VT = Op.getValueType();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
|
2011-11-11 04:11:56 +00:00
|
|
|
IsN64 ? Mips::FP_64 : Mips::FP, VT);
|
2011-06-02 00:24:44 +00:00
|
|
|
return FrameAddr;
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
|
2012-07-11 00:53:32 +00:00
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
// check the depth
|
|
|
|
assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
|
|
|
|
"Return address can be determined only for current frame.");
|
|
|
|
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2012-12-13 06:34:11 +00:00
|
|
|
MVT VT = Op.getSimpleValueType();
|
2012-07-11 00:53:32 +00:00
|
|
|
unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
|
|
|
|
MFI->setReturnAddressIsTaken(true);
|
|
|
|
|
|
|
|
// Return RA, which contains the return address. Mark it an implicit live-in.
|
|
|
|
unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
|
2012-07-11 00:53:32 +00:00
|
|
|
}
|
|
|
|
|
2013-01-30 00:26:49 +00:00
|
|
|
// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
|
|
|
|
// generated from __builtin_eh_return (offset, handler)
|
|
|
|
// The effect of this is to adjust the stack pointer by "offset"
|
|
|
|
// and then branch to "handler".
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
|
2013-01-30 00:26:49 +00:00
|
|
|
const {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
|
|
|
|
MipsFI->setCallsEhReturn();
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Offset = Op.getOperand(1);
|
|
|
|
SDValue Handler = Op.getOperand(2);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2013-01-30 00:26:49 +00:00
|
|
|
EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
|
|
|
|
|
|
|
|
// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
|
|
|
|
// EH_RETURN nodes, so that instructions are emitted back-to-back.
|
|
|
|
unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
|
|
|
|
unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
|
|
|
|
Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
|
|
|
|
Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
|
|
|
|
return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
|
|
|
|
DAG.getRegister(OffsetReg, Ty),
|
|
|
|
DAG.getRegister(AddrReg, getPointerTy()),
|
|
|
|
Chain.getValue(1));
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
|
2012-06-14 21:10:56 +00:00
|
|
|
SelectionDAG &DAG) const {
|
2011-07-27 22:21:52 +00:00
|
|
|
// FIXME: Need pseudo-fence for 'singlethread' fences
|
|
|
|
// FIXME: Set SType for weaker fences where supported/appropriate.
|
|
|
|
unsigned SType = 0;
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2013-03-12 00:16:36 +00:00
|
|
|
return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
|
2011-07-27 22:21:52 +00:00
|
|
|
DAG.getConstant(SType, MVT::i32));
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
|
2012-06-14 21:10:56 +00:00
|
|
|
SelectionDAG &DAG) const {
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-05-09 00:55:21 +00:00
|
|
|
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
|
|
|
|
SDValue Shamt = Op.getOperand(2);
|
|
|
|
|
|
|
|
// if shamt < 32:
|
|
|
|
// lo = (shl lo, shamt)
|
|
|
|
// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
|
|
|
|
// else:
|
|
|
|
// lo = 0
|
|
|
|
// hi = (shl lo, shamt[4:0])
|
|
|
|
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
|
|
|
|
DAG.getConstant(-1, MVT::i32));
|
|
|
|
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
|
|
|
|
DAG.getConstant(1, MVT::i32));
|
|
|
|
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
|
|
|
|
Not);
|
|
|
|
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
|
|
|
|
SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
|
|
|
|
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
|
|
|
|
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
|
|
|
|
DAG.getConstant(0x20, MVT::i32));
|
2012-06-14 21:10:56 +00:00
|
|
|
Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
|
|
|
|
DAG.getConstant(0, MVT::i32), ShiftLeftLo);
|
2012-05-09 00:55:21 +00:00
|
|
|
Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
|
|
|
|
|
|
|
|
SDValue Ops[2] = {Lo, Hi};
|
|
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
|
2012-05-09 00:55:21 +00:00
|
|
|
bool IsSRA) const {
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2012-05-09 00:55:21 +00:00
|
|
|
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
|
|
|
|
SDValue Shamt = Op.getOperand(2);
|
|
|
|
|
|
|
|
// if shamt < 32:
|
|
|
|
// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
|
|
|
|
// if isSRA:
|
|
|
|
// hi = (sra hi, shamt)
|
|
|
|
// else:
|
|
|
|
// hi = (srl hi, shamt)
|
|
|
|
// else:
|
|
|
|
// if isSRA:
|
|
|
|
// lo = (sra hi, shamt[4:0])
|
|
|
|
// hi = (sra hi, 31)
|
|
|
|
// else:
|
|
|
|
// lo = (srl hi, shamt[4:0])
|
|
|
|
// hi = 0
|
|
|
|
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
|
|
|
|
DAG.getConstant(-1, MVT::i32));
|
|
|
|
SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
|
|
|
|
DAG.getConstant(1, MVT::i32));
|
|
|
|
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
|
|
|
|
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
|
|
|
|
SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
|
|
|
|
SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
|
|
|
|
Hi, Shamt);
|
|
|
|
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
|
|
|
|
DAG.getConstant(0x20, MVT::i32));
|
|
|
|
SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
|
|
|
|
DAG.getConstant(31, MVT::i32));
|
|
|
|
Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
|
|
|
|
Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
|
|
|
|
IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
|
|
|
|
ShiftRightHi);
|
|
|
|
|
|
|
|
SDValue Ops[2] = {Lo, Hi};
|
|
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
|
|
}
|
|
|
|
|
2013-04-11 19:07:14 +00:00
|
|
|
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
|
2012-06-02 00:03:49 +00:00
|
|
|
SDValue Chain, SDValue Src, unsigned Offset) {
|
2012-06-13 19:06:08 +00:00
|
|
|
SDValue Ptr = LD->getBasePtr();
|
2012-06-02 00:03:49 +00:00
|
|
|
EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
|
2012-06-13 19:06:08 +00:00
|
|
|
EVT BasePtrVT = Ptr.getValueType();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(LD);
|
2012-06-02 00:03:49 +00:00
|
|
|
SDVTList VTList = DAG.getVTList(VT, MVT::Other);
|
|
|
|
|
|
|
|
if (Offset)
|
2012-06-13 19:06:08 +00:00
|
|
|
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
|
2012-06-02 00:03:49 +00:00
|
|
|
DAG.getConstant(Offset, BasePtrVT));
|
|
|
|
|
|
|
|
SDValue Ops[] = { Chain, Ptr, Src };
|
|
|
|
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
|
|
|
|
LD->getMemOperand());
|
|
|
|
}
|
|
|
|
|
|
|
|
// Expand an unaligned 32 or 64-bit integer load node.
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
|
2012-06-02 00:03:49 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(Op);
|
|
|
|
EVT MemVT = LD->getMemoryVT();
|
|
|
|
|
|
|
|
// Return if load is aligned or if MemVT is neither i32 nor i64.
|
|
|
|
if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
|
|
|
|
((MemVT != MVT::i32) && (MemVT != MVT::i64)))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
bool IsLittle = Subtarget->isLittle();
|
|
|
|
EVT VT = Op.getValueType();
|
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
|
|
SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
|
|
|
|
|
|
|
|
assert((VT == MVT::i32) || (VT == MVT::i64));
|
|
|
|
|
|
|
|
// Expand
|
|
|
|
// (set dst, (i64 (load baseptr)))
|
|
|
|
// to
|
|
|
|
// (set tmp, (ldl (add baseptr, 7), undef))
|
|
|
|
// (set dst, (ldr baseptr, tmp))
|
|
|
|
if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
|
2013-04-11 19:07:14 +00:00
|
|
|
SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
|
2012-06-02 00:03:49 +00:00
|
|
|
IsLittle ? 7 : 0);
|
2013-04-11 19:07:14 +00:00
|
|
|
return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
|
2012-06-02 00:03:49 +00:00
|
|
|
IsLittle ? 0 : 7);
|
|
|
|
}
|
|
|
|
|
2013-04-11 19:07:14 +00:00
|
|
|
SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
|
2012-06-02 00:03:49 +00:00
|
|
|
IsLittle ? 3 : 0);
|
2013-04-11 19:07:14 +00:00
|
|
|
SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
|
2012-06-02 00:03:49 +00:00
|
|
|
IsLittle ? 0 : 3);
|
|
|
|
|
|
|
|
// Expand
|
|
|
|
// (set dst, (i32 (load baseptr))) or
|
|
|
|
// (set dst, (i64 (sextload baseptr))) or
|
|
|
|
// (set dst, (i64 (extload baseptr)))
|
|
|
|
// to
|
|
|
|
// (set tmp, (lwl (add baseptr, 3), undef))
|
|
|
|
// (set dst, (lwr baseptr, tmp))
|
|
|
|
if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
|
|
|
|
(ExtType == ISD::EXTLOAD))
|
|
|
|
return LWR;
|
|
|
|
|
|
|
|
assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
|
|
|
|
|
|
|
|
// Expand
|
|
|
|
// (set dst, (i64 (zextload baseptr)))
|
|
|
|
// to
|
|
|
|
// (set tmp0, (lwl (add baseptr, 3), undef))
|
|
|
|
// (set tmp1, (lwr baseptr, tmp0))
|
|
|
|
// (set tmp2, (shl tmp1, 32))
|
|
|
|
// (set dst, (srl tmp2, 32))
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(LD);
|
2012-06-02 00:03:49 +00:00
|
|
|
SDValue Const32 = DAG.getConstant(32, MVT::i32);
|
|
|
|
SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
|
2012-06-04 17:46:29 +00:00
|
|
|
SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
|
|
|
|
SDValue Ops[] = { SRL, LWR.getValue(1) };
|
2012-06-02 00:03:49 +00:00
|
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
|
|
}
|
|
|
|
|
2013-04-11 19:07:14 +00:00
|
|
|
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
|
2012-06-02 00:03:49 +00:00
|
|
|
SDValue Chain, unsigned Offset) {
|
2012-06-13 19:06:08 +00:00
|
|
|
SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
|
|
|
|
EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(SD);
|
2012-06-02 00:03:49 +00:00
|
|
|
SDVTList VTList = DAG.getVTList(MVT::Other);
|
|
|
|
|
|
|
|
if (Offset)
|
2012-06-13 19:06:08 +00:00
|
|
|
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
|
2012-06-02 00:03:49 +00:00
|
|
|
DAG.getConstant(Offset, BasePtrVT));
|
|
|
|
|
|
|
|
SDValue Ops[] = { Chain, Value, Ptr };
|
|
|
|
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
|
|
|
|
SD->getMemOperand());
|
|
|
|
}
|
|
|
|
|
|
|
|
// Expand an unaligned 32 or 64-bit integer store node.
|
2013-05-16 20:45:17 +00:00
|
|
|
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
|
|
|
|
bool IsLittle) {
|
2012-06-02 00:03:49 +00:00
|
|
|
SDValue Value = SD->getValue(), Chain = SD->getChain();
|
|
|
|
EVT VT = Value.getValueType();
|
|
|
|
|
|
|
|
// Expand
|
|
|
|
// (store val, baseptr) or
|
|
|
|
// (truncstore val, baseptr)
|
|
|
|
// to
|
|
|
|
// (swl val, (add baseptr, 3))
|
|
|
|
// (swr val, baseptr)
|
|
|
|
if ((VT == MVT::i32) || SD->isTruncatingStore()) {
|
2013-04-11 19:07:14 +00:00
|
|
|
SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
|
2012-06-02 00:03:49 +00:00
|
|
|
IsLittle ? 3 : 0);
|
2013-04-11 19:07:14 +00:00
|
|
|
return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
|
2012-06-02 00:03:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
assert(VT == MVT::i64);
|
|
|
|
|
|
|
|
// Expand
|
|
|
|
// (store val, baseptr)
|
|
|
|
// to
|
|
|
|
// (sdl val, (add baseptr, 7))
|
|
|
|
// (sdr val, baseptr)
|
2013-04-11 19:07:14 +00:00
|
|
|
SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
|
|
|
|
return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
|
2012-06-02 00:03:49 +00:00
|
|
|
}
|
|
|
|
|
2013-05-16 21:17:15 +00:00
|
|
|
// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
|
|
|
|
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
|
|
|
|
SDValue Val = SD->getValue();
|
|
|
|
|
|
|
|
if (Val.getOpcode() != ISD::FP_TO_SINT)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
|
2013-05-25 02:42:55 +00:00
|
|
|
SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
|
2013-05-16 21:17:15 +00:00
|
|
|
Val.getOperand(0));
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
|
2013-05-16 21:17:15 +00:00
|
|
|
SD->getPointerInfo(), SD->isVolatile(),
|
|
|
|
SD->isNonTemporal(), SD->getAlignment());
|
|
|
|
}
|
|
|
|
|
2013-05-16 20:45:17 +00:00
|
|
|
SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
|
|
|
StoreSDNode *SD = cast<StoreSDNode>(Op);
|
|
|
|
EVT MemVT = SD->getMemoryVT();
|
|
|
|
|
|
|
|
// Lower unaligned integer stores.
|
|
|
|
if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
|
|
|
|
((MemVT == MVT::i32) || (MemVT == MVT::i64)))
|
|
|
|
return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
|
|
|
|
|
2013-05-16 21:17:15 +00:00
|
|
|
return lowerFP_TO_SINT_STORE(SD, DAG);
|
2013-05-16 20:45:17 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
|
2012-11-07 19:10:58 +00:00
|
|
|
if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
|
|
|
|
|| cast<ConstantSDNode>
|
|
|
|
(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
|
|
|
|
|| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// The pattern
|
|
|
|
// (add (frameaddr 0), (frame_to_args_offset))
|
|
|
|
// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
|
|
|
|
// (add FrameObject, 0)
|
|
|
|
// where FrameObject is a fixed StackObject with offset 0 which points to
|
|
|
|
// the old stack pointer.
|
|
|
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
EVT ValTy = Op->getValueType(0);
|
|
|
|
int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
|
|
|
|
SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
|
2012-11-07 19:10:58 +00:00
|
|
|
DAG.getConstant(0, ValTy));
|
|
|
|
}
|
|
|
|
|
2013-05-16 21:17:15 +00:00
|
|
|
SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
|
2013-05-25 02:42:55 +00:00
|
|
|
SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
|
2013-05-16 21:17:15 +00:00
|
|
|
Op.getOperand(0));
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
|
2013-05-16 21:17:15 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-11-23 03:31:01 +00:00
|
|
|
// TODO: Implement a generic logic using tblgen that can support this.
|
2009-03-19 02:12:28 +00:00
|
|
|
// Mips O32 ABI rules:
|
|
|
|
// ---
|
|
|
|
// i32 - Passed in A0, A1, A2, A3 and stack
|
2010-11-23 03:31:01 +00:00
|
|
|
// f32 - Only passed in f32 registers if no int reg has been used yet to hold
|
2009-03-19 02:12:28 +00:00
|
|
|
// an argument. Otherwise, passed in A1, A2, A3 and stack.
|
2010-11-23 03:31:01 +00:00
|
|
|
// f64 - Only passed in two aliased f32 registers if no int reg has been used
|
|
|
|
// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
|
2009-03-19 02:12:28 +00:00
|
|
|
// not used, it must be shadowed. If only A3 is avaiable, shadow it and
|
|
|
|
// go to stack.
|
2011-05-19 18:06:05 +00:00
|
|
|
//
|
|
|
|
// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2010-11-04 10:49:57 +00:00
|
|
|
static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
2013-08-20 23:38:40 +00:00
|
|
|
ISD::ArgFlagsTy ArgFlags, CCState &State,
|
|
|
|
const uint16_t *F64Regs) {
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
static const unsigned IntRegsSize=4, FloatRegsSize=2;
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2012-03-11 07:57:25 +00:00
|
|
|
static const uint16_t IntRegs[] = {
|
2009-03-19 02:12:28 +00:00
|
|
|
Mips::A0, Mips::A1, Mips::A2, Mips::A3
|
|
|
|
};
|
2012-03-11 07:57:25 +00:00
|
|
|
static const uint16_t F32Regs[] = {
|
2009-03-19 02:12:28 +00:00
|
|
|
Mips::F12, Mips::F14
|
|
|
|
};
|
|
|
|
|
2012-10-27 00:29:43 +00:00
|
|
|
// Do not process byval args here.
|
|
|
|
if (ArgFlags.isByVal())
|
|
|
|
return true;
|
2011-05-24 19:18:33 +00:00
|
|
|
|
2010-02-06 19:20:49 +00:00
|
|
|
// Promote i8 and i16
|
|
|
|
if (LocVT == MVT::i8 || LocVT == MVT::i16) {
|
|
|
|
LocVT = MVT::i32;
|
|
|
|
if (ArgFlags.isSExt())
|
|
|
|
LocInfo = CCValAssign::SExt;
|
|
|
|
else if (ArgFlags.isZExt())
|
|
|
|
LocInfo = CCValAssign::ZExt;
|
|
|
|
else
|
|
|
|
LocInfo = CCValAssign::AExt;
|
|
|
|
}
|
|
|
|
|
2011-03-04 20:27:44 +00:00
|
|
|
unsigned Reg;
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2011-05-19 18:06:05 +00:00
|
|
|
// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
|
|
|
|
// is true: function is vararg, argument is 3rd or higher, there is previous
|
|
|
|
// argument which is not f32 or f64.
|
|
|
|
bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
|
|
|
|
|| State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
|
2011-05-19 20:29:48 +00:00
|
|
|
unsigned OrigAlign = ArgFlags.getOrigAlign();
|
|
|
|
bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
|
2011-05-19 18:06:05 +00:00
|
|
|
|
|
|
|
if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
|
2011-03-04 20:27:44 +00:00
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
2011-05-19 20:29:48 +00:00
|
|
|
// If this is the first part of an i64 arg,
|
|
|
|
// the allocated register must be either A0 or A2.
|
|
|
|
if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
2011-03-04 20:27:44 +00:00
|
|
|
LocVT = MVT::i32;
|
2011-05-19 18:06:05 +00:00
|
|
|
} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
|
|
|
|
// Allocate int register and shadow next int register. If first
|
|
|
|
// available register is Mips::A1 or Mips::A3, shadow it too.
|
2011-03-04 20:27:44 +00:00
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
if (Reg == Mips::A1 || Reg == Mips::A3)
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
LocVT = MVT::i32;
|
2011-05-19 18:06:05 +00:00
|
|
|
} else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
|
|
|
|
// we are guaranteed to find an available float register
|
|
|
|
if (ValVT == MVT::f32) {
|
|
|
|
Reg = State.AllocateReg(F32Regs, FloatRegsSize);
|
|
|
|
// Shadow int register
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
} else {
|
|
|
|
Reg = State.AllocateReg(F64Regs, FloatRegsSize);
|
|
|
|
// Shadow int registers
|
|
|
|
unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
}
|
2011-03-04 20:27:44 +00:00
|
|
|
} else
|
|
|
|
llvm_unreachable("Cannot handle this ValVT.");
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2012-10-27 00:29:43 +00:00
|
|
|
if (!Reg) {
|
|
|
|
unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
|
|
|
|
OrigAlign);
|
2011-03-04 20:27:44 +00:00
|
|
|
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
2012-10-27 00:29:43 +00:00
|
|
|
} else
|
2011-03-04 20:27:44 +00:00
|
|
|
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2012-10-27 00:29:43 +00:00
|
|
|
return false;
|
2011-11-12 02:20:46 +00:00
|
|
|
}
|
|
|
|
|
2013-08-20 23:38:40 +00:00
|
|
|
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
|
|
|
|
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
|
|
|
ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
|
|
|
static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 };
|
|
|
|
|
|
|
|
return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
|
|
|
|
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
|
|
|
ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
|
|
|
static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 };
|
|
|
|
|
|
|
|
return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
|
|
|
|
}
|
|
|
|
|
2011-11-12 02:20:46 +00:00
|
|
|
#include "MipsGenCallingConv.inc"
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
// Call Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-09-23 00:58:33 +00:00
|
|
|
// Return next O32 integer argument register.
|
|
|
|
static unsigned getNextIntArgReg(unsigned Reg) {
|
|
|
|
assert((Reg == Mips::A0) || (Reg == Mips::A2));
|
|
|
|
return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
|
|
|
|
}
|
|
|
|
|
2012-10-30 19:23:25 +00:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDValue Chain, SDValue Arg, SDLoc DL,
|
2012-10-30 19:23:25 +00:00
|
|
|
bool IsTailCall, SelectionDAG &DAG) const {
|
|
|
|
if (!IsTailCall) {
|
|
|
|
SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
|
|
|
|
DAG.getIntPtrConstant(Offset));
|
|
|
|
return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
|
|
|
|
false, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
|
|
|
|
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
|
|
|
|
/*isVolatile=*/ true, false, 0);
|
|
|
|
}
|
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
void MipsTargetLowering::
|
|
|
|
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
|
|
|
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
|
|
|
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
|
|
|
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
|
|
|
|
// Insert node "GP copy globalreg" before call to function.
|
|
|
|
//
|
|
|
|
// R_MIPS_CALL* operators (emitted when non-internal functions are called
|
|
|
|
// in PIC mode) allow symbols to be resolved via lazy binding.
|
|
|
|
// The lazy binding stub requires GP to point to the GOT.
|
|
|
|
if (IsPICCall && !InternalLinkage) {
|
|
|
|
unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
|
|
|
|
EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
|
|
|
|
RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
|
2013-01-24 04:24:02 +00:00
|
|
|
}
|
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token
|
|
|
|
// chain and flag operands which copy the outgoing args into registers.
|
|
|
|
// The InFlag in necessary since all emitted instructions must be
|
|
|
|
// stuck together.
|
|
|
|
SDValue InFlag;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
|
|
Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
2013-01-24 04:24:02 +00:00
|
|
|
}
|
2013-03-13 00:54:29 +00:00
|
|
|
|
|
|
|
// Add argument registers to the end of the list so that they are
|
|
|
|
// known live into the call.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
|
|
Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
|
|
|
|
// Add a register mask operand representing the call-preserved registers.
|
|
|
|
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
|
|
|
|
const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
|
|
|
|
assert(Mask && "Missing call preserved mask for calling convention");
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
if (Subtarget->inMips16HardFloat()) {
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
|
|
|
|
llvm::StringRef Sym = G->getGlobal()->getName();
|
|
|
|
Function *F = G->getGlobal()->getParent()->getFunction(Sym);
|
|
|
|
if (F->hasFnAttribute("__Mips16RetHelper")) {
|
|
|
|
Mask = MipsRegisterInfo::getMips16RetHelperMask();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2013-03-13 00:54:29 +00:00
|
|
|
Ops.push_back(CLI.DAG.getRegisterMask(Mask));
|
|
|
|
|
|
|
|
if (InFlag.getNode())
|
|
|
|
Ops.push_back(InFlag);
|
2013-01-24 04:24:02 +00:00
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
/// LowerCall - functions arguments are copied from virtual regs to
|
2009-01-26 03:15:54 +00:00
|
|
|
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue
|
2012-05-25 16:35:28 +00:00
|
|
|
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
2010-04-17 15:26:15 +00:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const {
|
2012-05-25 16:35:28 +00:00
|
|
|
SelectionDAG &DAG = CLI.DAG;
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL = CLI.DL;
|
2013-07-14 04:42:23 +00:00
|
|
|
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
|
|
|
|
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
|
|
|
|
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
|
2012-07-31 18:46:41 +00:00
|
|
|
SDValue Chain = CLI.Chain;
|
2012-05-25 16:35:28 +00:00
|
|
|
SDValue Callee = CLI.Callee;
|
2013-03-12 00:16:36 +00:00
|
|
|
bool &IsTailCall = CLI.IsTailCall;
|
2012-05-25 16:35:28 +00:00
|
|
|
CallingConv::ID CallConv = CLI.CallConv;
|
2013-03-12 00:16:36 +00:00
|
|
|
bool IsVarArg = CLI.IsVarArg;
|
2012-05-25 16:35:28 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-07-11 23:16:16 +00:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2011-05-20 21:39:54 +00:00
|
|
|
const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
|
2009-09-01 17:27:58 +00:00
|
|
|
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2013-03-12 00:16:36 +00:00
|
|
|
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
|
2011-12-19 19:52:25 +00:00
|
|
|
getTargetMachine(), ArgLocs, *DAG.getContext());
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
MipsCC::SpecialCallingConvType SpecialCallingConv =
|
|
|
|
getSpecialCallingConv(Callee);
|
2013-08-20 23:38:40 +00:00
|
|
|
MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo,
|
|
|
|
SpecialCallingConv);
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
|
2013-08-30 19:40:56 +00:00
|
|
|
Subtarget->mipsSEUsesSoftFloat(),
|
2013-03-05 22:20:28 +00:00
|
|
|
Callee.getNode(), CLI.Args);
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
2011-06-08 17:39:33 +00:00
|
|
|
unsigned NextStackOffset = CCInfo.getNextStackOffset();
|
2012-07-26 23:27:01 +00:00
|
|
|
|
2012-10-19 21:47:33 +00:00
|
|
|
// Check if it's really possible to do a tail call.
|
2013-03-12 00:16:36 +00:00
|
|
|
if (IsTailCall)
|
|
|
|
IsTailCall =
|
|
|
|
isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
|
2012-10-30 20:16:31 +00:00
|
|
|
*MF.getInfo<MipsFunctionInfo>());
|
2012-10-19 21:47:33 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
if (IsTailCall)
|
2012-10-19 21:47:33 +00:00
|
|
|
++NumTailCalls;
|
|
|
|
|
2011-09-19 20:26:02 +00:00
|
|
|
// Chain is the output chain of the last Load/Store or CopyToReg node.
|
|
|
|
// ByValChain is the output chain of the last Memcpy node created for copying
|
|
|
|
// byval arguments to the stack.
|
2012-10-30 20:16:31 +00:00
|
|
|
unsigned StackAlignment = TFL->getStackAlignment();
|
|
|
|
NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
|
2011-09-19 20:26:02 +00:00
|
|
|
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
|
2012-10-19 21:47:33 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
if (!IsTailCall)
|
2013-05-29 22:03:55 +00:00
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
|
2012-07-31 18:46:41 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
|
2012-07-31 18:46:41 +00:00
|
|
|
IsN64 ? Mips::SP_64 : Mips::SP,
|
|
|
|
getPointerTy());
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-06-08 17:39:33 +00:00
|
|
|
// With EABI is it possible to have 16 args on registers.
|
2013-01-22 20:05:56 +00:00
|
|
|
std::deque< std::pair<unsigned, SDValue> > RegsToPass;
|
2011-06-08 17:39:33 +00:00
|
|
|
SmallVector<SDValue, 8> MemOpChains;
|
2012-10-27 00:29:43 +00:00
|
|
|
MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
|
2011-06-08 17:39:33 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Walk the register/memloc assignments, inserting copies/loads.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
2010-07-07 15:54:55 +00:00
|
|
|
SDValue Arg = OutVals[i];
|
2007-06-06 07:42:06 +00:00
|
|
|
CCValAssign &VA = ArgLocs[i];
|
2011-10-28 19:49:00 +00:00
|
|
|
MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
|
2011-11-12 02:34:50 +00:00
|
|
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
|
|
|
|
|
|
|
// ByVal Arg.
|
|
|
|
if (Flags.isByVal()) {
|
|
|
|
assert(Flags.getByValSize() &&
|
|
|
|
"ByVal args of size 0 should have been ignored by front-end.");
|
2012-10-27 00:29:43 +00:00
|
|
|
assert(ByValArg != MipsCCInfo.byval_end());
|
2013-03-12 00:16:36 +00:00
|
|
|
assert(!IsTailCall &&
|
2012-10-30 20:16:31 +00:00
|
|
|
"Do not tail-call optimize if there is a byval argument.");
|
2013-03-12 00:16:36 +00:00
|
|
|
passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
|
2012-10-27 00:29:43 +00:00
|
|
|
MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
|
|
|
|
++ByValArg;
|
2011-11-12 02:34:50 +00:00
|
|
|
continue;
|
|
|
|
}
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Promote the value if needed.
|
|
|
|
switch (VA.getLocInfo()) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unknown loc info!");
|
2010-11-23 03:31:01 +00:00
|
|
|
case CCValAssign::Full:
|
2011-10-28 19:49:00 +00:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
|
2013-03-05 22:20:28 +00:00
|
|
|
(ValVT == MVT::f64 && LocVT == MVT::i64) ||
|
|
|
|
(ValVT == MVT::i64 && LocVT == MVT::f64))
|
2013-03-12 00:16:36 +00:00
|
|
|
Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
|
2011-10-28 19:49:00 +00:00
|
|
|
else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
|
2011-04-15 21:51:11 +00:00
|
|
|
Arg, DAG.getConstant(0, MVT::i32));
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
|
2011-04-15 21:00:26 +00:00
|
|
|
Arg, DAG.getConstant(1, MVT::i32));
|
2011-04-15 19:52:08 +00:00
|
|
|
if (!Subtarget->isLittle())
|
|
|
|
std::swap(Lo, Hi);
|
2012-02-28 07:46:26 +00:00
|
|
|
unsigned LocRegLo = VA.getLocReg();
|
2011-09-23 00:58:33 +00:00
|
|
|
unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
|
|
|
|
RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
|
|
|
|
RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
|
2009-03-19 02:12:28 +00:00
|
|
|
continue;
|
2010-11-23 03:31:01 +00:00
|
|
|
}
|
2009-03-19 02:12:28 +00:00
|
|
|
}
|
|
|
|
break;
|
2008-03-17 06:57:02 +00:00
|
|
|
case CCValAssign::SExt:
|
2013-03-12 00:16:36 +00:00
|
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
|
2008-03-17 06:57:02 +00:00
|
|
|
break;
|
|
|
|
case CCValAssign::ZExt:
|
2013-03-12 00:16:36 +00:00
|
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
|
2008-03-17 06:57:02 +00:00
|
|
|
break;
|
|
|
|
case CCValAssign::AExt:
|
2013-03-12 00:16:36 +00:00
|
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
|
2008-03-17 06:57:02 +00:00
|
|
|
break;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2010-11-23 03:31:01 +00:00
|
|
|
|
|
|
|
// Arguments that can be passed on register must be kept at
|
2007-11-05 03:02:32 +00:00
|
|
|
// RegsToPass vector
|
2007-06-06 07:42:06 +00:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
2008-03-17 06:57:02 +00:00
|
|
|
continue;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2009-03-19 02:12:28 +00:00
|
|
|
// Register can't get to this point...
|
2008-03-17 06:57:02 +00:00
|
|
|
assert(VA.isMemLoc());
|
2010-11-23 03:31:01 +00:00
|
|
|
|
|
|
|
// emit ISD::STORE whichs stores the
|
2008-03-17 06:57:02 +00:00
|
|
|
// parameter value to a stack Location
|
2012-10-30 20:16:31 +00:00
|
|
|
MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
|
2013-03-12 00:16:36 +00:00
|
|
|
Chain, Arg, DL, IsTailCall, DAG));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Transform all store nodes into one single node because all store
|
|
|
|
// nodes are independent of each other.
|
2010-11-23 03:31:01 +00:00
|
|
|
if (!MemOpChains.empty())
|
2013-03-12 00:16:36 +00:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
2007-06-06 07:42:06 +00:00
|
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
|
2008-09-16 21:48:12 +00:00
|
|
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
2010-11-23 03:31:01 +00:00
|
|
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
|
|
|
// node so that legalize doesn't hack it.
|
2011-10-28 19:49:00 +00:00
|
|
|
bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
|
2012-12-13 03:17:29 +00:00
|
|
|
bool GlobalOrExternal = false, InternalLinkage = false;
|
2011-04-07 19:51:44 +00:00
|
|
|
SDValue CalleeLo;
|
2011-04-04 17:11:07 +00:00
|
|
|
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
2012-11-21 20:30:40 +00:00
|
|
|
if (IsPICCall) {
|
2012-12-13 03:17:29 +00:00
|
|
|
InternalLinkage = G->getGlobal()->hasInternalLinkage();
|
|
|
|
|
|
|
|
if (InternalLinkage)
|
2012-11-21 20:30:40 +00:00
|
|
|
Callee = getAddrLocal(Callee, DAG, HasMips64);
|
2012-11-21 20:40:38 +00:00
|
|
|
else if (LargeGOT)
|
|
|
|
Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
|
|
|
|
MipsII::MO_CALL_LO16);
|
2012-11-21 20:30:40 +00:00
|
|
|
else
|
|
|
|
Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
|
|
|
|
} else
|
2013-03-12 00:16:36 +00:00
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
|
2012-11-21 20:30:40 +00:00
|
|
|
MipsII::MO_NO_FLAG);
|
2011-12-09 01:45:12 +00:00
|
|
|
GlobalOrExternal = true;
|
2011-04-04 17:11:07 +00:00
|
|
|
}
|
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
|
2012-11-21 20:40:38 +00:00
|
|
|
if (!IsN64 && !IsPIC) // !N64 && static
|
2012-11-21 20:30:40 +00:00
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
|
|
|
|
MipsII::MO_NO_FLAG);
|
2012-11-21 20:40:38 +00:00
|
|
|
else if (LargeGOT)
|
|
|
|
Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
|
|
|
|
MipsII::MO_CALL_LO16);
|
2013-02-22 21:10:03 +00:00
|
|
|
else // N64 || PIC
|
2012-11-21 20:30:40 +00:00
|
|
|
Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
|
|
|
|
|
2011-12-09 01:45:12 +00:00
|
|
|
GlobalOrExternal = true;
|
2011-04-04 17:11:07 +00:00
|
|
|
}
|
|
|
|
|
2013-01-22 20:05:56 +00:00
|
|
|
SmallVector<SDValue, 8> Ops(1, Chain);
|
2013-03-13 00:54:29 +00:00
|
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
2013-01-22 20:05:56 +00:00
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
|
|
|
|
CLI, Callee, Chain);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
if (IsTailCall)
|
|
|
|
return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
|
2012-10-19 21:47:33 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
|
2013-03-13 00:54:29 +00:00
|
|
|
SDValue InFlag = Chain.getValue(1);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-01-30 18:32:07 +00:00
|
|
|
// Create the CALLSEQ_END node.
|
2012-07-26 23:27:01 +00:00
|
|
|
Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
|
2013-05-29 22:03:55 +00:00
|
|
|
DAG.getIntPtrConstant(0, true), InFlag, DL);
|
2010-01-30 18:32:07 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
|
|
// return.
|
2013-03-12 00:16:36 +00:00
|
|
|
return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
|
|
|
|
Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
/// LowerCallResult - Lower the result values of a call into the
|
|
|
|
/// appropriate copies out of appropriate physical registers.
|
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
2013-03-12 00:16:36 +00:00
|
|
|
CallingConv::ID CallConv, bool IsVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL, SelectionDAG &DAG,
|
2013-03-05 22:41:55 +00:00
|
|
|
SmallVectorImpl<SDValue> &InVals,
|
|
|
|
const SDNode *CallNode,
|
|
|
|
const Type *RetTy) const {
|
2007-06-06 07:42:06 +00:00
|
|
|
// Assign locations to each value returned by this call.
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2013-03-12 00:16:36 +00:00
|
|
|
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
|
2012-06-14 21:10:56 +00:00
|
|
|
getTargetMachine(), RVLocs, *DAG.getContext());
|
2013-08-20 23:38:40 +00:00
|
|
|
MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2013-08-30 19:40:56 +00:00
|
|
|
MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
|
2013-03-05 22:41:55 +00:00
|
|
|
CallNode, RetTy);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
|
2013-03-05 22:41:55 +00:00
|
|
|
RVLocs[i].getLocVT(), InFlag);
|
|
|
|
Chain = Val.getValue(1);
|
|
|
|
InFlag = Val.getValue(2);
|
|
|
|
|
|
|
|
if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
|
2013-03-12 00:16:36 +00:00
|
|
|
Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
|
2013-03-05 22:41:55 +00:00
|
|
|
|
|
|
|
InVals.push_back(Val);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2007-11-05 03:02:32 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
return Chain;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
// Formal Arguments Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-11-23 03:31:01 +00:00
|
|
|
/// LowerFormalArguments - transform physical registers into virtual registers
|
2010-02-06 19:20:49 +00:00
|
|
|
/// and generate load operations for arguments places on the stack.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
2011-04-15 21:00:26 +00:00
|
|
|
CallingConv::ID CallConv,
|
2013-03-12 00:16:36 +00:00
|
|
|
bool IsVarArg,
|
2011-12-19 19:52:25 +00:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL, SelectionDAG &DAG,
|
2011-04-15 21:00:26 +00:00
|
|
|
SmallVectorImpl<SDValue> &InVals)
|
2011-04-15 21:51:11 +00:00
|
|
|
const {
|
2008-08-04 07:12:52 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-06-06 07:42:06 +00:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-08-28 05:08:16 +00:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2010-04-17 14:41:14 +00:00
|
|
|
MipsFI->setVarArgsFrameIndex(0);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-02-06 19:20:49 +00:00
|
|
|
// Used with vargs to acumulate store chains.
|
|
|
|
std::vector<SDValue> OutChains;
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Assign locations to all of the incoming arguments.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2013-03-12 00:16:36 +00:00
|
|
|
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
|
2011-12-19 19:52:25 +00:00
|
|
|
getTargetMachine(), ArgLocs, *DAG.getContext());
|
2013-08-20 23:38:40 +00:00
|
|
|
MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
|
2013-03-05 22:13:04 +00:00
|
|
|
Function::const_arg_iterator FuncArg =
|
|
|
|
DAG.getMachineFunction().getFunction()->arg_begin();
|
2013-08-30 19:40:56 +00:00
|
|
|
bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2013-03-05 22:13:04 +00:00
|
|
|
MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
|
2012-10-30 19:37:25 +00:00
|
|
|
MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
|
|
|
|
MipsCCInfo.hasByValArg());
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2012-10-27 00:44:39 +00:00
|
|
|
unsigned CurArgIdx = 0;
|
2012-10-27 00:29:43 +00:00
|
|
|
MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
2012-10-27 00:44:39 +00:00
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
2007-06-06 07:42:06 +00:00
|
|
|
CCValAssign &VA = ArgLocs[i];
|
2012-10-27 00:44:39 +00:00
|
|
|
std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
|
|
|
|
CurArgIdx = Ins[i].OrigArgIndex;
|
2011-10-28 19:55:48 +00:00
|
|
|
EVT ValVT = VA.getValVT();
|
2011-11-12 02:29:58 +00:00
|
|
|
ISD::ArgFlagsTy Flags = Ins[i].Flags;
|
|
|
|
bool IsRegLoc = VA.isRegLoc();
|
|
|
|
|
|
|
|
if (Flags.isByVal()) {
|
|
|
|
assert(Flags.getByValSize() &&
|
|
|
|
"ByVal args of size 0 should have been ignored by front-end.");
|
2012-10-27 00:29:43 +00:00
|
|
|
assert(ByValArg != MipsCCInfo.byval_end());
|
2013-03-12 00:16:36 +00:00
|
|
|
copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
|
2012-10-27 00:29:43 +00:00
|
|
|
MipsCCInfo, *ByValArg);
|
|
|
|
++ByValArg;
|
2011-11-12 02:29:58 +00:00
|
|
|
continue;
|
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Arguments stored on registers
|
2011-11-12 02:29:58 +00:00
|
|
|
if (IsRegLoc) {
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT RegVT = VA.getLocVT();
|
2011-05-24 00:23:52 +00:00
|
|
|
unsigned ArgReg = VA.getLocReg();
|
2012-02-22 05:59:10 +00:00
|
|
|
const TargetRegisterClass *RC;
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2009-08-11 20:47:22 +00:00
|
|
|
if (RegVT == MVT::i32)
|
2012-12-20 06:06:35 +00:00
|
|
|
RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
|
2013-08-06 23:08:38 +00:00
|
|
|
&Mips::GPR32RegClass;
|
2011-09-24 01:34:44 +00:00
|
|
|
else if (RegVT == MVT::i64)
|
2013-08-06 23:08:38 +00:00
|
|
|
RC = &Mips::GPR64RegClass;
|
2010-11-23 03:31:01 +00:00
|
|
|
else if (RegVT == MVT::f32)
|
2012-04-20 07:30:17 +00:00
|
|
|
RC = &Mips::FGR32RegClass;
|
2011-09-26 21:37:50 +00:00
|
|
|
else if (RegVT == MVT::f64)
|
2013-08-20 23:38:40 +00:00
|
|
|
RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass :
|
|
|
|
&Mips::AFGR64RegClass;
|
2011-09-26 21:37:50 +00:00
|
|
|
else
|
2010-02-06 19:20:49 +00:00
|
|
|
llvm_unreachable("RegVT not supported by FormalArguments Lowering");
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// Transform the arguments stored on
|
2007-06-06 07:42:06 +00:00
|
|
|
// physical registers into virtual ones
|
2013-03-12 00:16:36 +00:00
|
|
|
unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
|
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
|
2010-11-23 03:31:01 +00:00
|
|
|
|
|
|
|
// If this is an 8 or 16-bit value, it has been passed promoted
|
|
|
|
// to 32 bits. Insert an assert[sz]ext to capture this, then
|
2007-06-06 07:42:06 +00:00
|
|
|
// truncate to the right size.
|
2009-03-19 02:12:28 +00:00
|
|
|
if (VA.getLocInfo() != CCValAssign::Full) {
|
2009-03-26 05:28:14 +00:00
|
|
|
unsigned Opcode = 0;
|
2009-03-19 02:12:28 +00:00
|
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
|
|
Opcode = ISD::AssertSext;
|
|
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
|
|
Opcode = ISD::AssertZext;
|
2009-03-26 05:28:14 +00:00
|
|
|
if (Opcode)
|
2013-03-12 00:16:36 +00:00
|
|
|
ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
|
2011-10-28 19:55:48 +00:00
|
|
|
DAG.getValueType(ValVT));
|
2013-03-12 00:16:36 +00:00
|
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
|
2009-03-19 02:12:28 +00:00
|
|
|
}
|
|
|
|
|
2013-03-05 22:13:04 +00:00
|
|
|
// Handle floating point arguments passed in integer registers and
|
|
|
|
// long double arguments passed in floating point registers.
|
2011-10-28 19:55:48 +00:00
|
|
|
if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
|
2013-03-05 22:13:04 +00:00
|
|
|
(RegVT == MVT::i64 && ValVT == MVT::f64) ||
|
|
|
|
(RegVT == MVT::f64 && ValVT == MVT::i64))
|
2013-03-12 00:16:36 +00:00
|
|
|
ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
|
2011-10-28 19:55:48 +00:00
|
|
|
else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
|
2013-03-12 00:16:36 +00:00
|
|
|
unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
|
2011-10-28 19:55:48 +00:00
|
|
|
getNextIntArgReg(ArgReg), RC);
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
|
2011-10-28 19:55:48 +00:00
|
|
|
if (!Subtarget->isLittle())
|
|
|
|
std::swap(ArgValue, ArgValue2);
|
2013-03-12 00:16:36 +00:00
|
|
|
ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
|
2011-10-28 19:55:48 +00:00
|
|
|
ArgValue, ArgValue2);
|
2009-03-19 02:12:28 +00:00
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
InVals.push_back(ArgValue);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
} else { // VA.isRegLoc()
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// sanity check
|
|
|
|
assert(VA.isMemLoc());
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
2012-10-27 00:29:43 +00:00
|
|
|
int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
|
2011-05-24 00:23:52 +00:00
|
|
|
VA.getLocMemOffset(), true);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Create load nodes to retrieve arguments from the stack
|
2012-10-27 00:29:43 +00:00
|
|
|
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
|
2013-03-12 00:16:36 +00:00
|
|
|
InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN,
|
2012-10-27 00:29:43 +00:00
|
|
|
MachinePointerInfo::getFixedStack(FI),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. Save the argument into
|
|
|
|
// a virtual register so that we can access it from the return points.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
if (!Reg) {
|
2012-10-19 22:11:40 +00:00
|
|
|
Reg = MF.getRegInfo().
|
|
|
|
createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
MipsFI->setSRetReturnReg(Reg);
|
|
|
|
}
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
if (IsVarArg)
|
|
|
|
writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// All stores are grouped in one node to allow the matching between
|
2010-02-06 19:20:49 +00:00
|
|
|
// the size of Ins and InVals. This only happens when on varg functions
|
|
|
|
if (!OutChains.empty()) {
|
|
|
|
OutChains.push_back(Chain);
|
2013-03-12 00:16:36 +00:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
2010-02-06 19:20:49 +00:00
|
|
|
&OutChains[0], OutChains.size());
|
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
return Chain;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Return Value Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2012-10-10 01:27:09 +00:00
|
|
|
bool
|
|
|
|
MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
|
2013-03-12 00:16:36 +00:00
|
|
|
MachineFunction &MF, bool IsVarArg,
|
2012-10-10 01:27:09 +00:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
LLVMContext &Context) const {
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2013-03-12 00:16:36 +00:00
|
|
|
CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
|
2012-10-10 01:27:09 +00:00
|
|
|
RVLocs, Context);
|
|
|
|
return CCInfo.CheckReturn(Outs, RetCC_Mips);
|
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerReturn(SDValue Chain,
|
2013-03-12 00:16:36 +00:00
|
|
|
CallingConv::ID CallConv, bool IsVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 15:54:55 +00:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL, SelectionDAG &DAG) const {
|
2007-06-06 07:42:06 +00:00
|
|
|
// CCValAssign - represent the assignment of
|
|
|
|
// the return value to a location
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2013-03-05 22:41:55 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// CCState - Info about the registers and stack slot.
|
2013-03-12 00:16:36 +00:00
|
|
|
CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
|
2013-03-05 22:41:55 +00:00
|
|
|
*DAG.getContext());
|
2013-08-20 23:38:40 +00:00
|
|
|
MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
// Analyze return values.
|
2013-08-30 19:40:56 +00:00
|
|
|
MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
|
2013-03-05 22:41:55 +00:00
|
|
|
MF.getFunction()->getReturnType());
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Flag;
|
2013-02-05 18:12:03 +00:00
|
|
|
SmallVector<SDValue, 4> RetOps(1, Chain);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
2013-03-05 22:41:55 +00:00
|
|
|
SDValue Val = OutVals[i];
|
2007-06-06 07:42:06 +00:00
|
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
|
2013-03-05 22:41:55 +00:00
|
|
|
if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
|
2013-03-12 00:16:36 +00:00
|
|
|
Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
|
2013-03-05 22:41:55 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2013-02-05 18:12:03 +00:00
|
|
|
// Guarantee that all emitted copies are stuck together with flags.
|
2007-06-06 07:42:06 +00:00
|
|
|
Flag = Chain.getValue(1);
|
2013-02-05 18:12:03 +00:00
|
|
|
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. We saved the argument into
|
|
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
|
|
// and into $v0.
|
2013-03-05 22:41:55 +00:00
|
|
|
if (MF.getFunction()->hasStructRetAttr()) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
if (!Reg)
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("sret virtual register not created in the entry block");
|
2013-03-12 00:16:36 +00:00
|
|
|
SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
|
2012-10-24 02:10:54 +00:00
|
|
|
unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
2013-03-12 00:16:36 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
Flag = Chain.getValue(1);
|
2013-02-05 18:12:03 +00:00
|
|
|
RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2013-02-05 18:12:03 +00:00
|
|
|
RetOps[0] = Chain; // Update chain.
|
|
|
|
|
|
|
|
// Add the flag if we have it.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (Flag.getNode())
|
2013-02-05 18:12:03 +00:00
|
|
|
RetOps.push_back(Flag);
|
2012-07-10 00:19:06 +00:00
|
|
|
|
2013-02-05 18:12:03 +00:00
|
|
|
// Return on Mips is always a "jr $ra"
|
2013-03-12 00:16:36 +00:00
|
|
|
return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2007-08-21 16:09:25 +00:00
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-21 16:09:25 +00:00
|
|
|
// Mips Inline Assembly Support
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-21 16:09:25 +00:00
|
|
|
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
|
|
/// constraint it is for this target.
|
|
|
|
MipsTargetLowering::ConstraintType MipsTargetLowering::
|
2010-11-23 03:31:01 +00:00
|
|
|
getConstraintType(const std::string &Constraint) const
|
2007-08-21 16:09:25 +00:00
|
|
|
{
|
2010-11-23 03:31:01 +00:00
|
|
|
// Mips specific constrainy
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// GCC config/mips/constraints.md
|
|
|
|
//
|
2010-11-23 03:31:01 +00:00
|
|
|
// 'd' : An address register. Equivalent to r
|
|
|
|
// unless generating MIPS16 code.
|
|
|
|
// 'y' : Equivalent to r; retained for
|
|
|
|
// backwards compatibility.
|
2012-05-07 06:25:10 +00:00
|
|
|
// 'c' : A register suitable for use in an indirect
|
|
|
|
// jump. This will always be $25 for -mabicalls.
|
2012-05-07 06:25:19 +00:00
|
|
|
// 'l' : The lo register. 1 word storage.
|
|
|
|
// 'x' : The hilo register pair. Double word storage.
|
2007-08-21 16:09:25 +00:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
2010-11-23 03:31:01 +00:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case 'f':
|
2012-05-07 06:25:10 +00:00
|
|
|
case 'c':
|
2012-05-07 06:25:15 +00:00
|
|
|
case 'l':
|
2012-05-07 06:25:19 +00:00
|
|
|
case 'x':
|
2007-08-21 16:09:25 +00:00
|
|
|
return C_RegisterClass;
|
2013-03-04 21:33:15 +00:00
|
|
|
case 'R':
|
|
|
|
return C_Memory;
|
2007-08-21 16:09:25 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
|
|
}
|
|
|
|
|
2010-10-29 17:29:13 +00:00
|
|
|
/// Examine constraint type and operand type and determine a weight value.
|
|
|
|
/// This object must already have been set up with the operand type
|
|
|
|
/// and the current alternative constraint selected.
|
|
|
|
TargetLowering::ConstraintWeight
|
|
|
|
MipsTargetLowering::getSingleConstraintMatchWeight(
|
|
|
|
AsmOperandInfo &info, const char *constraint) const {
|
|
|
|
ConstraintWeight weight = CW_Invalid;
|
|
|
|
Value *CallOperandVal = info.CallOperandVal;
|
|
|
|
// If we don't have a value, we can't do a match,
|
|
|
|
// but allow it at the lowest weight.
|
|
|
|
if (CallOperandVal == NULL)
|
|
|
|
return CW_Default;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *type = CallOperandVal->getType();
|
2010-10-29 17:29:13 +00:00
|
|
|
// Look at the constraint type.
|
|
|
|
switch (*constraint) {
|
|
|
|
default:
|
|
|
|
weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
|
|
|
|
break;
|
2010-11-23 03:31:01 +00:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
2010-10-29 17:29:13 +00:00
|
|
|
if (type->isIntegerTy())
|
|
|
|
weight = CW_Register;
|
|
|
|
break;
|
|
|
|
case 'f':
|
|
|
|
if (type->isFloatTy())
|
|
|
|
weight = CW_Register;
|
|
|
|
break;
|
2012-05-07 06:25:10 +00:00
|
|
|
case 'c': // $25 for indirect jumps
|
2012-05-07 06:25:15 +00:00
|
|
|
case 'l': // lo register
|
2012-05-07 06:25:19 +00:00
|
|
|
case 'x': // hilo register pair
|
2012-05-07 06:25:10 +00:00
|
|
|
if (type->isIntegerTy())
|
|
|
|
weight = CW_SpecificReg;
|
|
|
|
break;
|
2012-05-07 03:13:32 +00:00
|
|
|
case 'I': // signed 16 bit immediate
|
2012-05-07 03:13:42 +00:00
|
|
|
case 'J': // integer zero
|
2012-05-07 05:46:29 +00:00
|
|
|
case 'K': // unsigned 16 bit immediate
|
2012-05-07 05:46:37 +00:00
|
|
|
case 'L': // signed 32 bit immediate where lower 16 bits are 0
|
2012-05-07 05:46:43 +00:00
|
|
|
case 'N': // immediate in the range of -65535 to -1 (inclusive)
|
2012-05-07 05:46:48 +00:00
|
|
|
case 'O': // signed 15 bit immediate (+- 16383)
|
2012-05-07 06:25:02 +00:00
|
|
|
case 'P': // immediate in the range of 65535 to 1 (inclusive)
|
2012-05-07 03:13:32 +00:00
|
|
|
if (isa<ConstantInt>(CallOperandVal))
|
|
|
|
weight = CW_Constant;
|
|
|
|
break;
|
2013-03-04 21:33:15 +00:00
|
|
|
case 'R':
|
|
|
|
weight = CW_Memory;
|
|
|
|
break;
|
2010-10-29 17:29:13 +00:00
|
|
|
}
|
|
|
|
return weight;
|
|
|
|
}
|
|
|
|
|
2013-08-14 00:21:25 +00:00
|
|
|
/// This is a helper function to parse a physical register string and split it
|
|
|
|
/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
|
|
|
|
/// that is returned indicates whether parsing was successful. The second flag
|
|
|
|
/// is true if the numeric part exists.
|
|
|
|
static std::pair<bool, bool>
|
|
|
|
parsePhysicalReg(const StringRef &C, std::string &Prefix,
|
|
|
|
unsigned long long &Reg) {
|
|
|
|
if (C.front() != '{' || C.back() != '}')
|
|
|
|
return std::make_pair(false, false);
|
|
|
|
|
|
|
|
// Search for the first numeric character.
|
|
|
|
StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
|
|
|
|
I = std::find_if(B, E, std::ptr_fun(isdigit));
|
|
|
|
|
|
|
|
Prefix.assign(B, I - B);
|
|
|
|
|
|
|
|
// The second flag is set to false if no numeric characters were found.
|
|
|
|
if (I == E)
|
|
|
|
return std::make_pair(true, false);
|
|
|
|
|
|
|
|
// Parse the numeric characters.
|
|
|
|
return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
|
|
|
|
true);
|
|
|
|
}
|
|
|
|
|
|
|
|
std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
|
|
|
|
parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
|
|
|
|
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
|
|
|
|
const TargetRegisterClass *RC;
|
|
|
|
std::string Prefix;
|
|
|
|
unsigned long long Reg;
|
|
|
|
|
|
|
|
std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
|
|
|
|
|
|
|
|
if (!R.first)
|
|
|
|
return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
|
|
|
|
|
|
|
|
if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
|
|
|
|
// No numeric characters follow "hi" or "lo".
|
|
|
|
if (R.second)
|
|
|
|
return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
|
|
|
|
|
|
|
|
RC = TRI->getRegClass(Prefix == "hi" ?
|
2013-08-14 00:47:08 +00:00
|
|
|
Mips::HI32RegClassID : Mips::LO32RegClassID);
|
2013-08-14 00:21:25 +00:00
|
|
|
return std::make_pair(*(RC->begin()), RC);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!R.second)
|
|
|
|
return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
|
|
|
|
|
|
|
|
if (Prefix == "$f") { // Parse $f0-$f31.
|
|
|
|
// If the size of FP registers is 64-bit or Reg is an even number, select
|
|
|
|
// the 64-bit register class. Otherwise, select the 32-bit register class.
|
|
|
|
if (VT == MVT::Other)
|
|
|
|
VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
|
|
|
|
|
|
|
|
RC= getRegClassFor(VT);
|
|
|
|
|
|
|
|
if (RC == &Mips::AFGR64RegClass) {
|
|
|
|
assert(Reg % 2 == 0);
|
|
|
|
Reg >>= 1;
|
|
|
|
}
|
|
|
|
} else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7.
|
|
|
|
RC = TRI->getRegClass(Mips::FCCRegClassID);
|
|
|
|
} else { // Parse $0-$31.
|
|
|
|
assert(Prefix == "$");
|
|
|
|
RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(Reg < RC->getNumRegs());
|
|
|
|
return std::make_pair(*(RC->begin() + Reg), RC);
|
|
|
|
}
|
|
|
|
|
2011-06-29 19:33:04 +00:00
|
|
|
/// Given a register class constraint, like 'r', if this corresponds directly
|
|
|
|
/// to an LLVM register class, return a register of 0 and the register class
|
|
|
|
/// pointer.
|
2007-08-21 16:09:25 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
|
2013-06-22 18:37:38 +00:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
|
2007-08-21 16:09:25 +00:00
|
|
|
{
|
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
2011-06-29 19:04:31 +00:00
|
|
|
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
|
|
|
|
case 'y': // Same as 'r'. Exists for compatibility.
|
2007-08-21 16:09:25 +00:00
|
|
|
case 'r':
|
2012-09-12 23:27:55 +00:00
|
|
|
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
|
|
|
|
if (Subtarget->inMips16Mode())
|
|
|
|
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
|
2013-08-06 23:08:38 +00:00
|
|
|
return std::make_pair(0U, &Mips::GPR32RegClass);
|
2012-09-12 23:27:55 +00:00
|
|
|
}
|
2012-07-02 23:35:23 +00:00
|
|
|
if (VT == MVT::i64 && !HasMips64)
|
2013-08-06 23:08:38 +00:00
|
|
|
return std::make_pair(0U, &Mips::GPR32RegClass);
|
2012-05-07 03:13:22 +00:00
|
|
|
if (VT == MVT::i64 && HasMips64)
|
2013-08-06 23:08:38 +00:00
|
|
|
return std::make_pair(0U, &Mips::GPR64RegClass);
|
2012-05-07 03:13:22 +00:00
|
|
|
// This will generate an error message
|
|
|
|
return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case 'f':
|
2009-08-11 20:47:22 +00:00
|
|
|
if (VT == MVT::f32)
|
2012-04-20 07:30:17 +00:00
|
|
|
return std::make_pair(0U, &Mips::FGR32RegClass);
|
2012-01-04 02:45:01 +00:00
|
|
|
if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
|
|
|
|
if (Subtarget->isFP64bit())
|
2012-04-20 07:30:17 +00:00
|
|
|
return std::make_pair(0U, &Mips::FGR64RegClass);
|
|
|
|
return std::make_pair(0U, &Mips::AFGR64RegClass);
|
2012-01-04 02:45:01 +00:00
|
|
|
}
|
2012-05-07 06:25:10 +00:00
|
|
|
break;
|
|
|
|
case 'c': // register suitable for indirect jump
|
|
|
|
if (VT == MVT::i32)
|
2013-08-06 23:08:38 +00:00
|
|
|
return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
|
2012-05-07 06:25:10 +00:00
|
|
|
assert(VT == MVT::i64 && "Unexpected type.");
|
2013-08-06 23:08:38 +00:00
|
|
|
return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
|
2012-05-07 06:25:15 +00:00
|
|
|
case 'l': // register suitable for indirect jump
|
|
|
|
if (VT == MVT::i32)
|
2013-08-14 00:47:08 +00:00
|
|
|
return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
|
|
|
|
return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
|
2012-05-07 06:25:19 +00:00
|
|
|
case 'x': // register suitable for indirect jump
|
|
|
|
// Fixme: Not triggering the use of both hi and low
|
|
|
|
// This will generate an error message
|
|
|
|
return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
|
2007-08-21 16:09:25 +00:00
|
|
|
}
|
|
|
|
}
|
2013-08-14 00:21:25 +00:00
|
|
|
|
|
|
|
std::pair<unsigned, const TargetRegisterClass *> R;
|
|
|
|
R = parseRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
|
|
|
|
if (R.second)
|
|
|
|
return R;
|
|
|
|
|
2007-08-21 16:09:25 +00:00
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
}
|
|
|
|
|
2012-05-07 03:13:32 +00:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
|
|
|
void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
|
|
|
std::string &Constraint,
|
|
|
|
std::vector<SDValue>&Ops,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
SDValue Result(0, 0);
|
|
|
|
|
|
|
|
// Only support length 1 constraints for now.
|
|
|
|
if (Constraint.length() > 1) return;
|
|
|
|
|
|
|
|
char ConstraintLetter = Constraint[0];
|
|
|
|
switch (ConstraintLetter) {
|
|
|
|
default: break; // This will fall through to the generic implementation
|
|
|
|
case 'I': // Signed 16 bit constant
|
|
|
|
// If this fails, the parent routine will give an error
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
int64_t Val = C->getSExtValue();
|
|
|
|
if (isInt<16>(Val)) {
|
|
|
|
Result = DAG.getTargetConstant(Val, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 03:13:42 +00:00
|
|
|
case 'J': // integer zero
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
int64_t Val = C->getZExtValue();
|
|
|
|
if (Val == 0) {
|
|
|
|
Result = DAG.getTargetConstant(0, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 05:46:29 +00:00
|
|
|
case 'K': // unsigned 16 bit immediate
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
uint64_t Val = (uint64_t)C->getZExtValue();
|
|
|
|
if (isUInt<16>(Val)) {
|
|
|
|
Result = DAG.getTargetConstant(Val, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 05:46:37 +00:00
|
|
|
case 'L': // signed 32 bit immediate where lower 16 bits are 0
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
int64_t Val = C->getSExtValue();
|
|
|
|
if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
|
|
|
|
Result = DAG.getTargetConstant(Val, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 05:46:43 +00:00
|
|
|
case 'N': // immediate in the range of -65535 to -1 (inclusive)
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
int64_t Val = C->getSExtValue();
|
|
|
|
if ((Val >= -65535) && (Val <= -1)) {
|
|
|
|
Result = DAG.getTargetConstant(Val, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 05:46:48 +00:00
|
|
|
case 'O': // signed 15 bit immediate
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
int64_t Val = C->getSExtValue();
|
|
|
|
if ((isInt<15>(Val))) {
|
|
|
|
Result = DAG.getTargetConstant(Val, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 06:25:02 +00:00
|
|
|
case 'P': // immediate in the range of 1 to 65535 (inclusive)
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
|
|
EVT Type = Op.getValueType();
|
|
|
|
int64_t Val = C->getSExtValue();
|
|
|
|
if ((Val <= 65535) && (Val >= 1)) {
|
|
|
|
Result = DAG.getTargetConstant(Val, Type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2012-05-07 03:13:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (Result.getNode()) {
|
|
|
|
Ops.push_back(Result);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
|
|
|
|
}
|
|
|
|
|
2012-11-17 00:25:41 +00:00
|
|
|
bool
|
|
|
|
MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
|
|
|
|
// No global is ever allowed as a base.
|
|
|
|
if (AM.BaseGV)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
switch (AM.Scale) {
|
|
|
|
case 0: // "r+i" or just "i", depending on HasBaseReg.
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
if (!AM.HasBaseReg) // allow "r+i".
|
|
|
|
break;
|
|
|
|
return false; // disallow "r+r" or "r+r+i".
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
|
|
|
bool
|
|
|
|
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
|
|
// The Mips target isn't yet aware of offsets.
|
|
|
|
return false;
|
|
|
|
}
|
2009-10-27 19:56:55 +00:00
|
|
|
|
2012-06-13 19:33:32 +00:00
|
|
|
EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
|
2012-12-12 02:34:41 +00:00
|
|
|
unsigned SrcAlign,
|
|
|
|
bool IsMemset, bool ZeroMemset,
|
2012-06-13 19:33:32 +00:00
|
|
|
bool MemcpyStrSrc,
|
|
|
|
MachineFunction &MF) const {
|
|
|
|
if (Subtarget->hasMips64())
|
|
|
|
return MVT::i64;
|
|
|
|
|
|
|
|
return MVT::i32;
|
|
|
|
}
|
|
|
|
|
2009-10-28 01:43:28 +00:00
|
|
|
bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
|
|
|
|
if (VT != MVT::f32 && VT != MVT::f64)
|
|
|
|
return false;
|
2011-01-18 19:41:41 +00:00
|
|
|
if (Imm.isNegZero())
|
|
|
|
return false;
|
2009-10-27 19:56:55 +00:00
|
|
|
return Imm.isZero();
|
|
|
|
}
|
2012-02-03 04:33:00 +00:00
|
|
|
|
|
|
|
unsigned MipsTargetLowering::getJumpTableEncoding() const {
|
|
|
|
if (IsN64)
|
|
|
|
return MachineJumpTableInfo::EK_GPRel64BlockAddress;
|
2012-02-28 07:46:26 +00:00
|
|
|
|
2012-02-03 04:33:00 +00:00
|
|
|
return TargetLowering::getJumpTableEncoding();
|
|
|
|
}
|
2012-10-26 23:56:38 +00:00
|
|
|
|
2013-03-05 22:54:59 +00:00
|
|
|
/// This function returns true if CallSym is a long double emulation routine.
|
|
|
|
static bool isF128SoftLibCall(const char *CallSym) {
|
|
|
|
const char *const LibCalls[] =
|
|
|
|
{"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
|
|
|
|
"__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
|
|
|
|
"__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
|
|
|
|
"__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
|
|
|
|
"__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
|
|
|
|
"__trunctfdf2", "__trunctfsf2", "__unordtf2",
|
|
|
|
"ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
|
|
|
|
"log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
|
|
|
|
"truncl"};
|
|
|
|
|
|
|
|
const char * const *End = LibCalls + array_lengthof(LibCalls);
|
|
|
|
|
|
|
|
// Check that LibCalls is sorted alphabetically.
|
2013-03-13 00:54:29 +00:00
|
|
|
MipsTargetLowering::LTStr Comp;
|
2013-03-05 22:54:59 +00:00
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
#ifndef NDEBUG
|
2013-03-05 22:54:59 +00:00
|
|
|
for (const char * const *I = LibCalls; I < End - 1; ++I)
|
|
|
|
assert(Comp(*I, *(I + 1)));
|
|
|
|
#endif
|
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
return std::binary_search(LibCalls, End, CallSym, Comp);
|
2013-03-05 22:54:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// This function returns true if Ty is fp128 or i128 which was originally a
|
|
|
|
/// fp128.
|
|
|
|
static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
|
|
|
|
if (Ty->isFP128Ty())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
const ExternalSymbolSDNode *ES =
|
|
|
|
dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
|
|
|
|
|
|
|
|
// If the Ty is i128 and the function being called is a long double emulation
|
|
|
|
// routine, then the original type is f128.
|
|
|
|
return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
|
|
|
|
}
|
|
|
|
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
MipsTargetLowering::MipsCC::SpecialCallingConvType
|
|
|
|
MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
|
|
|
|
MipsCC::SpecialCallingConvType SpecialCallingConv =
|
|
|
|
MipsCC::NoSpecialCallingConv;;
|
|
|
|
if (Subtarget->inMips16HardFloat()) {
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
|
|
|
llvm::StringRef Sym = G->getGlobal()->getName();
|
|
|
|
Function *F = G->getGlobal()->getParent()->getFunction(Sym);
|
|
|
|
if (F->hasFnAttribute("__Mips16RetHelper")) {
|
|
|
|
SpecialCallingConv = MipsCC::Mips16RetHelperConv;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return SpecialCallingConv;
|
|
|
|
}
|
|
|
|
|
|
|
|
MipsTargetLowering::MipsCC::MipsCC(
|
2013-08-20 23:38:40 +00:00
|
|
|
CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
MipsCC::SpecialCallingConvType SpecialCallingConv_)
|
2013-08-20 23:38:40 +00:00
|
|
|
: CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
SpecialCallingConv(SpecialCallingConv_){
|
2012-10-26 23:56:38 +00:00
|
|
|
// Pre-allocate reserved argument area.
|
2013-02-15 21:45:11 +00:00
|
|
|
CCInfo.AllocateStack(reservedArgArea(), 1);
|
2012-10-26 23:56:38 +00:00
|
|
|
}
|
|
|
|
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
|
2012-10-26 23:56:38 +00:00
|
|
|
void MipsTargetLowering::MipsCC::
|
2013-02-15 21:45:11 +00:00
|
|
|
analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
|
2013-03-05 22:20:28 +00:00
|
|
|
bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
|
|
|
|
std::vector<ArgListEntry> &FuncArgs) {
|
2013-02-15 21:45:11 +00:00
|
|
|
assert((CallConv != CallingConv::Fast || !IsVarArg) &&
|
|
|
|
"CallingConv::Fast shouldn't be used for vararg functions.");
|
|
|
|
|
2012-10-26 23:56:38 +00:00
|
|
|
unsigned NumOpnds = Args.size();
|
2013-02-15 21:45:11 +00:00
|
|
|
llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
|
2012-10-26 23:56:38 +00:00
|
|
|
|
|
|
|
for (unsigned I = 0; I != NumOpnds; ++I) {
|
|
|
|
MVT ArgVT = Args[I].VT;
|
|
|
|
ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
|
|
|
|
bool R;
|
|
|
|
|
|
|
|
if (ArgFlags.isByVal()) {
|
|
|
|
handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2013-02-15 21:45:11 +00:00
|
|
|
if (IsVarArg && !Args[I].IsFixed)
|
2012-10-26 23:56:38 +00:00
|
|
|
R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
|
2013-03-05 22:20:28 +00:00
|
|
|
else {
|
|
|
|
MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
|
|
|
|
IsSoftFloat);
|
|
|
|
R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
|
|
|
|
}
|
2012-10-26 23:56:38 +00:00
|
|
|
|
|
|
|
if (R) {
|
|
|
|
#ifndef NDEBUG
|
|
|
|
dbgs() << "Call operand #" << I << " has unhandled type "
|
|
|
|
<< EVT(ArgVT).getEVTString();
|
|
|
|
#endif
|
|
|
|
llvm_unreachable(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsTargetLowering::MipsCC::
|
2013-03-05 22:13:04 +00:00
|
|
|
analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
|
|
|
|
bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
|
2012-10-26 23:56:38 +00:00
|
|
|
unsigned NumArgs = Args.size();
|
2013-02-15 21:45:11 +00:00
|
|
|
llvm::CCAssignFn *FixedFn = fixedArgFn();
|
2013-03-05 22:13:04 +00:00
|
|
|
unsigned CurArgIdx = 0;
|
2012-10-26 23:56:38 +00:00
|
|
|
|
|
|
|
for (unsigned I = 0; I != NumArgs; ++I) {
|
|
|
|
MVT ArgVT = Args[I].VT;
|
|
|
|
ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
|
2013-03-05 22:13:04 +00:00
|
|
|
std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
|
|
|
|
CurArgIdx = Args[I].OrigArgIndex;
|
2012-10-26 23:56:38 +00:00
|
|
|
|
|
|
|
if (ArgFlags.isByVal()) {
|
|
|
|
handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2013-03-05 22:13:04 +00:00
|
|
|
MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
|
|
|
|
|
|
|
|
if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
|
2012-10-26 23:56:38 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
dbgs() << "Formal Arg #" << I << " has unhandled type "
|
|
|
|
<< EVT(ArgVT).getEVTString();
|
|
|
|
#endif
|
|
|
|
llvm_unreachable(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-03-05 22:41:55 +00:00
|
|
|
template<typename Ty>
|
|
|
|
void MipsTargetLowering::MipsCC::
|
|
|
|
analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
|
|
|
|
const SDNode *CallNode, const Type *RetTy) const {
|
2013-03-05 22:54:59 +00:00
|
|
|
CCAssignFn *Fn;
|
|
|
|
|
|
|
|
if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
|
|
|
|
Fn = RetCC_F128Soft;
|
|
|
|
else
|
|
|
|
Fn = RetCC_Mips;
|
|
|
|
|
2013-03-05 22:41:55 +00:00
|
|
|
for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
|
|
|
|
MVT VT = RetVals[I].VT;
|
|
|
|
ISD::ArgFlagsTy Flags = RetVals[I].Flags;
|
|
|
|
MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
|
|
|
|
|
2013-03-05 22:54:59 +00:00
|
|
|
if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
|
2013-03-05 22:41:55 +00:00
|
|
|
#ifndef NDEBUG
|
|
|
|
dbgs() << "Call result #" << I << " has unhandled type "
|
|
|
|
<< EVT(VT).getEVTString() << '\n';
|
|
|
|
#endif
|
|
|
|
llvm_unreachable(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsTargetLowering::MipsCC::
|
|
|
|
analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
|
|
|
|
const SDNode *CallNode, const Type *RetTy) const {
|
|
|
|
analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsTargetLowering::MipsCC::
|
|
|
|
analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
|
|
|
|
const Type *RetTy) const {
|
|
|
|
analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
|
|
|
|
}
|
|
|
|
|
2012-10-26 23:56:38 +00:00
|
|
|
void
|
|
|
|
MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
|
|
|
|
MVT LocVT,
|
|
|
|
CCValAssign::LocInfo LocInfo,
|
|
|
|
ISD::ArgFlagsTy ArgFlags) {
|
|
|
|
assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
|
|
|
|
|
|
|
|
struct ByValArgInfo ByVal;
|
2013-02-15 21:45:11 +00:00
|
|
|
unsigned RegSize = regSize();
|
2012-10-26 23:56:38 +00:00
|
|
|
unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
|
|
|
|
unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
|
|
|
|
RegSize * 2);
|
|
|
|
|
2013-02-15 21:45:11 +00:00
|
|
|
if (useRegsForByval())
|
2012-10-26 23:56:38 +00:00
|
|
|
allocateRegs(ByVal, ByValSize, Align);
|
|
|
|
|
|
|
|
// Allocate space on caller's stack.
|
|
|
|
ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
|
|
|
|
Align);
|
|
|
|
CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
|
|
|
|
LocInfo));
|
|
|
|
ByValArgs.push_back(ByVal);
|
|
|
|
}
|
|
|
|
|
2013-02-15 21:45:11 +00:00
|
|
|
unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
|
|
|
|
return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
|
|
|
|
return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
|
|
|
|
return IsO32 ? O32IntRegs : Mips64IntRegs;
|
|
|
|
}
|
|
|
|
|
|
|
|
llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
|
|
|
|
if (CallConv == CallingConv::Fast)
|
|
|
|
return CC_Mips_FastCC;
|
|
|
|
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
if (SpecialCallingConv == Mips16RetHelperConv)
|
|
|
|
return CC_Mips16RetHelper;
|
2013-08-20 23:38:40 +00:00
|
|
|
return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
|
2013-02-15 21:45:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
|
2013-08-20 23:38:40 +00:00
|
|
|
return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
|
2013-02-15 21:45:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
|
|
|
|
return IsO32 ? O32IntRegs : Mips64DPRegs;
|
|
|
|
}
|
|
|
|
|
2012-10-26 23:56:38 +00:00
|
|
|
void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
|
|
|
|
unsigned ByValSize,
|
|
|
|
unsigned Align) {
|
2013-02-15 21:45:11 +00:00
|
|
|
unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
|
|
|
|
const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
|
2012-10-26 23:56:38 +00:00
|
|
|
assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
|
|
|
|
"Byval argument's size and alignment should be a multiple of"
|
|
|
|
"RegSize.");
|
|
|
|
|
|
|
|
ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
|
|
|
|
|
|
|
|
// If Align > RegSize, the first arg register must be even.
|
|
|
|
if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
|
|
|
|
CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
|
|
|
|
++ByVal.FirstIdx;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Mark the registers allocated.
|
|
|
|
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
|
|
|
|
ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
|
|
|
|
CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
|
|
|
|
}
|
2012-10-27 00:10:18 +00:00
|
|
|
|
2013-03-05 22:13:04 +00:00
|
|
|
MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
|
|
|
|
const SDNode *CallNode,
|
|
|
|
bool IsSoftFloat) const {
|
|
|
|
if (IsSoftFloat || IsO32)
|
|
|
|
return VT;
|
|
|
|
|
|
|
|
// Check if the original type was fp128.
|
2013-03-05 22:54:59 +00:00
|
|
|
if (originalTypeIsF128(OrigTy, CallNode)) {
|
2013-03-05 22:13:04 +00:00
|
|
|
assert(VT == MVT::i64);
|
|
|
|
return MVT::f64;
|
|
|
|
}
|
|
|
|
|
|
|
|
return VT;
|
|
|
|
}
|
|
|
|
|
2012-10-27 00:10:18 +00:00
|
|
|
void MipsTargetLowering::
|
2013-05-25 02:42:55 +00:00
|
|
|
copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
|
2012-10-27 00:10:18 +00:00
|
|
|
SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
|
|
|
|
SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
|
|
|
|
const MipsCC &CC, const ByValArgInfo &ByVal) const {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
|
|
|
|
unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
|
|
|
|
int FrameObjOffset;
|
|
|
|
|
|
|
|
if (RegAreaSize)
|
|
|
|
FrameObjOffset = (int)CC.reservedArgArea() -
|
|
|
|
(int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
|
|
|
|
else
|
|
|
|
FrameObjOffset = ByVal.Address;
|
|
|
|
|
|
|
|
// Create frame object.
|
|
|
|
EVT PtrTy = getPointerTy();
|
|
|
|
int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
|
|
|
|
SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
|
|
|
|
InVals.push_back(FIN);
|
|
|
|
|
|
|
|
if (!ByVal.NumRegs)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Copy arg registers.
|
2012-12-13 06:34:11 +00:00
|
|
|
MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
|
2012-10-27 00:10:18 +00:00
|
|
|
const TargetRegisterClass *RC = getRegClassFor(RegTy);
|
|
|
|
|
|
|
|
for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
|
|
|
|
unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
|
2013-03-12 00:16:36 +00:00
|
|
|
unsigned VReg = addLiveIn(MF, ArgReg, RC);
|
2012-10-27 00:10:18 +00:00
|
|
|
unsigned Offset = I * CC.regSize();
|
|
|
|
SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
|
|
|
|
DAG.getConstant(Offset, PtrTy));
|
|
|
|
SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
|
|
|
|
StorePtr, MachinePointerInfo(FuncArg, Offset),
|
|
|
|
false, false, 0);
|
|
|
|
OutChains.push_back(Store);
|
|
|
|
}
|
|
|
|
}
|
2012-10-27 00:16:36 +00:00
|
|
|
|
|
|
|
// Copy byVal arg to registers and stack.
|
|
|
|
void MipsTargetLowering::
|
2013-05-25 02:42:55 +00:00
|
|
|
passByValArg(SDValue Chain, SDLoc DL,
|
2013-01-22 20:05:56 +00:00
|
|
|
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
2013-07-14 04:42:23 +00:00
|
|
|
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
|
2012-10-27 00:16:36 +00:00
|
|
|
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
|
|
|
|
const MipsCC &CC, const ByValArgInfo &ByVal,
|
|
|
|
const ISD::ArgFlagsTy &Flags, bool isLittle) const {
|
|
|
|
unsigned ByValSize = Flags.getByValSize();
|
|
|
|
unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
|
|
|
|
unsigned RegSize = CC.regSize();
|
|
|
|
unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
|
|
|
|
EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
|
|
|
|
|
|
|
|
if (ByVal.NumRegs) {
|
|
|
|
const uint16_t *ArgRegs = CC.intArgRegs();
|
|
|
|
bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
|
|
|
|
unsigned I = 0;
|
|
|
|
|
|
|
|
// Copy words to registers.
|
|
|
|
for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
|
|
|
|
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
|
|
|
|
DAG.getConstant(Offset, PtrTy));
|
|
|
|
SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
|
|
|
|
MachinePointerInfo(), false, false, false,
|
|
|
|
Alignment);
|
|
|
|
MemOpChains.push_back(LoadVal.getValue(1));
|
|
|
|
unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
|
|
|
|
RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Return if the struct has been fully copied.
|
|
|
|
if (ByValSize == Offset)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Copy the remainder of the byval argument with sub-word loads and shifts.
|
|
|
|
if (LeftoverBytes) {
|
|
|
|
assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
|
|
|
|
"Size of the remainder should be smaller than RegSize.");
|
|
|
|
SDValue Val;
|
|
|
|
|
|
|
|
for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
|
|
|
|
Offset < ByValSize; LoadSize /= 2) {
|
|
|
|
unsigned RemSize = ByValSize - Offset;
|
|
|
|
|
|
|
|
if (RemSize < LoadSize)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Load subword.
|
|
|
|
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
|
|
|
|
DAG.getConstant(Offset, PtrTy));
|
|
|
|
SDValue LoadVal =
|
|
|
|
DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
|
|
|
|
MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
|
|
|
|
false, false, Alignment);
|
|
|
|
MemOpChains.push_back(LoadVal.getValue(1));
|
|
|
|
|
|
|
|
// Shift the loaded value.
|
|
|
|
unsigned Shamt;
|
|
|
|
|
|
|
|
if (isLittle)
|
|
|
|
Shamt = TotalSizeLoaded;
|
|
|
|
else
|
|
|
|
Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
|
|
|
|
|
|
|
|
SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
|
|
|
|
DAG.getConstant(Shamt, MVT::i32));
|
|
|
|
|
|
|
|
if (Val.getNode())
|
|
|
|
Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
|
|
|
|
else
|
|
|
|
Val = Shift;
|
|
|
|
|
|
|
|
Offset += LoadSize;
|
|
|
|
TotalSizeLoaded += LoadSize;
|
|
|
|
Alignment = std::min(Alignment, LoadSize);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
|
|
|
|
RegsToPass.push_back(std::make_pair(ArgReg, Val));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Copy remainder of byval arg to it with memcpy.
|
|
|
|
unsigned MemCpySize = ByValSize - Offset;
|
|
|
|
SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
|
|
|
|
DAG.getConstant(Offset, PtrTy));
|
|
|
|
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
|
|
|
|
DAG.getIntPtrConstant(ByVal.Address));
|
|
|
|
Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
|
|
|
|
DAG.getConstant(MemCpySize, PtrTy), Alignment,
|
|
|
|
/*isVolatile=*/false, /*AlwaysInline=*/false,
|
|
|
|
MachinePointerInfo(0), MachinePointerInfo(0));
|
|
|
|
MemOpChains.push_back(Chain);
|
|
|
|
}
|
2012-10-27 00:21:13 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
|
|
|
|
const MipsCC &CC, SDValue Chain,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL, SelectionDAG &DAG) const {
|
2012-10-27 00:21:13 +00:00
|
|
|
unsigned NumRegs = CC.numIntArgRegs();
|
|
|
|
const uint16_t *ArgRegs = CC.intArgRegs();
|
|
|
|
const CCState &CCInfo = CC.getCCInfo();
|
|
|
|
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
|
|
|
|
unsigned RegSize = CC.regSize();
|
2012-12-13 06:34:11 +00:00
|
|
|
MVT RegTy = MVT::getIntegerVT(RegSize * 8);
|
2012-10-27 00:21:13 +00:00
|
|
|
const TargetRegisterClass *RC = getRegClassFor(RegTy);
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
|
|
|
|
// Offset of the first variable argument from stack pointer.
|
|
|
|
int VaArgOffset;
|
|
|
|
|
|
|
|
if (NumRegs == Idx)
|
|
|
|
VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
|
|
|
|
else
|
|
|
|
VaArgOffset =
|
|
|
|
(int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
|
|
|
|
|
|
|
|
// Record the frame index of the first variable argument
|
|
|
|
// which is a value necessary to VASTART.
|
|
|
|
int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
|
|
|
|
MipsFI->setVarArgsFrameIndex(FI);
|
|
|
|
|
|
|
|
// Copy the integer registers that have not been used for argument passing
|
|
|
|
// to the argument register save area. For O32, the save area is allocated
|
|
|
|
// in the caller's stack frame, while for N32/64, it is allocated in the
|
|
|
|
// callee's stack frame.
|
|
|
|
for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
|
2013-03-12 00:16:36 +00:00
|
|
|
unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
|
2012-10-27 00:21:13 +00:00
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
|
|
|
|
FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
|
|
|
|
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
|
|
|
|
MachinePointerInfo(), false, false, 0);
|
|
|
|
cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
|
|
|
|
OutChains.push_back(Store);
|
|
|
|
}
|
|
|
|
}
|