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348 Commits

Author SHA1 Message Date
Evan Cheng
e63d746ef6 Use tblgen'd VECTOR_SHUFFLE selection code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 08:14:16 +00:00
Chris Lattner
dd4d2d0e40 Add support for generating vspltw, instead of a vperm instruction with a 
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:51:10 +00:00
Chris Lattner
3c0f9cc90c Check in some intermediate code that adds a skeleton for matching vsplt* 
instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:15:45 +00:00
Chris Lattner
08e25de4d3 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 05:05:55 +00:00
Chris Lattner
556aae0df0 add vsplat instructions, fix sched description for vperm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 04:47:33 +00:00
Chris Lattner
f1d0b2beda Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. 
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:53 +00:00
Chris Lattner
abdff1ee6d add the vperm instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:00:56 +00:00
Chris Lattner
b2177b9405 Custom lower SCALAR_TO_VECTOR into lve*x. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:55:52 +00:00
Chris Lattner
528180ed7b add support for vector undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:10:09 +00:00
Chris Lattner
a17409dfd6 minor fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:43:01 +00:00
Chris Lattner
0a7bff01d0 we don't use lmw/stmw. When we want them they are easy enough to add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26853 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 04:33:37 +00:00
Nate Begeman
79691bc1f3 Fix subfic to match subc by default instead of sub so that it is correctly 
cost-modeled as producing a flag.  This fixes the test I just added for neg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 22:41:37 +00:00
Nate Begeman
81e8097377 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 01:40:33 +00:00
Chris Lattner
be80fc8d09 Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26808 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:35:59 +00:00
Chris Lattner
335fd3c7c2 Add support for copying registers. still needed: spilling and reloading them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 20:03:58 +00:00
Nate Begeman
133decdceb Update scheduling info for vrsave instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26776 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-15 05:25:05 +00:00
Chris Lattner
1877ec9b02 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 21:52:10 +00:00
Chris Lattner
fd97734f36 Mark instructions that are cracked by the PPC970 decoder as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:15:10 +00:00
Chris Lattner
88d211f823 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-12 09:13:49 +00:00
Chris Lattner
bbf1c72d51 implement TII::insertNoop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 23:49:55 +00:00
Chris Lattner
5126984b1d Compile this: 
void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 05:50:56 +00:00
Nate Begeman
551bf3f800 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 05:43:56 +00:00
Nate Begeman
789fd42320 Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/ 
PowerPC/and-imm.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26136 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-12 09:09:52 +00:00
Chris Lattner
cedc6f4b30 PHI and INLINEASM are now built-in instructions provided by Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 01:46:15 +00:00
Chris Lattner
a613d267ea ahem :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25239 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-12 02:05:36 +00:00
Nate Begeman
35ef913ec2 Add bswap, rotl, and rotr nodes 
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 21:21:00 +00:00
Nate Begeman
49dddb273d Remove a comment that no longer applies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25167 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-10 00:15:59 +00:00
Chris Lattner
e5cf122869 add ret void support back 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25164 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 23:20:37 +00:00
Evan Cheng
6da8d99f70 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 
hasInFlag, hasOutFlag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 18:28:21 +00:00
Jim Laskey
abf6d1784b Added initial support for DEBUG_LABEL allowing debug specific labels to be 
inserted in the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-05 01:25:28 +00:00
Jim Laskey
5bf6f25b4a Add unique id to debug location for debug label use (work in progress.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-04 15:04:11 +00:00
Nate Begeman
b73628b5ab Add support for generating v4i32 altivec code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25046 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-30 00:12:56 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-26 09:11:45 +00:00
Evan Cheng
171049d10f * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 22:14:32 +00:00
Evan Cheng
6a3bfd97f2 Flip the meaning of FPContractions to reflect Requires<[]> change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24884 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-20 20:08:53 +00:00
Nate Begeman
9e4dd9dfc9 Pattern-match return. Includes gross hack! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-20 00:26:01 +00:00
Nate Begeman
7fd1edd32e Convert load/store over to being pattern matched 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 23:25:09 +00:00
Jim Laskey
f5395cee6a Added source file/line correspondence for dwarf (PowerPC only at this point.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 22:45:29 +00:00
Nate Begeman
f492f9901a Add a second vector type to the VRRC register class, and fix some patterns 
so that tablegen can infer all types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 09:19:13 +00:00
Nate Begeman
a07da92624 Use the new predicate support that Evan Cheng added to remove some code 
from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-14 22:54:33 +00:00
Evan Cheng
8c75ef9228 Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24716 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-14 22:07:12 +00:00
Nate Begeman
3fb6877cb4 Add support for fmul node of type v4f32. 
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-14 00:34:09 +00:00
Nate Begeman
993aeb2ed9 Prepare support for AltiVec multiply, divide, and sqrt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 22:55:22 +00:00
Chris Lattner
d717b19933 Remove type casts that are no longer needed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24661 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-11 07:45:47 +00:00
Nate Begeman
28a6b02626 Add support for TargetConstantPool nodes to the dag isel emitter, and use 
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-10 02:36:00 +00:00
Nate Begeman
0976122abc Add support patterns to many load and store instructions which will 
hopefully use patterns in the near future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-09 23:54:18 +00:00
Chris Lattner
4172b10ca1 Use new PPC-specific nodes to represent shifts which require the 6-bit 
amount handling that PPC provides.  These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits.  This fixes a miscompilation of crafty with
the new front-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 02:10:38 +00:00
Chris Lattner
bd05982b48 Add some explicit type casts so that tblgen knows the type of the shift 
amount, which is not necessarily the same as the type being shifted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24594 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:34:05 +00:00
Chris Lattner
937a79dbe3 Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen 
improvements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 19:01:59 +00:00
Chris Lattner
60a4ab2d5c Finish moving uncond br over to .td file, remove from .cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24590 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 18:48:01 +00:00
Chris Lattner
1e48478557 Define BR in the .td file now that Evan made tblgen smarter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 18:42:54 +00:00
Nate Begeman
7ac8e6b6a8 Represent the encoding of the SPR instructions as they actually are, so 
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-29 22:42:50 +00:00
Nate Begeman
9b14f66320 Add the remainder of the AltiVec 4 x float instructions. Further 
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-29 08:04:45 +00:00
Nate Begeman
01595c52b3 Small tweaks noticed while on the plane. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-26 22:39:34 +00:00
Nate Begeman
e4f17a5f9b Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-23 05:29:52 +00:00
Chris Lattner
3e7f86a037 disentangle call operands from branch operands a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24400 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-17 19:16:08 +00:00
Chris Lattner
490ad08097 Generate LA and ADDIS when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24395 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-17 17:52:01 +00:00
Chris Lattner
860e8862c1 Add an initial hack at legalizing GlobalAddress into the appropriate nodes 
on Darwin to remove smarts from the isel.  This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file.  However, we can currently emit stuff like
this:  :)

        li r2, lo16(L_x$non_lazy_ptr)
        lis r3, ha16(L_x$non_lazy_ptr)
        lwzx r2, r3, r2

The obvious improvements will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-17 07:30:41 +00:00
Chris Lattner
bae5b3c1c6 LI could theoretically be used for the lo-part of a global address, just like 
lis can be used for the high part.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24388 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-17 07:04:43 +00:00
Nate Begeman
422b0cee7a Patch to clean up function call pseudos and support the BLA instruction, 
which branches to an absolute address.  This is required to support objc
direct dispatch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24370 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-16 00:48:01 +00:00
Chris Lattner
6df2507121 add support for branch on ordered/unordered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24067 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-28 20:32:44 +00:00
Chris Lattner
6e61ca6fa7 autogen undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23991 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 21:03:41 +00:00
Chris Lattner
3075a4e94d Allow pseudos to have patterns, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 20:58:43 +00:00
Chris Lattner
9c73f095bb Autogen fsel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23987 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 20:55:47 +00:00
Chris Lattner
e6115b370a Autogen a few new ppc-specific nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23985 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 20:41:46 +00:00
Chris Lattner
dabb8291e8 Instead of aborting if not a case we can handle specially, break out and 
let the generic code handle it.  This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.

also, reindent this code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23874 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-21 21:17:10 +00:00
Nate Begeman
ae1641c39f Match rotate. This does actually match the rotates in an rc5 cipher, but I 
haven't seen it fire on our testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23863 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-21 06:36:18 +00:00
Nate Begeman
12a923408c Add some more patterns for i64 on ppc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23842 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 07:51:08 +00:00
Jim Laskey
538421411a Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 19:51:16 +00:00
Nate Begeman
2d5aff761d Write patterns for the various shl and srl patterns that don't involve 
doing something clever.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 18:42:01 +00:00
Chris Lattner
f6cd147471 now that tblgen is smarter, use integers directly. This should help Andrew too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23818 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 04:32:04 +00:00
Chris Lattner
8be1fa5dc5 Convert these cases to patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23811 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 01:38:02 +00:00
Nate Begeman
8d94832394 Woo, it kinda works. We now generate this atrociously bad, but correct, 
code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 01:12:32 +00:00
Nate Begeman
da32c9eed6 Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23803 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 00:05:37 +00:00
Chris Lattner
841d12d9ac Fix the JIT encoding of LWA, LD, STD, and STDU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23787 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 16:51:22 +00:00
Nate Begeman
1d9d7427c4 First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 00:28:58 +00:00
Chris Lattner
e0b2e6372f Add a pattern for FSQRTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23750 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 21:44:15 +00:00
Chris Lattner
f379997adc Rename PowerPC*.td -> PPC*.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23740 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:40:39 +00:00
Chris Lattner
7cb6491a0d Add patterns for FP round/extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23727 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 04:55:50 +00:00
Chris Lattner
7b1fe15de0 These definitions have been moved to common code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23681 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-10 06:01:00 +00:00
Chris Lattner
dff06f4348 add patterns for float binops and fma ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23592 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:46:28 +00:00
Chris Lattner
43f07a4bbc another solution to the fsel issue. Instead of having 4 variants, just force 
the comparison to be 64-bits.  This is fine because extensions from float
to double are free.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:07:49 +00:00
Chris Lattner
867940d1b7 fsel can take a different FP type for the comparison and for the result. As such 
split the FSEL family into 4 things instead of just two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:58:23 +00:00
Chris Lattner
919c032fa4 Modify the ppc backend to use two register classes for FP: F8RC and F4RC. 
These are used to represent float and double values, and the two regclasses
contain the same physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 01:35:02 +00:00
Chris Lattner
67ab118a6d Add a bunch of patterns for F64 FP ops, add some more integer ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 23:34:24 +00:00
Chris Lattner
c7a37a52cd tblgen autogens this pattern now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23530 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 22:37:24 +00:00
Chris Lattner
221e53caea now that tblgen is smarter, this pattern is not needed. Also, tblgen 
now inverts commuted versions of ANDC/ORC with the current .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23527 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 19:29:15 +00:00
Chris Lattner
79d0e9f3d1 Codegen ADD X, IMM -> addis/addi if needed. 
This implements PowerPC/fold-li.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23514 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 23:07:13 +00:00
Chris Lattner
e025574370 add a patter for SUBFIC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23509 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:47:06 +00:00
Chris Lattner
0648ccf1e9 Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but 
not associative.  Add [SU]REM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23508 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:38:27 +00:00
Chris Lattner
a5cac6f6eb Mark associative nodes as associative 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23503 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 20:58:39 +00:00
Chris Lattner
645992f595 Nate pointed out that mulh[us] are commutative as well. Thanks! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23500 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 19:01:44 +00:00
Chris Lattner
6bcf1b7eed expose commutativity information 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23498 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 18:27:58 +00:00
Chris Lattner
cfc828a3d0 add support for missed eqv tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23496 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 18:10:51 +00:00
Chris Lattner
91da8623be learn to codegen not as NOR instead of xoris/xori 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23490 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 17:13:15 +00:00
Chris Lattner
30e21a46f0 minor pattern shuffling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23458 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-26 22:20:16 +00:00
Chris Lattner
ea874f3306 Teach the dag isel generator how to construct arbitrary immediates. The 
generated isel now tries li then lis, then lis+ori.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23418 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-24 00:41:58 +00:00
Chris Lattner
4ac85b3e94 disable this for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23366 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-15 21:44:00 +00:00
Chris Lattner
43ef1318c6 give all operands names 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23356 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-14 21:10:24 +00:00
Chris Lattner
4345a4a452 Fix some issues exposed by more testing. XORIS had the wrong operands 
specified.  The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23352 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-14 20:53:05 +00:00
Chris Lattner
c36d065dce Fix some bugs noticed by new checking code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23350 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-14 18:18:39 +00:00
Chris Lattner
043870dd85 Teach the code generator that rlwimi is commutable if the rotate amount 
is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-09 18:17:41 +00:00
Chris Lattner
2eb2517fbe Introduce two new concepts: 
1. Add support for defining Pattern's, which can match expressions when there
   is no instruction that directly implements something.  Instructions usually
   implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
   This seperates the concept of a node xform out from the existing predicate
   support.

Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23286 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-09 00:39:56 +00:00
Chris Lattner
b85c64c4d8 whitespace/comment changes, no functionality diffs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23283 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 23:17:26 +00:00
Chris Lattner
47f01f1b44 Add a bunch of stuff needed for node type inference. Move 'BLR' down with 
the rest of the instructions, add comment markers to seperate portions of
the file into logical parts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23277 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 19:50:41 +00:00
Chris Lattner
bfde080ce0 add patterns for x?oris? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23268 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 17:40:49 +00:00
Chris Lattner
3e63ead49b add patterns to the addi/addis/mulli etc instructions. Define predicates 
for matching signed 16-bit and shifted 16-bit ppc immediates


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 17:33:10 +00:00
Chris Lattner
d1cdc7028c Add patterns for some new instructions, allowing the use of the ineg fragment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23266 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 17:01:54 +00:00
Chris Lattner
e147ceb2fa explicitly specify an operands list for patterns with inputs (e.g. neg) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23240 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-03 01:28:40 +00:00
Chris Lattner
7cd09cf942 rearrange logical ops to group them together more consistently. 
Define the PatFrag class which can be used to define subpatterns to match
things with.  Define 'not', and use it to define the patterns for andc,
nand, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23233 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-03 00:21:51 +00:00
Chris Lattner
6159fb20c2 Add AND/OR/XOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23232 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 22:35:53 +00:00
Chris Lattner
218a15d02c Add some initial patterns to simple binary instructions, though they 
currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23230 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 21:18:00 +00:00
Chris Lattner
e3f1c97734 The condition register being branched on may not be cr0, as such, print it. 
This fixes: UnitTests/2005-07-17-INT-To-FP.c


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23112 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 23:42:05 +00:00
Chris Lattner
28b9cc2d13 allow code using mtcrf to assemble 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23107 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 22:05:54 +00:00
Nate Begeman
a0df5d8da5 Remove operand type 'crbit', since it is no longer used 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23106 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 22:04:17 +00:00
Chris Lattner
8a2d3ca7df implement SELECT_CC fully for the DAG->DAG isel! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23101 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 21:23:58 +00:00
Nate Begeman
6718f11feb Fix JIT encoding of conditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23076 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 04:11:42 +00:00
Chris Lattner
fdf8366ecc LFS/STFS load and store FP values, not integer ones. This change allows us 
to codegen this: float foo() { return 1.245; }

into this:

_foo:
        lis r2, ha16(.CPI_foo_0)
        lfs f1, lo16(.CPI_foo_0)(r2)
        blr

instead of this:

_foo:
        lis r2, ha16(.CPI_foo_0)
        lfs r2, lo16(.CPI_foo_0)(r2)   <-- ouch
        or f1, r2, r2                  <-- ouch
        blr

with the dag isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23033 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-25 00:26:22 +00:00
Chris Lattner
2b54400f08 Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the 
instructions take a consistent reg class.  Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-24 23:08:16 +00:00
Nate Begeman
354df0ae6d Remove some instructions we no longer generate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22976 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 01:16:46 +00:00
Chris Lattner
1f24df6324 Remove some regs that are not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22975 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-22 22:32:13 +00:00
Chris Lattner
45fcb8f410 Fix operand numbers by marking variable arity nodes as such and by fixing 
the operand lists of a few other nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22883 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:25:33 +00:00
Nate Begeman
394cd13ba3 Fix JIT encoding of ppc mfocrf instruction; the operands were reversed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-08 20:04:52 +00:00
Nate Begeman
2497e6391f Support building non-PIC 
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-21 20:44:43 +00:00
Nate Begeman
adeb43ddf4 Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5. 
8-byte align doubles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-20 22:42:00 +00:00
Chris Lattner
fc87928ebb PPC "branch and link" instructions are branches in the PPC sense, but not 
in the LLVM code generator sense (they are calls).  Don't mark them as such,
which fixes the regressions on the ppc tester last night


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22065 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-05-15 20:11:44 +00:00
Chris Lattner
14522e31d9 switch over the rest of the formats that use RC to use isDOT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:21:30 +00:00
Chris Lattner
883059fb58 Convert the XForm instrs and XSForm instruction over to use isDOT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:15:18 +00:00
Chris Lattner
a611ab72ca convert over bform and iform instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:00:59 +00:00
Chris Lattner
57226fbc7b Convert over DForm and DSForm instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:59:28 +00:00
Chris Lattner
e19d0b1130 Convert XLForm and XForm instructions over to use PPC64 when appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:51:30 +00:00
Chris Lattner
5035cef732 Convert XO XS and XFX forms to use isPPC64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:40:07 +00:00
Chris Lattner
0bdc6f1fd4 Turn PPC64 and VMX into classes that can be added to instructions instead of 
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:32:54 +00:00
Nate Begeman
16ac709c63 Change codegen for setcc to read the bit directly out of the condition 
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-18 02:43:24 +00:00
Nate Begeman
7bfba7d5e3 Implement multi-way branches through logical ops on condition registers. 
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21298 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 09:45:08 +00:00
Nate Begeman
ef7288c824 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 03:20:38 +00:00
Nate Begeman
7af0248af4 Initial support for allocation condition registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 07:04:16 +00:00
Nate Begeman
9f833d3085 Implement bitfield clears 
Implement divide by negative power of two


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21240 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 00:10:02 +00:00
Chris Lattner
5eef9f3bc9 ORo sets CR0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21227 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:48 +00:00
Chris Lattner
6b4ea2cfa2 Revert the previous patch, which I didn't mean to check in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:41 +00:00
Chris Lattner
26d4fdb968 Fix a minor bug (ORo didn't mark that it set CR0). 
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:01:39 +00:00
Nate Begeman
c7bd4827cd Add recording variants of ISD::AND and ISD::OR. This kills almost 1000 
(1.5%) instructions in 186.crafty


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21222 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 06:34:10 +00:00
Nate Begeman
cd08e4cb7e Add rlwnm instruction for variable rotate 
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21187 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 20:09:12 +00:00
Nate Begeman
815d6dac1e Add support for MULHS and MULHU nodes 
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 00:25:27 +00:00
Nate Begeman
178bb34ee5 Add support for multiply-add, multiply-sub, and their negated versions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 23:01:51 +00:00
Nate Begeman
27eeb00a1a Set shift amount to Extend 
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 05:59:34 +00:00
Nate Begeman
3316252034 Implement SetCC, fix ZERO_EXTEND_INREG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20933 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-29 21:54:38 +00:00
Nate Begeman
ca12a2bd91 Remove fake instruction 'subc' (mnemonic for subfc). 
More pattern isel updates


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20902 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-28 22:28:37 +00:00
Chris Lattner
7a823bd01f Fix a problem where the PPC backend lost track of the fact that it had 
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool.  This should hopefully
fix oscar from sending the PPC tester spinning out of control.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20197 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-02-15 20:26:49 +00:00
Chris Lattner
be686a8897 Factor out common .td file chunks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18982 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-12-16 16:31:57 +00:00
Chris Lattner
a1ab451392 Fix encoding of fneg instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18226 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-25 03:53:44 +00:00
Nate Begeman
3b78e3b6a9 Fix encoding of bctrl, and remove some unused instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18192 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-24 00:16:37 +00:00
Chris Lattner
6f407893e2 Fix encoding of blr and bctr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18178 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 22:06:24 +00:00
Chris Lattner
943f45208c Fix encodings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18164 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 19:23:18 +00:00
Chris Lattner
6540c6c344 LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18138 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 05:54:25 +00:00
Chris Lattner
dd99885da3 Comment out a couple of unused instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18135 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-22 23:07:01 +00:00
Misha Brukman
145a5a3746 Add BCTR and LWZU instruction opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17851 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-15 21:20:09 +00:00
Misha Brukman
40a55e1e29 Add BA, BL, and BLA opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17193 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 20:29:24 +00:00
Misha Brukman
da8d96d1a1 Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions. 
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17182 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 06:05:49 +00:00
Misha Brukman
15f74b3f4f The value of the XO field for MFLR and MFCTR is 339, not 399 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17181 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 05:38:55 +00:00
Nate Begeman
2d4c98d79b Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly 
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.

This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17068 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-16 20:43:38 +00:00
Nate Begeman
b816f0298d Several fixes and enhancements to the PPC32 backend. 
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16826 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-07 22:30:03 +00:00
Nate Begeman
a2de102a5b add optimized code sequences for setcc x, 0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16478 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-22 04:40:25 +00:00
Nate Begeman
20136a21ba Add 64 bit divide instructions, and use them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16198 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-06 18:46:59 +00:00
Nate Begeman
ed42853be1 All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-04 05:00:00 +00:00
Nate Begeman
b7a8f2cdaa Convert remaining X-Form and Pseudo instructions over to asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-02 08:13:00 +00:00
Nate Begeman
cc8bd9ca7c convert M and MD form instructions to generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16121 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-31 02:28:08 +00:00
Nate Begeman
07aada8b0f Move yet more instructions over to being printed by the generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16112 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-30 02:28:06 +00:00
Nate Begeman
6b3dc55ef8 Convert A-Form instructions to auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16107 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:45:13 +00:00
Nate Begeman
d332fd54f5 Improvements to int->float cast code for PPC-64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16105 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:02:43 +00:00
Nate Begeman
f2f0781a10 Implement the following missing functionality in the PPC backend: 
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite.  Fixes Regression/casts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16081 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 08:19:32 +00:00
Nate Begeman
c3306120cc Move XForm instructions over to the auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 05:56:39 +00:00
Nate Begeman
b47321ba2b Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15952 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-20 09:56:22 +00:00
Nate Begeman
81d265d692 Clean up floating point instruction selection. 
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15913 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 05:20:54 +00:00
Chris Lattner
0ea3171fbf Convert all of the DForm_6* operations, which makes all of the Zimm16 users 
dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15754 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 05:46:14 +00:00
Chris Lattner
97b2a2e389 Convert the DForm_4 over to the asmprintergen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15751 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 05:20:16 +00:00
Chris Lattner
7bb424fafc Print mflr using the asmwriter generator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15749 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 23:27:29 +00:00
Nate Begeman
b0b8b93e58 Add indexed forms of load doubleword and load word algebraic for 64 bit targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15743 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 22:12:20 +00:00
Nate Begeman
244e64ead2 Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15710 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-13 02:19:26 +00:00
Misha Brukman
55eee3dc7a Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15668 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 23:33:34 +00:00
Misha Brukman
f1f6cef161 Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15667 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 20:56:14 +00:00
Misha Brukman
96b6110685 Add doubleword load/store (64-bit only). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15665 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 15:54:36 +00:00
Nate Begeman
b64af918cb Fix casts of float to unsigned long 
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 20:42:36 +00:00
Misha Brukman
4ad7d1bee7 Use instruction formats as defined in the PowerPC ISA manual 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15577 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-09 17:24:04 +00:00
Misha Brukman
68f3459994 Remove unused opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15447 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-03 20:23:44 +00:00
Misha Brukman
37dcae63eb * Use simpler instruction templates to define instructions 
* Fix several extended opcodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15423 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-02 21:58:52 +00:00
Misha Brukman
28791dd17f Separate instruction formats from instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15414 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-02 16:54:54 +00:00
Misha Brukman
8c02c1cbb8 Renamed files: 
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 23:29:16 +00:00
Misha Brukman
f228fa0580 Add COND_BRANCH pseudo instruction, patch by Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15283 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 18:35:54 +00:00
Misha Brukman
53f567817c MovePCtoLR (which is `bl' in disguise) modifies LR implicitly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15272 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 17:15:05 +00:00
Misha Brukman
53d9a48855 Add SUBI instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15077 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-21 15:53:04 +00:00
Misha Brukman
86ddcf9d4f Differentiate between global and weak symbol loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15037 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-20 15:52:25 +00:00
Misha Brukman
2bf5438931 Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14895 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-16 20:33:41 +00:00
Misha Brukman
c661c3001c * Coalesce the handy CALL* alias opcodes with the standard ones 
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14511 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-30 22:00:45 +00:00
Misha Brukman
5fa2b028b8 * Use LA instead of LWZ for LoadLoAddr 
* Specify the isCall bit and caller-save registers for some call instrs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14501 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-29 23:37:36 +00:00
Misha Brukman
3905b57442 Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14470 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-28 18:27:08 +00:00
Misha Brukman
b2edb443e0 Set isBranch and isTerminator bits on all branch instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14469 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-28 18:23:35 +00:00
Misha Brukman
5dfe3a9c3b Initial revision 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-21 16:55:25 +00:00