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8239 Commits

Author SHA1 Message Date
Craig Topper
39a9e485f2 Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150296 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 06:24:48 +00:00
Craig Topper
f41ab77847 More tweaks to get the size of the X86 disassembler tables down. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-09 08:58:07 +00:00
Craig Topper
ce8f4c58d8 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-09 07:45:30 +00:00
Jakob Stoklund Olesen
450b3850ce Handle register masks when searching for EFLAGS clobbers. 
Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150117 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-09 00:17:22 +00:00
Elena Demikhovsky
f602040c49 Fixed a bug in printing "cmp" pseudo ops. 
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0  llc             0x0000000001355803
> 1  llc             0x0000000001355dc9
> 2  libpthread.so.0 0x00007f79a30575d0
> 3  libc.so.6       0x00007f79a23a1945 gsignal + 53
> 4  libc.so.6       0x00007f79a23a2f21 abort + 385
> 5  libc.so.6       0x00007f79a239a810 __assert_fail + 240
> 6  llc             0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119

I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.

You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 08:37:26 +00:00
Craig Topper
bc0e4bf754 Remove a couple unneeded intrinsic patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150067 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 08:29:30 +00:00
Craig Topper
5a313bb7e8 Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 06:36:57 +00:00
Evan Cheng
de1df103b9 Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 22:50:41 +00:00
Craig Topper
dbd98a4b1b Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 06:28:42 +00:00
Derek Schuff
2ea93875b2 Enable streaming of bitcode 
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 22:30:29 +00:00
Chris Lattner
7302d80490 Remove some dead code and tidy things up now that vectors use ConstantDataVector 
instead of always using ConstantVector.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149912 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 21:56:39 +00:00
Benjamin Kramer
699ddcbcb3 X86: Don't call malloc for 4 bits. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 12:06:18 +00:00
Craig Topper
d156dc11f9 Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149859 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 07:17:51 +00:00
Duncan Sands
5b8a1db7ea Persuade GCC that there is nothing worth warning about here (there isn't). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 14:20:11 +00:00
Chandler Carruth
69f44692bf Begin fleshing out more convenience predicates in llvm::Triple and 
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.

This round of predicates is focused on OS-categorization predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149815 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 08:26:40 +00:00
Craig Topper
655b8de7b2 Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 07:21:30 +00:00
Craig Topper
6d1263acb9 Convert assert(0) to llvm_unreachable in X86 Target directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 05:38:58 +00:00
Craig Topper
abb94d0687 Convert some assert(0) in default of switch statements to llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149808 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 03:43:23 +00:00
Craig Topper
5b209e84f4 Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 03:14:49 +00:00
Craig Topper
eea723fe02 Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 00:55:56 +00:00
Andrew Trick
061efcfb3e TargetPassConfig: confine the MC configuration to TargetMachine. 
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-04 02:56:59 +00:00
Craig Topper
a02556679e Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 06:52:33 +00:00
Craig Topper
fa5b70e1d8 Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 06:32:21 +00:00
Andrew Trick
843ee2e6a4 Added TargetPassConfig. The first little step toward configuring codegen passes. 
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 05:12:41 +00:00
Andrew Trick
8247e0dca6 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 05:12:30 +00:00
Lang Hames
6e3f7e4913 Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 01:13:49 +00:00
Jakob Stoklund Olesen
478a8a02bc Require non-NULL register masks. 
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 23:52:57 +00:00
Elena Demikhovsky
0f1ead47a0 Minor change in signature of the getZeroVector() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:20:18 +00:00
Elena Demikhovsky
dcabc7bca9 Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:10:43 +00:00
Francois Pichet
1ae52f686c Unbreak the MSVC build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 08:36:09 +00:00
Lang Hames
50a36f7102 Set EFLAGS correctly in EmitLoweredSelect on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 07:48:37 +00:00
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 23:20:51 +00:00
Mon P Wang
845b1899b6 Avoid creating an extract element to an illegal type after LegalizeTypes has run. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 22:15:20 +00:00
Chad Rosier
c2348d5c08 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149521 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 18:45:51 +00:00
Elena Demikhovsky
1766971769 Passing AVX 256-bit structures in Win64 was wrong. 
Fixed Win64 calling conventions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149494 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 10:46:14 +00:00
Elena Demikhovsky
732525758f Shortened code in shuffle masks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 10:33:05 +00:00
Elena Demikhovsky
3ae98150e3 Optimization for "truncate" operation on AVX. 
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 07:56:44 +00:00
Craig Topper
a1902a18cd Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149478 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 06:51:58 +00:00
Devang Patel
0db58bfece Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149396 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-31 18:14:05 +00:00
Craig Topper
cac50c5ab8 Remove pcmpgt/pcmpeq intrinsics as clang is not using them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-31 06:52:44 +00:00
Evan Cheng
893a045cdb PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149294 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 23:10:32 +00:00
Devang Patel
885f65b4a1 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 22:47:12 +00:00
Devang Patel
be3e310d5e Intel syntax. Support .intel_syntax directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 20:02:42 +00:00
Benjamin Kramer
630ecf0f53 Fix refacto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149269 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 20:01:35 +00:00
Douglas Gregor
b2f1b5028c Eliminate narrowing conversion in initializer list, to make C++11 happy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149254 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 16:57:18 +00:00
Benjamin Kramer
9c68354956 X86: Simplify shuffle mask generation code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149248 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 15:16:21 +00:00
Craig Topper
cc30006391 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 07:50:31 +00:00
Craig Topper
86c7c583a3 Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 01:10:15 +00:00
Devang Patel
a28101e61a Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-27 19:48:28 +00:00
Craig Topper
3982b3cc7b Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-27 07:09:40 +00:00
Jim Grosbach
cb5dca3815 Keep source location information for X86 MCFixup's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-27 00:51:27 +00:00
Jakob Stoklund Olesen
53fa56e8dc Handle call-clobbered ymm registers on Win64. 
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.

Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered.  This allows live xmm
registers across calls.

This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 22:59:28 +00:00
Victor Umansky
668f7ac9e4 Fix for the following bug in AVX codegen for double-to-int conversions: 
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 08:51:39 +00:00
Craig Topper
a3937416e4 Add HasXOP predicate check covering a bunch of XOP intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149054 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 07:51:55 +00:00
Craig Topper
15388c4666 Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 07:31:30 +00:00
Craig Topper
e566cd0f4d Remove some more patterns by custom lowering intrinsics to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 07:18:03 +00:00
Chris Lattner
9748479590 fix a bug I introduced in r148929, this is not a splat! 
Thanks to Eli for noticing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 09:56:22 +00:00
Craig Topper
969ba287cd Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 06:43:11 +00:00
Chris Lattner
4ca829e895 use ConstantVector::getSplat in a few places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 06:02:56 +00:00
Craig Topper
4bb3f34b22 Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 05:37:32 +00:00
Craig Topper
bce73e0a8c Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 04:42:03 +00:00
Craig Topper
042883f5da Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 03:52:09 +00:00
Devang Patel
3b96e1fe3b Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 21:43:36 +00:00
Elena Demikhovsky
28d7e71a30 ZERO_EXTEND operation is optimized for AVX. 
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 13:54:13 +00:00
Craig Topper
dfc8e470b6 Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148771 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 03:03:17 +00:00
Devang Patel
392ad6d8aa Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148751 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 23:56:33 +00:00
Devang Patel
f2d213745e Intel syntax: Robustify parsing of memory operand's displacement experssion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 22:35:25 +00:00
Devang Patel
3e08131185 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 20:20:06 +00:00
Devang Patel
7c64fe651a Intel syntax: Parse segment registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 18:31:58 +00:00
Craig Topper
7925e2555d Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148687 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 08:18:28 +00:00
Craig Topper
7fb8b0c5d3 Update more places to use target specific nodes for vector shifts instead of intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148685 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 06:46:22 +00:00
Craig Topper
80e46360e9 Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148684 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 06:16:53 +00:00
Craig Topper
2b21fbaf11 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148672 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 00:06:44 +00:00
Craig Topper
1906d32e55 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 23:36:02 +00:00
Craig Topper
67609fd0eb Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 22:42:16 +00:00
Craig Topper
ed2e13d667 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 19:15:14 +00:00
Craig Topper
07a276277f Make code a little less verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 03:07:48 +00:00
Craig Topper
6a32b6f0c0 Remove unused X86 ISD node type defines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148644 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 01:15:56 +00:00
Craig Topper
6fdf3d54d2 Move some vector shift patterns into their instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148643 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 00:41:20 +00:00
Craig Topper
babb1459f3 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148641 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-21 18:37:15 +00:00
Benjamin Kramer
8608cc9473 Remove unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148635 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-21 10:42:44 +00:00
Craig Topper
d9ec725db4 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148632 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-21 08:49:33 +00:00
Devang Patel
1aea430b88 Intel syntax: Robustify register parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 22:32:05 +00:00
David Blaikie
4d6ccb5f68 More dead code removal (using -Wunreachable-code) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:51:11 +00:00
Devang Patel
fdd3b30151 Intel syntax: Parse ... PTR [-8] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:14:06 +00:00
Craig Topper
8f35c13842 Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 09:29:03 +00:00
Craig Topper
0e2037ba2b Add support for selecting 256-bit PALIGNR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 05:53:00 +00:00
Eli Friedman
9a2478ac1a Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 00:05:46 +00:00
Devang Patel
a951f77ca3 Post process 'and', 'sub' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380 Intel syntax: There is no need to create unary expr for simple negative displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 17:53:25 +00:00
Craig Topper
40385c8104 Folding table additions and fixes for AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148467 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 08:50:38 +00:00
Craig Topper
1a7700a3fa Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 08:19:12 +00:00
Nick Lewycky
22de16dc75 Add a TargetOption for disabling tail calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-19 00:34:10 +00:00
Jakob Stoklund Olesen
c38c4561cd Add experimental -x86-use-regmask command line option. 
It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148438 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
71f0fc1ca8 Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 23:52:19 +00:00
Devang Patel
b8ba13f009 Process instructions after match to select alternative encoding which may be more desirable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 22:42:29 +00:00
Jim Grosbach
ec3433852d Tidy up. MCAsmBackend naming conventions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
31867660cb Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
0bd2ae92b0 Move X86 callee saved register lists to the X86CallConv .td file. 
Add a trivial implementation of the getCallPreservedMask() hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148347 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 22:47:01 +00:00
Devang Patel
2f8af1d643 Intel syntax: Fix parser match class to check memory operand size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:48:03 +00:00
Devang Patel
6220fea2a8 Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 21:25:10 +00:00
Devang Patel
bc51e501a0 Untabify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148322 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 19:09:22 +00:00
Devang Patel
9a3d293cf3 Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 19:08:07 +00:00
Devang Patel
d37ad247cc Intel syntax: Robustify memory operand parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 18:00:18 +00:00
Nadav Rotem
a16d441430 Fix warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148301 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 09:31:09 +00:00
Nadav Rotem
0b94b5f52b Fix 11769. 
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 09:13:19 +00:00
Craig Topper
8b5a6b63dd Remove unnecessary AVX check from an assert. hasSSE2 is enough. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 08:23:44 +00:00
Craig Topper
37c2677fbc Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-17 04:44:50 +00:00
Eli Friedman
1857b51ef5 Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148240 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 16:42:21 +00:00
Eli Friedman
a20b71518a Get rid of unused codegen-only instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148239 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 16:29:35 +00:00
Craig Topper
b7ab7fe053 Give priority to AVX over SSE for 128-bit floating point unpck instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148233 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 09:56:42 +00:00
Nadav Rotem
cc6165695f [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. 
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.

Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-15 19:27:55 +00:00
Benjamin Kramer
ed4c8c633c Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-15 13:16:05 +00:00
Craig Topper
d07ef50ca1 Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:29:57 +00:00
Craig Topper
446626d236 Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148194 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:14:53 +00:00
Chad Rosier
d32d3b758f Fix pasto from r146196. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148167 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 01:50:21 +00:00
Devang Patel
85d5aaecd0 Revert r148131, it was committed before it was ready. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:28:58 +00:00
Devang Patel
c798cc4283 Refactor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 19:12:18 +00:00
Craig Topper
0518970dc8 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148112 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 09:21:41 +00:00
Craig Topper
562659ff6b use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:32:21 +00:00
Craig Topper
12216172c0 Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:12:35 +00:00
Craig Topper
c30432ab57 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:59:47 +00:00
Craig Topper
b9c7f652d7 Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:12:41 +00:00
Craig Topper
e6cf4a070d Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 05:04:25 +00:00
Bill Wendling
b4ee5168ab Fix off-by-one error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 00:41:53 +00:00
Bill Wendling
86b1a7d614 Fix the code that was WRONG. 
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 23:05:03 +00:00
Elena Demikhovsky
16db710898 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:33:10 +00:00
Rafael Espindola
85b9d43d4c Support segmented stacks on 64-bit FreeBSD. 
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148041 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:24:30 +00:00
Rafael Espindola
e4d18de5d1 Support segmented stacks on win32. 
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148040 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:22:08 +00:00
Devang Patel
dd929fc704 Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148032 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 18:03:40 +00:00
Benjamin Kramer
e2eb92578a After Jakob's r147938 exception handling on i386 was completely broken. 
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.

This should fix nightly tester failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148030 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 17:37:18 +00:00
Nadav Rotem
d2070b00ef Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors. 
The attached testcase was stuck in an endless loop.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 15:31:55 +00:00
Benjamin Kramer
fb418bab97 X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148024 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 12:41:34 +00:00
Devang Patel
c59d9df248 Add predicate method check match memory operand size, if available. 
In att style asm syntax memory operand size is derived from suffix attached with mnemonic.  In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148006 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 01:51:42 +00:00
Devang Patel
0a338868b7 Add intel style operand parser skeleton. 
This is a work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148002 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 01:36:43 +00:00
Chandler Carruth
0fe9a92b33 Switch all of the uses of my InsertDAGNode helper to follow the exact 
same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.

I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.

I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 01:34:44 +00:00
Rafael Espindola
2028b793e1 Support segmented stacks on mac. 
This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support
frames with static size
Patch by Brian Anderson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147960 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 19:00:37 +00:00
Rafael Espindola
25cd4ff97e Generate the segmented stack prologue for fastcc too. 
Patch by Brian Anderson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147958 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 18:41:19 +00:00
Chandler Carruth
11f0e7b158 Revert r147945 which disabled an addressing mode transformation. I had 
hoped this would revive one of the llvm-gcc selfhost build bots, but it
didn't so it doesn't appear that my transform is the culprit.

If anyone else is seeing failures, please let me know!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147957 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 18:36:12 +00:00
Rafael Espindola
313c703831 Use unsigned comparison in segmented stack prologue. 
This is a comparison of two addresses, and GCC does the comparison unsigned.

Patch by Brian Anderson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147954 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 18:23:35 +00:00
Rafael Espindola
014f7a3b37 Explicitly set the scale to 1 on some segstack prologue instrs. 
Patch by Brian Anderson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147952 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 18:14:03 +00:00
Jan Sjödin
46df3adb4e Add XOP Intrinsics and tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 15:20:20 +00:00
Nadav Rotem
394a1f53b9 Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147948 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 14:07:51 +00:00
Chandler Carruth
e4bc80a14b Disable the transformation I added in r147936 to see if it fixes some 
strange build bot failures that look like a miscompile into an infloop.
I'll investigate this tomorrow, but I'd both like to know whether my
patch is the culprit, and get the bots back to green.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147945 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 12:17:47 +00:00
Chandler Carruth
d65a9106cd Hoist a really redundant code pattern into a helper function, and delete 
lots of lines of code. No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147942 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 11:04:36 +00:00
Chandler Carruth
93b7358fc9 Simplify the AND-rooted mask+shift checking code to match that of the 
SRL-rooted code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147941 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 09:35:04 +00:00
Chandler Carruth
dddcd78e24 Unify the interface of the three mask+shift transform helpers, and 
factor the differences that were hiding in one of them into its other
caller, the SRL handling code. No change in behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147940 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 09:35:02 +00:00
Chandler Carruth
fde2c1a4c6 Clarify and make explicit some of the requirements for transforming 
mask+shift pairs at the beginning of the ISD::AND case block, and then
hoist the final pattern into a helper function, simplifying and
reflowing it appropriately. This should have no observable behavior
change, but several simplifications fell out of this such as directly
computing the new mask constant, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147939 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 09:35:00 +00:00
Jakob Stoklund Olesen
dec1f99615 Fix undefined code and reenable test case. 
I don't think the compact encoding code is right, but at least is has
defined behavior now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 09:08:04 +00:00
Chandler Carruth
6ae18e5092 Hoist the logic to transform shift+mask combinations into sub-register 
extracts and scaled addressing modes into its own helper function. No
functionality changed here, just hoisting and layout fixes falling out
of that hoisting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 08:48:20 +00:00
Chandler Carruth
f103b3d1b9 Teach the X86 instruction selection to do some heroic transforms to 
detect a pattern which can be implemented with a small 'shl' embedded in
the addressing mode scale. This happens in real code as follows:

  unsigned x = my_accelerator_table[input >> 11];

Here we have some lookup table that we look into using the high bits of
'input'. Each entity in the table is 4-bytes, which means this
implicitly gets turned into (once lowered out of a GEP):

  *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2));

The shift right followed by a shift left is canonicalized to a smaller
shift right and masking off the low bits. That hides the shift right
which x86 has an addressing mode designed to support. We now detect
masks of this form, and produce the longer shift right followed by the
proper addressing mode. In addition to saving a (rather large)
instruction, this also reduces stalls in Intel chips on benchmarks I've
measured.

In order for all of this to work, one part of the DAG needs to be
canonicalized *still further* than it currently is. This involves
removing pointless 'trunc' nodes between a zextload and a zext. Without
that, we end up generating spurious masks and hiding the pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 08:41:08 +00:00
Lang Hames
9ffaa6a8a9 Fixed order of operands in comment to match code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147890 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 22:53:20 +00:00
Joerg Sonnenberger
216f63702f Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes. 
Add a test that checks the stack alignment of a simple function for
Darwin, Linux and NetBSD for 32bit and 64bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147888 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 22:43:53 +00:00
Chad Rosier
1b2983bb23 Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a few 
failing test cases on our internal AVX nightly tester.
rdar://10663637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 22:14:06 +00:00
Bill Wendling
f6c0747ae3 For i386, don't use the generic code. 
As the comment around 7746 says, it's better to use the x87 extended precision
here than SSE. And the generic code doesn't know how to do that. It also regains
the speed lost for the uint64_to_float.c testcase.
<rdar://problem/10669858>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 19:41:30 +00:00
Devang Patel
4ba0e75e4b Add definition for intel asm variant. 
Right now, this just adds additional entries in match table. The parser does not use them yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147859 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 17:51:54 +00:00
David Blaikie
2bd335470f Remove unnecessary default cases in switches that cover all enum values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 16:47:17 +00:00
Benjamin Kramer
66a7fd78ee Add definitions for AMD's bobcat (aka btver1) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 11:50:02 +00:00
Craig Topper
a937633893 Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147844 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 08:23:59 +00:00
Craig Topper
1accb7ed98 Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147843 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 06:54:16 +00:00
Craig Topper
d0a3117768 Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147842 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 06:37:29 +00:00
Craig Topper
c6d59954d8 Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 06:30:56 +00:00
Devang Patel
c16d96f6f4 Fix asm string wrt variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147805 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 21:32:02 +00:00
Devang Patel
0dbcadaa2f Split AsmParser into two components - AsmParser and AsmParserVariant 
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 19:13:28 +00:00
Chandler Carruth
4e3a40293f Don't rely on the fact that shift values are never very large, and thus 
this substraction will result in small negative numbers at worst which
become very large positive numbers on assignment and are thus caught by
the <=4 check on the next line. The >0 check clearly intended to catch
these as negative numbers.

Spotted by inspection, and impossible to trigger given the shift widths
that can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147773 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 09:47:25 +00:00
Craig Topper
16de4632bb Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 09:02:13 +00:00
Craig Topper
8ffc964582 Add HasAVX predicate to some of the AVX patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147769 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 08:34:00 +00:00
Craig Topper
47cf1003fa Reorder a bunch of patterns to put the AVX version first thus giving it priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147768 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 08:10:38 +00:00
Craig Topper
5feb5dae93 Clean up patterns for MOVNT*. Not sure why there were floating point types on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147767 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 06:52:46 +00:00
Craig Topper
8974cd85cc Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no AVX equivalent so we should use the SSE version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147766 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 06:38:55 +00:00
Craig Topper
dfa5f573e7 Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147765 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 05:07:01 +00:00
Craig Topper
6202e45d53 Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147764 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 02:28:15 +00:00
Craig Topper
39f227e4dd Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147762 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 00:11:29 +00:00
Craig Topper
a8224ddf80 Enable FISTTP* instructions when AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147758 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-08 23:04:21 +00:00
Victor Umansky
435d0bd09d Reverted commit #147601 upon Evan's request. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147748 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-08 17:20:33 +00:00
Craig Topper
eb3d460b25 Fix typo in the X86 backend readme. Patch from Jaeden Amero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147739 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-07 20:35:21 +00:00
Benjamin Kramer
f321e1075e Remove VectorExtras. This unused helper was written for a type of API that is discouraged now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-07 19:42:13 +00:00
Craig Topper
272cc580f8 Remove unnecessary check of hasAVX(). It's already included in hasXMM(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147734 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-07 18:48:43 +00:00
Eric Christopher
5548755201 Make the 'x' constraint work for AVX registers as well. 
Fixes rdar://10614894

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147704 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-07 01:02:09 +00:00
Craig Topper
193cf04f5b Mark scalar FMA4 instructions as ignoring the VEX.L bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147602 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-05 08:56:10 +00:00
Victor Umansky
19d8559019 Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. 
Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX)

Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-05 08:46:19 +00:00
Bill Wendling
397ae210ce Replace the uint64_t -> double convertion algorithm with one that's more efficient. 
This small bit of ASM code is sufficient to do what the old algorithm did:

     movq       %rax,  %xmm0
     punpckldq  (c0),  %xmm0  // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
     subpd      (c1),  %xmm0  // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
   #ifdef __SSE3__
     haddpd   %xmm0, %xmm0          
   #else
     pshufd   $0x4e, %xmm0, %xmm1 
     addpd    %xmm1, %xmm0
   #endif

It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on
all processors.
<rdar://problem/7719814>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147593 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-05 02:13:20 +00:00
Benjamin Kramer
a5f8942e05 Silence warnings of a mysterious compiler that still defaults to C89. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147553 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 22:06:45 +00:00
Evan Cheng
56f582d664 For x86, canonicalize max 
(x > y) ? x : y
=>
(x >= y) ? x : y

So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0

This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl   %esi, %edi
testl  %edi, %edi
movl   $0, %eax
cmovgl %edi, %eax
=>
xorl   %eax, %eax
subl   %esi, $edi
cmovsl %eax, %edi

rdar://10633221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147512 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 01:41:39 +00:00
Chad Rosier
b90d2a9046 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 23:19:12 +00:00
Nadav Rotem
c2d064f028 Revert 147426 because it caused pr11696. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 22:19:42 +00:00
Chad Rosier
3d1161e9ae Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather 
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147481 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 21:05:52 +00:00
Devang Patel
b1666b971e Intel style asm variant does not need '%' prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 18:22:10 +00:00
Craig Topper
c612d79817 Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147430 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 09:17:37 +00:00
Craig Topper
a51bb3aa75 Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147428 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 08:46:48 +00:00
Nadav Rotem
a46f35d3d6 Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147426 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 08:05:46 +00:00
Craig Topper
a86bcfb565 Allow CRC32 instructions to be selected when AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 19:51:58 +00:00
Craig Topper
de9e4c728e Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147409 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 19:40:22 +00:00
Benjamin Kramer
8943574b44 X86Disassembler: Fix undefined behavior found by GCC 4.6 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147404 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 17:55:36 +00:00
Craig Topper
b3982da7d2 Merge X86 SHUFPS and SHUFPD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 23:50:21 +00:00
Craig Topper
3ee6d22c78 Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 23:24:49 +00:00
Craig Topper
e00805d52f Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 23:15:11 +00:00
Craig Topper
7ba2725f5d Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 07:16:00 +00:00
Craig Topper
06f554d06a Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 05:20:36 +00:00
Craig Topper
5d1a38cbfa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 04:48:54 +00:00
Craig Topper
4d5c4423b9 Combine FMA4 SS/SD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:33:59 +00:00
Craig Topper
ca28590d8b Combine FMA4 PS/PD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:17:15 +00:00
Craig Topper
2e9ed29449 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 02:18:36 +00:00
Craig Topper
57d4b3315f Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 01:49:53 +00:00
Craig Topper
1604ccfc01 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:43:40 +00:00
Craig Topper
19f18be449 Expose FMA3 instructions to the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:03:14 +00:00
Craig Topper
c38fff4277 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:46:19 +00:00
Craig Topper
5ebee4494b Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:25:56 +00:00
Craig Topper
8493e39014 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:47:31 +00:00
Craig Topper
b75f5f7d5d Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:08:36 +00:00
Craig Topper
78be212d1b Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:00:08 +00:00
Craig Topper
d65c7da5b0 Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 17:41:56 +00:00
Craig Topper
d4d3513d37 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 15:51:45 +00:00
Craig Topper
19ec2a9db1 Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:34:54 +00:00
Craig Topper
d62c16e535 Remove some elses after returns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:20:51 +00:00
Craig Topper
3224e6b60a Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:09:33 +00:00
Eli Friedman
da813f4209 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 21:24:44 +00:00
Elena Demikhovsky
021c0a2ee7 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 08:14:01 +00:00
Craig Topper
3738ccd7eb Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 06:27:23 +00:00
Rafael Espindola
ce618af3e8 Section relative fixups are a coff concept, not a x86 one. Replace the 
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 14:47:52 +00:00
Chandler Carruth
7782102c70 Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the 
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type

We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 12:12:34 +00:00
Chandler Carruth
3d636ea8ed Add systematic testing for cttz as well, and fix the bug I spotted by 
inspection earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 11:46:10 +00:00
Benjamin Kramer
32d720bb2f Chandler fixed this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 11:23:32 +00:00
Chandler Carruth
d873a4b89b Expand more when we have a nice 'tzcnt' instruction, to avoid generating 
'bsf' instructions here.

This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 11:11:38 +00:00
Chandler Carruth
acc068e873 Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the 
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:

  (sizeof(x)*8 - 1) ^ __builtin_clz(x)

Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.

The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.

Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.

These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 10:55:54 +00:00
Rafael Espindola
df09270ae8 Move x86 specific bits of the COFF writer to lib/Target/X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147231 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 02:14:02 +00:00
Chad Rosier
30450e89d9 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:35:21 +00:00
Chad Rosier
5c0d761d63 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:59:09 +00:00
Chad Rosier
649326ab15 No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't 
necessary.  Please chime in if I'm mistaken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:14:52 +00:00
Rafael Espindola
edae8e1e4d Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:30:17 +00:00
Rafael Espindola
dc9a8a378d Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:00:36 +00:00
Craig Topper
224c1b275d Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 08:06:52 +00:00
Craig Topper
e1a18a66df Fix typo in a couple comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 06:30:53 +00:00
Elena Demikhovsky
ba4f83b4e9 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 13:34:28 +00:00
Chandler Carruth
f2d7693fbb Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 11:19:37 +00:00
Chandler Carruth
cfb75fba73 Fix up the CMake build for the new files added in r146960, they're 
likely to stay either way that discussion ends up resolving itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 08:42:11 +00:00
David Blaikie
2d24e2a396 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 02:50:00 +00:00
Jakob Stoklund Olesen
570f9a972e Emit a getMatchingSuperRegClass() implementation for every target. 
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 16:53:34 +00:00
Benjamin Kramer
0581ed792b Another variadics tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 20:51:31 +00:00
Benjamin Kramer
2ea4cdb81f Use the fancy new VariadicFunction template instead of a plain variadic function. 
Some compilers were complaining about passing StringRef to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 19:59:20 +00:00
Craig Topper
ab44d3cf49 Remove an unused X86ISD node type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 19:16:44 +00:00
Benjamin Kramer
e6cddb77dc X86: Factor the bswap asm matching to be slightly less horrible to read. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 14:36:05 +00:00
Rafael Espindola
8f7d12ccfd Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:14:52 +00:00
Lang Hames
8b99c1e42c Make sure that the lower bits on the VSELECT condition are properly set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:08:46 +00:00
Craig Topper
94438ba538 Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 08:06:31 +00:00
Eli Friedman
7e840efc23 Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:46:18 +00:00
Chad Rosier
c8dd20170e Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:11:31 +00:00