David Greene
1924aabf99
Move DebugInfo checks into EmitComments and remove them from
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target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 21:34:57 +00:00
David Goodwin
87d21b92fc
Allow target to specify regclass for which antideps will only be broken along the critical path.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 19:52:48 +00:00
Jim Grosbach
c1a07be185
Block renumbering
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 01:19:24 +00:00
Jim Grosbach
f4cbc0e421
use lower case for readability
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87054 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 01:17:22 +00:00
David Greene
b9c2fd964e
Make the MachineFunction argument of getFrameRegister const.
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This also fixes a build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 21:00:03 +00:00
David Greene
3f2bf85d14
Add a bool flag to StackObjects telling whether they reference spill
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slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 20:49:22 +00:00
Jim Grosbach
80697d1b26
Update TB[BH] layout optimization. Add support for moving the target block
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to directly follow the jump table. Move the layout changes to prior to any
constant island handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86999 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 17:25:07 +00:00
Evan Cheng
b9d2c03d20
Use table to separate opcode from operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:16:34 +00:00
Evan Cheng
06b53c0d51
isLegalICmpImmediate should take a signed integer; code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86964 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:13:11 +00:00
Jim Grosbach
01dec0e545
Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86945 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 03:28:35 +00:00
Evan Cheng
77e4751011
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86858 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:05:52 +00:00
Jim Grosbach
f4997e87e3
Do jump table adjustment before constant island allocation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86857 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:04:24 +00:00
Jim Grosbach
1fc7d715aa
The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
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can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86791 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 02:47:19 +00:00
Evan Cheng
4b6bbe1e9c
Change Thumb1 address mode printing, instead of
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[r0, #2 * 4]
Now
[r0, #8 ]
This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 19:48:13 +00:00
Evan Cheng
1e13c797e5
Add a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86706 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 19:44:56 +00:00
David Goodwin
c2e8a7e8d2
Fixed to address code review. No functional changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:48:55 +00:00
David Goodwin
0855dee564
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:15:47 +00:00
Jim Grosbach
803b48a155
Now that the default is 'enabled,' a separate command line option for ARM is
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not necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86621 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 23:11:45 +00:00
Jim Grosbach
92eb919e80
Enable dynamic stack realignment by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86604 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 22:32:40 +00:00
Jim Grosbach
ad353c74ad
Set dynamic stack realignment to real values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86602 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 22:32:03 +00:00
Jim Grosbach
43cca695a8
Work around assembler not recognizing #0.0 form immediate for vmcp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86548 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 15:27:51 +00:00
Jim Grosbach
e5165490b7
Use Unified Assembly Syntax for the ARM backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 00:11:35 +00:00
Jim Grosbach
31bc849123
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-08 00:27:19 +00:00
Evan Cheng
fdc834046e
Refactor code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-08 00:15:23 +00:00
Jim Grosbach
31c24bf5b3
80-column cleanup of file header comments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 22:00:39 +00:00
Jim Grosbach
8a5ec86a3d
Support alignment specifier for NEON vld/vst instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 21:25:39 +00:00
Evan Cheng
bf992817f2
t2ldrpci_pic can be used for blockaddress as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86400 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 19:40:04 +00:00
Chris Lattner
59a9178fbe
indicate what the native integer types for the target are.
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Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 19:07:32 +00:00
Anton Korobeynikov
e8ea011cc7
It turns out that the testcase in question uncovered subreg-handling bug.
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Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 15:20:32 +00:00
Jeffrey Yasskin
2d274412ed
Make the need-stub variables accurate and consistent. In the case of
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MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 08:51:52 +00:00
Evan Cheng
d457e6e9a5
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 04:04:34 +00:00
Evan Cheng
78e5c1140a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
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except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 03:52:02 +00:00
Ted Kremenek
b6aae88ac0
Update CMake file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86325 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 03:26:59 +00:00
Johnny Chen
0430152a11
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
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was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86319 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 00:54:36 +00:00
Jim Grosbach
bd79fc8ef2
80-columns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86310 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 00:13:30 +00:00
Evan Cheng
b9803a8fa6
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:52:48 +00:00
Anton Korobeynikov
fc2cba8362
Honour subreg machine operands during asmprinting
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:45:15 +00:00
Bob Wilson
54c78ef2fe
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
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will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:33:28 +00:00
Evan Cheng
e7e0d62efd
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 22:24:13 +00:00
Daniel Dunbar
2928c83b01
Pass StringRef by value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 10:58:06 +00:00
Dan Gohman
40c57860da
Factor out the printing of the leading tab into printInlineAsm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86199 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 00:04:54 +00:00
Dan Gohman
73bb251cd7
Remove uninteresting and confusing debug output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-05 18:47:09 +00:00
Jim Grosbach
4371cda7f8
Grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86068 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 23:20:40 +00:00
Jim Grosbach
db1751a922
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
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aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86064 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 23:11:07 +00:00
Jim Grosbach
6db06a0866
If a function has no stack frame at all, dynamic realignment isn't necessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 22:41:51 +00:00
Jim Grosbach
c5848f4ced
dynamic stack realignment necessitates scanning the floating point callee-
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saved instructions even if no stack adjustment for those saves is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 22:41:00 +00:00
Jakob Stoklund Olesen
ad68264f59
Print out an informative comment for KILL instructions.
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The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86041 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 19:24:37 +00:00
Evan Cheng
b9f51cbe98
The .n suffix must go after the predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 07:38:48 +00:00
Evan Cheng
7883fa942f
Use ldr.n to workaround a darwin assembler bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85980 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 00:00:39 +00:00
Evan Cheng
5a1cd36019
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 23:13:34 +00:00
Evan Cheng
b23b2015eb
fconsts / fconstd immediate should be proceeded with #.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 21:59:33 +00:00
Anton Korobeynikov
747409a290
Move subtarget check upper for NEON reg-reg fixup pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 18:46:11 +00:00
Evan Cheng
f6c0bffa8d
Trim unnecessary include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 07:08:08 +00:00
Bob Wilson
af14e663ac
For Thumb indirect branches, use "mov pc, reg" which does not switch
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between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 06:29:56 +00:00
Evan Cheng
ba908640b3
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 05:52:54 +00:00
Evan Cheng
b4db6a46e0
Clean up copyRegToReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85870 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 05:51:39 +00:00
Evan Cheng
3f4e47be0a
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 05:50:57 +00:00
Ted Kremenek
92dbd0b320
Update CMake file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85861 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 04:14:12 +00:00
Anton Korobeynikov
7aaf94bb0d
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 01:04:26 +00:00
Anton Korobeynikov
ab453e0641
Revert r85049, it is causing PR5367
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 00:24:48 +00:00
Bob Wilson
b62d257cf5
Revert previous change to a comment. The BlockAddresses go in the
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constant pool so they don't get wrapped separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 00:02:05 +00:00
Bob Wilson
907eebd5a6
Put BlockAddresses into ARM constant pools.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 20:59:23 +00:00
Kevin Enderby
60131c0d0b
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
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have been passed as a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85823 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 20:14:39 +00:00
David Goodwin
2f54a2fd85
Fix schedule model for BFC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 17:28:36 +00:00
Bob Wilson
31ba10b743
Hyphenate some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85808 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 17:10:37 +00:00
Bob Wilson
28989a8ddc
Add support for BlockAddress values in ARM constant pools.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85806 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 16:59:06 +00:00
Bob Wilson
69e8445ced
Prune unnecessary include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85805 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 16:58:31 +00:00
Evan Cheng
d3e18fad7e
These are done / no longer care.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 07:58:25 +00:00
Evan Cheng
e3b88fc01e
Add an entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85797 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 07:51:19 +00:00
Evan Cheng
7baae87d8f
Unbreak ARMBaseRegisterInfo::copyRegToReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 04:44:55 +00:00
Anton Korobeynikov
2ae0eec1c0
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:12:06 +00:00
Anton Korobeynikov
3a639a07ea
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
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PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:11:39 +00:00
Anton Korobeynikov
2e1da9fea4
64-bit FP loads & stores operate on both NEON and VFP pipelines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:11:06 +00:00
Anton Korobeynikov
f95215f551
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:10:38 +00:00
Evan Cheng
e3ce8aab0a
Fix a couple more places where we are creating ld / st instructions without memoperands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-01 22:04:35 +00:00
Evan Cheng
48d8afab73
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-01 21:12:51 +00:00
Evan Cheng
de17fb6e4d
Use cbz and cbnz instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 23:46:45 +00:00
Jim Grosbach
8cd0a8cb82
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
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them for scalar floating point operations for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:57:36 +00:00
Jim Grosbach
bcf2f2c159
Expand 64-bit logical shift right inline
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304
Expand 64-bit arithmetic shift right inline
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe
Expand 64 bit left shift inline rather than using the libcall. For now, this
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is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 19:38:01 +00:00
Evan Cheng
9eda68988e
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 03:39:36 +00:00
Kevin Enderby
9c41fa87ea
Updates to the ARM target assembler for llvm-mc per review comments from
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Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 22:55:57 +00:00
Bob Wilson
57f224a5a4
Add a note about Robert Muth's alternate jump table implementation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85624 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 22:22:46 +00:00
Bob Wilson
929ffa2414
Fix a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 20:13:25 +00:00
Rafael Espindola
c1382b745f
This fixes functions like
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void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 14:33:14 +00:00
Bob Wilson
ddb16df912
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 05:45:42 +00:00
Jim Grosbach
95d9504d46
Dial back the realignment a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 00:08:40 +00:00
Dan Gohman
533297b58d
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
Jim Grosbach
84e58d03c9
To get more thorough testing from llc-beta nightly runs, do dynamic stack
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realignment regardless of whether it's strictly necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 02:41:21 +00:00
Bob Wilson
a597103c32
Revert r85346 change to control tail merging by CodeGenOpt::Level.
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I'm going to redo this using the OptimizeForSize function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 20:46:46 +00:00
Bob Wilson
8d4de5abfa
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 18:26:41 +00:00
Evan Cheng
30c80211b6
fconsts and fconstd are obviously re-materializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 18:19:56 +00:00
Jim Grosbach
ca5dfb71ba
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 17:33:28 +00:00
Evan Cheng
c59420867e
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 06:55:03 +00:00
Evan Cheng
39382427f1
Use fconsts and fconstd to materialize small fp constants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 01:44:26 +00:00
Bob Wilson
04ea6e5150
Add an indirect branch pattern for ARM. Testcase will be coming soon.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 00:37:03 +00:00
Bob Wilson
cd4f04d6bc
Record CodeGen optimization level in the BranchFolding pass so that we can
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use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 23:49:38 +00:00
Jim Grosbach
a6a99b4e16
Enable virtual register based frame index scavenging by default for ARM & T2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 22:52:29 +00:00
Jim Grosbach
3dab277857
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
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default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 22:45:39 +00:00
Johnny Chen
90d7dcfdd9
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 20:51:49 +00:00
Johnny Chen
eadeffb306
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
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BL_pred and BLr9_pred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 20:45:15 +00:00
Bob Wilson
f3b0d1a555
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
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instruction format that already takes care of setting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 19:52:03 +00:00
Johnny Chen
76b39e88e4
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
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for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 18:44:24 +00:00
Johnny Chen
6a3b5eec89
Test commit. Added '.' to the comment line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 17:25:15 +00:00
Rafael Espindola
f87611272b
Correctly align double arguments in the stack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 14:09:44 +00:00
Evan Cheng
dd22a45acc
Now VFP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 00:20:49 +00:00
Evan Cheng
699bebac4f
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 00:08:59 +00:00
Evan Cheng
162e30921d
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 23:45:59 +00:00
Bob Wilson
dda9583e51
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
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bits. Johnny, please review -- I do not have a good track record of getting
these right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 22:59:12 +00:00
Bob Wilson
d9ecd3108f
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 22:42:13 +00:00
Bob Wilson
7e053bb33c
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
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bits. Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 22:34:44 +00:00
David Goodwin
2e7be612d5
Break anti-dependence breaking out into its own class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 16:59:04 +00:00
Jim Grosbach
dd5694203b
of -> or
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 19:14:48 +00:00
Jim Grosbach
f639e9f9e6
80-column cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 18:55:46 +00:00
Evan Cheng
4f54c1293a
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 07:53:28 +00:00
Evan Cheng
ed3ad212ec
Don't forget subreg indices when folding load / store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 07:52:27 +00:00
Nick Lewycky
f5a86f45e7
Remove includes of Support/Compiler.h that are no longer needed after the
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VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 06:57:41 +00:00
Nick Lewycky
6726b6d75a
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
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Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 06:33:48 +00:00
Evan Cheng
5a850beb2e
80 col violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-24 02:07:42 +00:00
Jim Grosbach
2f1abe2dae
Restrict Thumb1 register allocation to low registers, even for instructions that
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can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-24 00:19:24 +00:00
Jim Grosbach
7388037dd1
FIXME no longer applies. R12 and R3 are available for allocation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-23 23:07:42 +00:00
David Goodwin
4c3715c2e5
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 23:19:17 +00:00
Bob Wilson
bac6ed4ba4
Revert 84843. Evan, this was breaking some of the if-conversion tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 16:52:21 +00:00
Evan Cheng
87689d3b70
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 06:48:32 +00:00
Evan Cheng
faf93aa233
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 06:47:35 +00:00
Evan Cheng
62d1723a9c
Trim more includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 05:11:00 +00:00
Evan Cheng
268c79350e
Trim include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 05:08:49 +00:00
Evan Cheng
8000c6c535
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 00:40:00 +00:00
Jim Grosbach
41fff8c19a
Missing piece of the ARM frame index post-scavenging conditionalization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 23:40:56 +00:00
Jim Grosbach
1d6827bbe9
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
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for a few bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 22:59:24 +00:00
Bob Wilson
20d108140e
Most of the NEON shuffle instructions do not support 64-bit element types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 21:36:27 +00:00
Jim Grosbach
65b7f3af76
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
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immediate operands when they will fit into the using instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 20:44:34 +00:00
Bob Wilson
b27b51aaa6
Fix NEON VST2LN instruction encoding.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 17:54:01 +00:00
Bob Wilson
407d57489f
Revert 84732. It was the wrong fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 17:52:34 +00:00
Evan Cheng
2095659a85
Match more patterns to movt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 08:15:52 +00:00
Chris Lattner
1ce75ef5ef
tidy
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 04:10:24 +00:00
Bob Wilson
b3c8359360
Fix some more NEON instruction encoding problems.
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Thanks to Johnny Chen for discovering the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 02:27:20 +00:00
Bob Wilson
507df402b0
Leave some NEON instruction encoding bits unspecified instead of setting
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a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 02:15:46 +00:00
Daniel Dunbar
a7cc65283a
Fix -Asserts warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 22:10:05 +00:00
Jim Grosbach
3229b0bcf1
Disable by default while debugging
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 20:31:31 +00:00
Jim Grosbach
18ed9c9a2b
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 20:19:50 +00:00
Benjamin Kramer
174101e13a
Random #include pruning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 11:44:38 +00:00
Chris Lattner
235e2f6a68
implement some more easy hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 06:22:33 +00:00
Chris Lattner
bf16faa16a
Implement some hooks, make printOperand abort if unknown modifiers are
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present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84613 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 06:15:28 +00:00
Chris Lattner
c6b8a99207
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84611 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 05:58:02 +00:00
Daniel Dunbar
2685a29a8d
Wire up the ARM MCInst printer, for llvm-mc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 05:15:36 +00:00
Jim Grosbach
8fa4efeabf
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
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functions are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:32:47 +00:00
Jim Grosbach
7e831db1d4
Enable post-pass frame index register scavenging for ARM and Thumb2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:26:58 +00:00
Chris Lattner
161dcbf799
lower ARM::MOVi32imm properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84583 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:11:37 +00:00
Chris Lattner
292df8eb1f
add support for external symbols. The mc instprinter can now handle
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reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84582 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:56:16 +00:00
Chris Lattner
96bc2173bb
get fancy: support basic block operands. Yay for jumps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84579 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:52:47 +00:00
Chris Lattner
233917c072
add supprort for the 'sbit' operand, MOVi apparently has one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:46:11 +00:00
Chris Lattner
413ae25fb5
add support for instruction predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84575 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:42:49 +00:00
Chris Lattner
017d9478d5
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:40:56 +00:00
Jim Grosbach
1fc1dc0682
Refs: A8-598.
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Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:38:19 +00:00
Jim Grosbach
780d207d1c
Add missing encoding bits to NLdSt class of instructions.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:19:08 +00:00
Chris Lattner
306d14f9aa
handle addmode4 modifiers, fix a fixme in printRegisterList
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by ignoring all implicit regs when lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 23:31:43 +00:00
Jim Grosbach
6009751244
Enable allocation of R3 in Thumb1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:57:03 +00:00
Chris Lattner
5a207897bc
use EmitLabel instead of text emission
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:51:16 +00:00
Chris Lattner
7c5b021793
add a twine version of MCContext::GetOrCreateSymbol.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:49:00 +00:00
Chris Lattner
a70e644820
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
...
like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:33:05 +00:00
Jim Grosbach
d482f55af1
Adjust the scavenge register spilling to allow the target to choose an
...
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:27:30 +00:00
Chris Lattner
4d15222341
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84553 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:23:04 +00:00
Chris Lattner
e306d8d6cc
add register list and hacked up addrmode #4 support, we now get this:
...
_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84546 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:09:23 +00:00
Chris Lattner
084f87d445
add addrmode2 support, getting us up to:
...
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:57:05 +00:00
Chris Lattner
6f99776f6c
add jump tables, constant pools and some trivial global
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lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84542 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:53:00 +00:00
Chris Lattner
8514e21deb
reduce #includes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:23:15 +00:00
Chris Lattner
61d35c273e
add printing support for SOImm operands, getting us to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:21:39 +00:00
Chris Lattner
8bc86cba60
wire up some basic printOperand goodness, giving us stuff like this before
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we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84532 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 20:59:55 +00:00
Chris Lattner
9cf0eb5e58
add the files that go with the previous rev
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84531 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 20:21:05 +00:00
Chris Lattner
97f0693744
wire up skeletal support for having llc print instructions
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through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 20:20:46 +00:00
Chris Lattner
6a71afaec1
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
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"something" when printing MCInsts, it will just be missing all the
operand info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84528 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 19:59:05 +00:00
Chris Lattner
fd60382e75
stub out a minimal ARMInstPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84527 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 19:56:26 +00:00
Chris Lattner
b8f64a72d8
simplify code, reducing string thrashing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:49:14 +00:00
Chris Lattner
e4d9ea83c0
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:44:38 +00:00
Chris Lattner
b0f294c14b
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84519 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:38:33 +00:00
Chris Lattner
ee8b32981e
remove dead map
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:11:25 +00:00
Chris Lattner
a10343f039
don't bother trying to avoid emitting redundant constant pool alignment directives.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:08:02 +00:00
Chris Lattner
74cd3b7ceb
emit .subsections_via_symbols through MCStreamer instead of textually.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84509 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:03:08 +00:00
Chris Lattner
4a071d667d
cleanup doFinalization -> EmitEndOfAsmFile.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 17:59:19 +00:00
Evan Cheng
ff89dcb06f
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 18:16:27 +00:00
Evan Cheng
491f54f1fd
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84326 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17 09:20:14 +00:00
Evan Cheng
6553155172
Revert 84315 for now. Re-thinking the patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17 07:53:04 +00:00
Evan Cheng
bf125583f8
Rename getFixedStack to getStackObject. The stack objects represented are not
...
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17 06:22:26 +00:00
Evan Cheng
fa16354e03
Change createPostRAScheduler so it can be turned off at llc -O1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 21:06:15 +00:00
Evan Cheng
b46aea1032
I am no spelling bee.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84250 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:18:09 +00:00
Evan Cheng
d3dd50fec0
Enable post-alloc scheduling for all ARM variants except for Thumb1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:11:08 +00:00
Evan Cheng
fee0c1074c
Add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84246 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 05:33:58 +00:00
Bob Wilson
1dd4348408
Fix more NEON instruction encodings.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84243 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 03:58:44 +00:00
Bob Wilson
934f98b536
Revert svn r80498 and replace it with a different solution. The only problem
...
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 23:12:05 +00:00
Sandeep Patel
452b54a8ae
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 22:25:32 +00:00
Bob Wilson
6f122625dd
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
...
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84206 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 21:57:47 +00:00
Kevin Enderby
e2a98dd2a4
Fix ARM memory operand parsing of post indexing with just a base register, that
...
is just "[Rn]" and no tailing comma with an offset, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84205 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 21:42:45 +00:00
Bob Wilson
b923953733
Fix a potential performance problem in placing ARM constant pools.
...
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references. This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84202 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 20:49:47 +00:00
Kevin Enderby
515d509360
More bits of the ARM target assembler for llvm-mc, code added to parse labels
...
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these). Some clean up of the operand parsing code
and adding some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 20:48:48 +00:00
Bob Wilson
549dda9d82
Be smarter about reusing constant pool entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84173 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 05:52:29 +00:00
Bob Wilson
36fa5321ba
Fix another problem with ARM constant pools. Radar 7303551.
...
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them. My recent change exposed a problem in this area. We may
sometimes append to the same block more than one unconditional branch. The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.
This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before. The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block. The insertion point could be out of range. When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.
The fix is to only append an unconditional branch if the block does not
already end with one. I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.
There is more to be done here, but I think this fixes the immediate problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84172 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 05:10:36 +00:00
Bob Wilson
b3642dccee
Fix instruction encoding bits for NEON VPADAL.
...
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84146 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 21:43:17 +00:00
Bob Wilson
681a2ad403
Remove unused variables to fix build warning.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 21:40:45 +00:00
Jim Grosbach
b9d319b585
Inst{11-8} for vshl should be 0b0101, not 0b1111.
...
Refs: A7-17 & A8-750.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84131 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 20:31:01 +00:00
Bob Wilson
8e86b5195b
Set instruction encoding bits 4 and 7 for ARM register-register and
...
register-shifted-register instructions. Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84124 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 19:00:24 +00:00
Bob Wilson
24f995d84b
Refactor code to select NEON VST intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 18:32:29 +00:00
Bob Wilson
3e36f13ba7
Refactor code to select NEON VLD intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84117 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 17:28:52 +00:00
Bob Wilson
9649344cb5
More refactoring. NEON vst lane intrinsics can share almost all the code for
...
vld lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84110 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 16:46:45 +00:00
Bob Wilson
a7c397c9c3
Refactor code for selecting NEON load lane intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84109 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-14 16:19:03 +00:00
Kevin Enderby
079469f649
Correct comment about ARM immediates using '#' not '$' and TODO for modifiers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84055 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 23:33:38 +00:00
Bob Wilson
e72142aa5b
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
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by creating TargetConstants during instruction selection instead of during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 22:29:24 +00:00
Kevin Enderby
cfe0724016
More bits of the ARM target assembler for llvm-mc to parse immediates.
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Also fixed a couple of coding style things that crept in. And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84040 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 22:19:02 +00:00
Bob Wilson
73d64a6fd3
NEON VLD/VST are now fully implemented. For operations that expand to
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multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 21:55:24 +00:00
Bob Wilson
765cc0b9d5
Revise ARM inline assembly memory operands to require the memory address to
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be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 20:50:28 +00:00
Sandeep Patel
4e1ed88026
Fix method name in comment, per Bob Wilson.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84017 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 20:25:58 +00:00
Sandeep Patel
47eedaa8fa
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 18:59:48 +00:00
Bob Wilson
5361cd2c7d
Add some ARM instruction encoding bits.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83983 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 17:35:30 +00:00
Bob Wilson
4796ba2e70
Fix regression introduced by r83894.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 17:29:13 +00:00
Bob Wilson
a7fcb9b840
Fix a tab. Thanks to Johnny Chen for pointing it out.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83973 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 15:27:23 +00:00
Kevin Enderby
6bd266e567
Fix two warnings about unused variables that are only used in assert() calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 22:51:49 +00:00
Bob Wilson
af4b735219
Delete a comment that makes no sense to me. The statement that moving a CPE
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before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb. Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83916 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 22:49:05 +00:00
Kevin Enderby
9d36962ab6
Fix a problem in the code where ARMAsmParser::ParseShift() second argument
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should have been a pointer to a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83915 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 22:39:54 +00:00
Bob Wilson
757652c5ba
Change CreateNewWater method to return NewMBB by reference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83905 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 21:39:43 +00:00
Bob Wilson
f98032ef64
Last week, ARMConstantIslandPass was failing to converge for the
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MultiSource/Benchmarks/MiBench/automotive-susan test. The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now. Radar 7291928.
The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it. There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code. The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range. On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted. The second CPE had
been in range but the newly inserted entry pushed it too far away. Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range. Etc.
Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references. In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs. This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it. This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs. This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.
To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion. The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses. This is a very simple change to the code and should not cause
any significant degradation in the results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 21:23:15 +00:00
Bob Wilson
32c50e8f99
Another minor clean-up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 20:45:53 +00:00
Bob Wilson
d637c1a495
Remove redundant parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 20:37:23 +00:00
Bob Wilson
3b7573517c
Use early exit to reduce indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 19:04:03 +00:00
Bob Wilson
9d16f2c0ba
Change to return a value by reference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83873 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 19:01:12 +00:00
Bob Wilson
034de5f65f
Add a typedef for an iterator.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83872 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 18:52:13 +00:00
Dan Gohman
59ac57153b
Mark the LDR instruction with isReMaterializable, as it is rematerializable
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when loading from an invariant memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83688 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 23:28:27 +00:00
Kevin Enderby
d7894f105a
Added another bit of the ARM target assembler to llvm-mc to parse register
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lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers. Also added the
rest of the arm register names to the currently hacked up version to allow more
testing. Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 21:12:28 +00:00
Bob Wilson
5631139a69
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 00:01:36 +00:00
Bob Wilson
8cdb269686
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 23:51:31 +00:00
Bob Wilson
c5c6edb74f
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 23:38:24 +00:00
Bob Wilson
62e053e5a1
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 22:53:57 +00:00
Bob Wilson
0bf7d998b4
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 22:27:33 +00:00
Anton Korobeynikov
632606c724
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 20:43:22 +00:00
Bob Wilson
30aea9d96e
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 18:56:10 +00:00
Bob Wilson
cd7e327cdf
Clean up some unnecessary initializations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83566 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 18:52:56 +00:00
Bob Wilson
af4a891273
Clean up a comment (indentation was wrong).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 18:51:31 +00:00
Bob Wilson
deb3141cf5
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 05:18:18 +00:00
Jim Grosbach
1f30dcbd8d
Cleanup up unused R3LiveIn tracking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 01:50:26 +00:00
Jim Grosbach
65c58daa8b
Re-enable register scavenging in Thumb1 by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 01:46:59 +00:00
Bob Wilson
5adf60c03b
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 00:21:01 +00:00
Bob Wilson
0ea38bb939
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:54:04 +00:00
Bob Wilson
c67160c010
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:57:01 +00:00
Jim Grosbach
9f3a559dff
reverting thumb1 scavenging default due to test failure while I figure out what's up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:49:41 +00:00
Jim Grosbach
ec1434dd89
Enable thumb1 register scavenging by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:26:14 +00:00
Bob Wilson
b07c171624
Add some instruction encoding bits for NEON load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 21:53:04 +00:00
Bob Wilson
63c9063434
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:30:08 +00:00