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15328 Commits

Author SHA1 Message Date
Chris Lattner
c06cbad141 some notes about suboptimal insertps's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107613 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 05:48:41 +00:00
Chris Lattner
a5b412581c rip out even more sporadic v2f32 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 04:38:33 +00:00
Chris Lattner
39aa20a981 rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 04:36:27 +00:00
Chris Lattner
f172ecd964 Just rip v2f32 support completely out of the X86 backend. In 
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 23:07:25 +00:00
Chris Lattner
e35d9842f7 fix PR7518 - terrible codegen of <2 x float>, by only marking 
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 22:57:10 +00:00
Chris Lattner
9d19989fe3 indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107599 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 22:56:10 +00:00
Bill Wendling
f43f6bc3ec Revert r107583. I no longer think that this is the way to solve the problem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 09:16:57 +00:00
Bill Wendling
4a991a6fa6 Mark sse_load_f32 and sse_load_f64 as having memory operands 
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 08:59:55 +00:00
Eli Friedman
b482829abb Minor amendment to switch-lowering improvement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107569 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 08:43:32 +00:00
Eli Friedman
b4a74c1d82 Note switch-lowering inefficiency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes
68b559e5f3 Add AVX SSE4.1 blend, mpsadbw and vdp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:49:21 +00:00
Evan Cheng
ed2ae136d2 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
2c70d4ad35 Add AVX SSE4.1 round instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
03560600b4 Simple refactoring of SSE4.1 instructions, making room for the AVX forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
f5cd8c51e3 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 22:06:54 +00:00
Evan Cheng
dca653951c Remove early IT block formation. It's not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 21:07:09 +00:00
Evan Cheng
98ec91ea80 - Two-address pass should not assume unfolding is always successful. 
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 20:36:18 +00:00
Gabor Greif
135d7fe9bb beautify output 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107500 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 19:26:28 +00:00
Gabor Greif
53ba550df1 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107498 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 19:08:46 +00:00
Bob Wilson
e45f72c833 Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so 
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 17:23:44 +00:00
Gabor Greif
9d135f0ba5 use ArgOperand API (found by my previous commit) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 13:37:16 +00:00
Bruno Cardoso Lopes
f12ad66741 Shrink down SSE3 code by more multiclass refactoring 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
944facac2e Shrink down SSE3 code by some multiclass refactoring - 1st part 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 22:33:18 +00:00
Bob Wilson
b5b5057a70 ARM function alignments were off by a power of two. svn 83242 changed 
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 22:26:26 +00:00
Bill Wendling
5e721d7682 Implement the "linker_private_weak" linkage type. This will be used for 
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.

For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:

      .globl l_objc_msgSend_fixup_alloc
      .weak_definition l_objc_msgSend_fixup_alloc
      .section __DATA, __objc_msgrefs, coalesced
      .align 3
l_objc_msgSend_fixup_alloc:
       .quad   _objc_msgSend_fixup
       .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

Currently only supported on Darwin platforms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 21:55:59 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9 Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61 Add AVX SSE3 packed addsub instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:08:18 +00:00
Dan Gohman
20d4be151b Enable on-demand fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:57 +00:00
Dan Gohman
abd1d859b3 Fix X86FastISel's add folding to actually work, and not fall back 
to SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
79b634c244 Add AVX SSE3 replicate and convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:33:39 +00:00
Dan Gohman
5c87bf64d6 Teach X86FastISel to fold constant offsets and scaled indices in 
the same address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
6596a62076 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a Move MOVD/MODQ code around, creating sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150 Add AVX SSE2 mask creation and conditional store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20 Add AVX SSE2 packed integer extract/insert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 17:03:03 +00:00
Gabor Greif
e1c2b9cc3d use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
876085dcfa Add AVX SSE2 integer unpack instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae Add AVX SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd Small refactoring of SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2 Add AVX SSE2 pack with saturation integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c Add AVX SSE2 integer packed compare instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716 Add *several* AVX integer packed binop instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 23:47:49 +00:00
Bill Wendling
07d3177117 Revert r107205 and r107207. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:34:52 +00:00
Eric Christopher
33634d0672 Add another bswap idiom that isn't matched. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:22:22 +00:00
Bruno Cardoso Lopes
2c818072cc Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e Add AVX Move Aligned/Unaligned packed integers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 21:25:12 +00:00
Bill Wendling
207855cff9 Introducing the "linker_weak" linkage type. This will be used for Objective-C 
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 21:24:00 +00:00
Bruno Cardoso Lopes
147b7cad2f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:35:48 +00:00
Bob Wilson
21773e716f Add support for encoding VDUP (ARM core register) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:13:29 +00:00
Bruno Cardoso Lopes
721ef73d88 Add AVX non-temporal stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb Move non-temporal movs to their own section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:42:37 +00:00
Bob Wilson
d5a563de07 Add support for encoding NEON VMOV (from core register to scalar) instructions. 
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:34:07 +00:00
Bruno Cardoso Lopes
ea86423cbd Add sqrt, rsqrt and rcp AVX instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:26:30 +00:00
Jim Grosbach
077f1bfa91 skip dbg_value instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 16:55:24 +00:00
Bob Wilson
1ab38469df The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add 
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 16:25:11 +00:00
Rafael Espindola
d31f972bd3 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses 
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 14:02:34 +00:00
Duncan Sands
31a3a3ebaf Remove pointless variable LastDef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:23:22 +00:00
Duncan Sands
58c86910b3 Remove unused variable Loc and pointless variables unified_syntax 
and thumb_mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:04:35 +00:00
Duncan Sands
978189e090 Remove an unused and a pointless variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 13:00:29 +00:00
Duncan Sands
78337b4d4d Remove pointless and unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 12:48:49 +00:00
Duncan Sands
90c64f4aac Remove initialized but otherwise unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 11:22:26 +00:00
Evan Cheng
c36b5b9730 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:38:36 +00:00
Evan Cheng
c170f66742 Change if-cvt options to something that actually as useable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 05:37:59 +00:00
Bruno Cardoso Lopes
b22dc70a5c Refactoring of arithmetic instruction classes with unary operator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:33:09 +00:00
Jakob Stoklund Olesen
628a79771b When no memoperands are present, assume unaligned, volatile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:13:07 +00:00
Bruno Cardoso Lopes
4548260ab5 Described the missing AVX forms of SSE2 convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:36:02 +00:00
Bob Wilson
5cdede43e9 Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is 
the same as ARM except that the condition code field is always set to ARMCC::AL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:26:13 +00:00
Bob Wilson
62d24a4b92 Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead 
of the Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 22:23:17 +00:00
Jim Grosbach
e89c5e57cc tidy up style. no functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:29:17 +00:00
Bob Wilson
08baddbc07 Refactor encoding function for NEON 1-register with modified immediate format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:16:30 +00:00
Bob Wilson
d896a97dc7 Support Thumb mode encoding of NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:12:19 +00:00
Bill Wendling
c25ccf85e5 Reduce indentation via early exit. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:08:32 +00:00
Jim Grosbach
e9e3f20ffb minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 04:27:01 +00:00
Gabor Greif
7a1d92a2cb use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106946 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 12:17:21 +00:00
Gabor Greif
6bec14fea0 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 12:09:10 +00:00
Gabor Greif
1cfe44a460 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 11:51:52 +00:00
Eli Friedman
a2c6f457a4 Followup to r106770: actually generate SXTB and SXTH for sign-extensions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 04:36:50 +00:00
Bob Wilson
52e4a0a074 Add support for encoding NEON VMOV (from scalar to core register) instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 04:07:15 +00:00
Evan Cheng
f6799394d5 It's now possible to run code placement pass for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 01:52:05 +00:00
Jakob Stoklund Olesen
4f5d84e4ad When creating X86 MUL8 and DIV8 instructions, make sure we don't produce 
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:39:23 +00:00
Bob Wilson
80d9bc0336 Renumber NEON instruction formats to be consecutive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:05:09 +00:00
Bob Wilson
184723d9be Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to 
"N..." instead of "NEON..." for consistency with the other NEON format names.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:56:05 +00:00
Bruno Cardoso Lopes
bdffc16d65 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:47:23 +00:00
Bob Wilson
2653263165 Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. 
Renumber MiscFrm to 25.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:45:37 +00:00
Bruno Cardoso Lopes
161476ec34 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:33:42 +00:00
Daniel Dunbar
e39e06af38 Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was 
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:14:54 +00:00
Bruno Cardoso Lopes
95325b08a3 revert this now, it's using avx instead of sse :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:04:29 +00:00
Evan Cheng
13151432ed Change if-conversion block size limit checks to add some flexibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:42:03 +00:00
Bob Wilson
5e7b607f72 Add support for encoding 3-register NEON instructions, and fix 
emitNEON2RegInstruction's handling of 2-address operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:40:46 +00:00
Bruno Cardoso Lopes
544a95d716 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:27:51 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:55:36 +00:00
Bob Wilson
583a2a0615 Add support for encoding 2-register NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:17:19 +00:00
Dan Gohman
ca5b8553ea pcmpeqd and friends are Commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:05:35 +00:00
Bob Wilson
8c605c601d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:54:44 +00:00
Bill Wendling
730c07e50d - Reapply r106066 now that the bzip2 build regression has been fixed. 
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
39afa908de Move the last piece of SSE2 convert instructions to the Convert Instructions section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4 More SSE refactoring, this time with different types of MOVs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:22:12 +00:00
Jim Grosbach
57bb394803 IT instructions are considered to be scheduling hazards, but are scheduled 
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.

Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:43:14 +00:00
Bruno Cardoso Lopes
0491e132fc Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:06:22 +00:00
Bob Wilson
ade57fa619 Add missing ARM and Thumb data layout info for vector types. 
Radar 8128745.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 04:41:08 +00:00
Bob Wilson
86fe66db3a Reduce indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 04:12:31 +00:00
Bruno Cardoso Lopes
a0ae87fd5d Add some AVX convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727 Refactoring of SSE convert intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792 Refactoring of SSE conversion instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
e0c437333e Refactor SSE cmp intrinsics and declare the same for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
788184365a - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 20:48:23 +00:00
Dale Johannesen
e5ff9ef195 Disallow matching "i" constraint to symbol addresses when 
address requires a register or secondary load to compute
(most PIC modes).  This improves "g" constraint handling.  8015842.

The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously.  Fixed to use Linux x86-64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 20:14:51 +00:00
Evan Cheng
8acf67672b Oops. IT block formation pass needs to be run at any optimization level. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 19:10:14 +00:00
Eli Friedman
761fa7af9e Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f PR7458: Try commuting Thumb2 instruction operands to put them into 2-address 
form so they can be narrowed to 16-bit instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 16:50:20 +00:00
Dan Gohman
4e39e9da0f Reapply r106634, now that the bug it exposed is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 14:30:44 +00:00
Chris Lattner
645b209c4a Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:29:18 +00:00
Chris Lattner
adabe1a92c more cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106724 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:18:14 +00:00
Chris Lattner
02758a44e4 reduce indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:16:25 +00:00
Chris Lattner
f8cbde46fb fix breakage from r98938 by correctly marking msp430 calls as variadic. 
Patch by Ben Ransford!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 06:46:50 +00:00
Dan Gohman
6b13cbca61 Fix a bug in the code which determines when it's safe to use the 
bt instruction, which was exposed by r106263.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106718 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 02:07:59 +00:00
Eric Christopher
37106afe02 Add a couple more quick comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 02:07:57 +00:00
Devang Patel
e9916a302f Use ValueMap instead of DenseMap. 
The ValueMapper used by various cloning utility maps MDNodes also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106706 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:33:28 +00:00
Bruno Cardoso Lopes
6539dc6e6c Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
34a491bd8e Move SSE and AVX shuffle, unpack and compare code to more appropriate places 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:15:50 +00:00
Bill Wendling
4b722108e2 We are missing opportunites to use ldm. Take code like this: 
void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 23:00:16 +00:00
Bruno Cardoso Lopes
e93e300ad0 Add AVX MOVMSK{PS,PD}rr instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818 Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 21:10:57 +00:00
Eric Christopher
749bb7e2d9 Update according to feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:49:35 +00:00
Bruno Cardoso Lopes
7dbfd07e32 Add AVX SHUF{PS,PD}{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:07:15 +00:00
Nico Weber
50b9efc2a8 Add support for the x86 instructions "pusha" and "popa". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:00:58 +00:00
Dale Johannesen
e39fdbe118 Do not do tail calls to external symbols. If the 
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 18:52:34 +00:00
Daniel Dunbar
cbe762b5d1 Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 17:09:26 +00:00
Jim Grosbach
f1ab49e83a The generic DAG combiner can now fold atomic fences when needed, so switch 
to using that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 16:25:07 +00:00
Jim Grosbach
5def57aaf4 When using libcall expansions for the atomic intrinsics, the explicit 
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 16:08:49 +00:00
Eric Christopher
18ebf74781 Update uses, defs, and comments for darwin tls patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 08:01:49 +00:00
Daniel Dunbar
d24c9d5f91 Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang. 
Conflicts:

	lib/CodeGen/MachineSink.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 00:48:25 +00:00
Bruno Cardoso Lopes
62a76c6401 Add AVX compare packed instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b Reapply support for AVX unpack and interleave instructions, with 
testcases this time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c Add AVX MOV{SS,SD}{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:38:56 +00:00
Bill Wendling
19d8597bca Fix the formatting of the switch statement and add a missing break. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:16:17 +00:00
Bob Wilson
a3a204664d Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. 
Radar 8031193.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:04:24 +00:00
Jim Grosbach
dd11ee2273 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 20:52:02 +00:00
Bruno Cardoso Lopes
d3a067bbc2 Reorganize logical and arithmetic SSE 1 & 2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 18:17:40 +00:00
Bruno Cardoso Lopes
f23919b3e9 Reorganize SSE instructions, making easier to see oportunities for refactoring 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106556 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 18:09:32 +00:00
Dan Gohman
fe60104ac9 Use pre-increment instead of post-increment when the result is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 15:08:57 +00:00
Evan Cheng
4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 01:18:16 +00:00
Chris Lattner
ceea301c1d make sure to initialize indent_level 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 00:40:26 +00:00
Chris Lattner
3284877064 add some support for blockaddress. This isn't really enough to be useful, 
but it will cover uses of blockaddress that are actually in a function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106502 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 23:19:36 +00:00
Chris Lattner
1018c24c13 eliminate a mutable global variable, use raw_ostream::indent instead of 
rolling our own.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 23:14:47 +00:00
Chris Lattner
7e6d7451ae un-indent a huge amount of code out of an anonymous namespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106500 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 23:12:56 +00:00
Bruno Cardoso Lopes
c27d1e4d17 revert r106482 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106499 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 22:59:03 +00:00
Bruno Cardoso Lopes
b7cc3f6ae6 change parameter name to avoid confusion with global definition 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:28:07 +00:00
Bob Wilson
56a1a69a35 sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. 
Radar 8104310.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:34 +00:00
Jim Grosbach
a967d1121a LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:27 +00:00
Bruno Cardoso Lopes
b44e8b2d11 Add unpack and interleave AVX instructions, encoding tests cooming soon 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:48 +00:00
Evan Cheng
d95ea2da28 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:14 +00:00
Eric Christopher
be4e066ff9 Remove isTwoAddress from SystemZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:25:57 +00:00
Eric Christopher
c63a404d56 Remove isTwoAddress from Sparc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:22:35 +00:00
Eric Christopher
c452d79c43 Remove isTwoAddress from Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:19:21 +00:00
Eric Christopher
b82a7ea1b2 Remove isTwoAddress from Blackfin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:13:37 +00:00
Eric Christopher
f704408bf7 Remove isTwoAddress from MSP430. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:07:30 +00:00
Eric Christopher
658ebcc7ec Make 80-column. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:56:55 +00:00
Eric Christopher
90301312d5 Remove isTwoAddress from PIC16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:55:01 +00:00
Eric Christopher
4a232f0836 Remove isTwoAddress from XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106446 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:51:38 +00:00
Eric Christopher
23265d0054 Remove isTwoAddress from Alpha. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106445 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:48:55 +00:00
Bruno Cardoso Lopes
c79e43aee3 Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:36:04 +00:00
Bruno Cardoso Lopes
59bb6fae9a Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106436 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:22:54 +00:00
Dale Johannesen
b0ccb757b3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:21:49 +00:00
Eric Christopher
18fb00b4b9 Add some codegen patterns for x86_64-linux-gnu tls codegen matching. 
Based on a patch by Patrick Marlier!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:21:27 +00:00
Jim Grosbach
9cfcfeb24b early exit for dbg_value instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 17:49:23 +00:00
Chris Lattner
9e13715fd5 remove some dead variables reported by clang++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 17:20:18 +00:00
Kalle Raiskila
951b229ccf Mark the SPU 'lr' instruction to never have side effects. 
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 15:08:16 +00:00
Kalle Raiskila
91fdee125c Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 14:42:19 +00:00
Rafael Espindola
c2b3e00cdf Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch. 
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 13:31:32 +00:00
Kalle Raiskila
4794807134 Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm 
used to choke llc with the attached test.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 10:17:36 +00:00
Rafael Espindola
f0efafa61e wip 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 02:17:34 +00:00
Nick Lewycky
2a3ee5e8e9 Fix warning in no-asserts build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 20:27:42 +00:00
Evan Cheng
859df5e9f9 Fix a crash caused by dereference of MBB.end(). rdar://8110842 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 00:54:38 +00:00
Bob Wilson
31ef8e6663 Remove a fixme comment that is no longer relevant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 05:32:41 +00:00
Bob Wilson
dc076da4d2 Fix error message to match function name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 05:32:09 +00:00
Bruno Cardoso Lopes
f6ff003043 Refactoring of regular logical packed instructions to prepare for AVX ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
f4f4bad696 Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 02:44:01 +00:00
Evan Cheng
02ba9e19c7 Ignore dbg_value's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 02:36:21 +00:00
Bruno Cardoso Lopes
1e8d06282f Move new sse 1 & 2 generic classes to a more appropriate place 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
efc9b69deb Remove unnecessary arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
17227db062 Add AVX packed intrinsics for MIN, MAX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:17:05 +00:00
Evan Cheng
0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:01:32 +00:00
Eric Christopher
a938cfb13a Finish ripping isTwoAddress out of X86. Some mindless formatting 
and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:37:40 +00:00
Bruno Cardoso Lopes
be4d595afd Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:37:31 +00:00
Chris Lattner
617e595022 rip out dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:34:14 +00:00
Chris Lattner
1cf44fc051 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:34:00 +00:00
Evan Cheng
6523d2ff7f Indentation and remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:11:54 +00:00
Bruno Cardoso Lopes
fda1acb389 Clean up: remove now unnecessary Constraints 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106361 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:09:27 +00:00
Dan Gohman
9559e3b99a Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:02:06 +00:00
Bruno Cardoso Lopes
c82f199892 more refactoring! yay! big win over the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:00:22 +00:00
Eric Christopher
96ab7f494d Remove isTwoAddress from here too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
ccf30bd984 Fix typo, SSE1 should be used by XS, not SSE2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:53:27 +00:00
Eric Christopher
f6bc0b9d4b Remove isTwoAddress from 64-bit files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:51:21 +00:00
Evan Cheng
96c3da6436 Move ARM if-conversion before post-ra scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:32:07 +00:00
Dan Gohman
db4971259c Teach regular and fast isel to set dead flags on unused implicit defs 
on calls and similar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
8af5ed9e15 Apply some refactor to packed instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:13:35 +00:00
Evan Cheng
3ee608c5aa Update cmake list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:12:10 +00:00
Evan Cheng
886459456c Thumb2 hazard recognizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:11:35 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:09:54 +00:00
Jim Grosbach
ef6eb9c7ab back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:03:10 +00:00
Jim Grosbach
68741be5e6 Enable Expand handling of atomics for subtargets that can't do them inline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:35:32 +00:00
Bruno Cardoso Lopes
4b8921d1c7 Use the new 'defm' class inheritance in SSE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:10:11 +00:00
Bob Wilson
ebe99b2c19 Rewrite chained if's as switches and replace assertions with llvm_unreachable 
(as suggested in radar 8104405).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:32:42 +00:00
Dale Johannesen
51bd47edbc Fix ARM/Thumb reversal in previous attempt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
52c61ec164 When using ADDri to get the address of a stack object, 255 is a conservative 
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:59:25 +00:00
Dan Gohman
1415a602ad Make this comment less specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:45:41 +00:00
Dan Gohman
ea9f151cbc Fix X86FastISel's address-mode folding to stay within the 
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:47 +00:00
Dale Johannesen
10416803c1 An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:28 +00:00
Dale Johannesen
c66cdf74a9 Enable tail calls on ARM by default, with some 
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 19:00:18 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:55 +00:00
Dale Johannesen
df50d7e238 Last round of changes for ARM tail calls. 
Not turning them on yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:11 +00:00
Jakob Stoklund Olesen
0d8ba3303b Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 16:49:33 +00:00
Dan Gohman
027657db7c Change UpdateNodeOperands' operand and return value from SDValue to 
SDNode *, since it doesn't care about the ResNo value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 15:30:29 +00:00
Dan Gohman
5ff12fc41a Delete unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:32:32 +00:00
Dan Gohman
e368b460a2 Eliminate unnecessary uses of getZExtValue(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:22:04 +00:00
Dan Gohman
7720cb3823 isValueValidForType can be a static member function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:01:07 +00:00
Eric Christopher
f627dc37bf Some assorted isTwoAddress -> Constraints cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 02:41:19 +00:00
Dan Gohman
e54081088e Don't maintain a set of deleted nodes; instead, use a HandleSDNode 
to track a node over CSE events. This fixes PR7368.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
d7f9cc4de7 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:12:56 +00:00
Dan Gohman
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:05:21 +00:00
Bruno Cardoso Lopes
597ec8ed51 Use new tablegen resources in SSE tablegen code. This will 
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 23:05:30 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This 
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 22:43:56 +00:00
Jim Grosbach
7072cf62a5 Thumb1 and any pre-v6 ARM target should use the libcall expansion of 
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 02:02:03 +00:00
Jim Grosbach
c73993b678 simplify code a bit and add a more explanatory assert for cases that 
previously would result in 'cannot yet select' errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 01:37:00 +00:00
Eric Christopher
e98ad83543 Hack to let the move lowering handle dynamic-no-pic absolute moves of 
TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 00:51:48 +00:00
Jim Grosbach
7616b646f1 format and 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 23:45:49 +00:00
Jakob Stoklund Olesen
a2846b4bee Don't attempt preserving conservative kill flags. We were doing it wrong. 
This is before LiveVariables anyway, where these kill flags are recalculated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 22:11:08 +00:00
Bob Wilson
07f6e805b1 Remove the hidden "neon-reg-sequence" option. The reg sequences are working 
now, so there's no need to disable them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 21:34:01 +00:00
Benjamin Kramer
0f471e018f TODO-- 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 15:47:00 +00:00
Evan Cheng
46df4eb46e Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 07:35:02 +00:00
Bill Wendling
d361a77f14 Create a more targeted fix for not sinking instructions into a range where it 
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:46:31 +00:00
Eric Christopher
6102549737 For 32-bit non-pic tlv mach-o addressing we don't need a pic base or 
a relative address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:08:42 +00:00
Dale Johannesen
38d5f0441c Add file missing from previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:24:08 +00:00
Dale Johannesen
6470a116f1 Next round of tail call changes. Register used in a tail 
call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:08:33 +00:00
Dale Johannesen
bf37850e42 Reapply 105986 with fix for bug pointed out by Jakob: 
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 21:36:43 +00:00
Chris Lattner
868ee9460c fix fastisel to handle GS and FS relative pointers. Patch by 
Nelson Elhage!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:08:40 +00:00
Bob Wilson
827b2106fe Add basic support for NEON modified immediates besides VMOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:05:35 +00:00
Daniel Dunbar
f4a7bf4ec3 Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 14:50:42 +00:00
Bob Wilson
14f1d4e74b VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 05:51:27 +00:00
Dale Johannesen
69ba5c6aa8 Revert 105986; looks like I'd better try bootstrapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 04:55:06 +00:00
Dale Johannesen
4b559f070a The form of BuildMI used for TAILJMPr was changing the register 
containing the target address, an input, into an output.  I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105986 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 03:13:49 +00:00
Jim Grosbach
400c95fe38 Make sure to skip dbg_value instructions when finding an insertion point for 
the combined load/store instruction. rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 00:41:09 +00:00
Bob Wilson
d3c4284849 Rename functions referring to VMOV immediates to refer to NEON "modified 
immediate" operands.  These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands.  No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 22:19:57 +00:00
Chris Lattner
6b601536ff fix a nasty bug where we were not treating available_externally 
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 20:11:56 +00:00
Chris Lattner
ef66df4da8 fix a -Wbool-conversions warning from clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105943 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 18:28:57 +00:00