Jim Grosbach
97a884d602
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
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possible. They were duplicates for everything exception the source pattern
before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 20:41:06 +00:00
Evan Cheng
52f21e35e8
Code clean up; no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 20:11:46 +00:00
Evan Cheng
9801b5c822
Code clean up; no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 19:59:34 +00:00
Jim Grosbach
5169220624
Encode the literal field for tCMPzi instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 17:48:24 +00:00
Benjamin Kramer
6aa4943599
Add parens to pacify gcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 15:50:35 +00:00
Jay Foad
40f8f6264d
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
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zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 08:25:19 +00:00
Owen Anderson
eb6779c5b9
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 00:45:21 +00:00
Jim Grosbach
662a816e89
Add fixup for Thumb1 BL/BLX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 23:57:07 +00:00
Rafael Espindola
179821ac1f
Remove the instruction fragment to data fragment lowering since it was causing
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freed data to be read. I will open a bug to track it being reenabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 19:08:48 +00:00
Owen Anderson
c76c59840b
Revert r121021, which broke the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:57:40 +00:00
Jim Grosbach
ba3368ceae
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:47:44 +00:00
Owen Anderson
4c386fc754
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:35:51 +00:00
Jim Grosbach
04f74942f2
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
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the instruction is predicated, reg0 otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:30:57 +00:00
Jim Grosbach
d67641b6f8
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
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not an immediate. It stores either ARM::CPSR or reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:21:12 +00:00
Evan Cheng
04e2b639c1
Eliminate unneeded #include's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
714e07f75d
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120966 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:08:57 +00:00
Evan Cheng
167be80ee7
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:03:45 +00:00
Evan Cheng
f79ed109ec
Remove an unused variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 23:03:35 +00:00
Evan Cheng
48575f6ea7
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
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difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 22:04:16 +00:00
Bob Wilson
c24130bade
The Thumb tADDrSPi instruction is not valid when the destination is SP.
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Check for that and try narrowing it to tADDspi instead. Radar 8724703.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-04 04:40:19 +00:00
Jim Grosbach
ceab50198e
Encode condition code for Thumb1 conditional branch instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-04 00:20:40 +00:00
Jim Grosbach
ed09087dd3
Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.
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tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 23:54:18 +00:00
Bill Wendling
fb62d550de
Use correct variable names to match the patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 23:44:24 +00:00
Jim Grosbach
1b555d9f96
Match pattern operand names to expected encoding field names. This corrects the
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operand encoding ordering of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 23:21:25 +00:00
Jim Grosbach
4fa102b84e
Remove incorrect BL target encoding (it's similar to, but not the same as the
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ARM instruction). Add encoding of bits 13 and 11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 22:33:42 +00:00
Jim Grosbach
d91f4e40e6
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
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halfword being emitted to the stream first. rdar://8728174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 22:31:40 +00:00
Jim Grosbach
41ad0c4c73
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
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32-bit wide version by adding the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 20:33:01 +00:00
Benjamin Kramer
b3a04d46e8
Remove unused variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:55:37 +00:00
Jim Grosbach
6e57298127
Reduce t2 ldr/str instructions to the correct t1 versions when there's an
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immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:47:11 +00:00
Jason W Kim
2ccf148fba
fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120832 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:40:23 +00:00
Jim Grosbach
0b951ceb02
No need to declare EncoderMethod property anymore; just assign to it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 19:31:00 +00:00
Jim Grosbach
d253545c17
Add FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 18:37:17 +00:00
Jim Grosbach
2c971ab9d9
Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 18:31:03 +00:00
Bill Wendling
278b6e81c8
Don't overwrite the opcode passed into the T1Special pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 02:02:58 +00:00
Bill Wendling
534a5e4305
Add Thumb encoding for some more instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 01:55:47 +00:00
Bill Wendling
0bdf0c05b9
The tLDR instruction wasn't encoded properly:
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<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>
Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 00:53:22 +00:00
Jim Grosbach
7721e7f279
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 23:05:38 +00:00
Jim Grosbach
1ab4b211ea
When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,
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not thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 16:42:25 +00:00
Jim Grosbach
ce4fadf884
Fix copy/pasto in vmin.f32 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 16:30:58 +00:00
Jim Grosbach
dff84b0325
Add support for binary encoding of ARM 'adr' instructions referencing constant
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pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02 00:28:45 +00:00
Evan Cheng
1bf891ae6e
Fix and re-enable tail call optimization of expanded libcalls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 22:59:46 +00:00
Jason W Kim
0c628c2617
fixing style nit: move class static to global static
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 22:46:50 +00:00
Bill Wendling
cf590263cd
Add a post encoder method to the VFP instructions to convert them to the Thumb2
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encoding if we're in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 21:54:50 +00:00
Jim Grosbach
5177f79c37
Use the correct fixup type for ARM VLDR*
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 21:09:40 +00:00
Jim Grosbach
5d14f9be7b
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
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instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:47:31 +00:00
Owen Anderson
9d63d90de5
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:18:46 +00:00
Jason W Kim
1920d82f75
kill trailing space
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 19:07:22 +00:00
Jim Grosbach
3990d8f89f
10 bits, not 12.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 18:51:32 +00:00
Jim Grosbach
887c0e4cbf
Elaborate on FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 04:01:17 +00:00
Jim Grosbach
baf120fbe8
Move the ARMAsmPrinter class defintiion into a header file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 03:45:07 +00:00
Bill Wendling
ff25116a09
Remove "comparison of integers of different signs" warning by making the
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variable unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:49:04 +00:00
Bill Wendling
43f7b2d370
General cleanups of comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:42:55 +00:00
Jason W Kim
85fed5e0c5
ARM/MC/ELF relocation "hello world" for movw/movt.
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Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
refactor ELFObjectWriter::RecordRelocation more.
Possibly share more code with Darwin?
Lots more relocations...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:40:06 +00:00
Bill Wendling
0480e28fb2
Formatting. It's all the rage!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:36:55 +00:00
Bill Wendling
1d045ee884
More refactoring. This time the T1pI pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 02:28:08 +00:00
Eric Christopher
564857f776
Refactor load/store handling again. Simplify and make some room for
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reg+reg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:40:24 +00:00
Jan Wen Voung
a63bf704b4
Initialize an ARMConstantPoolValue field.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:38:58 +00:00
Bill Wendling
40062fb747
s/T1pIEncode/T1pILdStEncode/g
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s/T1pIEncodeImm/T1pILdStEncodeImm/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:38:08 +00:00
Bill Wendling
0b424dc6b7
Renaming variables to coincide with documentation. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:32:02 +00:00
Bill Wendling
76f4e10388
Refactor T1sI and T1sIt encodings into helper classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 01:20:15 +00:00
Bill Wendling
a5a42d9b3c
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
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statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 00:48:44 +00:00
Owen Anderson
ca6945e5e2
Use by-name rather than by-order matching for NEON operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01 00:28:25 +00:00
Evan Cheng
3d2125c9db
Enable sibling call optimization of libcalls which are expanded during
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legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:55:39 +00:00
Bill Wendling
3f8c110dc6
Rename operands to match ARM documentation. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:54:45 +00:00
Jim Grosbach
b0708d292b
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:51:41 +00:00
Jim Grosbach
d309b413a5
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120497 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:29:24 +00:00
Jason W Kim
61db62990b
Thanks to JimG for catching this!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:27:18 +00:00
Bill Wendling
2cbc9fe837
Inline classes that were used in only one place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:16:25 +00:00
Bill Wendling
1fd374e9c1
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
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t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:57:21 +00:00
Owen Anderson
80dd3e0612
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
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Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:45:47 +00:00
Jim Grosbach
97dd28fb89
Fix handling of ARM negative pc-relative fixups for loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:40:36 +00:00
Owen Anderson
c7373f8158
Provide Thumb2 encodings for a few miscellaneous instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 20:00:01 +00:00
Jim Grosbach
c02ba66d41
Add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:25:56 +00:00
Owen Anderson
0e1bcdf4f7
Add encoding support for Thumb2 PLD and PLI instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:19:31 +00:00
Eric Christopher
06a86da323
Noticed this on inspection, fix and update some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 19:14:07 +00:00
Jim Grosbach
2e812e1635
Pseudo-ize ARM MOVPCRX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:56:36 +00:00
Owen Anderson
eb05a8d250
Provide encodings for a few more load/store variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:38:28 +00:00
Jim Grosbach
a0d2c8a40f
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
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rdar://8685712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:30:19 +00:00
Bill Wendling
ef4a68badb
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
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certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 07:44:32 +00:00
Bill Wendling
0e45a5a901
Minor cleanups. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:50:22 +00:00
Bill Wendling
6e46d84eea
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:48:15 +00:00
Bill Wendling
647fea57fd
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
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able to match this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:34:08 +00:00
Jim Grosbach
532c2f1d50
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction
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and which are pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:24:05 +00:00
Bill Wendling
67077419c6
Add some encoding for the adr instruction. Labels still need to be finished.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:18:30 +00:00
Owen Anderson
6af50f7dd1
Correct Thumb2 encodings for a much wider range of loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:14:31 +00:00
Jim Grosbach
5c86a0a2b5
Make a few more ARM pseudo instructions actually use the PseudoInst base class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:09:06 +00:00
Bill Wendling
8ca2fd6665
Predicate encoding should be withing {}s. And general cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:08:20 +00:00
Bill Wendling
194271a76e
Predicate encoding should be withing {}s.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:05:25 +00:00
Bob Wilson
8e0c7b5287
Fix the encoding of VLD4-dup alignment.
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The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:42 +00:00
Bob Wilson
173fb1421a
Rename VLDnDUP instructions with double-spaced registers
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in an attempt to make things a little more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:38 +00:00
Bob Wilson
6c4c982f83
Add support for NEON VLD3-dup instructions.
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The encoding for alignment in VLD4-dup instructions is still a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 00:00:35 +00:00
Jim Grosbach
e76473d9ba
Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:51:31 +00:00
Jim Grosbach
6e4221153b
Parameterize ARMPseudoInst size property.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:48:41 +00:00
Jim Grosbach
00a257af5b
Add a few missing initializers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:41:10 +00:00
Jim Grosbach
03f44a04e6
Nuke trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:18:01 +00:00
Jim Grosbach
cd3c7cb915
Nuke a FIXME. No need to be fancier here, as ARM handles constant pools
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locations and formatting specially. rdar://7353441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:09:20 +00:00
Owen Anderson
75579f739f
Provide Thumb2 encodings for basic loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:44:32 +00:00
Evan Cheng
1e0eab122b
Mark Darwin call instructions as using "r7" to prevent the frame-register
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assignment instructions from being moved below / above calls.
rdar://8690640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:43:27 +00:00
Jim Grosbach
a0bb253119
Nuke dead isCodeGenOnly annotation and extraneous comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:40:58 +00:00
Jim Grosbach
fbf0cb18cb
tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120335 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:38:48 +00:00
Bill Wendling
9b0e92ca5b
Thumb encodings for conditional moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:37:46 +00:00
Jim Grosbach
5ca66696e7
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
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instructions. This simplifies instruction printing and disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:37:40 +00:00
Bill Wendling
a46a493c02
Refactor some of the "disassembly-only" instructions into a base class. This
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reduces some code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 22:15:03 +00:00
Eric Christopher
7bb5996e47
Update fastisel for the changes in r120272.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 21:56:23 +00:00
Jim Grosbach
d092a87ba3
Rename t2 TBB and TBH instructions to reference that they encode the jump table
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data. Next up, pseudo-izing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 21:28:32 +00:00
Owen Anderson
5404c2b36e
Improving the factoring of several instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 20:38:48 +00:00
Bob Wilson
86c6d80a7a
Add support for NEON VLD3-dup instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 19:35:29 +00:00
Bob Wilson
2fcda63763
Fix copy-and-paste errors in VLD2-dup scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120311 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 19:35:23 +00:00
Jim Grosbach
f1aa47dc1a
ARM Pseudo-ize tBR_JTr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 19:32:47 +00:00
Owen Anderson
00a035f74f
Thumb2 encodings for MSR and MRS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 19:29:15 +00:00
Owen Anderson
d18a9c9b9d
Thumb2 encodings for system instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 19:22:08 +00:00
Owen Anderson
05bf595122
Thumb2 encodings for branches and IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 18:54:38 +00:00
Jim Grosbach
11fbff8085
The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to
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get the pretty-printer. That's handled explicityly by the MC lowering now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120305 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 18:53:24 +00:00
Michael J. Spencer
3cc52ea33c
I swear I did a make clean and make before committing all this...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 18:47:54 +00:00
Jim Grosbach
2dc7768d73
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 18:37:44 +00:00
Bill Wendling
2f17bf2a44
Add more Thumb encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 01:07:48 +00:00
Bill Wendling
5cbbf68e35
More Thumb encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 01:00:43 +00:00
Bill Wendling
d19ac0c75a
Add Thumb encodings for REV instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 00:42:50 +00:00
Bill Wendling
849f2e381e
Add more Thumb encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 00:18:15 +00:00
Bob Wilson
b1dfa7a8e0
Add support for NEON VLD2-dup instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28 06:51:26 +00:00
Bob Wilson
f3d2f9d4be
Another minor refactoring for VLD1DUP instructions.
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The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28 06:51:15 +00:00
Bob Wilson
364a72a8e5
Add entry in getTargetNodeName() for ARMISD::VBICIMM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28 06:51:11 +00:00
Anton Korobeynikov
94c5ae0875
Move more PEI-related hooks to TFI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 23:05:25 +00:00
Anton Korobeynikov
cd775ceff0
Move callee-saved regs spills / reloads to TFI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 23:05:03 +00:00
Bob Wilson
bce55776af
Refactor. Set alignment bit in VLD1-dup instruction classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 07:12:02 +00:00
Bob Wilson
2a0e97431e
Add NEON VLD1-dup instructions (load 1 element to all lanes).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 06:35:16 +00:00
Bob Wilson
8d41294664
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
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I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 06:35:09 +00:00
Daniel Dunbar
36d76a8dbc
MC/Mach-O: Switch to using MachOFormat.h.
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- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 04:38:36 +00:00
Rafael Espindola
fd46797d0d
Remove the unused TheTarget member.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-26 04:24:21 +00:00
Jason W Kim
13534672de
Move the ARM reloc constants to Support/ELF.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23 19:40:36 +00:00
Bob Wilson
626613d5e8
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
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We need to check if the individual vector elements are sign/zero-extended
values. For now this only handles constants values. Radar 8687140.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23 19:38:38 +00:00
Wesley Peck
bf17cfa3f9
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23 03:31:01 +00:00
Evan Cheng
ab5c703fdb
Fix epilogue codegen to avoid leaving the stack pointer in an invalid
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state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22 18:12:04 +00:00
Duncan Sands
3d93893895
Fix a compiler warning about Kind being used uninitialized
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when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22 09:38:00 +00:00
Eric Christopher
9d89311df8
Pseudos default to 4byte size, let the instruction size field notice
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that branch tables are special.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 23:38:19 +00:00
Bill Wendling
dcf0a47b76
More Thumb encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 11:49:36 +00:00
Bill Wendling
af2b573614
Add encoding for ARM "trap" instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 11:05:29 +00:00
Bill Wendling
9717fa9f29
The "trap" instruction is one of this which doesn't have a condition code. Hack
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the code to not add a "condition code" if it's trap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 10:56:05 +00:00
Bill Wendling
7d0affdf02
- Give "trap" the correct encoding, at least according to Darwin's assembler.
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- Add comments saying where the encodings for other instructions came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 10:55:23 +00:00
Owen Anderson
aa54524a44
Use by-name rather than by-order operand matching for some NEON encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 06:47:06 +00:00
Jim Grosbach
0eb49c57f0
BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119918 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 01:26:01 +00:00
Bill Wendling
5cc88a205d
A few more thumb instruction MC encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119913 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 22:52:33 +00:00
Eric Christopher
827656dab4
Rewrite address handling to use a structure with all the possible address
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mode variables. Handle frame indexes in load/store and allocas again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 22:38:27 +00:00
Eric Christopher
13df1a0bac
STRH only needs the additional operand, not t2STRH. Also invert conditional
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to match the one from the load emitter above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 22:01:38 +00:00
Anton Korobeynikov
82f58740c7
Move some more hooks to TargetFrameInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 15:59:32 +00:00
Bill Wendling
a09cc2b429
Add more Thumb add instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 01:18:47 +00:00
Bill Wendling
95a6d1759d
Add Thumb encodings for some add instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 01:00:29 +00:00
Bill Wendling
6179c31e07
Add more encodings for Thumb instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 00:53:35 +00:00
Bill Wendling
20272a7c5a
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
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value that the one in ARMMCCodeEmitter.cpp does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20 00:26:37 +00:00
Jim Grosbach
078e239f69
Fix ARM LDR* post-indexed operand encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 23:14:43 +00:00