Thomas Harte
4bf81d3b90
Decodes the 6850 control register, and starts working on standardised serial ports.
2019-10-12 18:19:55 -04:00
Thomas Harte
cd75978e4e
Nudges 6850 towards coherence.
2019-10-12 00:04:02 -04:00
Thomas Harte
c5ebf75351
Attempts to start producing actual video.
2019-10-10 22:46:58 -04:00
Thomas Harte
d7ce2c26e8
Adds an empty shell for the ACIA.
2019-10-10 20:54:29 -04:00
Thomas Harte
f88e1b1373
Adds enough logic to advance to an ACIA access error.
2019-10-09 23:01:11 -04:00
Thomas Harte
1de1818ebb
Makes an unsuccessful first attempt at some timer functionality.
2019-10-07 22:44:35 -04:00
Thomas Harte
885f890df1
Adds a target for MFP read/write operations.
...
Completely without any implementation, so far.
2019-10-06 23:14:05 -04:00
Thomas Harte
6c99048211
Copies in a few more hardware notes.
2019-10-02 19:18:09 -04:00
Thomas Harte
2638a901d9
Improves documentation of existing degree of implementation.
2019-09-30 21:36:37 -04:00
Thomas Harte
929475d31e
Minor correction: round down, not up.
2019-09-28 23:49:32 -04:00
Thomas Harte
7758f9d0a9
Improves nomenclature.
2019-09-24 22:31:36 -04:00
Thomas Harte
8d4a96683a
Reduces output noise.
2019-09-18 21:41:29 -04:00
Thomas Harte
f53411a319
Removes local NDEBUG.
2019-09-18 21:35:26 -04:00
Thomas Harte
962275c22a
Removes clock for NCR 5380.
...
It doesn't have one in real life, and now can live off the time counting that occurs on the SCSI bus.
2019-09-18 20:17:47 -04:00
Thomas Harte
2f6c366668
Makes a concerted effort at properly wrapping a hard disk image.
2019-09-17 21:30:04 -04:00
Thomas Harte
2ce1f0a3b1
Implements multi-sector read/write.
...
This once again unblocks Apple HD SC Setup. Progress!
2019-09-16 22:20:42 -04:00
Thomas Harte
960b289e70
Edges closer towards proper DMA operation.
...
Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
2019-09-15 15:03:06 -04:00
Thomas Harte
243e40cd79
Adds signalling of DACK.
2019-09-14 13:48:33 -04:00
Thomas Harte
64dad35026
Decreases logging, at least temporarily.
2019-09-03 22:40:32 -04:00
Thomas Harte
1c7e0f3c9d
Fixes control line modification by the 5380 and SCSI target command chaining.
...
So now I'm back to trying to guess how a SCSI command terminates re: the relative meanings of a message phase and a status phase.
2019-09-02 23:14:37 -04:00
Thomas Harte
ca08716c52
Introduces real hard disk images to the nascent world of SCSI.
2019-08-25 17:03:41 -04:00
Thomas Harte
c86db12f1c
Starts implementing DMA support on the 5380.
...
The Macintosh doesn't actually use the DMA signals, but uses pseudo-DMA mode so they nevertheless need to be appropriate.
2019-08-24 22:47:11 -04:00
Thomas Harte
2d82855f26
Attempts to provide a data out phase.
2019-08-22 23:16:58 -04:00
Thomas Harte
faec516a2c
Starts pushing towards figuring out a proper infrastructure for mass storage.
2019-08-21 23:22:58 -04:00
Thomas Harte
bb1a0a0b76
Sketches out further SCSI infrastructure.
2019-08-21 22:37:39 -04:00
Thomas Harte
252650808d
Starts seeking to unbind SCSI bus logic and command performance.
2019-08-19 22:47:01 -04:00
Thomas Harte
e3d9254555
Implements phase-match bit.
...
Seemingly causing the command phase to proceed.
2019-08-18 23:15:54 -04:00
Thomas Harte
955e909e61
Attempts to nudge the command phase further towards functioning.
2019-08-18 22:39:27 -04:00
Thomas Harte
8339e2044c
Switches to proper SCSI terminology and better attempts a command phase.
2019-08-18 15:10:07 -04:00
Thomas Harte
0e0c789b02
Starts attempting to introduce a direct access device.
...
Without having access to the SCSI-1 standard, a lot of this is guesswork.
2019-08-17 23:43:42 -04:00
Thomas Harte
7e001c1d03
Corrects data line loading.
...
Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
2019-08-17 21:30:59 -04:00
Thomas Harte
9047932b81
Corrected basic error. Arbitration now seems to succeed.
...
This is seemingly followed by a pattern of signalling BUSY+SEL followed by just SEL with the various other potential device IDs in turn. To which nothing ever responds as currently implemented.
2019-08-15 23:28:30 -04:00
Thomas Harte
f668e4a54c
Makes an attempt at getting the 5380 past arbitration.
...
Not entirely successful. Also gets a bit smarter with `final` on ClockingHint::Sources.
2019-08-15 23:14:40 -04:00
Thomas Harte
ce1c96d68c
Starts thinking out the mechanics of emulating a SCSI-1 bus.
2019-08-13 23:09:11 -04:00
Thomas Harte
0f67e490e8
Adjusts NCR address decoding to produce a more plausible initial interaction.
2019-08-11 22:43:25 -04:00
Thomas Harte
a90a74a512
Stubs in just enough of the 5380 to get a Mac Plus too boot.
2019-08-11 20:55:20 -04:00
Thomas Harte
949c1e1668
Adds an empty shell for what will be my 5380 implementation.
2019-08-10 23:53:52 -04:00
Thomas Harte
96005261c7
Adds activity lights for Macintosh disk activity.
...
Prompting a quick fix to drives not spinning down.
2019-08-02 16:26:23 -04:00
Thomas Harte
335dda3d55
Attempts more accurately to match Apple's windowing logic.
2019-08-02 12:49:45 -04:00
Thomas Harte
9bbccd89d3
Adds an extended rationale for current implementation.
...
Also strips some cruft of prior guesses.
2019-07-31 23:19:46 -04:00
Thomas Harte
2aa308efdd
Tweaks magic formulas.
...
The computer now at least seeks outward, until this attempt at drive speed calculation fails.
2019-07-30 16:18:36 -04:00
Thomas Harte
74c18d7861
Attempts a full wiring up of 400kb drive speed.
2019-07-30 15:08:55 -04:00
Thomas Harte
a43ada82b2
Experiments with a JustInTimeActor in the Master System.
2019-07-29 15:38:41 -04:00
Thomas Harte
85cf8d89bc
Ensures an initial non-zero value.
2019-07-25 21:47:44 -04:00
Thomas Harte
0469f0240b
Moves interrupt level selection outside the loop.
2019-07-23 23:13:03 -04:00
Thomas Harte
d69aee4972
Removes stray \n.
2019-07-23 22:17:46 -04:00
Thomas Harte
ee8d853fcb
Ensures you can't get a phase 2 for free with run_for(0)
.
2019-07-17 14:20:27 -04:00
Thomas Harte
67055d8b56
Reduces CheckingWriteProtect
costs, negligibly.
2019-07-15 22:39:55 -04:00
Thomas Harte
7baad61746
Attempts a full implementation of asynchronous write mode.
2019-07-15 17:11:12 -04:00
Thomas Harte
1d1e0d74f8
Corrects and introduces new parts.
2019-07-12 21:37:33 -04:00
Thomas Harte
d53d1c616f
Continues trying to get to write support.
2019-07-12 21:20:05 -04:00
Thomas Harte
2c39229b13
Adds has-new-disk flag, allowing mounting of software from the desktop.
2019-07-12 13:17:24 -04:00
Thomas Harte
b730ac5d5a
Reintroduces 1-second disable implementation.
2019-07-11 23:02:47 -04:00
Thomas Harte
c8917e677b
Edging towards implementing IWM write support, but mainly tidied up.
2019-07-11 21:42:34 -04:00
Thomas Harte
cac97a9663
Devolves drive responsibility.
2019-07-10 22:39:56 -04:00
Thomas Harte
be251d6b03
Begins substituting the DoubleDensityDrive for the Sony.
2019-07-10 16:24:48 -04:00
Thomas Harte
6cfaf920ee
Added attribution and commentary on rotation speeds.
2019-07-10 16:22:06 -04:00
Thomas Harte
1657f8768c
Transfers and slightly extends drive logic into the drive.
2019-07-10 16:17:51 -04:00
Thomas Harte
c4ab0bb867
Starts sketching out an interface for IWM drives, eliminating a dangling use of unsigned
as it goes.
2019-07-10 16:05:59 -04:00
Thomas Harte
fb6da1de4a
Reduces logging temporarily.
2019-07-08 17:37:15 -04:00
Thomas Harte
245e27c893
Solidifies belief that the shift register bit is cleared on read/write.
2019-07-08 16:45:15 -04:00
Thomas Harte
28de629c08
Fixes the 6522 sufficiently to fix keyboard input.
2019-07-08 15:29:34 -04:00
Thomas Harte
210bcaa56d
Introduces an initial shift unit test, and makes it pass.
2019-07-07 22:13:36 -04:00
Thomas Harte
191a7a9386
Reintroduces an empty second drive.
...
This prevents the uninitialised disk error. Which is a clue.
2019-07-02 16:59:00 -04:00
Thomas Harte
b9c2c42bc0
Switches drives to using floats for time counting.
...
Hopefully to eliminate a lot of unnecessary `Time` work; inaccuracies should still be within tolerable range.
2019-07-02 15:43:03 -04:00
Thomas Harte
6c588a1510
Makes some further random swings at tracking the startup procedure.
2019-06-28 13:03:47 -04:00
Thomas Harte
00c32e4b59
Further miscellaneous changes to debug logging. All temporary.
2019-06-18 10:34:31 -04:00
Thomas Harte
877b46d2c1
Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'.
2019-06-15 16:08:54 -04:00
Thomas Harte
cc7226ae9f
Starts trying to get a bit more rigorous about collected meanings.
2019-06-13 22:48:10 -04:00
Thomas Harte
bde975a3b9
Possibly mights the tiniest bit of headway with 'the IWM'.
...
I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
2019-06-13 22:38:09 -04:00
Thomas Harte
f6f9024631
Corrects Macintosh aspect ratio (and framing).
2019-06-13 18:41:38 -04:00
Thomas Harte
535747e3f2
Restores single-line logging format.
2019-06-13 13:35:03 -04:00
Thomas Harte
d6150645c0
By hook or by crook, mouse input now works.
2019-06-12 22:19:25 -04:00
Thomas Harte
ccd2cb44a2
Fills in enough of the SCC to allow completion of the Macintosh side of that relationship.
2019-06-12 17:51:50 -04:00
Thomas Harte
ad8b68c998
Switches to a proper form of zero-upon-read data.
...
Not that it's necessarily correct.
2019-06-11 19:53:51 -04:00
Thomas Harte
3c075e9542
Switches drives 0 and 1.
2019-06-10 14:58:39 -04:00
Thomas Harte
9230969f43
Corrects enough of the 6522 and Keyboard to get an initial command seemingly working.
2019-06-10 09:28:27 -04:00
Thomas Harte
0e16c67805
Improves shift register connection, towards having the keyboard function properly.
...
It now seems not to receive a command terminator, but is at least getting a command.
2019-06-08 23:04:55 -04:00
Thomas Harte
697e094a4e
Sketches out the absolute basics of an SCC interface.
2019-06-08 18:47:11 -04:00
Thomas Harte
50d37798a2
Eradicates magic constants.
2019-06-06 21:37:43 -04:00
Thomas Harte
e9d0676e75
Fiddles further with the tachometer.
2019-06-06 21:36:19 -04:00
Thomas Harte
7591906777
Numerous IWM fixes: the machine now seems to be trying to measure the tachometer.
2019-06-06 18:32:11 -04:00
Thomas Harte
a413ae11cb
Makes some sort of first attempt at having the IWM read.
2019-06-04 22:13:00 -04:00
Thomas Harte
b8a1553368
Adds putative support for PlusToo-style BIN files.
...
Albeit a bit of a guess, since it's not intended to be an emulator file format.
2019-06-04 21:41:09 -04:00
Thomas Harte
8557558bd8
Mildly improves investigatory reporting.
2019-06-03 21:51:45 -04:00
Thomas Harte
abe55fe950
Adds Timer 1 toggling of PB7.
2019-06-03 15:39:20 -04:00
Thomas Harte
da2b190288
Stores expected bit length.
2019-06-01 19:08:29 -04:00
Thomas Harte
48d837c636
Attempts to respond more sensibly to various queries.
...
Including adding a 1-second delay on motor off.
2019-06-01 18:43:47 -04:00
Thomas Harte
723137c0d4
With some time additions to the 6522, starts wiring in Macintosh audio.
...
The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
2019-06-01 14:39:40 -04:00
Thomas Harte
4197c6f149
Attempts to make some further semantic sense of the various IWM controls.
2019-05-30 22:17:49 -04:00
Thomas Harte
4632be4fe5
Wires up the final IWM signal, SEL, preparatory to an implementation.
2019-05-30 12:08:00 -04:00
Thomas Harte
8293b18278
Adds a TODO on what I think might be an incorrect implementation?
2019-05-08 15:06:40 -04:00
Thomas Harte
2ba0364850
Adds the shift register interrupt.
2019-05-08 15:02:07 -04:00
Thomas Harte
2e7bc0b98a
Attempts the shift register.
2019-05-08 14:54:40 -04:00
Thomas Harte
8278809383
Attempts to get more rigorous on communicating outward control line changes.
2019-05-08 13:33:22 -04:00
Thomas Harte
4367459cf2
Takes a first go at handshake and pulse modes.
2019-05-08 12:48:29 -04:00
Thomas Harte
254132b83d
Eliminates 6522Base in pursuit of working handshake modes.
...
Specifically: this means that the places from which the BusHandler may be called are more numerous.
2019-05-08 12:35:17 -04:00
Thomas Harte
7e6d4f5a3e
Adds emulation of the real-time clock.
2019-05-08 00:12:19 -04:00
Thomas Harte
ce099a297a
Eliminates RAM writes in ROM area.
...
I no longer think that logic is correct.
2019-05-07 17:16:22 -04:00
Thomas Harte
96facc103a
Adds an IWM shim and corrects graphics output.
...
... now that there is some.
2019-05-05 21:55:34 -04:00
Thomas Harte
62a1d69cee
Implements proper AY IO output behaviour.
2019-03-05 20:20:26 -05:00
Thomas Harte
d97348dd38
Eliminates dangling uses of printf
.
2019-03-02 18:07:05 -05:00
Thomas Harte
7030abca97
Corrects PAL colours for the Vic-20.
2019-02-25 19:28:52 -05:00
Thomas Harte
e5addb27ec
Corrects log output.
2019-02-18 20:49:01 -05:00
Thomas Harte
2ef6d4327c
Resolves further build warnings.
2019-01-13 20:37:50 -05:00
Thomas Harte
248a8efd2f
Corrects declared pixel clock GCD.
2019-01-06 16:32:13 -05:00
Thomas Harte
601961deeb
Wires through set_display_type
.
2018-11-29 20:44:21 -08:00
Thomas Harte
64465f97b6
Starts towards reintroducing the proper mechanisms for selecting a display type at runtime.
2018-11-28 17:53:33 -08:00
Thomas Harte
5618288459
Reduces visible area, producing a tighter crop.
2018-11-25 22:32:12 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
770d7e90e9
Removes stale sampling functions.
2018-11-22 22:47:29 -05:00
Thomas Harte
b9aca39eb0
Reintroduces Vic-20 output.
...
Resolving errors in shader generation while I'm here.
2018-11-22 22:43:42 -05:00
Thomas Harte
c5d9bf2c12
Optimises slightly for black borders.
...
Specifically to help to debug proper display of unused lines in the new scan target.
2018-11-17 18:23:42 -05:00
Thomas Harte
15b1176841
Ensures no border output if space is not allocated.
2018-11-14 22:32:33 -05:00
Thomas Harte
9dff13cbbf
Re-establishes output from the machines with 9918s and derivatives.
2018-11-14 22:25:19 -05:00
Thomas Harte
6d277fecd5
Makes ScanTarget
a little more communicative and orthogonal.
2018-11-10 19:52:57 -05:00
Thomas Harte
f6562de325
Possibly adds enough for the Electron and ZX80 to start outputting dummy lines.
...
Let's see!
2018-11-03 23:40:39 -04:00
Thomas Harte
b40211d2c0
Starts to bend 'CRTMachine' to a world farther from owning the GPU relationship.
2018-11-03 21:54:25 -04:00
Thomas Harte
da4d883321
Adds first, incomplete attempts to talk to a ScanTarget from the CRT.
...
Does away with the hassle of `unsigned` while I'm here; that was a schoolboy error.
2018-11-03 19:58:44 -04:00
Thomas Harte
f65d80b7d1
Ensures offset and flags are initialised to 0.
...
This prevents a potential crash at startup.
2018-10-29 22:09:32 -04:00
Thomas Harte
8652d8b23d
(Mostly) randomises the 9918 start position.
2018-10-26 21:02:56 -04:00
Thomas Harte
e02aa885d8
Testing against the ColecoVision suggests this is probably always 7.
2018-10-26 20:59:12 -04:00
Thomas Harte
bb09762029
Introduces extra delays to VRAM access.
2018-10-26 20:19:08 -04:00
Thomas Harte
05a5c7120e
Shunts CRAM dots into their proper place.
2018-10-26 20:06:51 -04:00
Thomas Harte
521d603902
Adds a first attempt at CRAM dot output. With a TODO.
2018-10-26 19:26:46 -04:00
Thomas Harte
916710353a
Makes it explicit that I want the reference.
2018-10-25 23:18:34 -04:00
Thomas Harte
53b00dea3f
Adds missing include.
2018-10-25 23:12:41 -04:00
Thomas Harte
0587b9f257
Edges to within millimetres of CRAM dots.
...
... but all the way up to bedtime.
2018-10-25 23:12:03 -04:00
Thomas Harte
5accd8cf08
Fixes broken implementation of 9918 multicolour mode.
2018-10-24 22:40:38 -04:00
Thomas Harte
a8645f80bf
Introduces 'non-exclusive' emulator-space keyboards.
...
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
2018-10-24 21:59:30 -04:00
Thomas Harte
d61c3a9442
Fixes sprite list termination in 224- and 240-line modes.
2018-10-24 19:53:46 -04:00
Thomas Harte
2cdeaa2575
Moves misplaced bracket.
2018-10-23 22:37:19 -04:00
Thomas Harte
286783e880
Accepts GCC's suggestion of extra clarity brackets.
2018-10-23 22:36:23 -04:00
Thomas Harte
00e7958a97
Separates request for an SMS2 VDP from current graphics mode.
...
Thereby fixes various minor segments of Codemasters games.
2018-10-23 22:19:45 -04:00
Thomas Harte
2f995eb622
Adjusts vertical timing for display height.
2018-10-23 21:20:44 -04:00
Thomas Harte
90fbad0f1c
Implements SMS2-style addressing if in a 224 or 240-line mode.
...
This isn't quite accurate, but it'll do for development.
2018-10-23 20:30:08 -04:00
Thomas Harte
2cbd28478d
Allows the sprite terminator to be specified.
2018-10-23 20:01:47 -04:00
Thomas Harte
7855145ebd
Slightly adjusts pixel output time.
...
i.e. respective to reading; sprite collision times now seem correct.
2018-10-22 19:58:33 -04:00
Thomas Harte
883680731a
Uses explicit state to determine whether a pixel target has been requested.
2018-10-21 21:18:41 -04:00
Thomas Harte
c07f9fed99
Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
2018-10-21 18:42:49 -04:00
Thomas Harte
16f08eb654
Slightly tweaks Master System timing numbers.
2018-10-21 13:58:34 -04:00
Thomas Harte
30b99f0049
Fixes a couple of interrupt prediction errors.
2018-10-20 18:25:28 -04:00
Thomas Harte
b61de65b43
Restores proper phase with the CPU.
2018-10-19 23:18:16 -04:00
Thomas Harte
0822c96ce0
Implements the proper row counter values for > 192 row modes.
2018-10-19 22:37:56 -04:00
Thomas Harte
f9a6c00493
Makes first attempt to support PAL timings.
2018-10-19 21:36:13 -04:00
Thomas Harte
4cd65eab5c
Seeks to avoid bad macro expansion.
2018-10-18 22:36:25 -04:00
Thomas Harte
9bc09046c0
Attempts to ensure that sprites can go off the top of the screen.
2018-10-18 21:48:57 -04:00
Thomas Harte
512f085891
Ensures proper left clipping of sprites.
2018-10-18 21:14:16 -04:00
Thomas Harte
da00c832f5
Corrects colour fetching for multicolour text mode.
2018-10-18 20:38:00 -04:00
Thomas Harte
8ff265c3a1
Corrects multicolour text mode.
2018-10-18 20:25:42 -04:00
Thomas Harte
1fc88c4eff
Corrects off-by-one error in line fetching coroutines.
2018-10-16 21:36:31 -04:00
Thomas Harte
58ca74c68a
Resolves right-side TMS sprite droppages.
2018-10-16 21:25:08 -04:00
Thomas Harte
b4f871a2ef
Corrects first line sprite row selection.
2018-10-16 21:16:29 -04:00
Thomas Harte
0f7bf6d6c6
Resolves attempt to output graphics on the line one before the display.
2018-10-16 21:02:31 -04:00
Thomas Harte
5dfe7d8596
Corrects most of TMS sprite drawing.
2018-10-16 20:49:04 -04:00
Thomas Harte
231009b901
Makes faulty attempt to reintroduce TMS-mode sprites.
2018-10-16 20:00:06 -04:00
Thomas Harte
1c5f939aea
Reintroduces tiles and some element of sprites in regular TMS mode.
2018-10-14 21:52:13 -04:00
Thomas Harte
c1e6406fc9
Corrects sprite accumulation.
2018-10-14 19:56:09 -04:00
Thomas Harte
d66979c68f
Switched to a very large number of buffers, and resolved stupid attempt to reassign a reference.
2018-10-14 18:19:11 -04:00
Thomas Harte
6c09abc6cb
Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer.
...
Specifically because closer inspection of the TMS modes shows it isn't quite valid to model output of one line as having fully completed prior to fetching of the next. So some sort of extra buffer is required. At which point it is most natural to continue with the logic that each fetch routine is oriented around the fetching process for a single line, and each output routine has the same view, suggesting separate read/write addresses.
Something is wrong though, as video data is being output too rapidly (I think) and with occasional sync issues (again: subject to investigation).
2018-10-14 16:23:45 -04:00
Thomas Harte
9e52ead09a
Ensures sprite scanning doesn't improperly set collision flag; that slot 151 is filled.
2018-10-12 19:50:48 -04:00
Thomas Harte
9ab0c54426
Eliminates faulty attempt to satisfy SMSVDP vertical counter test.
2018-10-12 18:57:07 -04:00
Thomas Harte
f6af6778ab
Moves scrolling latch to proper position and implements 4-window fetching offset.
2018-10-11 22:36:27 -04:00
Thomas Harte
6a94dda60d
Selects potentially-correct interrupt times.
2018-10-11 21:42:09 -04:00
Thomas Harte
82b7944599
Fixes horizontal counter wrapping.
2018-10-11 20:37:29 -04:00
Thomas Harte
52e02db5c8
Introduces horizontal counter latching and reading.
...
Then makes a new guess at frame IRQ position. But gets it wrong. Hmmm.
2018-10-11 19:56:32 -04:00
Thomas Harte
9a933993f5
Added TODO.
2018-10-10 22:17:17 -04:00
Thomas Harte
062b2ae8d3
Corrects calculation of [NTSC, 192 line] current row.
2018-10-10 22:15:38 -04:00
Thomas Harte
9f69dbf31a
Adds half-updating of RAM pointer.
...
This emulator now passes the first screen of the SMS VDP test.
2018-10-10 21:59:08 -04:00
Thomas Harte
63fb3f03d1
Corrects address loading upon accesses of registers other than 0.
2018-10-10 21:47:48 -04:00
Thomas Harte
2e379b0834
Adds latching of scroll values.
2018-10-10 21:28:18 -04:00
Thomas Harte
f00f6c8c23
Allows the frame interrupt to be placed anywhere in the frame.
2018-10-10 21:07:39 -04:00
Thomas Harte
50e23f4a2e
Fixes 16px-high sprites.
2018-10-10 20:34:00 -04:00
Thomas Harte
acdc84e08c
Improves test slightly, and fixes line interrupt reload value setting.
2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549
Introduces a first unit test for line interrupts and corrects backup behaviour.
2018-10-09 21:49:21 -04:00
Thomas Harte
dccf17e770
Makes a first serious attempt at Master System line interrupts.
2018-10-09 20:51:09 -04:00
Thomas Harte
2d8ab72e22
Fixed proper starting position for (interrupted) tile drawing.
2018-10-08 23:13:37 -04:00
Thomas Harte
748366c70e
Corrects buffer overrun when the horizontal scroll lock is on.
2018-10-08 23:06:22 -04:00
Thomas Harte
7a74fe2ff7
Corrects tile plotting window and eliminates a redundant local.
2018-10-08 22:56:31 -04:00
Thomas Harte
e410302237
Switches to real SMS line output composition.
...
Including setting the sprite collision bit.
2018-10-08 22:43:10 -04:00
Thomas Harte
bca2161a05
Fixes TMS text mode for the new addressing order.
2018-10-07 21:09:01 -04:00
Thomas Harte
5f789092be
Flips sprite priority in the temporary renderer.
...
The better to test other issues in the interim.
2018-10-07 19:16:35 -04:00
Thomas Harte
6975ed22c0
Doubles down on address-storage format, and implements the vertical scrolling lock.
2018-10-07 18:55:35 -04:00
Thomas Harte
3bead07043
Introduces proper indirection for sprite patterns.
...
This seems to work, so the onus is now back on the rendering loop.
2018-10-07 17:15:42 -04:00
Thomas Harte
ee20e42372
Makes initial attempt at collecting sprite contents.
...
With test plotting, indicating some sort of issue.
2018-10-07 16:53:25 -04:00
Thomas Harte
df411b4ede
Corrects storage of visible sprites.
2018-10-07 16:40:32 -04:00
Thomas Harte
bfb9d8ccb6
At least attempts to use proper addressing for sprite info fetches.
2018-10-07 14:32:20 -04:00
Thomas Harte
338aec2930
Groups background fetches and experimentally seeks to daub sprites as white.
2018-10-06 22:07:04 -04:00
Thomas Harte
e6510dc87b
Attempts to get at least as far as picking visible sprite indices.
2018-10-06 19:27:19 -04:00
Thomas Harte
7830cda912
Implements line querying and most of line interrupts.
2018-10-04 22:50:35 -04:00
Thomas Harte
aac97a8983
Re-revokes fine scroll on the top two lines when requested.
2018-10-04 19:18:15 -04:00
Thomas Harte
ca26dfcd61
Correct Master System palette writes.
2018-10-04 19:12:31 -04:00
Thomas Harte
858721a7a5
Added left border hiding.
2018-10-04 18:52:23 -04:00
Thomas Harte
89db1d6a6a
Switches to a more accurate means of left-padding.
2018-10-04 18:44:49 -04:00
Thomas Harte
de4e5c40aa
Implements horizontal scrolling lock.
2018-10-03 23:28:33 -04:00
Thomas Harte
05248ab990
Starts to reimplement Master System output.
2018-10-03 23:13:21 -04:00
Thomas Harte
252f47a425
Ensures no pixel output on line one before end, and adds a temporary debugging test.
2018-10-02 22:59:20 -04:00
Thomas Harte
be52b31b5c
Attempts fully to revive text mode.
2018-10-02 22:05:58 -04:00
Thomas Harte
23c3fa6993
Fixed: it's the SMS that has 8 sprites, not text mode (which has none).
2018-10-02 22:01:43 -04:00
Thomas Harte
499fc62187
Sets things up for implementation of the inner mode-specific logic.
2018-10-02 21:58:09 -04:00
Thomas Harte
1dd5272190
Ensures real-time output of all areas, to ensure proper palette response.
2018-10-02 21:18:28 -04:00
Thomas Harte
5361120353
Restores a stable frame.
2018-10-02 21:05:30 -04:00
Thomas Harte
60bab8fdf1
Starts to reformulate TMS collection as coroutines.
...
For the time being, thereby breaks all video. A static screen of the border colour is all you'll see.
2018-10-01 23:03:17 -04:00
Thomas Harte
91aa8f9295
Amps up colour content a little.
2018-09-30 20:47:26 -04:00
Thomas Harte
23191efc05
Starts writing and referring to colour RAM for colours.
2018-09-29 19:50:13 -04:00
Thomas Harte
0d8af010b6
Takes a stab at tile reversal and vertical scrolling.
2018-09-28 22:37:10 -04:00
Thomas Harte
7b9bb772ca
Corrected to give a not-exactly-indexed-correctly approximation of what's on display.
2018-09-28 21:03:51 -04:00
Thomas Harte
f7e211c245
Makes first attempt to put something vaguely like the Master System tile map on screen.
2018-09-28 20:39:14 -04:00
Thomas Harte
35c2e74af8
Attempts to establish a coroutine-ish structure for access patterns.
...
The Master System mode, inevitably, is the test case.
2018-09-27 22:33:41 -04:00
Thomas Harte
19482a563f
Attempts to explicitly make room for the SMS VDP mode.
2018-09-27 21:22:57 -04:00
Thomas Harte
9683c8f664
Advances towards the Master System actually receiving interrupts.
2018-09-23 15:58:23 -04:00
Thomas Harte
e7f4babf41
Starts taking steps towards SMS/GG and V9938/9958 support.
...
Specifically: routine namespace stuff, plus the intention to move to a table-based operation+cost version of timing. Reordering works fine for the TMS, and probably would also for the SMS/GG, but it'd be problematic with the command engine of the V9938/9958 and maintaining a consistent set of code is easier.
2018-09-17 22:59:16 -04:00
Thomas Harte
a38639d099
Eliminates the concept of an iCoordinate.
...
Real-life precision appears not to support the idea of sub-sample pixel storage.
2018-09-12 20:05:39 -04:00
Thomas Harte
31b048f966
Ensures all bool
s start in a valid state.
2018-09-10 22:21:03 -04:00
Thomas Harte
7b9c1bb69c
Makes minor layout improvements.
2018-09-09 21:02:31 -04:00
Thomas Harte
70c4d6b9b3
Adds a one second delay between controller and drive motor off.
2018-08-03 21:13:18 -04:00
Thomas Harte
98bb5bd9f1
Ensures flux bits are observable for two cycles rather than one; it should be 1us.
2018-07-31 23:01:11 -04:00
Thomas Harte
92065813ef
Ensures only the first 8px of sprites is output in 8x8 mode.
...
Also adds a little extra documentation.
2018-07-15 22:21:29 -04:00
Thomas Harte
cd464fc7de
Corrects status logging.
2018-06-26 20:53:08 -04:00
Thomas Harte
df8c896193
Removes unused state and implements AND output readback.
2018-06-26 19:31:16 -04:00
Thomas Harte
59f8eeb05a
Ensures the AY goes high impedance when not in read mode.
2018-06-25 20:48:24 -04:00
Thomas Harte
5ab4cfee84
Factors out repeated hex-size setting.
2018-06-21 19:27:54 -04:00
Thomas Harte
a9eb0d02c6
Returns sanity to 8272 logging.
2018-06-20 23:02:32 -04:00
Thomas Harte
adca862166
Finally makes an initial pass at logging macros.
2018-06-18 22:37:19 -04:00
Thomas Harte
dde9b73a22
Creates the through-path that will be necessary for RWTS acceleration.
2018-06-09 12:51:53 -04:00
Thomas Harte
076fa55651
Corrects: flux set is no-flux incoming.
...
This restores good sleeping behaviour.
2018-06-03 08:11:17 -04:00
Thomas Harte
1a9cea050e
Minor: ensure AY registers *read* as 0 from reset, as well as being 0.
2018-06-01 19:48:42 -04:00
Thomas Harte
35e84ff1a8
Corrects NTSC quadrature phase.
2018-05-31 21:40:46 -04:00
Thomas Harte
75f9e3caeb
Resolves incorrect bracketing.
2018-05-28 17:48:35 -04:00
Thomas Harte
928aab13dc
Introduces more granular clocking announcements to the Disk II.
...
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
2018-05-28 17:19:29 -04:00
Thomas Harte
db8d8d8404
Commutes Sleeper
to ClockingHint::Source
, making state more granular.
2018-05-27 23:17:06 -04:00
Thomas Harte
086b801c29
Mildly rearranges to avoid unnecessary call.
2018-05-22 21:50:07 -04:00
Thomas Harte
e482929da8
Enhances the Disk II's ability to sleep.
...
Also enables Disk II sleep observation in the Oric.
2018-05-19 23:15:28 -04:00
Thomas Harte
ed06533e60
Implements write support out of the Disk II.
2018-05-18 22:07:58 -04:00
Thomas Harte
7b7beb13a3
Eliminates the fiction of setting and getting registers.
...
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
2018-05-17 21:39:11 -04:00
Thomas Harte
c46007332a
Switches to returning the shift register contents on every even read.
2018-05-17 20:18:34 -04:00
Thomas Harte
908d3b0ee5
Slightly wrong as to the details, but gets the controller trying to output.
...
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
2018-05-16 22:37:22 -04:00
Thomas Harte
8a031b1137
Eliminates 'data' register as it doesn't exist; rejigs state machine command set.
2018-05-16 22:09:59 -04:00
Thomas Harte
1aba9f807e
Ensures proper upward propagation of sleeping from first start.
2018-05-16 22:07:54 -04:00
Thomas Harte
4c49963988
Switches to proper handling of the motor control and write protection.
...
Per Understanding the Apple II the drive looks write protected while phase 1 is enabled.
2018-05-16 21:44:09 -04:00
Thomas Harte
ad9b0cd4e3
Eliminates all endashes.
2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
d703328114
Adds missing #include for memcpy.
2018-05-12 17:54:13 -04:00
Thomas Harte
bc464e247f
The 1540 and, by extension, the Vic-20 are now activity sources.
2018-05-11 22:24:33 -04:00
Thomas Harte
a43ca0db35
Makes the Apple II an activity source.
2018-05-10 22:17:13 -04:00
Thomas Harte
c3144382c5
Shuffles the Disk II ROM at load time into B.A.P. form.
...
Only if required. In order to support various potential forms of supplied ROM.
2018-05-09 22:03:59 -04:00
Thomas Harte
c3a2f7717b
Makes attempt to implement support for the Pravetz 8D + 8DOS.
...
i.e. the Disk II wired up to the Oric, with some ROM swaps.
2018-05-08 22:05:43 -04:00
Thomas Harte
f65c65569a
Makes disk head position explicitly something with sub-integral precision.
...
Also as a drive-by fix, corrects accidental assumption of 10 sectors for all MFMSectorDump descendants.
2018-05-06 23:17:36 -04:00
Thomas Harte
aacf26f05d
Removed logged comment.
2018-04-30 22:03:09 -04:00
Thomas Harte
10c0e687f5
Attempts to introduce sleeping for the Disk II.
2018-04-29 17:51:10 -04:00
Thomas Harte
41075356e2
Makes a first attempt at NIB support.
2018-04-26 22:49:07 -04:00
Thomas Harte
d59db504a3
Adjusted stepper logic; some disks load now.
2018-04-25 21:59:18 -04:00
Thomas Harte
4c6dc597f4
Converts Time::get into a template, introduces a via-a-double fallback for the timed event loop.
2018-04-25 19:54:39 -04:00
Thomas Harte
7061537ff5
Makes joined-up attempt to run data through the Disk II.
2018-04-24 19:44:45 -07:00
Thomas Harte
99de8f1c5c
Inverts the pulse strobe.
2018-04-24 09:03:03 -07:00
Thomas Harte
af61bbc3e2
Attempts actual performance of the state machine.
2018-04-24 08:29:05 -07:00
Thomas Harte
56d88f23ef
Teeters closer and closer to trying actually to run the Disk II state machine.
2018-04-23 22:29:36 -07:00
Thomas Harte
4bff44377a
Attempts to route Disk II requests to the thing itself.
2018-04-23 22:11:31 -07:00
Thomas Harte
e87a3cffd4
Merge branch 'master' into DiskII
2018-04-21 15:02:18 -07:00
Thomas Harte
5968c9a391
Corrects Apple II output audio.
2018-04-21 14:56:50 -07:00
Thomas Harte
72bc5f8d7b
Adds a class to contain the Disk II and begins Apple GCR conversion routines.
2018-04-21 14:33:42 -07:00
Thomas Harte
f22c23cb4c
Attempts to bring audio to the Apple II.
...
By factoring the audio toggle out from the MSX.
2018-04-17 22:28:13 -04:00
Thomas Harte
1c605d58e3
Removes the CRT requirement for an integral relationship between cycles and samples.
2018-04-16 20:00:56 -04:00
Thomas Harte
467cd5450f
Adjusts PAL Vic timing.
2018-04-12 21:12:09 -04:00
Thomas Harte
428b6145fa
Converts 6560 to more project normative templated form.
2018-04-11 22:00:42 -04:00
Thomas Harte
4c8a68c6a4
Implements late-0 with proper timing, and NTSC interlaced raster count timing.
2018-04-11 08:00:37 -04:00
Thomas Harte
0b4b6f4aec
Tweaks luminances and reintroduces late-to-zero line counts.
2018-04-10 23:05:18 -04:00
Thomas Harte
cf6f6c5c15
Eliminates the full_frame_counter_ and slightly tweaks NTSC raster timing.
2018-04-08 18:51:20 -04:00
Thomas Harte
f541986333
Switches to more normative preincrement.
2018-04-08 18:50:42 -04:00
Thomas Harte
1c5972f7b0
Ensures NTSC raster count rollover; previously it was positing a line '261' for half of '0'.
2018-04-08 16:18:41 -04:00
Thomas Harte
3e846f89a1
Introduces different clipping zones for NTSC and PAL output.
2018-04-05 21:25:19 -04:00
Thomas Harte
60c1da6a66
Causes the 6560 to obey set_sample_volume_range
.
...
Thereby resolves a clipping issue.
2018-04-05 21:04:46 -04:00
Thomas Harte
0ee40e8556
Reintroduces 90% crop for VIC output.
2018-03-31 20:57:45 -04:00
Thomas Harte
912791d3d4
Causes the s-video path correctly to function.
2018-03-30 18:24:18 -04:00
Thomas Harte
163a61dd63
Corrects SVideo-as-composite output; the Atari and Vic-20 now both supply svideo.
2018-03-30 13:16:18 -04:00
Thomas Harte
33281b9d89
Introduces S-Video as a video signal type at the interface level.
2018-03-30 10:25:41 -04:00
Thomas Harte
e1aa3e5a7f
Imports chrominances from the TED documentation. They seem to apply to the VIC-I also.
2018-03-29 20:04:37 -04:00
Thomas Harte
3b26e0a7c5
Tweaks NTSC colour generation.
2018-03-26 21:22:06 -04:00
Thomas Harte
a776bec46a
Tweaks PAL colours for the 6560 to be closer to screenshots found online.
2018-03-26 19:02:16 -04:00
Thomas Harte
a301964bd0
Ensures all audio queues are fully merged before machine destruction.
...
Thereby avoids a race condition.
2018-03-22 21:59:19 -04:00
Thomas Harte
48737a32a7
Introduces formal setting of the output volume to SampleSource
.
...
Previously every output device was making its own decision. Which is increasingly less sustainable due to the CompoundSource.
2018-03-09 13:23:18 -05:00
Thomas Harte
705d53cc21
Picks a phase for the TMS empirically.
2018-03-03 13:53:00 -05:00
Thomas Harte
3c5a8d9ff3
Adds Super Game Module support for the ColecoVision.
2018-03-03 13:08:33 -05:00
Thomas Harte
ea13c7dd32
Implements multicolour mode on the TMS.
2018-03-02 23:08:01 -05:00
Thomas Harte
86239469e7
Allows SN76489 consumers to apply an additional divider that reduces computation.
2018-03-01 18:51:05 -05:00
Thomas Harte
7890506b16
Gives the SN76489 its proper dividers and personalities.
2018-02-28 22:36:03 -05:00
Thomas Harte
5b854d51e7
Corrects out-of-bounds access.
2018-02-27 22:45:45 -05:00
Thomas Harte
d4df101ab6
Makes a first attempt at implementing the SN76489.
2018-02-27 22:25:12 -05:00
Thomas Harte
0ad2676640
Adds a class for the SN76489 and wires it into the ColecoVision.
2018-02-26 22:04:34 -05:00
Thomas Harte
cabad6fc05
Optimises the inner TMS loops slightly.
2018-02-21 21:29:17 -05:00
Thomas Harte
2fe0ceb52a
Sets TMS input gamma.
2018-01-13 22:19:41 -05:00
Thomas Harte
2f59226300
Fixes: DiskROM drive motor control, track_for_sectors' sides.
2018-01-07 20:02:40 -05:00
Thomas Harte
793ef68206
Implements unconditional force interrupt for the WD.
2018-01-07 19:42:38 -05:00
Thomas Harte
2ffde4c3c2
Corrects SCC volume errors.
...
Which were leading to substantial overflow.
2018-01-07 09:59:00 -05:00
Thomas Harte
57ddfcd645
Corrects AY counter type.
2018-01-06 23:16:01 -05:00
Thomas Harte
fc16e8eb8c
Makes first attempt at actually implementing the SCC.
2018-01-06 23:15:42 -05:00
Thomas Harte
655b971976
Establishes that there is such as a thing as a Konami SCC.
...
Creates one, ensures it appears in memory when intended to, lets it handle reads and writes. It currently does nothing.
2018-01-06 20:15:55 -05:00
Thomas Harte
bcc7ad0c30
Corrects bad TMS sprite selections on the top row of the screen.
2018-01-06 16:26:11 -05:00
Thomas Harte
2dc1d4443e
Separates LowpassFilter and SampleSource.
2017-12-18 21:39:23 -05:00
Thomas Harte
f8a2459c91
Corrects two lingering adaptation errors in the Vic-20.
2017-12-17 21:43:08 -05:00
Thomas Harte
ac80d10cd8
Separates the component parts of running an audio stream: task deferral, filtering and generation.
...
Walking towards improving opportunities for composition.
2017-12-17 21:26:06 -05:00
Thomas Harte
ec4c259695
Removes unused file.
2017-12-14 21:19:09 -05:00
Thomas Harte
ad50b6b1fb
Corrects TMS' get_time_until_interrupt
when the next interrupt is exactly a frame away.
2017-12-14 21:12:51 -05:00
Thomas Harte
3da323c657
Corrects lingering free TMS read.
2017-12-14 20:30:56 -05:00
Thomas Harte
aca7842ca4
Better documents and tidies the TMS9918.
2017-12-14 20:27:26 -05:00
Thomas Harte
c36de4f640
Attempts real VRAM access timings, correcting a frame timing error as I go.
2017-12-13 22:37:27 -05:00
Thomas Harte
5d0c33d545
Corrects occasional TMS sprite glitching.
2017-12-12 22:19:33 -05:00
Thomas Harte
b0616ee10c
Adds one-before-the-graphics as a line for video collection.
...
Thereby corrects sprites on line 0.
2017-12-12 21:35:33 -05:00
Thomas Harte
798cdba979
8255: update_outputs now affects only those ports designated as outputs.
2017-12-10 17:55:37 -05:00
Thomas Harte
f957344ac4
Corrects TMS failure to show background through tile layer.
2017-12-09 23:15:04 -05:00
Thomas Harte
b3fbd0f352
Tidies up some of the TMS' magic constants.
2017-12-09 23:08:07 -05:00
Thomas Harte
042edc72f7
Adjusts TMS declared timing so as to be in-phase with an NTSC clock, and adopts an alternative palette.
2017-12-09 22:28:34 -05:00
Thomas Harte
943418c434
Reformulates TMS sprite plotting to set the collision flag and to support magnified sprites.
2017-12-09 20:30:12 -05:00
Thomas Harte
7d7e2538bd
Introduces a computationally simplified inner loop for TMS graphics modes, modelled on that for text.
2017-12-09 16:02:33 -05:00
Thomas Harte
7a544731e2
Makes minor tidiness improvements to the TMS.
2017-12-08 22:20:21 -05:00
Thomas Harte
e1914b4f16
Attempts to add a proper intermediate buffer for sprites to allow the split of collection and output.
2017-12-08 22:12:39 -05:00
Thomas Harte
8653eb8b55
Corrects various latent errors in optimised TMS video collection.
2017-12-06 20:24:29 -05:00
Thomas Harte
a4f0a260fd
Reformulates the TMS graphics mode fetch loop to try to eliminate heavy conditionality. Temporarily introduces some sprite selection issues.
2017-12-05 22:39:03 -05:00
Thomas Harte
d4a53e82bb
Replaces manual retread of memcpy
with standard memcpy
.
2017-12-05 18:21:34 -05:00
Thomas Harte
6eedc99286
Makes substantial optimisations to text mode.
...
Character optimisations to come.
2017-12-04 22:18:51 -05:00
Thomas Harte
a473338abe
Makes minor type conversion fixes.
2017-12-03 22:24:48 -05:00
Thomas Harte
ad3df36c20
Corrects sprite information collection to cover all four.
2017-12-03 14:51:55 -05:00
Thomas Harte
38b11893e8
Takes first steps towards sprite display on the TMS.
2017-12-02 22:13:43 -05:00
Thomas Harte
e4534775b0
Cleans up and zooms in on the TMS slightly.
2017-12-02 17:48:31 -05:00
Thomas Harte
fe0cdc8d69
Corrects colour fetching in TMS Graphics II to be a function of row.
2017-12-02 16:10:29 -05:00
Thomas Harte
ca26ce8400
Slightly corrects style errors in the Cartridge hierarchy, and introduces mapping of .ROM to the MSX when appropriate.
2017-12-02 16:01:30 -05:00
Thomas Harte
d3dd8f3f2a
Implements screen 2 addressing.
2017-12-02 14:05:52 -05:00
Thomas Harte
3c8d2d579d
Resolves remaining sources of text mode instability.
2017-11-30 22:48:07 -05:00
Thomas Harte
edcbb3dfed
Tidies code a little and thereby uncovers and corrects one cause of output instability.
2017-11-30 22:19:53 -05:00
Thomas Harte
9c8158753e
Makes a first attempt at displaying text mode.
2017-11-30 21:35:26 -05:00
Thomas Harte
ee84f33ab5
Ensures that the 9918 admits that it is the source of interrupts.
2017-11-29 21:33:43 -05:00
Thomas Harte
aa4eef41d8
Seeks to introduce MSX interrupts.
2017-11-29 20:31:55 -05:00
Thomas Harte
ecd7d4731b
Advances emulation to showing what looks like appropriate text on screen.
2017-11-28 21:27:15 -05:00
Thomas Harte
563aa051e4
Simplifies code a little and gives something on screen.
2017-11-28 21:19:28 -05:00
Thomas Harte
642bb8333f
Introduces something of a first attempt at graphics collection and display. An unsuccessful attempt.
2017-11-28 21:10:30 -05:00
Thomas Harte
c558e86e03
Adds border colour output.
2017-11-27 22:05:40 -05:00
Thomas Harte
dbb14ea2e2
Corrects counting deficiencies that could produce an unstable display.
2017-11-27 21:36:12 -05:00
Thomas Harte
173e16b107
Corrects the 9918 so that it terminates.
2017-11-27 19:48:04 -05:00
Thomas Harte
7d2adad67e
Adds the absolute most basic version of in-frame time keeping, to display a white square.
2017-11-27 19:43:33 -05:00
Thomas Harte
d33612def5
Ensures the MSX provides a clock to the VDP.
2017-11-26 20:07:30 -05:00
Thomas Harte
9cb6ca3440
Adds elementary decoding of VDP accesses.
2017-11-26 20:01:11 -05:00
Thomas Harte
0eb5dd9688
Introduces the fundamentals of bus routing for the MSX.
2017-11-26 16:47:59 -05:00
Thomas Harte
a14b53a9ab
Adds a TMS9918 skeleton plus enough in the MSX to get to a blank screen in SDL/kiosk mode.
2017-11-26 13:28:26 -05:00
Thomas Harte
c827d14d97
Corrects various GCC warnings across the 6560, CPC, TIA, Oric video and elsewhere.
2017-11-12 17:17:27 -05:00
Thomas Harte
5408efe9b5
Flags obvious default options within the 6560, Vic-20 and DynamicMachine.
2017-11-12 16:41:09 -05:00
Thomas Harte
6d80856f02
Attempts to eliminate warnings around a meaningless value and an unused label in the 8272.
2017-11-12 16:34:51 -05:00
Thomas Harte
4778616fd7
Eliminates unused result and unused label.
2017-11-12 16:30:23 -05:00
Thomas Harte
5aef81cf24
Commutes cross-platform #pragma mark
s to //MARK:
s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
5b6ea35d96
Corrects initialisation ordering for the ZX80/81, C1540 and AY-3-8910.
2017-11-10 22:31:27 -05:00
Thomas Harte
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
Thomas Harte
ff7ba526fb
Corrects improper initialisation order on the 6560.
2017-11-10 22:05:35 -05:00
Thomas Harte
cb015c83e1
Eliminated C99-style struct initialisations.
2017-11-10 19:14:19 -05:00
Thomas Harte
c0055a5a5f
Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
2017-11-09 22:04:49 -05:00
Thomas Harte
f95515ae81
Eliminates a large number of instance of end-of-line tabs.
2017-11-07 22:51:06 -05:00
Thomas Harte
ad9df4bb90
Commutes uint8_t *
, uint16_t *
, uint32_t *
, size_t
, off_t
and long
to functional-style casts.
2017-10-21 22:30:15 -04:00
Thomas Harte
ec999446e8
Commutes int
and unsigned
casts to the functional style.
2017-10-21 21:00:40 -04:00
Thomas Harte
5e3e91373a
Switches all unsigned int
and double
casts to functional style.
2017-10-21 19:49:04 -04:00
Thomas Harte
91b867a7b3
Ensures full 8272 instance state initialisation.
2017-10-17 22:11:01 -04:00
Thomas Harte
3944e734d3
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-17 22:10:28 -04:00
Thomas Harte
97a2be71e3
Introduces flush_tracks to Drive, while switching its interface to using Track::Address and adjusting associated integer types.
2017-10-06 21:45:12 -04:00
Thomas Harte
edb9fd301c
Begins this project's conversion to functional-style casts.
2017-10-03 22:04:15 -04:00
Thomas Harte
c7f27b2db4
Renames MFM.[c/h]pp as per its new remit: encoding only.
2017-09-24 21:40:43 -04:00
Thomas Harte
2a08bd9ecc
Factors shifting plus stateful [M]FM token recognition out of the MFMDiskController.
...
Given the proliferation of MFM-related classes, establishes a subdirectory for them.
2017-09-24 20:07:56 -04:00
Thomas Harte
698e4fe550
Tidies the Disk
file hierarchy.
2017-09-22 22:39:23 -04:00
Thomas Harte
d6a5f9a29e
Revokes unnecessary change.
2017-09-16 18:24:13 -04:00
Thomas Harte
0d84b4b9dd
Removes some redundant end_writing calls.
2017-09-16 17:09:17 -04:00
Thomas Harte
98751e6ac8
Ensures that all result phases are exactly the intended length by replacing accumulation with assignment.
...
Also attempts a different version of control mark behaviour. Experiments.
2017-09-15 22:59:26 -04:00
Thomas Harte
35fe4d50d4
Adds command termination upon drive becoming unready, and copies head and drive selection into ST0.
2017-09-15 20:26:41 -04:00
Thomas Harte
4d4a0cf1d2
Puts the disk controller back into the loop with knowledge about reading mode, and uses that knowledge to cut off the PLL.
2017-09-14 22:30:40 -04:00
Thomas Harte
b62f3e726a
Adds a start-of-execution-phase get-out for drives that aren't ready.
2017-09-12 20:43:53 -04:00
Thomas Harte
2f13517f38
Adjusts the 1770 not to talk directly to the drive about motor status.
2017-09-11 22:10:56 -04:00
Thomas Harte
d3c385b471
Separates the 8272's drive selection signalling from actual drive ownership.
...
Thereby returns working motor control to the CPC.
2017-09-11 21:25:26 -04:00
Thomas Harte
96bf133924
Withdraws requirement for DiskController users to specify a PLL multiplier or to provide rotation speed.
...
In the latter case because it's no longer of any interest to the controller, and in the former because I'd rather it be picked automatically.
2017-09-10 22:56:05 -04:00
Thomas Harte
0622187ddf
Strips Controller of all capabilities now housed on the Drive.
2017-09-10 19:23:23 -04:00
Thomas Harte
90c7056d12
Started devolving timed event loop logic down to the drives, moving them closer to modelling real life.
2017-09-10 14:43:20 -04:00
Thomas Harte
ff510f3b84
Explicitly disallows copying of VIAs, and marks the constructor as noexcept.
2017-09-05 21:21:23 -04:00
Thomas Harte
7fd6699e0b
Corrects comment indentation.
2017-09-05 21:15:15 -04:00
Thomas Harte
450712f39c
Improves and corrects 6522 header documentation.
2017-09-04 14:32:34 -04:00
Thomas Harte
24b3faa427
Deconstitutes the 6522 into component parts, templated and non-templated.
...
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
2017-09-04 14:26:04 -04:00
Thomas Harte
b30bb2a234
Adds an initial implementation of display skew, as a completely live property.
2017-08-29 22:16:40 -04:00
Thomas Harte
334afbc710
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 18:13:55 -04:00
Thomas Harte
17c13624e5
Improved comments.
2017-08-27 18:11:40 -04:00
Thomas Harte
113349d272
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 18:10:07 -04:00
Thomas Harte
bdda701207
Reverts previous unevidenced change.
2017-08-26 22:58:16 -04:00
Thomas Harte
487fe83dca
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 17:54:54 -04:00
Thomas Harte
6c5a03187b
Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
2017-08-26 17:22:48 -04:00
Thomas Harte
7d7aa2f5d5
Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
2017-08-26 14:37:03 -04:00
Thomas Harte
28550c0227
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 13:56:23 -04:00
Thomas Harte
6e99169348
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 12:59:59 -04:00
Thomas Harte
3caa4705ca
Limits sync counter size.
2017-08-26 12:31:19 -04:00
Thomas Harte
039aed1bd1
Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
2017-08-25 21:26:01 -04:00
Thomas Harte
a914eadc85
Ensured that register 6 is checked on every loop.
2017-08-22 22:17:45 -04:00
Thomas Harte
e956740c56
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-22 21:54:48 -04:00
Thomas Harte
e88a51e75e
Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
2017-08-20 12:05:00 -04:00
Thomas Harte
2d9efccc98
Introduced a master 'is sleeping' flag. I'm starting to think there's a pattern forming here.
2017-08-20 10:43:53 -04:00
Thomas Harte
8ce46b6e49
Having spotted that I was using my single-character loop counter names incorrectly (quelle surprise!), got a bit more explicit. Also flattened into a single loop so that I can break rather than returning.
2017-08-20 10:32:09 -04:00
Thomas Harte
669e0caff5
Ensured the head_unload_delay values are properly seeded, and generalised the quick escape.
2017-08-19 22:06:56 -04:00
Thomas Harte
e208f03636
Corrects the US colour palette, effectively undoing what was a mistaken adjustment for the time when Oric-centric phase alignment was built into the CRT based on a false calculation that it wouldn't affect the machines that generate chrominance functionally.
2017-08-16 09:58:34 -04:00