Nate Begeman
14d12caf1d
Enable SSE4 codegen and pattern matching.
...
Add some notes to the README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-11 04:19:36 +00:00
Nate Begeman
ab5d56c6b9
xmm0 variable blends
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46931 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:47:57 +00:00
Nate Begeman
fea2be50b9
memopv16i8 had wrong alignment requirement, would have broken pabsb
...
pabs{b,w,d} are not two address
fix extract-to-mem sse4 ops
add sse4 vector sign extend nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46915 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-09 23:46:37 +00:00
Nate Begeman
1426d52cab
Skeleton of insert and extract matching, more to come
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46902 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-09 01:38:08 +00:00
Nate Begeman
204e84e138
The rest of the SSE4.1 intrinsic patterns that are obvious to me. Getting
...
Evan's help with the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46697 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 06:00:24 +00:00
Nate Begeman
2f6f1c02ca
Some more SSE 4.1 intrinsic patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 05:34:34 +00:00
Nate Begeman
63ec90a6a8
SSE 4.1 Intrinsics and detection
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
Chris Lattner
d43d00cf3a
Significantly simplify and improve handling of FP function results on x86-32.
...
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
Chris Lattner
f77e037309
add some missing flags.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45859 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-11 06:59:07 +00:00
Chris Lattner
ba7e756c22
Start inferring side effect information more aggressively, and fix many bugs in the
...
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects. It would be really nice if we could
write patterns for copy instructions.
I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 07:59:24 +00:00
Chris Lattner
dd41527a7d
remove explicit sets of 'neverHasSideEffects' that can now be
...
inferred from the instr patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45824 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 05:45:39 +00:00
Chris Lattner
834f1ce031
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-06 23:38:27 +00:00
Chris Lattner
4ee451de36
Remove attribution from file headers, per discussion on llvmdev.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Evan Cheng
700a0fba97
Fix JIT encoding for CMPSD as well.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45268 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-20 19:57:09 +00:00
Bill Wendling
627c00b663
Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
...
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45132 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-17 23:07:56 +00:00
Chris Lattner
d7610e16fc
Fix the JIT encoding of cmp*ss, which aborts with this assertion currently:
...
X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'
I *think* this is right, but Evan, please verify. It also looks like
CMPSDrr and maybe others are missing this info. Evan, plz investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45074 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-16 20:12:41 +00:00
Evan Cheng
7a831ce85f
Make better use of instructions that clear high bits; fix various 2-wide shuffle bugs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45058 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-15 03:00:47 +00:00
Evan Cheng
6e141fd048
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-12 23:12:09 +00:00
Evan Cheng
1076210ee3
Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44669 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-06 22:14:22 +00:00
Chris Lattner
8a594489bf
Fix a long standing deficiency in the X86 backend: we would
...
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-25 00:24:49 +00:00
Nate Begeman
b348d18caf
Add support for vectors to int <-> float casts.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44204 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-17 03:58:34 +00:00
Dale Johannesen
c784208a73
Add missing SSE builtins: CVTPD2PI, CVTPS2PI,
...
CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
Arnold Schwaighofer
48abc5cf6b
Corrected many typing errors. And removed 'nest' parameter handling
...
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12 21:30:57 +00:00
Dale Johannesen
83e105c600
Add missing argument to PALIGNR
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42874 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11 20:58:37 +00:00
Evan Cheng
c231e8c8a5
Added DAG xforms. e.g.
...
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42677 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-06 02:46:29 +00:00
Evan Cheng
fef922a4d5
Typo. X86comi doesn't read / write chain's.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42492 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-01 18:12:48 +00:00
Evan Cheng
e5f6204cd5
Enabling new condition code modeling scheme.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-29 00:00:36 +00:00
Evan Cheng
0488db9b99
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
...
all the kinks are worked out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42285 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-25 01:57:46 +00:00
Dale Johannesen
f1fc3a8fa6
Fix PR 1681. When X86 target uses +sse -sse2,
...
keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42246 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-23 14:52:20 +00:00
Evan Cheng
24f2ea3971
Add implicit def of EFLAGS on those instructions that may modify flags.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-14 21:48:26 +00:00
Evan Cheng
071a279e94
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 19:55:27 +00:00
Dan Gohman
1ab79897e2
Avoid storing and reloading zeros and other constants from stack slots
...
by flagging the associated instructions as being trivially rematerializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41775 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-07 21:32:51 +00:00
Evan Cheng
2f39426ec9
Mark load instructions with isLoad = 1.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41595 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 05:49:43 +00:00
Bill Wendling
01284b4d55
64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment.
...
Make a 'memop' pattern just for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41017 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-11 09:52:53 +00:00
Bill Wendling
ae9671b838
For kicks, I though it would be fun to use the correct opcode.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40985 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 09:00:17 +00:00
Bill Wendling
76d708b76f
Adding SSSE3 intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
Dan Gohman
7f55fcbc6b
Fix the alignment requirements of several unpck and shuf instructions.
...
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40756 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 21:17:01 +00:00
Dan Gohman
f3372d1d64
Fix pastos in vector arithmetic intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40754 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 21:06:40 +00:00
Dan Gohman
73a902b228
Mark the SSE and MMX load instructions that
...
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 14:27:55 +00:00
Evan Cheng
c5dd54154a
Missing Requires.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40691 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 21:42:24 +00:00
Dan Gohman
b1576f56c8
Change the x86 assembly output to use tab characters to separate the
...
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-31 20:11:57 +00:00
Evan Cheng
c64a1a921c
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-31 08:04:03 +00:00
Dan Gohman
d300622eba
Re-apply 40504, but with a fix for the segfault it caused in oggenc:
...
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40555 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 17:16:43 +00:00
Evan Cheng
3e22947d9a
Reverting 40504 for now. It's breaking oggenc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40547 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 01:37:47 +00:00
Dan Gohman
1704c2f9b9
Fix a whitespace difference between CMPSSrr and CMPSDrr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40528 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 15:11:50 +00:00
Dan Gohman
d3283832aa
Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
...
x86 target, replacing them with the new alignment attributes on memory
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40504 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 00:31:09 +00:00
Evan Cheng
b4162fd393
Because we promote SSE logical ops and loads to v2i64, we often end up generate
...
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40076 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 00:27:43 +00:00
Evan Cheng
31d3a65052
Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40070 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 23:34:10 +00:00
Evan Cheng
64d80e3387
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Dan Gohman
4106f3714e
Implement initial memory alignment awareness for SSE instructions. Vector loads
...
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40015 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-18 20:23:34 +00:00
Dan Gohman
2038252c6a
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
...
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38478 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 00:05:58 +00:00
Dale Johannesen
849f214a4e
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-03 00:53:03 +00:00
Dan Gohman
d45eddd214
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 00:48:07 +00:00
Dan Gohman
32791e06d8
Make minor adjustments to whitespace and comments to reduce differences
...
between SSE1 instructions and their respective SSE2 analogues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37718 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-25 15:44:19 +00:00
Dan Gohman
01976307d2
Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37717 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-25 15:19:03 +00:00
Dan Gohman
82a87a0172
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:48:05 +00:00
Evan Cheng
174f803395
Added missing patterns for UNPCKH* and PUNPCKH*.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37172 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-17 18:44:37 +00:00
Bill Wendling
ddd35321fb
Non-algorithmic change. Moved definitions around into separate sections
...
for SSE1, SSE2, SSE3, and SSSE3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36656 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 23:11:52 +00:00
Dan Gohman
23420c09c0
Fix the spelling of the prefetchnta instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36256 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 14:09:14 +00:00
Bill Wendling
bb1ee05253
Add support for our first SSSE3 instruction "pmulhrsw".
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 22:10:25 +00:00
Evan Cheng
768143547b
Mark re-materializable instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35230 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-21 00:16:56 +00:00
Chris Lattner
569bdc7bb7
add missing braces
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34905 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04 06:13:52 +00:00
Evan Cheng
58866f43fa
How the heck did I forget patterns for llvm.x86.sse2.cmp.sd?
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34434 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-20 00:39:09 +00:00
Evan Cheng
73d6cf12ad
- FCOPYSIGN custom lowering bug. Clear the sign bit of operand 0 first before
...
or'ing in the sign bit of operand 1.
- Tweaking: rather than left shift the sign bit, fp_extend operand 1 first
before taking its sign bit if its type is smaller than that of operand 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32932 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-05 21:37:56 +00:00
Evan Cheng
68c47cba35
With SSE2, expand FCOPYSIGN to a series of SSE bitwise operations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32900 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-05 07:55:56 +00:00
Evan Cheng
c9f0923f17
- Rename MOVDSS2DIrr to MOVSS2DIrr for consistency sake.
...
- Add MOVDI2SSrm and MOVSS2DImr to fold load / store for i32 <-> f32 bit_convert
patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32582 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-14 19:43:11 +00:00
Chris Lattner
f3597a13ae
If we have ScalarSSE, we can select bitconvert into single instructions.
...
This compiles bitcast.ll:test3/test4 into:
_test3:
movd %xmm0, %eax
ret
_test4:
movd %edi, %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-05 18:45:06 +00:00
Evan Cheng
ebf01d63b0
Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31795 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-16 23:33:25 +00:00
Evan Cheng
8ca29326e1
Don't dag combine floating point select to max and min intrinsics. Those
...
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.
This fixes PR996.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31645 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10 21:43:37 +00:00
Evan Cheng
6e56e2c602
Fixed a bug which causes x86 be to incorrectly match
...
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31519 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-07 22:14:24 +00:00
Chris Lattner
3751844b39
remove dead/redundant vars
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31435 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-03 23:48:56 +00:00
Evan Cheng
acf7f2e3a9
Fix ldmxcsr JIT encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31343 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-01 06:53:52 +00:00
Evan Cheng
f686d9b71f
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31228 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-27 21:08:32 +00:00
Evan Cheng
009073d839
X86ISD::PEXTRW 3rd operand type is always target pointer type.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31185 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-25 21:35:05 +00:00
Evan Cheng
82a9164fb4
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30892 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 21:06:01 +00:00
Evan Cheng
f2ea84aadc
Don't go too crazy with these AddComplexity. Try matching shufps with load
...
folding first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30848 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09 21:42:15 +00:00
Evan Cheng
466685d41a
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09 20:57:25 +00:00
Chris Lattner
3a7cd951c1
completely disable folding of loads into scalar sse instructions and provide
...
a framework for doing it right. This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.
Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30817 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 21:55:32 +00:00
Chris Lattner
6f98773203
convert packed FP add/sub/mul/div to use a multiclass.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30815 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 21:17:13 +00:00
Chris Lattner
941cc4561c
one multiclass now defines all 8 variants of binary-scalar-sse-fp operations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30814 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 20:55:57 +00:00
Chris Lattner
d2c99d5f7a
Switch ADD/MUL/DIV/SUB scalarsse fp ops to a multiclass
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30813 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 20:35:44 +00:00
Chris Lattner
6970eda7ca
Random acts of shrinkage
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30812 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 19:49:05 +00:00
Chris Lattner
a7ebe556c8
Convert pand/por/pxor to use multiclass
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30811 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 19:37:30 +00:00
Chris Lattner
70f4f2e513
Convert some more instructions over to use a new multiclass.
...
Fix a bug where the asmstring for PSUBQrm was wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30810 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 19:34:33 +00:00
Chris Lattner
5650eeb38e
Fix a bug where PADDQrm printed paddd instead of paddq.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 19:15:46 +00:00
Chris Lattner
7c47f9a7ea
Add multiclass for SSE2 instructions that correspond to simple binops.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30808 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 19:14:49 +00:00
Chris Lattner
45e123c62a
rename:
...
PDI_binop_rm -> PDI_binop_rm_int
PDI_binop_rmi -> PDI_binop_rmi_int
to make it clear that these are for use with intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30807 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 19:02:31 +00:00
Chris Lattner
d4060cc989
Convert saturating PADD/PSUB's to use a multiclass
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30806 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 18:48:46 +00:00
Chris Lattner
8139e28a79
Convert PAVG*, PMADDWD, and PMUL* to use multiclasses.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30805 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 18:39:00 +00:00
Chris Lattner
3dca490ff0
Fix typo in packsswb instr definition, where the load had the wrong type.
...
This allows us to use the multiclass for other packs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 18:23:58 +00:00
Chris Lattner
783d45ef14
handle pmin/pmax with multiclasses
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30800 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 07:49:33 +00:00
Chris Lattner
7733799464
simplify pack and shift intrinsics with multiclasses
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30797 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 07:06:17 +00:00
Chris Lattner
01998742c3
Use a multiclass to simplify 'SSE2 Integer comparison'
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30796 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 06:47:08 +00:00
Chris Lattner
736c020fc8
move class defns close to uses to make it easier to read
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30795 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 06:33:36 +00:00
Chris Lattner
fb996ee727
simplify horizontal op definitions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30794 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 06:31:41 +00:00
Chris Lattner
3b57a833a5
remove more unneeded type info
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30793 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 06:27:03 +00:00
Chris Lattner
aab370db24
remove unneeded definitions and type info
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30792 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 06:19:41 +00:00
Chris Lattner
15258d5f9d
remove some unneeded type info
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30791 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 06:17:43 +00:00
Chris Lattner
845fb75536
simplify patterns by merging in operand info
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30790 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:50:25 +00:00
Chris Lattner
d1b651d5de
Factor operands into packed unary classes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30789 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:47:20 +00:00
Chris Lattner
dc5aa21b10
remove dead/duplicate instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30788 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:41:52 +00:00
Chris Lattner
a0ea63db75
Pull operand info up into parent class for scalar sse intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30787 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:26:13 +00:00
Chris Lattner
86c1b3a2fd
convert the sole sd unary intrinsic to a multiclass for consistency
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30786 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:19:31 +00:00
Chris Lattner
3b8378552e
pull operand string into the multiclass
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30785 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:13:26 +00:00
Chris Lattner
9498ed8ac9
Remove RSQRTSS[rm] RCPSS[rm], which are dead.
...
Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30784 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 05:09:48 +00:00
Chris Lattner
4cc84edd3b
eliminate redundancy
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30783 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-07 04:52:09 +00:00
Evan Cheng
485130fbf4
These don't have immediate operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30694 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-03 06:55:11 +00:00
Evan Cheng
734503be59
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
...
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30241 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-11 02:19:56 +00:00
Evan Cheng
23b3122c44
JIT encoding bug.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30112 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-05 05:59:25 +00:00
Evan Cheng
55371739de
Can't commute shufps. The high / low parts elements come from different vectors.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29275 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-25 20:25:40 +00:00
Evan Cheng
206ee9d86c
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
...
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29042 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-07 08:33:52 +00:00
Evan Cheng
775ff18257
Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28984 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-29 18:04:54 +00:00
Evan Cheng
a8e83ec8c3
Always use xorps to clear XMM registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28979 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-29 00:34:23 +00:00
Chris Lattner
30da68acce
Remove some ugly now-redundant casts.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28864 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 00:25:29 +00:00
Chris Lattner
a973993c0c
Fix some mismatched type constraints
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28862 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 00:12:37 +00:00
Evan Cheng
b21495043e
Minor clean up.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28860 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-19 19:25:30 +00:00
Evan Cheng
015188ffbc
Type of vector extract / insert index operand should be iPTR.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28796 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15 08:14:54 +00:00
Evan Cheng
190717d3cf
Rename instructions for consistency sake.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28594 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-31 19:00:07 +00:00
Evan Cheng
9d09b89f39
Select vector_shuffle v1, undef <2, 3, ?, ?> to MOVHLPS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28582 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-31 00:51:37 +00:00
Evan Cheng
b5e406afc3
MAXP{D|S} and MINP{D|S} are commutable.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28578 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30 23:47:30 +00:00
Evan Cheng
efeaed8fb4
Commute shufps / shufpd.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28577 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30 23:34:30 +00:00
Evan Cheng
ccba76bb25
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28565 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30 20:26:50 +00:00
Evan Cheng
069287d460
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 07:21:53 +00:00
Chris Lattner
bd04aa5796
Teach the code generator to use cvtss2sd as extload f32 -> f64
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28131 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-05 21:35:18 +00:00
Evan Cheng
9e062ed516
Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when
...
movlps cannot be used (e.g. when load from m64 has multiple uses).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28089 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-03 20:32:03 +00:00
Evan Cheng
3d1be07141
Fix a typo.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27968 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-25 17:48:41 +00:00
Evan Cheng
a2137b592e
Explicitly specify result type for def : Pat<> patterns (if it produces a vector
...
result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27965 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-25 00:50:01 +00:00
Evan Cheng
a7fc64222a
Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is
...
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27964 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-24 23:34:56 +00:00
Evan Cheng
64e9769339
Some missing movlps, movhps, movlpd, and movhpd patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27960 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-24 21:58:20 +00:00
Evan Cheng
017dcc6e55
Now generating perfect (I think) code for "vector set" with a single non-zero
...
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
Evan Cheng
fd111b5be5
Prefer {p}unpack* and mov*dup over {p}shuf* as well.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27844 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 21:15:24 +00:00
Evan Cheng
2dadaea5d2
- Renamed AddedCost to AddedComplexity.
...
- Added more movhlps and movlhps patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27842 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 20:37:34 +00:00
Evan Cheng
f66a094cac
More mov{h|l}p{d|s} patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27836 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 18:20:17 +00:00
Evan Cheng
cc0e98c8ed
- More mov{h|l}ps patterns.
...
- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
are preferred over shufps in most cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27835 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 18:11:52 +00:00
Evan Cheng
f0d4e3d7c0
- PEXTRW cannot take a memory location as its first source operand.
...
- PINSRWrmi encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27818 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 21:59:43 +00:00
Evan Cheng
b7a5c527ae
Name change for clarity sake
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27816 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 21:55:35 +00:00
Evan Cheng
7b7bd57abd
Name change for clarity sake
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27814 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 21:29:50 +00:00
Evan Cheng
fb2a3b2964
Left a pattern out
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27813 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 21:29:08 +00:00
Evan Cheng
df2a1908b2
Fixed an encoding bug: movd from XMM to R32.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27807 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 18:19:00 +00:00
Evan Cheng
cdfc3c82a7
Use movss to insert_vector_elt(v, s, 0).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27782 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 22:45:49 +00:00
Evan Cheng
23b72005fa
Encoding bug
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27773 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 21:33:57 +00:00
Evan Cheng
083248e143
Errors in patterns preventing load folding
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27762 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 18:05:01 +00:00
Evan Cheng
06aef15843
movduprm, movshduprm bugs
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27734 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-16 18:11:28 +00:00
Evan Cheng
d8e8223ea1
Encoding bugs
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-16 07:02:22 +00:00
Evan Cheng
60d3fa24ba
More encoding bugs
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27722 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-15 06:10:09 +00:00
Evan Cheng
1af18985b8
pslldrm, psrawrm, etc. encoding bug
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27721 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-15 05:59:08 +00:00
Evan Cheng
7076e2daee
hsubp{s|d} encoding bug
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27720 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-15 05:52:42 +00:00
Evan Cheng
57ebe9fbf0
Silly bug
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27719 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-15 05:37:34 +00:00
Evan Cheng
9ab1ac5e99
Some clean up
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27715 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 23:32:40 +00:00
Evan Cheng
d953947d26
Last few SSE3 intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
Evan Cheng
f3e1b1d716
Misc. SSE2 intrinsics: clflush, lfench, mfence
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27699 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 07:43:12 +00:00
Evan Cheng
bb5c43e73d
pcmpeq* and pcmpgt* intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27685 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 01:39:53 +00:00
Evan Cheng
0ac8ea9a4f
psll*, psrl*, and psra* intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27684 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 00:14:05 +00:00
Evan Cheng
2b21ac6d4c
Doh. PANDrm, etc. are not commutable.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27668 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 18:11:28 +00:00
Evan Cheng
00586948aa
psad, pmax, pmin intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27647 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 06:11:45 +00:00
Evan Cheng
2f40b1b27e
Various SSE2 packed integer intrinsics: pmulhuw, pavgw, etc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27645 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:24:54 +00:00
Evan Cheng
49ac1bf1c4
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
Evan Cheng
a50a086341
Naming inconsistency.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27638 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:00:23 +00:00
Evan Cheng
d2a6d54f26
SSE / SSE2 conversion intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27637 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 23:42:44 +00:00
Evan Cheng
2c3ae37213
All "integer" logical ops (pand, por, pxor) are now promoted to v2i64.
...
Clean up and fix various logical ops issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27633 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 21:21:57 +00:00
Evan Cheng
91b740da12
Promote v4i32, v8i16, v16i8 load to v2i64 load.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27612 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 17:12:36 +00:00
Evan Cheng
d03db7a36c
Various SSE2 conversion intrinsics
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
Evan Cheng
397edeff50
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
...
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27599 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 22:28:25 +00:00
Evan Cheng
df3c33c57e
gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support
...
later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27591 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 18:04:57 +00:00
Evan Cheng
135c6a9d83
Misc. intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27590 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 17:35:57 +00:00
Evan Cheng
fcf5e21b96
movnt* and maskmovdqu intrinsics
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27587 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 06:57:30 +00:00
Evan Cheng
d6d1cbd692
Added support for _mm_move_ss and _mm_move_sd.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27575 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 00:19:04 +00:00
Evan Cheng
3d60df480a
Remove some bogus patterns; clean up.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27569 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:35:16 +00:00
Evan Cheng
56e73013c7
Added some missing shuffle patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27564 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 21:42:19 +00:00
Evan Cheng
aa9fb8c70e
movups / movupd
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27562 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 21:11:06 +00:00
Evan Cheng
f7c378e9ea
Conditional move of vector types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27556 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 07:23:14 +00:00
Evan Cheng
372db540d9
ldmxcsr and stmxcsr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27506 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 00:47:44 +00:00
Evan Cheng
664ade71b9
Added patterns for MOVHPSmr and MOVLPSmr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27497 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-07 21:20:58 +00:00
Evan Cheng
85c0965db1
A MOVPS2SSmr, i.e. _mm_store_ss, encoding bug.
...
Also MOVPDI2DIrr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27476 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-06 23:53:29 +00:00
Evan Cheng
5ced1d812e
- movlp{s|d} and movhp{s|d} support.
...
- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27474 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-06 23:23:56 +00:00
Evan Cheng
c6cb5bb679
POR encoded as PAND, yikes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27446 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-06 01:49:20 +00:00
Evan Cheng
6be2c58c8c
Support for comi / ucomi intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27444 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:38:46 +00:00
Evan Cheng
1d5a8cca00
Handle canonical form of e.g.
...
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 07:20:06 +00:00
Evan Cheng
ff65e38aaf
Added pslldq and psrldq.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27412 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 21:49:39 +00:00
Evan Cheng
8703be4ab6
Minor fixes + naming changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27410 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 19:12:30 +00:00
Evan Cheng
5333b7b8e2
PSHUF* encoding bugs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27405 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 18:40:36 +00:00
Evan Cheng
21760460b9
cmpps / cmppd encoding bug
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27393 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 03:04:07 +00:00
Evan Cheng
6e96740c6c
Compact some intrinsic definitions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27388 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 00:10:53 +00:00
Evan Cheng
97ac5fadb7
Some SSE1 intrinsics: min, max, sqrt, etc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27384 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 23:49:17 +00:00
Evan Cheng
20e3ed102b
Use movlpd to: store lower f64 extracted from v2f64.
...
Use movhpd to: store upper f64 extracted from v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27382 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 22:30:54 +00:00
Evan Cheng
11e15b38e9
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27377 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 20:53:28 +00:00
Evan Cheng
653159f4aa
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
...
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:55:24 +00:00
Evan Cheng
4b1734f70b
Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27310 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:29:33 +00:00
Evan Cheng
b067a1e7e6
Add support to use pextrw and pinsrw to extract and insert a word element
...
from a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27304 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 19:22:53 +00:00
Evan Cheng
7d9061e300
Make sure all possible shuffles are matched.
...
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27259 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-30 19:54:57 +00:00
Evan Cheng
1b32f22b0f
More logical ops patterns
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27257 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-30 07:33:32 +00:00
Evan Cheng
0876aa5178
Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27256 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-30 06:21:22 +00:00
Evan Cheng
c5fb2b14ca
Add 128-bit pmovmskb intrinsic support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27255 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-30 00:33:26 +00:00
Evan Cheng
591f740a40
Change SSE pack operation definitions to fit what the intrinsics expected.
...
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27254 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:53:14 +00:00
Evan Cheng
506d3dfa90
- Added some SSE2 128-bit packed integer ops.
...
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:07:14 +00:00
Evan Cheng
691c923e47
Need to special case splat after all. Make the second operand of splat
...
vector_shuffle undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 19:02:40 +00:00
Evan Cheng
5aa97b200b
Floating point logical operation patterns should match bit_convert. Or else
...
integer vector logical operations would match andp{s|d} instead of pand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27248 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 18:47:40 +00:00
Evan Cheng
475aecf467
- More shuffle related bug fixes.
...
- Whenever possible use ops of the right packed types for vector shuffles /
splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27246 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 03:04:49 +00:00
Evan Cheng
4f5633883b
- Only use pshufd for v4i32 vector shuffles.
...
- Other shuffle related fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27244 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 01:30:51 +00:00
Evan Cheng
c46349de29
Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
...
The source operands type are v4sf with upper bits passes through.
Added matching code for these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27240 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 23:51:43 +00:00
Evan Cheng
9bbfd4f68c
movlps and movlpd should be modeled as two address code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27221 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 07:01:28 +00:00
Evan Cheng
be296ac5ca
Typo
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27219 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 06:53:49 +00:00
Evan Cheng
2064a2b47e
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
...
* Bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27218 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 06:50:32 +00:00
Evan Cheng
4fcb922c70
- Clean up / consoladate various shuffle masks.
...
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27210 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 02:43:26 +00:00
Evan Cheng
0038e59803
Model unpack lower and interleave as vector_shuffle so we can lower the
...
intrinsics as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27200 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 00:39:58 +00:00
Chris Lattner
749b758b2e
unbreak the build
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27174 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 16:52:45 +00:00
Evan Cheng
a0b3afbe14
Use pcmpeq to generate vector of all ones.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27167 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 07:00:16 +00:00
Evan Cheng
ffea91e522
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 09:53:12 +00:00
Evan Cheng
c60bd97b94
Build arbitrary vector with more than 2 distinct scalar elements with a
...
series of unpack and interleave ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 09:37:23 +00:00
Evan Cheng
ecac9cb959
Added SSE cachebility ops
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27103 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:03:26 +00:00
Evan Cheng
7b1d34bc6c
Added 128-bit packed integer subtraction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 01:33:37 +00:00
Evan Cheng
7dda4052f5
Added CVTSS2SI.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27094 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 01:00:18 +00:00
Evan Cheng
bc4832bc64
Support for scalar to vector with zero extension.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 23:15:12 +00:00
Evan Cheng
c653d48022
Added LDMXCSR
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27087 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 22:28:37 +00:00
Chris Lattner
ac53eadc29
plug the intrinsics into the patterns for movmsk*
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27083 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:49:18 +00:00
Evan Cheng
386031a06f
Handle BUILD_VECTOR with all zero elements.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:29:27 +00:00
Evan Cheng
2c0dbd01d2
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 02:58:06 +00:00
Evan Cheng
14aed5e66b
Handle more shuffle cases with SHUFP* instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 01:18:28 +00:00
Evan Cheng
24dc1f5975
Following icc's lead: use movdqa to load / store 128-bit integer vectors
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26980 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 07:44:07 +00:00
Evan Cheng
3b047f7bfa
Add v4i32 <-> v4f32 bitconvert patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26969 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 02:36:37 +00:00
Evan Cheng
a971f6f967
Add 128-bit integer vector load and add (for testing).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 01:57:24 +00:00
Evan Cheng
0cea6d2b9c
SHUFP* are two address code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26959 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 20:08:18 +00:00
Evan Cheng
1bffadd7fb
- Supposely movlhps is faster / better than unpcklpd.
...
- Don't forget pshufd is only available with sse2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26956 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 19:16:21 +00:00
Evan Cheng
0188ecba85
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
...
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 18:59:22 +00:00
Evan Cheng
63d3300da1
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
...
PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 08:01:21 +00:00
Evan Cheng
2da953f77a
Fix PSHUF* and SHUF* jit code emission problems
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26949 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 07:10:28 +00:00
Evan Cheng
b9df0ca67b
Some splat and shuffle support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 02:53:00 +00:00
Evan Cheng
48090aa814
- Use movaps to store 128-bit vector integers.
...
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 23:01:21 +00:00
Evan Cheng
82521dd838
- Remove scalar to vector pseudo ops. They are just wrong.
...
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 07:09:35 +00:00
Evan Cheng
811ec1c92a
x86 ISD::SCALAR_TO_VECTOR support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26911 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 00:33:35 +00:00
Evan Cheng
ba753c61b7
Move a few things around.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 06:04:52 +00:00
Evan Cheng
c12e6c488e
Vector undef's
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26870 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 09:38:54 +00:00
Evan Cheng
2246f8449f
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26838 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-18 01:23:20 +00:00
Evan Cheng
06a8aa14b3
Move some pattern fragments to the right files.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26831 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 19:55:52 +00:00
Evan Cheng
470a6adc78
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 02:26:30 +00:00
Evan Cheng
4e4c71e423
One more round of reorg so sabre doesn't freak out. :-)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26303 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 20:00:20 +00:00
Evan Cheng
beb07e117d
A big more cleaning up.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 19:30:30 +00:00
Evan Cheng
bf156d1ae6
Moving things to their proper places.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 19:26:52 +00:00
Evan Cheng
ffcb95beab
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26300 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 19:13:53 +00:00