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13034 Commits

Author SHA1 Message Date
Anton Korobeynikov
747409a290 Move subtarget check upper for NEON reg-reg fixup pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 18:46:11 +00:00
Evan Cheng
f6c0bffa8d Trim unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 07:08:08 +00:00
Bob Wilson
af14e663ac For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 06:29:56 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:52:54 +00:00
Evan Cheng
b4db6a46e0 Clean up copyRegToReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85870 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:51:39 +00:00
Evan Cheng
3f4e47be0a Add QPR_8 as a superreg class of SPR_8 and DPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:50:57 +00:00
Ted Kremenek
92dbd0b320 Update CMake file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85861 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 04:14:12 +00:00
Anton Korobeynikov
7aaf94bb0d Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 01:04:26 +00:00
Anton Korobeynikov
ab453e0641 Revert r85049, it is causing PR5367 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:24:48 +00:00
Bob Wilson
b62d257cf5 Revert previous change to a comment. The BlockAddresses go in the 
constant pool so they don't get wrapped separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:02:05 +00:00
Bob Wilson
907eebd5a6 Put BlockAddresses into ARM constant pools. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 20:59:23 +00:00
Kevin Enderby
60131c0d0b Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should 
have been passed as a reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85823 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 20:14:39 +00:00
David Goodwin
2f54a2fd85 Fix schedule model for BFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 17:28:36 +00:00
Bob Wilson
31ba10b743 Hyphenate some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85808 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 17:10:37 +00:00
Bob Wilson
28989a8ddc Add support for BlockAddress values in ARM constant pools. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 16:59:06 +00:00
Bob Wilson
69e8445ced Prune unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85805 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 16:58:31 +00:00
Evan Cheng
d3e18fad7e These are done / no longer care. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:58:25 +00:00
Evan Cheng
e3b88fc01e Add an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:51:19 +00:00
Evan Cheng
7baae87d8f Unbreak ARMBaseRegisterInfo::copyRegToReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
2ae0eec1c0 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Anton Korobeynikov
2e1da9fea4 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
f95215f551 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:10:38 +00:00
Evan Cheng
e3ce8aab0a Fix a couple more places where we are creating ld / st instructions without memoperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 22:04:35 +00:00
Evan Cheng
48d8afab73 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 21:12:51 +00:00
Chris Lattner
43f44aa160 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85703 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 03:25:03 +00:00
Evan Cheng
de17fb6e4d Use cbz and cbnz instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 23:46:45 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 22:57:36 +00:00
Jim Grosbach
bcf2f2c159 Expand 64-bit logical shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304 Expand 64-bit arithmetic shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:38:01 +00:00
Evan Cheng
9eda68988e It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 03:39:36 +00:00
Kevin Enderby
9c41fa87ea Updates to the ARM target assembler for llvm-mc per review comments from 
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:55:57 +00:00
Bob Wilson
57f224a5a4 Add a note about Robert Muth's alternate jump table implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85624 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:22:46 +00:00
Dan Gohman
0115e164ba Fix MachineLICM to use the correct virtual register class when 
unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:18:41 +00:00
Bob Wilson
929ffa2414 Fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 20:13:25 +00:00
Rafael Espindola
c1382b745f This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 14:33:14 +00:00
Bob Wilson
ddb16df912 Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 05:45:42 +00:00
Dan Gohman
f705adbe5e Initial x86 support for BlockAddresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 01:28:02 +00:00
Jim Grosbach
95d9504d46 Dial back the realignment a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 00:08:40 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Jim Grosbach
84e58d03c9 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 02:41:21 +00:00
Bob Wilson
a597103c32 Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 20:46:46 +00:00
Bob Wilson
8d4de5abfa Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:26:41 +00:00
Evan Cheng
30c80211b6 fconsts and fconstd are obviously re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:19:56 +00:00
Jim Grosbach
ca5dfb71ba Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 17:33:28 +00:00
Evan Cheng
c59420867e Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:55:03 +00:00
Evan Cheng
89321166da X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85379 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:30:34 +00:00
Chris Lattner
0eeb913aa1 Previously, all operands to Constant were themselves constant. 
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85375 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 05:14:34 +00:00
Evan Cheng
39382427f1 Use fconsts and fconstd to materialize small fp constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:44:26 +00:00
Evan Cheng
a1eaa3c52b Add a second ValueType argument to isFPImmLegal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:43:28 +00:00
Dan Gohman
aa123224c4 Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides 
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:55:57 +00:00
Bob Wilson
04ea6e5150 Add an indirect branch pattern for ARM. Testcase will be coming soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:37:03 +00:00
Chris Lattner
ab21db79ef rename indbr -> indirectbr to appease the residents of #llvm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85351 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:19:10 +00:00
Bob Wilson
cd4f04d6bc Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 23:49:38 +00:00
Bill Wendling
c872e9c07d Add new note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85341 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 23:30:07 +00:00
Jim Grosbach
a6a99b4e16 Enable virtual register based frame index scavenging by default for ARM & T2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:52:29 +00:00
Bill Wendling
5a56927345 Move and clarify note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85334 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:48:31 +00:00
Jim Grosbach
3dab277857 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:45:39 +00:00
Bill Wendling
de020736c0 Note corrected. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85332 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:43:24 +00:00
Bill Wendling
d8499c9b7f Modify note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85331 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:40:45 +00:00
Bill Wendling
1ff2c485e2 Add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:34:43 +00:00
Chris Lattner
627b470981 cppbackend support for indbr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85312 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 21:24:48 +00:00
Chris Lattner
f0dca28da7 CBE support for indbr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85311 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 21:21:06 +00:00
Johnny Chen
90d7dcfdd9 Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:51:49 +00:00
Johnny Chen
eadeffb306 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:45:15 +00:00
Evan Cheng
eb2f969a4d Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 19:56:55 +00:00
Bob Wilson
f3b0d1a555 Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 19:52:03 +00:00
Johnny Chen
76b39e88e4 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 18:44:24 +00:00
Sanjiv Gupta
e70b897126 Remove unnecessary gotos to fall-thru successors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85257 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:40:24 +00:00
Johnny Chen
6a3b5eec89 Test commit. Added '.' to the comment line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:25:15 +00:00
Chris Lattner
1995051395 apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:01:03 +00:00
Rafael Espindola
f87611272b Correctly align double arguments in the stack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 14:09:44 +00:00
Evan Cheng
dd22a45acc Now VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:20:49 +00:00
Evan Cheng
699bebac4f Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:08:59 +00:00
Evan Cheng
162e30921d Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:45:59 +00:00
Victor Hernandez
046e78ce55 Remove FreeInst. 
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85176 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:43:48 +00:00
Bob Wilson
dda9583e51 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:59:12 +00:00
Bob Wilson
d9ecd3108f Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:42:13 +00:00
Bob Wilson
7e053bb33c Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:34:44 +00:00
Ted Kremenek
7c44beaf93 Update CMake files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85161 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:06:01 +00:00
Anton Korobeynikov
8b5af25a14 Revert r85134, it breaks mingw build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 18:40:24 +00:00
Sanjiv Gupta
be9e763697 Make PIC16 overlay a loadable pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85134 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 18:22:59 +00:00
David Goodwin
2e7be612d5 Break anti-dependence breaking out into its own class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 16:59:04 +00:00
Chandler Carruth
8b67f774e9 Move DataTypes.h to include/llvm/System, update all users. This breaks the last 
direct inclusion edge from System to Support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85086 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 01:35:46 +00:00
Jim Grosbach
dd5694203b of -> or 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 19:14:48 +00:00
Jim Grosbach
f639e9f9e6 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 18:55:46 +00:00
Sanjiv Gupta
e1ef91d275 Reapply 85006 with a minor fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 08:14:11 +00:00
Evan Cheng
4f54c1293a Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:53:28 +00:00
Evan Cheng
ed3ad212ec Don't forget subreg indices when folding load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:52:27 +00:00
Nick Lewycky
f5a86f45e7 Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:57:41 +00:00
Nick Lewycky
6726b6d75a Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:33:48 +00:00
Chris Lattner
a1e1446056 this is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85041 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:17:51 +00:00
Nick Lewycky
4a134afaef Remove ICmpInst::isSignedPredicate which was a reimplementation 
CmpInst::isSigned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85037 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 05:20:17 +00:00
Sanjiv Gupta
ecb28f2b49 Revert back 85006 for now as it breaks PIC16 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85008 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 18:19:41 +00:00
Sanjiv Gupta
209e6c69d9 Adding support for placing global objects in shared data memory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 18:02:44 +00:00
Evan Cheng
5a850beb2e 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 02:07:42 +00:00
Jim Grosbach
2f1abe2dae Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 00:19:24 +00:00
Jim Grosbach
7388037dd1 FIXME no longer applies. R12 and R3 are available for allocation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 23:07:42 +00:00
Chris Lattner
9ff9b34dd1 some stuff is done, we still have constantexpr simplification to do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 07:00:55 +00:00
Evan Cheng
c869d063d4 X86 needs critical path anti-dependency breaking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 05:57:35 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 23:19:17 +00:00
Bob Wilson
bac6ed4ba4 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 16:52:21 +00:00
Benjamin Kramer
1395d1df09 Shift art to the right to keep GCC from complaining about multi-line comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84849 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 09:28:49 +00:00
Evan Cheng
87689d3b70 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:48:32 +00:00
Evan Cheng
faf93aa233 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:47:35 +00:00
Evan Cheng
62d1723a9c Trim more includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 05:11:00 +00:00
Evan Cheng
268c79350e Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 05:08:49 +00:00
Chris Lattner
c5e5498058 fix warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84826 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 03:42:27 +00:00
Evan Cheng
8000c6c535 Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:40:00 +00:00
Anton Korobeynikov
f32df4ce3e Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected. 
Yay for ASCII graphics!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84808 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:16:00 +00:00
Jim Grosbach
41fff8c19a Missing piece of the ARM frame index post-scavenging conditionalization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 23:40:56 +00:00
Jim Grosbach
1d6827bbe9 Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 22:59:24 +00:00
Bob Wilson
20d108140e Most of the NEON shuffle instructions do not support 64-bit element types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 21:36:27 +00:00
Anton Korobeynikov
a55d33d96e Revert r84764, it breaks mingw build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84783 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 21:15:18 +00:00
Jim Grosbach
65b7f3af76 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 20:44:34 +00:00
Anton Korobeynikov
a91f4c561e Add DAG printing for RMW stuff debugging 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84776 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:18:28 +00:00
Anton Korobeynikov
83fceb9481 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84775 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:17:55 +00:00
Anton Korobeynikov
90593d2e1f Implement branch folding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84774 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:17:18 +00:00
Anton Korobeynikov
3926fb63c2 Cosmetic changes, no functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84773 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:16:49 +00:00
Bob Wilson
b27b51aaa6 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:54:01 +00:00
Bob Wilson
407d57489f Revert 84732. It was the wrong fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:52:34 +00:00
Sanjiv Gupta
36a9c8f0b3 Build shared lib instead of an archive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:27:23 +00:00
Sanjiv Gupta
4e4bba5c80 Add a pass to overlay pic16 data sections for function frame and automatic 
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph 
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84753 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 10:42:44 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Chris Lattner
1ce75ef5ef tidy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 04:10:24 +00:00
Bob Wilson
b3c8359360 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:27:20 +00:00
Bob Wilson
507df402b0 Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:15:46 +00:00
Chris Lattner
7d26443bb7 IPSCCP is missing stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84725 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 01:10:37 +00:00
Anton Korobeynikov
12ddf139ce Add note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:14:15 +00:00
Anton Korobeynikov
514200d5ef Be crazy and assert in case of unsupported modifier passed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84712 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:58 +00:00
Anton Korobeynikov
0a2e206b40 Handle external symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84711 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:42 +00:00
Anton Korobeynikov
8ecaf237e0 Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84710 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:25 +00:00
Anton Korobeynikov
dc2165e18e Add basic block operands & jump kinds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84709 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:05 +00:00
Anton Korobeynikov
3d6e560eef Ignore all implicit reg operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:12:44 +00:00
Anton Korobeynikov
efa236f40d Add a workaround for different memops prefixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84707 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:12:27 +00:00
Anton Korobeynikov
9b0b852698 Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84706 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:12:08 +00:00
Anton Korobeynikov
b5a921679f Add simple operand printing stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84704 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:11:27 +00:00
Anton Korobeynikov
13853e233b Add experimental MSP430 MCInstLowering stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84703 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:11:08 +00:00
Anton Korobeynikov
1074aae0d1 Wire up MSP430 printMCInst() method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84702 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:10:47 +00:00
Anton Korobeynikov
680dec703c Add MSP430 InstPrinter stub 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84701 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:10:30 +00:00
Anton Korobeynikov
51f3f9a8a7 Use proper target data 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84700 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:10:00 +00:00
Daniel Dunbar
a7cc65283a Fix -Asserts warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 22:10:05 +00:00
Jim Grosbach
3229b0bcf1 Disable by default while debugging 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 20:31:31 +00:00
Jim Grosbach
18ed9c9a2b add cmd line opt to disable frame index reuse for ARM and T2. debug aid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 20:19:50 +00:00
Dan Gohman
bab42bdd87 Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84652 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 18:14:49 +00:00
Dan Gohman
1a49295eae Make TranslateX86CC return COND_INVALID instead of aborting when it 
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84640 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 16:22:37 +00:00
Benjamin Kramer
174101e13a Random #include pruning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 11:44:38 +00:00
Sanjiv Gupta
2edef7efdc This file is replaeced by PIC16Section.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84628 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 09:16:32 +00:00
Chris Lattner
235e2f6a68 implement some more easy hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84614 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 06:22:33 +00:00
Chris Lattner
bf16faa16a Implement some hooks, make printOperand abort if unknown modifiers are 
present.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84613 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 06:15:28 +00:00
Chris Lattner
c6b8a99207 t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84611 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 05:58:02 +00:00
Daniel Dunbar
2685a29a8d Wire up the ARM MCInst printer, for llvm-mc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 05:15:36 +00:00
Jim Grosbach
8fa4efeabf Now that all ARM subtargets use frame index scavenging, the Thumb1 requires* 
functions are not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 01:32:47 +00:00
Jim Grosbach
7e831db1d4 Enable post-pass frame index register scavenging for ARM and Thumb2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 01:26:58 +00:00
Chris Lattner
161dcbf799 lower ARM::MOVi32imm properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84583 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 01:11:37 +00:00
Chris Lattner
292df8eb1f add support for external symbols. The mc instprinter can now handle 
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing 
identical output except for superior formatting of constant pool entries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:56:16 +00:00
Chris Lattner
96bc2173bb get fancy: support basic block operands. Yay for jumps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:52:47 +00:00
Chris Lattner
233917c072 add supprort for the 'sbit' operand, MOVi apparently has one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:46:11 +00:00
Chris Lattner
413ae25fb5 add support for instruction predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84575 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:42:49 +00:00
Chris Lattner
017d9478d5 implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:40:56 +00:00
Jim Grosbach
1fc1dc0682 Refs: A8-598. 
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:38:19 +00:00
Jim Grosbach
780d207d1c Add missing encoding bits to NLdSt class of instructions. 
Patch by Johnny Chen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:19:08 +00:00
Chris Lattner
af0df67d2b X86 should ignore implicit regs when lowering to MCInst also, 
no functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84567 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 23:35:57 +00:00
Chris Lattner
306d14f9aa handle addmode4 modifiers, fix a fixme in printRegisterList 
by ignoring all implicit regs when lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 23:31:43 +00:00
Chris Lattner
84d8bf9d28 simplify by using the twine form of GetOrCreateSymbol 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 23:05:23 +00:00
Jim Grosbach
6009751244 Enable allocation of R3 in Thumb1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:57:03 +00:00
Chris Lattner
5a207897bc use EmitLabel instead of text emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:51:16 +00:00
Chris Lattner
7c5b021793 add a twine version of MCContext::GetOrCreateSymbol. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84561 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:49:00 +00:00
Chris Lattner
a70e644820 lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries 
like:

@ BB#1:
	.align	2
LCPI1_0:
	.long	L_.str-(LPC0+8)

Note that proper indentation of the label :)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:33:05 +00:00
Jim Grosbach
d482f55af1 Adjust the scavenge register spilling to allow the target to choose an 
appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:27:30 +00:00
Chris Lattner
4d15222341 add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84553 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:23:04 +00:00
Chris Lattner
e306d8d6cc add register list and hacked up addrmode #4 support, we now get this: 
_main:
	stmsp! sp!, {r7, lr}
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldmsp! sp!, {r7, pc}

Note the unhappy ldm/stm because of modifiers being ignored.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84546 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:09:23 +00:00
Chris Lattner
3310a963cf revert r84540, fixing build breakage I didn't see because of 
broken makefile deps :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84544 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:59:25 +00:00
Chris Lattner
084f87d445 add addrmode2 support, getting us up to: 
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldm , 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84543 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:57:05 +00:00
Chris Lattner
6f99776f6c add jump tables, constant pools and some trivial global 
lowering stuff.  We can now compile hello world to:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 
	ldr r0, 
	bl _printf
	ldr r0, 
	mov sp, r7
	ldm , 

Almost looks like arm code :)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84542 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:53:00 +00:00
Chris Lattner
83e43ca1b6 pass mangler in as a reference instead of a pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84540 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:45:31 +00:00
Chris Lattner
8514e21deb reduce #includes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84536 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:23:15 +00:00
Chris Lattner
61d35c273e add printing support for SOImm operands, getting us to: 
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84535 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:21:39 +00:00
Chris Lattner
8bc86cba60 wire up some basic printOperand goodness, giving us stuff like this before 
we abort:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, 
	mov r0, 
	str r0, 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84532 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 20:59:55 +00:00
Chris Lattner
9cf0eb5e58 add the files that go with the previous rev 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84531 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 20:21:05 +00:00
Chris Lattner
97f0693744 wire up skeletal support for having llc print instructions 
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag.  Currently this
is very "aborty".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84530 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 20:20:46 +00:00
Chris Lattner
6a71afaec1 wire up ARM's printMCInst method. Now llvm-mc should be able to produce 
"something" when printing MCInsts, it will just be missing all the 
operand info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:59:05 +00:00
Chris Lattner
fd60382e75 stub out a minimal ARMInstPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84527 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:56:26 +00:00
Chris Lattner
172862a2a7 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:51:42 +00:00
Chris Lattner
b8f64a72d8 simplify code, reducing string thrashing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:49:14 +00:00
Chris Lattner
e4d9ea83c0 switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:44:38 +00:00
Chris Lattner
b0f294c14b use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:38:33 +00:00
Chris Lattner
ee8b32981e remove dead map 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:11:25 +00:00
Chris Lattner
a10343f039 don't bother trying to avoid emitting redundant constant pool alignment directives. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84512 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:08:02 +00:00
Chris Lattner
fc5451e82f remove accidental comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84510 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:03:41 +00:00
Chris Lattner
74cd3b7ceb emit .subsections_via_symbols through MCStreamer instead of textually. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84509 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:03:08 +00:00
Chris Lattner
4a071d667d cleanup doFinalization -> EmitEndOfAsmFile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 17:59:19 +00:00
Nate Begeman
ed748a0677 PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 17:31:16 +00:00
Torok Edwin
6602922878 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. 
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 11:00:58 +00:00
Nate Begeman
a09008bf6d Add support for matching shuffle patterns with palignr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84459 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 02:17:23 +00:00
Evan Cheng
d36076e4a3 Turn on post-alloc scheduling for x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 19:57:27 +00:00
Evan Cheng
eb6e1daa43 Oops. I forgot to change the tests first. Disable post-alloc scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84425 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 18:31:31 +00:00
Evan Cheng
ff89dcb06f -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 18:16:27 +00:00
Evan Cheng
20270c9093 Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 06:27:36 +00:00
Evan Cheng
491f54f1fd Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84326 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 09:20:14 +00:00
Evan Cheng
6553155172 Revert 84315 for now. Re-thinking the patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 07:53:04 +00:00
Evan Cheng
bf125583f8 Rename getFixedStack to getStackObject. The stack objects represented are not 
necessarily fixed. Only those will negative frame indices are "fixed."


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 06:22:26 +00:00
Victor Hernandez
a276c603b8 Remove MallocInst from LLVM Instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84299 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 01:18:07 +00:00
Evan Cheng
fa16354e03 Change createPostRAScheduler so it can be turned off at llc -O1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 21:06:15 +00:00
Benjamin Kramer
6f892bbaf9 Update CMake file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 10:29:08 +00:00
Sanjiv Gupta
5386a35c5a Cleaned up some code. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84251 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 08:58:34 +00:00
Evan Cheng
b46aea1032 I am no spelling bee. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84250 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:18:09 +00:00
Evan Cheng
d3dd50fec0 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:11:08 +00:00
Evan Cheng
fee0c1074c Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84246 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 05:33:58 +00:00
Bob Wilson
1dd4348408 Fix more NEON instruction encodings. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84243 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 03:58:44 +00:00
Bob Wilson
934f98b536 Revert svn r80498 and replace it with a different solution. The only problem 
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)

Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations.  The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now.  If there are cases that we're missing, let me know.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 23:12:05 +00:00
Anton Korobeynikov
4fac9470c4 Dllexport stuff cleanup: 
1. Emit external function type information for all COFF targets since it's
a feature of object format
2. Emit linker directives only for cygming (since this is ld-specific stuff)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84214 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 22:36:18 +00:00
Sandeep Patel
452b54a8ae Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 22:25:32 +00:00
Bob Wilson
6f122625dd Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 21:57:47 +00:00
Kevin Enderby
e2a98dd2a4 Fix ARM memory operand parsing of post indexing with just a base register, that 
is just "[Rn]" and no tailing comma with an offset, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84205 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 21:42:45 +00:00
Bob Wilson
b923953733 Fix a potential performance problem in placing ARM constant pools. 
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references.  This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84202 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 20:49:47 +00:00
Kevin Enderby
515d509360 More bits of the ARM target assembler for llvm-mc, code added to parse labels 
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these).  Some clean up of the operand parsing code
and adding some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84201 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 20:48:48 +00:00
Evan Cheng
79f7400e4f Remove X86Subtarget::IsLinux. It's no longer being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 20:23:21 +00:00
Benjamin Kramer
5814fefc7f Add files Sanjiv forgot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84196 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 19:46:34 +00:00
Sanjiv Gupta
753ec15d5f Re-apply 84180 with the fixed test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84195 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 19:26:25 +00:00
Jakob Stoklund Olesen
6ad8c84d70 Move Blackfin intrinsics into the Target/Blackfin directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 18:50:52 +00:00
Jakob Stoklund Olesen
0383606b65 Clean up TargetIntrinsicInfo API. Add pure virtual methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 18:49:26 +00:00
Daniel Dunbar
1ead150c92 Revert "Complete Rewrite of AsmPrinter, TargetObjectFile based on new 
PIC16Section class", it breaks globals.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 15:02:14 +00:00
Sanjiv Gupta
8da373cf62 Complete Rewrite of AsmPrinter, TargetObjectFile based on new PIC16Section class 
derived from MCSection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84180 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 10:10:43 +00:00
Sanjiv Gupta
cf1e5be2a2 Few changes to comply with new DebugInfo Metadata representation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84179 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 09:48:25 +00:00
Bob Wilson
549dda9d82 Be smarter about reusing constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 05:52:29 +00:00
Bob Wilson
36fa5321ba Fix another problem with ARM constant pools. Radar 7303551. 
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them.  My recent change exposed a problem in this area.  We may
sometimes append to the same block more than one unconditional branch.  The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.

This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before.  The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block.  The insertion point could be out of range.  When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.

The fix is to only append an unconditional branch if the block does not
already end with one.  I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.

There is more to be done here, but I think this fixes the immediate problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 05:10:36 +00:00
Bob Wilson
b3642dccee Fix instruction encoding bits for NEON VPADAL. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 21:43:17 +00:00
Bob Wilson
681a2ad403 Remove unused variables to fix build warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 21:40:45 +00:00
Jim Grosbach
b9d319b585 Inst{11-8} for vshl should be 0b0101, not 0b1111. 
Refs: A7-17 & A8-750.

Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84131 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 20:31:01 +00:00
Bob Wilson
8e86b5195b Set instruction encoding bits 4 and 7 for ARM register-register and 
register-shifted-register instructions.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 19:00:24 +00:00
Bob Wilson
24f995d84b Refactor code to select NEON VST intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84122 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 18:32:29 +00:00
Bob Wilson
3e36f13ba7 Refactor code to select NEON VLD intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84117 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 17:28:52 +00:00
Bob Wilson
9649344cb5 More refactoring. NEON vst lane intrinsics can share almost all the code for 
vld lane intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84110 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 16:46:45 +00:00
Bob Wilson
a7c397c9c3 Refactor code for selecting NEON load lane intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84109 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 16:19:03 +00:00
Dan Gohman
1b1764b3f7 Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards 
(for uses marked kill and defs marked dead) a few instructions in
addition to forwards. Also, increase the maximum number of instructions
to scan, as it appears to help in a fair number of cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84061 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 00:08:59 +00:00
Kevin Enderby
079469f649 Correct comment about ARM immediates using '#' not '$' and TODO for modifiers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84055 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 23:33:38 +00:00
Devang Patel
1619dc3b9e s/DebugLoc.CompileUnit/DebugLoc.Scope/g 
s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84054 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 23:28:53 +00:00
Bob Wilson
e72142aa5b More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics 
by creating TargetConstants during instruction selection instead of during
legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 22:29:24 +00:00
Kevin Enderby
cfe0724016 More bits of the ARM target assembler for llvm-mc to parse immediates. 
Also fixed a couple of coding style things that crept in.  And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84040 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 22:19:02 +00:00
Bob Wilson
73d64a6fd3 NEON VLD/VST are now fully implemented. For operations that expand to 
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 21:55:24 +00:00
Bob Wilson
765cc0b9d5 Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 20:50:28 +00:00
Sandeep Patel
4e1ed88026 Fix method name in comment, per Bob Wilson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84017 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 20:25:58 +00:00
Sandeep Patel
47eedaa8fa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 18:59:48 +00:00
Ted Kremenek
59e00d31d1 Update CMake file (lexically order files). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84008 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 18:57:27 +00:00
Bob Wilson
5361cd2c7d Add some ARM instruction encoding bits. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83983 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 17:35:30 +00:00
Bob Wilson
4796ba2e70 Fix regression introduced by r83894. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 17:29:13 +00:00
Bob Wilson
a7fcb9b840 Fix a tab. Thanks to Johnny Chen for pointing it out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83973 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 15:27:23 +00:00
Kevin Enderby
6bd266e567 Fix two warnings about unused variables that are only used in assert() calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-12 22:51:49 +00:00