Eric Christopher
79ab2fe01a
Revert the accidental commit I made reverting the previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:50:14 +00:00
Jim Grosbach
d1d5a39cad
ARM fixup encoding for direct call instructions (BL).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 20:05:40 +00:00
Eric Christopher
6c50119ba3
Revert this temporarily.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:47:02 +00:00
Eric Christopher
391f228e7e
Change the prologue and epilogue to use push/pop for the low ARM registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:26:03 +00:00
Owen Anderson
c7139a6f0d
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
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More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 19:07:48 +00:00
Wesley Peck
60f923c5e2
Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118807 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:41:33 +00:00
Chris Lattner
af510f16ec
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:23:57 +00:00
Jim Grosbach
c466b937db
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 18:04:49 +00:00
Chris Lattner
1e68fdb946
add pr#
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 17:17:56 +00:00
Jim Grosbach
7eab97f260
Encoding for ARM LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 16:55:29 +00:00
Rafael Espindola
3f2d13c98e
Remove some explicit arguments to getELFSection. This is
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a leftover from the removal of isExplicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 03:40:25 +00:00
Jim Grosbach
928f3325a7
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616
Fix encoding of Ra register for ARM smla* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691
ARM STRH encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b
Move LDM predicate operand encoding into base clase. Add STM missing STM
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encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e
Fix ARM encoding of non-return LDM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca
Fix ARM encoding of LDM+Return instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 23:12:48 +00:00
Nate Begeman
bf5be2654e
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 21:35:41 +00:00
Jim Grosbach
7c7ddb21c3
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
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double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
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VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes
c4bb67c8d9
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 02:13:22 +00:00
Bill Wendling
8ea974039a
Emit a '!' if this is a "writeback" register or memory address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
cc8d10e1a8
Rename a parameter to avoid confusion with a local variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 00:08:58 +00:00
Bill Wendling
8e8b18bcfa
Emit the warning about the register list not being in ascending order only once.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 23:45:59 +00:00
Bill Wendling
5fa22a1975
s/std::vector/SmallVector/
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 23:28:44 +00:00
Bill Wendling
c3236753d6
Delete the allocated vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:51:42 +00:00
Bob Wilson
66f6c79450
Define the subtarget feature for the architecture version,
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as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:47 +00:00
Bob Wilson
54f9256380
Do not use MEMBARRIER_MCR for any Thumb code.
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It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:44 +00:00
Bill Wendling
7729e06c12
Two types of instructions have register lists:
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* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:44:22 +00:00
Jim Grosbach
3a2429a86c
Change the ARMConstantPoolValue modifier string to an enumeration. This will
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help in MC'izing the references that use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 21:36:17 +00:00
Jim Grosbach
c9962aca8f
Handle ARM constant pool values that need an explicit reference to the '.'
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pseudo-label. (TLS stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:40:22 +00:00
Chris Lattner
274191fa70
add a case we fail to devirt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:37:28 +00:00
Jim Grosbach
16cb3763c5
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 19:22:26 +00:00
Jim Grosbach
5df08d8f55
Further MCize ARM constant pool values. This allows basic PIC references for
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object file emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:45:04 +00:00
Jim Grosbach
e0ee08e367
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 18:43:54 +00:00
Jim Grosbach
d92354c574
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
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a left shift by zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:38:15 +00:00
Jim Grosbach
a9a0dde872
ARM .word data fixups don't need an adjustment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:36:59 +00:00
Bruno Cardoso Lopes
9e03061b2f
Fix trailing whitespace and style, no functionality change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:25:34 +00:00
Jim Grosbach
54fea632b1
Add encoder method for ARM load/store shifted register offset operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 17:20:53 +00:00
Jim Grosbach
679cbd3b21
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
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constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 01:37:15 +00:00
Bill Wendling
5e559a22c1
Revert r118457 and r118458. These won't hold for GPRs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 00:30:18 +00:00
Bill Wendling
4b97c55648
Get the register and count from the register list operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:51:20 +00:00
Bill Wendling
3734ef3fb4
reglist has two operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:50:20 +00:00
Bill Wendling
87f4f9a946
The "addRegListOperands()" function returns the start register and the total
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number of registers in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:49:57 +00:00
Owen Anderson
c24cb3551e
Add support for ARM's specialized vector-compare-against-zero instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 23:21:22 +00:00
Bruno Cardoso Lopes
2c2304c623
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:42:32 +00:00
Bill Wendling
85c3f24da3
Add "write back" bit encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:28:03 +00:00
Bruno Cardoso Lopes
a84ad90c06
Fix PR8211
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:24:59 +00:00
Wesley Peck
0a67d92938
Adding working version of assembly parser for the MBlaze backend
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Major cleanup of whitespace and formatting issues in MBlaze backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:40:01 +00:00
Dale Johannesen
7179d1e5c0
Revert 118422 in search of bot verdancy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 19:17:22 +00:00
Jason W Kim
69ad7138b7
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 17:58:07 +00:00
Jason W Kim
6cecceb2f6
Complete listing of ARM/MC/ELF relocation enums
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 16:47:27 +00:00
Che-Liang Chiou
df65963a34
Add generating function declaration for PTX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 03:06:08 +00:00
Che-Liang Chiou
3278c4260c
Add physical register counting functions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118397 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 03:00:52 +00:00
Che-Liang Chiou
d77f2a45aa
Add a dummy PTXMCAsmStreamer class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 02:58:44 +00:00
Bill Wendling
5991487c10
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:39:58 +00:00
Bill Wendling
b32e7844e9
Revert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:32:40 +00:00
Duncan Sands
1ac7c9979a
Fix a README item: when doing a comparison with the result
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of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07 16:12:23 +00:00
Bill Wendling
e8399c6e01
In this context, a reglist is a reg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07 13:08:28 +00:00
Chris Lattner
689cf3cb62
implement aliases for div/idiv that have an explicit A register operand,
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implementing rdar://8431864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:41:18 +00:00
Bill Wendling
e717610f53
Add support for parsing register lists. We can't use a bitfield to keep track of
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the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:36:58 +00:00
Chris Lattner
04a75abe23
add aliases for movs between seg registers and mem. There are multiple
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different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:35:34 +00:00
Chris Lattner
d5b2f1aa8c
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:25:39 +00:00
Bill Wendling
8155e5b753
Return the base register of a register list for the "getReg()" method. This is
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to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:19:43 +00:00
Chris Lattner
17671510a7
work-in-progress
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 22:05:43 +00:00
Bill Wendling
146018fc64
General cleanup:
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- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:42:12 +00:00
Chris Lattner
db28788e4a
go to great lengths to work around a GAS bug my previous patch
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exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
Chris Lattner
8c24b0c699
rework the rotate-by-1 instructions to be defined like the
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shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:23:40 +00:00
Chris Lattner
235705b9ca
change the fp comparison instructions to not have %st0 explicitly
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listed in its asm string, for consistency with the other similar
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 20:55:09 +00:00
Chris Lattner
3af0e7d5cd
move the plethora of fp stack aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 20:47:38 +00:00
Chris Lattner
90fd797dc7
add (and document) the ability for alias results to have
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fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:57:21 +00:00
Bill Wendling
8d5acb7007
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
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(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:56:04 +00:00
Chris Lattner
98c870f87b
generalize alias support to allow the result of an alias to
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add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:25:43 +00:00
Chris Lattner
dea546b623
move fnstsw aliases to .td file, fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:58:32 +00:00
Chris Lattner
7e925cc3c9
move in/out aliases to the .td files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:52:40 +00:00
Chris Lattner
9c1dbc69d7
move sldt, imul, and movabsq aliases from c++ to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:44:26 +00:00
Chris Lattner
fb7000fcbd
correct suffix matching to search for s/l/t suffixes on
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floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 18:28:02 +00:00
Bill Wendling
12f40e9a63
Fix grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:51:53 +00:00
Bill Wendling
a60f157b7c
Fix grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:48:18 +00:00
Bill Wendling
d68fd9c79e
MatchRegisterName() returns 0 if it can't match the register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:45:34 +00:00
Bill Wendling
1d6a26507b
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
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while the latter doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:40:24 +00:00
Benjamin Kramer
019e378754
Add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 10:37:16 +00:00
Chris Lattner
5bde734598
fix a bug where we had an implicit assumption that the
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result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 08:20:59 +00:00
Eric Christopher
5e262bc943
Make sure we have movw on the target before using it.
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Fixes 8559.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:53:11 +00:00
Chris Lattner
8caa290a77
move the lcall/ljmp aliases to the .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:48:45 +00:00
Chris Lattner
02ff6ba6f6
move the "movsd -> movsl" alias to the .td files,
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tidy up the movsx and movzx aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:34:58 +00:00
Chris Lattner
414098571b
fix some bugs in the alias support, unblocking changing of "clr" aliases
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from c++ hacks to proper .td InstAlias definitions. Change them!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:31:43 +00:00
Chris Lattner
662e5a30e8
Reimplement BuildResultOperands to be in terms of the result instruction's
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operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:14:44 +00:00
Jim Grosbach
2a301704ea
Hook up the '.code {16|32}' directive to the streamer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:40:53 +00:00
Jim Grosbach
642fc9c24b
Hook up the '.thumb_func' directive to the streamer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:33:53 +00:00
Jim Grosbach
83c4018fcc
Fix past-o.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:11:33 +00:00
Jim Grosbach
ce79299f78
MC'ize the '.code 16' and '.thumb_func' ARM directives.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118301 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 22:08:08 +00:00
Owen Anderson
36fa3ea566
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 21:57:54 +00:00
Jim Grosbach
8da0a5785c
MC'ize simple ARMConstantValue entry emission (with a FIXME).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 20:34:24 +00:00
Owen Anderson
080c092297
Add codegen and encoding support for the immediate form of vbic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 19:27:46 +00:00
Jim Grosbach
a55661b6bd
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
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(relocations, e.g.), but this will allow simple things to flow through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 18:50:35 +00:00
Jim Grosbach
c9d1439051
Allow targets to specify the MachO CPUType/CPUSubtype information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 18:48:58 +00:00
Jim Grosbach
6d87bca865
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05 17:37:13 +00:00
Duncan Sands
1e92ec6886
When passing a huge parameter using the byval mechanism, a long
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sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead. PR7170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 21:16:46 +00:00
Duncan Sands
1e96bab329
In the calling convention logic, ValVT is always a legal type,
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 10:49:57 +00:00
Evan Cheng
416941d50f
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 05:19:35 +00:00
Jim Grosbach
70933266ae
Add ARM fixup info for load/store label references. Probably will need a bit of
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tweaking when we start using it for object file emission or JIT, but it's a
start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 01:12:30 +00:00
Bill Wendling
2f46f1f59c
Add encoding for VSTR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 00:59:42 +00:00
Jim Grosbach
806e80ef42
Teach ARM Target to use the tblgen support for generating an MC'ized
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CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 23:52:49 +00:00
Owen Anderson
60f4870c22
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
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This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 23:15:26 +00:00
Owen Anderson
d966817f3c
Add support for code generation of the one register with immediate form of vorr.
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We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 22:44:51 +00:00
Jim Grosbach
35b2de012d
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 22:03:20 +00:00
Eric Christopher
e5b13cfdd0
Optimize generated code for integer materialization a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 20:21:17 +00:00
Owen Anderson
7a25825033
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
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all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 18:16:27 +00:00
Bob Wilson
d168cef664
Add codegen patterns for VST1-lane instructions. Radar 8599955.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 16:24:53 +00:00
Bob Wilson
3468c2ee20
Check for extractelement with a variable operand for the element number.
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For NEON we had been assuming this was always an immediate constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 16:24:50 +00:00
Duncan Sands
cdfad36b40
Simplify uses of MVT and EVT. An MVT can be compared directly
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 12:17:33 +00:00
Duncan Sands
1440e8b918
Inside the calling convention logic LocVT is always a simple
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 11:35:31 +00:00
Evan Cheng
dfed19fe2c
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 05:14:24 +00:00
Bill Wendling
cdbbec43a8
Put the PC encoding in the correct bit position.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 04:57:44 +00:00
Eric Christopher
000cf708ef
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 04:29:11 +00:00
Bill Wendling
92b5a2eb16
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
Jim Grosbach
2915eb4430
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:35:15 +00:00
Jim Grosbach
0a2287b909
Remove the no longer used 'Modifier' optional operand to the ARM
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printOperand() asm printer helper functions. rdar://8425198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:11:15 +00:00
Jim Grosbach
496e2b2908
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:07:48 +00:00
Jim Grosbach
e6913600c7
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:01:43 +00:00
Evan Cheng
8239daf7c8
Two sets of changes. Sorry they are intermingled.
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 00:45:17 +00:00
Evan Cheng
41957f6eb2
Modify scheduling itineraries to correct instruction latencies (not operand
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latencies) of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 00:40:22 +00:00
Eric Christopher
4c914125c4
Make sure we're only storing a single bit here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:59:09 +00:00
Chris Lattner
491561dcac
per a suggestion by Frits van Bommel, mark all MBlaze Pseudo
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instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:57:05 +00:00
Owen Anderson
f431edae5c
Revert r118097 to fix buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:47:29 +00:00
Chris Lattner
a1ca91af4e
Completely reject instructions that have an operand in their
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:40:41 +00:00
Bill Wendling
0800ce7189
Obsessive formatting changes. No functionality impact.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:53:11 +00:00
Bill Wendling
d3a124db4d
Omit unused parameter name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:46:04 +00:00
Bill Wendling
7292e0a656
Simplify the EncodeInstruction method now that a lot of the special case stuff
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is handled with the MC encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:44:12 +00:00
Owen Anderson
1ba6064437
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:41:42 +00:00
Bill Wendling
5df0e0a61d
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
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with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
Owen Anderson
a2b50b300e
Rename encoder methods to match naming convention.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:28:01 +00:00
Chris Lattner
d6e623ad15
mark a few codegenonly instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:26:33 +00:00
Owen Anderson
b20594fce6
Provide correct encodings for the remaining vst variants that we currently generate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:18:18 +00:00
Owen Anderson
e95c946aeb
Tentative encodings for the "single element from one lane" variant of vst1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:54:45 +00:00
Owen Anderson
a1a45fd254
Add correct encodings for basic variants for vst3 and vst4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:47:03 +00:00
Bob Wilson
d0c6bc2204
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118069 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:18:25 +00:00
Owen Anderson
d2f3794e4d
Add correct encodings for the basic variants for vst2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:16:58 +00:00
Owen Anderson
cfebe3a8b1
Add correct encodings for the basic form of vst1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:06:06 +00:00
Owen Anderson
d138d7034e
Factor out a common encoding class for loads and stores with a lane parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 20:47:39 +00:00
Owen Anderson
f0ea0f2b15
Add correct encodings for the rest of the vld instructions that we generate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 20:40:59 +00:00
Jim Grosbach
28b108250d
Sort bit assignments. Cosmetic change only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 17:59:04 +00:00
Jim Grosbach
ab3d00e535
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
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assumptions about stack layout. Specifically, LR must be saved next to FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 17:35:25 +00:00
Owen Anderson
cf667be17b
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 01:24:55 +00:00
Eric Christopher
4053e63a4b
Remove an assert - it's possible to be hit, and we just want to avoid
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handling those cases for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 01:24:49 +00:00
Eric Christopher
61d69da051
Whitespeace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 01:22:45 +00:00
Eric Christopher
aaa8df4cad
No really, no thumb1 for arm fast isel. Also add an informative comment as
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to what someone would need to do to support thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 01:21:28 +00:00
Owen Anderson
e85bd773e6
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
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since we can neither generate nor parse them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117988 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 00:24:52 +00:00
Owen Anderson
b552174a8c
Add aesthetic break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 00:14:00 +00:00
Owen Anderson
d9aa7d30aa
Add correct NEON encodings for the "multiple single elements" form of vld.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 00:05:05 +00:00
Jim Grosbach
9af3d1c0dc
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
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for handling the fixup necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:45:50 +00:00
Jim Grosbach
a502423d1e
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:40:56 +00:00
Bob Wilson
665814b6be
Add support for alignment operands on VLD1-lane instructions.
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This is another part of the fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:40:51 +00:00
Bill Wendling
cd944a424c
Missed reverting this bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:17:54 +00:00
Bill Wendling
160accad6b
Minor cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:11:22 +00:00
Chris Lattner
efd8dadb4f
rearrange a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:07:52 +00:00
Bob Wilson
b796bbb6de
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 22:04:05 +00:00
Bill Wendling
c2bf50245f
Move the machine operand MC encoding patterns to the parent classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:17:06 +00:00
Chris Lattner
99f535242c
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks
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from X86AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:06:34 +00:00
Bill Wendling
40a5eb18b0
When we look at instructions to convert to setting the 's' flag, we need to look
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at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 20:41:43 +00:00
Bob Wilson
24645a1a6d
NEON does not support truncating vector stores. Radar 8598391.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:31:39 +00:00
Jim Grosbach
469ebbe148
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:11:14 +00:00
Jim Grosbach
6797f89815
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
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codegen using the patterns; the latter gates the assembler recognizing the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 17:08:58 +00:00
Jim Grosbach
833c93c795
Mark ARM subtarget features that are available for the assembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 16:59:54 +00:00
Jim Grosbach
d4462a5a4f
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 16:44:21 +00:00
Jim Grosbach
9729d2e998
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
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patterns as such
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 15:59:52 +00:00
Bill Wendling
69661191ce
Move instruction encoding bits into the parent class and remove the temporary
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*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 06:00:39 +00:00
Chris Lattner
acc473fcf9
"mov[zs]x (mem), GR16" are not ambiguous: the mem
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must be 8 bits. Support this memory form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:41:10 +00:00
Chris Lattner
b501d4f673
Implement enough of the missing instalias support to get
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aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:34:34 +00:00
Chris Lattner
4164f6bbbf
make the asm matcher emitter reject instructions that have comments
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in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:44:29 +00:00
Chris Lattner
4d1189f385
reject instructions that contain a \n in their asmstring. Mark
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various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 00:46:16 +00:00
Chris Lattner
150d20e8fc
fix the !eq operator in tblgen to return a bit instead of an int.
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Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:22:57 +00:00
Chris Lattner
a4a3a5e3c2
two changes: make the asmmatcher generator ignore ARM pseudos properly,
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and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:15:18 +00:00
Chris Lattner
39ee036f40
reapply r117858 with apparent editor malfunction fixed (somehow I
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got a dulicated line).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:10:56 +00:00
Chris Lattner
8b2f0822f3
revert r117858 while I check out a failure I missed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:05:32 +00:00
Chris Lattner
efa53760fe
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
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Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 18:48:12 +00:00
Chris Lattner
a33b93f7f1
sketch out the planned instruction alias mechanism, add some comments about
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how the push/pop mnemonic aliases are wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 18:43:46 +00:00
Duncan Sands
4590766580
Factorize the duplicated logic for choosing the right argument
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calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 13:21:44 +00:00
Duncan Sands
e26032d5b2
Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
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which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 13:02:38 +00:00
Eric Christopher
76d61478df
Make sure we have a legal type (and simple) before continuing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 21:25:26 +00:00
Chris Lattner
0f899c78e1
Resolve a terrible hack in tblgen: instead of hardcoding
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"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:38:20 +00:00
Chris Lattner
693173feef
Implement (and document!) support for MnemonicAlias's to have Requires
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directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:23:13 +00:00
Chris Lattner
a47b265b1a
really zap alias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:23:25 +00:00
Chris Lattner
b3c417845d
move fcompi alias to .td file and zap some useless code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:22:53 +00:00
Chris Lattner
6f96b0899b
move rep aliases to td file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:17:33 +00:00
Chris Lattner
a17a9a00dc
move sal aliases to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:14:54 +00:00
Chris Lattner
1a1ecc9f3c
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
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for shl. Caught by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:13:10 +00:00
Chris Lattner
8b260a7644
move a bunch more aliases from .cpp -> .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:07:17 +00:00
Chris Lattner
8cb441c9e0
move cmov aliases to .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:56:50 +00:00
Chris Lattner
b69fc28e92
move setcc and jcc aliases from .cpp to .td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:51:45 +00:00
Chris Lattner
537ca844dd
move some code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:38:55 +00:00
Chris Lattner
674c1dcca2
implement (and document!) the first kind of MC assembler alias, which
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just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:36:36 +00:00
Jim Grosbach
7644971232
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 14:54:23 +00:00
Jim Grosbach
604cdf6ea7
Clean up comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 13:48:28 +00:00
Jim Grosbach
4aaf59d8ed
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 12:59:16 +00:00
Chris Lattner
9a82e70275
stay out of the reserved namespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 04:57:14 +00:00
Chris Lattner
dba34d874d
simplify this code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 04:35:59 +00:00
Chris Lattner
e5658fa15e
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 04:09:10 +00:00
Jim Grosbach
4b5236c966
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 01:40:16 +00:00
Bob Wilson
f74a429816
Overhaul memory barriers in the ARM backend. Radar 8601999.
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There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:54:37 +00:00
Jim Grosbach
6b5252db2d
Encode the register list operands for ARM mode LDM/STM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:37:59 +00:00
Bill Wendling
52925b60f1
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
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conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Jim Grosbach
f38bfd1918
Remove hard tab characters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:23:15 +00:00
Jim Grosbach
c4bc2111a7
80 column fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:57 +00:00
Jim Grosbach
d8a11c25fa
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:03 +00:00
Jim Grosbach
0d2d2e9246
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
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encoder functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:19:55 +00:00
Evan Cheng
e09206d4d7
Fix fpscr <-> GPR latency info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:16:55 +00:00
Jim Grosbach
3df518e67e
add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:56:51 +00:00
Jim Grosbach
8e0a3eb957
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
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the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:35:25 +00:00
Eric Christopher
0e6233bfd7
Handle comparison values we already have - this fixes the consumer-typeset
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failure for llvm-gcc on arm fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:08:19 +00:00
Jim Grosbach
a3c1629ff5
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
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handle it in the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:37:06 +00:00
Jim Grosbach
e317b13a2d
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:21:49 +00:00
Jim Grosbach
f32ecc69e5
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:21:36 +00:00
Jim Grosbach
86875a2463
ARM mode LDREX*/STREX* binary encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 19:58:57 +00:00
Jim Grosbach
27e900888e
Encoding information for ARM conditional move instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 19:28:17 +00:00
Evan Cheng
089751535d
Avoiding overly aggressive latency scheduling. If the two nodes share an
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operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 18:09:28 +00:00
Evan Cheng
d7e473c629
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
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- Compute CopyToReg use operand latency correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 18:07:31 +00:00
Jim Grosbach
80eb233a3c
Handle ARM addrmode5 instructions with an offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 17:41:25 +00:00
John Thompson
44ab89eb37
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 17:29:13 +00:00
Jim Grosbach
d8d716fad3
Revert 117660. Apparently it's not as trivial as that...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 16:50:53 +00:00
Jim Grosbach
da54c6dd4f
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 16:38:59 +00:00
Jim Grosbach
16c7425cff
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117651 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 14:46:02 +00:00
Benjamin Kramer
61a4d56a03
ARMAsmParser: Plug a memory leak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 09:43:39 +00:00
Eric Christopher
c223e2b10b
Add an unreachable to silence warning - the switch is actually
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fully enumerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117647 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 09:26:59 +00:00
Chris Lattner
14b93851cc
add simple support for addrmode5 operands, allowing
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vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 00:27:31 +00:00
Chris Lattner
e73d4f8ec7
give better error diagnostics, for example:
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t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:41:58 +00:00
Chris Lattner
6274ec48b3
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
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the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:37:33 +00:00
Chris Lattner
fa42fad8bf
move a method out of line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:01 +00:00
Chris Lattner
550276ee5b
remove the rest of hte owningptr's, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 20:52:15 +00:00
Benjamin Kramer
57ca3ccd45
Reduce malloc thrashing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 18:41:23 +00:00
Jim Grosbach
ab682a2090
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 18:34:10 +00:00
Chris Lattner
c0ddfaa134
rearrange ParseRegisterList.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 17:23:41 +00:00
Chris Lattner
3a69756e39
refactor some code to simplify it, eliminating some owningptr's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 17:20:03 +00:00
Evan Cheng
7e2fe9150f
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 06:47:08 +00:00
Evan Cheng
9e08ee5d16
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 02:00:25 +00:00
Evan Cheng
0104d9de04
- Assign load / store with shifter op address modes the right itinerary classes.
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- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 01:49:06 +00:00
Dale Johannesen
e49406fd63
Fix pastos in handling of AVX cvttsd2si, PR8491.
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Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 00:35:54 +00:00
Owen Anderson
cfd0e1f3ae
Add correct NEON encodings for vtbl and vtbx.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 00:18:46 +00:00
Owen Anderson
3eff4af42d
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:56:39 +00:00
Bob Wilson
1fa9d301a8
Fix compiler warnings about signed/unsigned comparisons.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:49:00 +00:00
Evan Cheng
f40deed62f
Shifter ops are not always free. Do not fold them (especially to form
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complex load / store addressing mode) when they have higher cost and
when they have more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:41:30 +00:00
Jim Grosbach
7e3383c007
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
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for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 22:49:00 +00:00
Jim Grosbach
6b15639e26
Trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:39:08 +00:00
Owen Anderson
d2fbdb7f5c
Provide correct encodings for the get_lane and set_lane variants of vmov.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:28:09 +00:00
Kevin Enderby
529b1a4398
Added the x86 instruction ud2b (2nd official undefined instruction).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:46:49 +00:00
Jim Grosbach
ccf72caa92
JIT imm12 encoding for constant pool entry references.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:39:40 +00:00