2010-10-05 05:32:15 +00:00
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//===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
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2010-10-20 23:40:27 +00:00
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//
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2003-10-21 15:17:13 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2010-10-20 23:40:27 +00:00
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//
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2003-10-21 15:17:13 +00:00
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//===----------------------------------------------------------------------===//
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2003-08-03 21:54:21 +00:00
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//
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// This file describes the X86 instruction set, defining the instructions, and
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// properties of the instructions which are needed for code generation, machine
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// code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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2005-12-17 01:24:02 +00:00
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//===----------------------------------------------------------------------===//
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// X86 specific DAG Nodes.
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//
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2006-01-09 18:33:28 +00:00
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def SDTIntShiftDOp: SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisInt<0>, SDTCisInt<3>]>;
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Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
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def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
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2005-12-17 01:24:02 +00:00
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2011-06-03 23:53:54 +00:00
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def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
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def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
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2007-09-29 00:00:36 +00:00
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def SDTX86Cmov : SDTypeProfile<1, 4,
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2007-09-25 01:57:46 +00:00
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[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
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2005-12-17 01:24:02 +00:00
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2009-03-04 19:44:21 +00:00
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// Unary and binary operator instructions that set EFLAGS as a side-effect.
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2010-03-24 00:47:47 +00:00
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def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
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[SDTCisInt<0>, SDTCisVT<1, i32>]>;
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2010-03-24 00:49:29 +00:00
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def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
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[SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>,
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SDTCisInt<0>, SDTCisVT<1, i32>]>;
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2010-12-20 00:59:46 +00:00
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2011-01-26 02:03:37 +00:00
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// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
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2010-12-20 00:59:46 +00:00
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def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
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[SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>,
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SDTCisInt<0>,
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SDTCisVT<1, i32>,
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SDTCisVT<4, i32>]>;
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it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
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// RES1, RES2, FLAGS = op LHS, RHS
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def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
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[SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>,
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SDTCisInt<0>, SDTCisVT<1, i32>]>;
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2007-09-29 00:00:36 +00:00
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def SDTX86BrCond : SDTypeProfile<0, 3,
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2007-09-25 01:57:46 +00:00
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[SDTCisVT<0, OtherVT>,
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SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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2005-12-17 01:24:02 +00:00
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2007-09-29 00:00:36 +00:00
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def SDTX86SetCC : SDTypeProfile<1, 2,
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2007-09-25 01:57:46 +00:00
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[SDTCisVT<0, i8>,
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SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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2009-12-16 00:53:11 +00:00
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def SDTX86SetCC_C : SDTypeProfile<1, 2,
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[SDTCisInt<0>,
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SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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2005-12-21 20:21:51 +00:00
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2010-10-20 23:40:27 +00:00
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def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
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2008-03-01 21:52:34 +00:00
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SDTCisVT<2, i8>]>;
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2011-08-26 21:21:21 +00:00
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def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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2008-03-01 21:52:34 +00:00
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2008-10-02 18:53:47 +00:00
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def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
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SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
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2008-03-11 03:23:40 +00:00
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def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
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2005-12-19 23:12:38 +00:00
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2009-06-23 23:25:37 +00:00
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def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
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SDTCisVT<1, i32>]>;
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2006-01-09 18:33:28 +00:00
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2008-05-29 19:57:41 +00:00
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def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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2006-01-09 18:33:28 +00:00
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2009-08-15 01:38:56 +00:00
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def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
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SDTCisVT<1, iPTR>,
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SDTCisVT<2, iPTR>]>;
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2010-10-12 18:00:49 +00:00
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def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
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SDTCisPtrTy<1>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i8>,
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SDTCisVT<4, i32>]>;
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2010-03-28 07:38:39 +00:00
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def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
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2010-03-06 19:32:29 +00:00
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def SDTX86Void : SDTypeProfile<0, 0, []>;
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2005-12-21 02:39:21 +00:00
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2006-02-25 10:02:21 +00:00
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def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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2009-04-17 14:35:58 +00:00
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def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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2007-04-20 21:38:10 +00:00
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2010-12-09 06:25:53 +00:00
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def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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2010-06-03 04:07:48 +00:00
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2011-08-30 19:43:21 +00:00
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def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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2007-07-14 14:06:15 +00:00
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def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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2007-10-11 19:40:01 +00:00
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def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
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2010-07-22 02:48:34 +00:00
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def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
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def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
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[SDNPHasChain]>;
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def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
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[SDNPHasChain]>;
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def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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[SDNPHasChain]>;
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def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
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[SDNPHasChain]>;
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def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
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[SDNPHasChain]>;
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2010-03-28 05:07:17 +00:00
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def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
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def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
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2006-01-09 18:33:28 +00:00
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def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
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def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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2005-12-21 02:39:21 +00:00
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2007-09-29 00:00:36 +00:00
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
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2008-12-23 22:45:23 +00:00
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def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
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2007-09-29 00:00:36 +00:00
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def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
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2006-01-09 18:33:28 +00:00
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def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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2007-09-25 01:57:46 +00:00
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[SDNPHasChain]>;
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2007-09-29 00:00:36 +00:00
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def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
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2009-12-16 00:53:11 +00:00
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def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
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2005-12-21 02:39:21 +00:00
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2008-03-01 21:52:34 +00:00
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def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
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2010-09-22 00:34:38 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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2011-08-26 21:21:21 +00:00
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def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
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2010-09-22 00:34:38 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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2011-08-26 21:21:21 +00:00
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def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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2008-10-02 18:53:47 +00:00
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def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-02 18:53:47 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-02 18:53:47 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-02 18:53:47 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-02 18:53:47 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-02 18:53:47 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-02 18:53:47 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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2008-10-03 22:25:52 +00:00
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def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
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2010-10-20 23:40:27 +00:00
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[SDNPHasChain, SDNPMayStore,
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2008-10-03 22:25:52 +00:00
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SDNPMayLoad, SDNPMemOperand]>;
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2006-01-09 18:33:28 +00:00
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def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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2005-12-21 02:39:21 +00:00
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2009-08-15 01:38:56 +00:00
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def X86vastart_save_xmm_regs :
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SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
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SDT_X86VASTART_SAVE_XMM_REGS,
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2010-03-19 05:07:09 +00:00
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[SDNPHasChain, SDNPVariadic]>;
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2010-10-12 18:00:49 +00:00
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def X86vaarg64 :
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SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
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[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
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SDNPMemOperand]>;
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2006-01-09 18:33:28 +00:00
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def X86callseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOutGlue]>;
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2006-01-09 18:33:28 +00:00
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def X86callseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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2005-12-21 02:39:21 +00:00
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2006-01-09 18:33:28 +00:00
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def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
|
2010-03-19 05:07:09 +00:00
|
|
|
SDNPVariadic]>;
|
2005-12-17 01:24:02 +00:00
|
|
|
|
2010-03-28 07:38:39 +00:00
|
|
|
def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
|
2010-03-28 07:38:39 +00:00
|
|
|
def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
|
2008-01-10 05:12:37 +00:00
|
|
|
SDNPMayLoad]>;
|
2006-01-11 22:15:48 +00:00
|
|
|
|
2010-03-06 19:32:29 +00:00
|
|
|
def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
|
2006-01-05 00:27:02 +00:00
|
|
|
|
2006-11-30 21:55:46 +00:00
|
|
|
def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
|
|
|
|
|
def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
|
2006-02-25 10:02:21 +00:00
|
|
|
|
2007-04-20 21:38:10 +00:00
|
|
|
def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
|
2007-04-20 21:38:10 +00:00
|
|
|
|
2007-07-14 14:06:15 +00:00
|
|
|
def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
|
|
|
|
|
[SDNPHasChain]>;
|
|
|
|
|
|
2010-10-20 23:40:27 +00:00
|
|
|
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
2007-04-20 21:38:10 +00:00
|
|
|
|
2010-01-04 20:51:05 +00:00
|
|
|
def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
|
2010-01-05 00:44:20 +00:00
|
|
|
[SDNPCommutative]>;
|
2009-03-04 19:44:21 +00:00
|
|
|
def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
|
2010-01-04 20:51:05 +00:00
|
|
|
def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
|
2010-01-05 00:44:20 +00:00
|
|
|
[SDNPCommutative]>;
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
|
2010-01-05 00:44:20 +00:00
|
|
|
[SDNPCommutative]>;
|
2010-12-20 00:59:46 +00:00
|
|
|
def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
|
|
|
|
|
def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
|
2010-10-20 23:40:27 +00:00
|
|
|
|
2009-03-04 19:44:21 +00:00
|
|
|
def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
|
|
|
|
|
def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
|
2010-01-04 20:51:05 +00:00
|
|
|
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
|
2010-01-05 00:44:20 +00:00
|
|
|
[SDNPCommutative]>;
|
2010-01-04 20:51:05 +00:00
|
|
|
def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
|
2010-01-05 00:44:20 +00:00
|
|
|
[SDNPCommutative]>;
|
2010-01-04 20:51:05 +00:00
|
|
|
def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
|
2010-01-05 00:44:20 +00:00
|
|
|
[SDNPCommutative]>;
|
2011-10-14 07:06:56 +00:00
|
|
|
def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
|
2008-12-12 00:56:36 +00:00
|
|
|
|
2009-03-30 21:36:47 +00:00
|
|
|
def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
|
|
|
|
|
|
2010-10-21 01:41:01 +00:00
|
|
|
def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
|
2010-10-21 01:41:01 +00:00
|
|
|
|
2011-08-30 19:43:21 +00:00
|
|
|
def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
|
|
|
|
|
[SDNPHasChain]>;
|
|
|
|
|
|
2010-06-03 04:07:48 +00:00
|
|
|
def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
|
2010-12-23 18:28:41 +00:00
|
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
|
2010-03-06 19:32:29 +00:00
|
|
|
|
2005-12-17 01:24:02 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// X86 Operand Definitions.
|
|
|
|
|
//
|
|
|
|
|
|
2009-07-30 01:56:29 +00:00
|
|
|
// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
|
|
|
|
|
// the index operand of an address, to conform to x86 encoding restrictions.
|
|
|
|
|
def ptr_rc_nosp : PointerLikeRegClass<1>;
|
2009-06-20 19:34:09 +00:00
|
|
|
|
2004-08-11 02:25:00 +00:00
|
|
|
// *mem - Operand definitions for the funky X86 addressing mode operands.
|
|
|
|
|
//
|
2009-08-10 18:41:10 +00:00
|
|
|
def X86MemAsmOperand : AsmOperandClass {
|
|
|
|
|
let Name = "Mem";
|
2010-05-22 21:02:29 +00:00
|
|
|
let SuperClasses = [];
|
2009-08-10 18:41:10 +00:00
|
|
|
}
|
2010-05-06 22:39:14 +00:00
|
|
|
def X86AbsMemAsmOperand : AsmOperandClass {
|
|
|
|
|
let Name = "AbsMem";
|
2010-07-08 23:46:44 +00:00
|
|
|
let SuperClasses = [X86MemAsmOperand];
|
2010-05-06 22:39:14 +00:00
|
|
|
}
|
2006-05-17 21:21:41 +00:00
|
|
|
class X86MemOperand<string printMethod> : Operand<iPTR> {
|
2005-11-30 18:54:35 +00:00
|
|
|
let PrintMethod = printMethod;
|
2009-07-30 01:56:29 +00:00
|
|
|
let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
|
2009-08-10 18:41:10 +00:00
|
|
|
let ParserMatchClass = X86MemAsmOperand;
|
2004-08-11 02:25:00 +00:00
|
|
|
}
|
2005-11-30 18:54:35 +00:00
|
|
|
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_MEMORY" in {
|
2009-09-03 00:04:47 +00:00
|
|
|
def opaque32mem : X86MemOperand<"printopaquemem">;
|
|
|
|
|
def opaque48mem : X86MemOperand<"printopaquemem">;
|
|
|
|
|
def opaque80mem : X86MemOperand<"printopaquemem">;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def opaque512mem : X86MemOperand<"printopaquemem">;
|
|
|
|
|
|
2005-12-17 19:47:05 +00:00
|
|
|
def i8mem : X86MemOperand<"printi8mem">;
|
|
|
|
|
def i16mem : X86MemOperand<"printi16mem">;
|
|
|
|
|
def i32mem : X86MemOperand<"printi32mem">;
|
|
|
|
|
def i64mem : X86MemOperand<"printi64mem">;
|
2006-02-22 02:26:30 +00:00
|
|
|
def i128mem : X86MemOperand<"printi128mem">;
|
2010-07-19 23:32:44 +00:00
|
|
|
def i256mem : X86MemOperand<"printi256mem">;
|
2005-12-17 19:47:05 +00:00
|
|
|
def f32mem : X86MemOperand<"printf32mem">;
|
|
|
|
|
def f64mem : X86MemOperand<"printf64mem">;
|
2007-08-05 18:49:15 +00:00
|
|
|
def f80mem : X86MemOperand<"printf80mem">;
|
2006-01-31 22:28:30 +00:00
|
|
|
def f128mem : X86MemOperand<"printf128mem">;
|
2010-07-09 18:27:43 +00:00
|
|
|
def f256mem : X86MemOperand<"printf256mem">;
|
2011-07-14 21:47:22 +00:00
|
|
|
}
|
2005-11-30 18:54:35 +00:00
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
|
|
|
|
|
// plain GR64, so that it doesn't potentially require a REX prefix.
|
|
|
|
|
def i8mem_NOREX : Operand<i64> {
|
|
|
|
|
let PrintMethod = "printi8mem";
|
2009-07-30 01:56:29 +00:00
|
|
|
let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
|
2009-08-10 18:41:10 +00:00
|
|
|
let ParserMatchClass = X86MemAsmOperand;
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_MEMORY";
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
|
|
|
|
|
2011-01-26 02:04:09 +00:00
|
|
|
// GPRs available for tailcall.
|
|
|
|
|
// It represents GR64_TC or GR64_TCW64.
|
|
|
|
|
def ptr_rc_tailcall : PointerLikeRegClass<2>;
|
|
|
|
|
|
2010-03-14 03:48:46 +00:00
|
|
|
// Special i32mem for addresses of load folding tail calls. These are not
|
|
|
|
|
// allowed to use callee-saved registers since they must be scheduled
|
|
|
|
|
// after callee-saved register are popped.
|
|
|
|
|
def i32mem_TC : Operand<i32> {
|
|
|
|
|
let PrintMethod = "printi32mem";
|
|
|
|
|
let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
|
|
|
|
|
let ParserMatchClass = X86MemAsmOperand;
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_MEMORY";
|
2010-03-14 03:48:46 +00:00
|
|
|
}
|
|
|
|
|
|
2010-10-05 06:37:31 +00:00
|
|
|
// Special i64mem for addresses of load folding tail calls. These are not
|
|
|
|
|
// allowed to use callee-saved registers since they must be scheduled
|
|
|
|
|
// after callee-saved register are popped.
|
|
|
|
|
def i64mem_TC : Operand<i64> {
|
|
|
|
|
let PrintMethod = "printi64mem";
|
2011-01-26 02:04:09 +00:00
|
|
|
let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
|
|
|
|
|
ptr_rc_tailcall, i32imm, i8imm);
|
2010-10-05 06:37:31 +00:00
|
|
|
let ParserMatchClass = X86MemAsmOperand;
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_MEMORY";
|
2010-10-05 06:37:31 +00:00
|
|
|
}
|
2006-09-08 06:48:29 +00:00
|
|
|
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_PCREL",
|
|
|
|
|
ParserMatchClass = X86AbsMemAsmOperand,
|
2010-01-30 01:02:48 +00:00
|
|
|
PrintMethod = "print_pcrel_imm" in {
|
2010-01-30 00:24:12 +00:00
|
|
|
def i32imm_pcrel : Operand<i32>;
|
2010-07-07 22:27:31 +00:00
|
|
|
def i16imm_pcrel : Operand<i16>;
|
2010-01-30 00:24:12 +00:00
|
|
|
|
|
|
|
|
def offset8 : Operand<i64>;
|
|
|
|
|
def offset16 : Operand<i64>;
|
|
|
|
|
def offset32 : Operand<i64>;
|
|
|
|
|
def offset64 : Operand<i64>;
|
|
|
|
|
|
|
|
|
|
// Branch targets have OtherVT type and print as pc-relative values.
|
|
|
|
|
def brtarget : Operand<OtherVT>;
|
|
|
|
|
def brtarget8 : Operand<OtherVT>;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2005-07-15 00:38:55 +00:00
|
|
|
def SSECC : Operand<i8> {
|
|
|
|
|
let PrintMethod = "printSSECC";
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_IMMEDIATE";
|
2005-07-15 00:38:55 +00:00
|
|
|
}
|
2004-08-11 02:25:00 +00:00
|
|
|
|
2010-05-22 21:02:33 +00:00
|
|
|
class ImmSExtAsmOperandClass : AsmOperandClass {
|
2010-05-22 21:02:29 +00:00
|
|
|
let SuperClasses = [ImmAsmOperand];
|
2010-05-22 21:02:33 +00:00
|
|
|
let RenderMethod = "addImmOperands";
|
2010-05-20 20:20:39 +00:00
|
|
|
}
|
|
|
|
|
|
2011-07-27 23:01:50 +00:00
|
|
|
class ImmZExtAsmOperandClass : AsmOperandClass {
|
|
|
|
|
let SuperClasses = [ImmAsmOperand];
|
|
|
|
|
let RenderMethod = "addImmOperands";
|
|
|
|
|
}
|
|
|
|
|
|
2010-05-22 21:02:33 +00:00
|
|
|
// Sign-extended immediate classes. We don't need to define the full lattice
|
|
|
|
|
// here because there is no instruction with an ambiguity between ImmSExti64i32
|
|
|
|
|
// and ImmSExti32i8.
|
|
|
|
|
//
|
|
|
|
|
// The strange ranges come from the fact that the assembler always works with
|
|
|
|
|
// 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
|
|
|
|
|
// (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
|
|
|
|
|
|
2010-07-08 23:46:44 +00:00
|
|
|
// [0, 0x7FFFFFFF] |
|
|
|
|
|
// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
|
2010-05-22 21:02:33 +00:00
|
|
|
def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
|
|
|
|
|
let Name = "ImmSExti64i32";
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-08 23:46:44 +00:00
|
|
|
// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
|
|
|
|
|
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
|
2010-05-22 21:02:33 +00:00
|
|
|
def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
|
|
|
|
|
let Name = "ImmSExti16i8";
|
|
|
|
|
let SuperClasses = [ImmSExti64i32AsmOperand];
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-08 23:46:44 +00:00
|
|
|
// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
|
|
|
|
|
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
|
2010-05-22 21:02:33 +00:00
|
|
|
def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
|
|
|
|
|
let Name = "ImmSExti32i8";
|
|
|
|
|
}
|
|
|
|
|
|
2011-07-27 23:01:50 +00:00
|
|
|
// [0, 0x000000FF]
|
|
|
|
|
def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
|
|
|
|
|
let Name = "ImmZExtu32u8";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2010-07-08 23:46:44 +00:00
|
|
|
// [0, 0x0000007F] |
|
|
|
|
|
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
|
2010-05-22 21:02:33 +00:00
|
|
|
def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
|
|
|
|
|
let Name = "ImmSExti64i8";
|
2010-07-08 23:46:44 +00:00
|
|
|
let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
|
|
|
|
|
ImmSExti64i32AsmOperand];
|
2009-08-10 18:41:10 +00:00
|
|
|
}
|
|
|
|
|
|
2005-11-18 01:04:42 +00:00
|
|
|
// A couple of more descriptive operand definitions.
|
|
|
|
|
// 16-bits but only 8 bits are significant.
|
2009-08-09 07:20:21 +00:00
|
|
|
def i16i8imm : Operand<i16> {
|
2010-05-22 21:02:33 +00:00
|
|
|
let ParserMatchClass = ImmSExti16i8AsmOperand;
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_IMMEDIATE";
|
2009-08-09 07:20:21 +00:00
|
|
|
}
|
2005-11-18 01:04:42 +00:00
|
|
|
// 32-bits but only 8 bits are significant.
|
2009-08-09 07:20:21 +00:00
|
|
|
def i32i8imm : Operand<i32> {
|
2010-05-22 21:02:33 +00:00
|
|
|
let ParserMatchClass = ImmSExti32i8AsmOperand;
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_IMMEDIATE";
|
2009-08-09 07:20:21 +00:00
|
|
|
}
|
2011-07-27 23:01:50 +00:00
|
|
|
// 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
|
|
|
|
|
def u32u8imm : Operand<i32> {
|
|
|
|
|
let ParserMatchClass = ImmZExtu32u8AsmOperand;
|
|
|
|
|
let OperandType = "OPERAND_IMMEDIATE";
|
|
|
|
|
}
|
2005-11-18 01:04:42 +00:00
|
|
|
|
2010-10-05 06:37:31 +00:00
|
|
|
// 64-bits but only 32 bits are significant.
|
|
|
|
|
def i64i32imm : Operand<i64> {
|
|
|
|
|
let ParserMatchClass = ImmSExti64i32AsmOperand;
|
2011-07-14 21:47:22 +00:00
|
|
|
let OperandType = "OPERAND_IMMEDIATE";
|
2010-10-05 06:37:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// 64-bits but only 32 bits are significant, and those bits are treated as being
|
|
|
|
|
// pc relative.
|
|
|
|
|
def i64i32imm_pcrel : Operand<i64> {
|
|
|
|
|
let PrintMethod = "print_pcrel_imm";
|
|
|
|
|
let ParserMatchClass = X86AbsMemAsmOperand;
|
2011-08-22 22:55:32 +00:00
|
|
|
let OperandType = "OPERAND_PCREL";
|
2010-10-05 06:37:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// 64-bits but only 8 bits are significant.
|
|
|
|
|
def i64i8imm : Operand<i64> {
|
|
|
|
|
let ParserMatchClass = ImmSExti64i8AsmOperand;
|
2011-08-22 22:55:32 +00:00
|
|
|
let OperandType = "OPERAND_IMMEDIATE";
|
2010-10-05 06:37:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
def lea64_32mem : Operand<i32> {
|
|
|
|
|
let PrintMethod = "printi32mem";
|
|
|
|
|
let AsmOperandLowerMethod = "lower_lea64_32mem";
|
|
|
|
|
let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
|
|
|
|
|
let ParserMatchClass = X86MemAsmOperand;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2005-12-17 01:24:02 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// X86 Complex Pattern Definitions.
|
|
|
|
|
//
|
|
|
|
|
|
2005-12-08 02:01:35 +00:00
|
|
|
// Define X86 specific addressing mode.
|
2010-09-21 22:07:31 +00:00
|
|
|
def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
|
2010-07-08 23:46:44 +00:00
|
|
|
def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
|
2009-08-02 16:09:17 +00:00
|
|
|
[add, sub, mul, X86mul_imm, shl, or, frameindex],
|
|
|
|
|
[]>;
|
2010-07-08 23:46:44 +00:00
|
|
|
def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
|
2009-06-20 20:38:48 +00:00
|
|
|
[tglobaltlsaddr], []>;
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2010-10-05 06:37:31 +00:00
|
|
|
def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
|
|
|
|
|
[add, sub, mul, X86mul_imm, shl, or, frameindex,
|
|
|
|
|
X86WrapperRIP], []>;
|
|
|
|
|
|
|
|
|
|
def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
|
|
|
|
|
[tglobaltlsaddr], []>;
|
|
|
|
|
|
2005-12-20 22:59:51 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// X86 Instruction Predicate Definitions.
|
2010-03-14 18:31:44 +00:00
|
|
|
def HasCMov : Predicate<"Subtarget->hasCMov()">;
|
|
|
|
|
def NoCMov : Predicate<"!Subtarget->hasCMov()">;
|
2010-12-03 22:29:15 +00:00
|
|
|
|
2010-12-10 00:26:57 +00:00
|
|
|
def HasMMX : Predicate<"Subtarget->hasMMX()">;
|
2010-10-03 18:08:05 +00:00
|
|
|
def Has3DNow : Predicate<"Subtarget->has3DNow()">;
|
|
|
|
|
def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
|
2010-12-10 00:26:57 +00:00
|
|
|
def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
|
|
|
|
|
def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
|
|
|
|
|
def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
|
|
|
|
|
def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
|
|
|
|
|
def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
|
|
|
|
|
def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
|
|
|
|
|
def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
|
2010-12-03 22:29:15 +00:00
|
|
|
|
2009-06-26 22:46:54 +00:00
|
|
|
def HasAVX : Predicate<"Subtarget->hasAVX()">;
|
2010-12-10 00:26:57 +00:00
|
|
|
def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
|
|
|
|
|
|
2011-10-11 07:13:09 +00:00
|
|
|
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
|
2010-12-10 00:26:57 +00:00
|
|
|
def HasAES : Predicate<"Subtarget->hasAES()">;
|
2010-07-23 01:17:51 +00:00
|
|
|
def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
|
2009-06-26 22:46:54 +00:00
|
|
|
def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
|
|
|
|
|
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
|
2011-10-03 17:28:23 +00:00
|
|
|
def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
|
|
|
|
|
def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
|
2011-10-09 07:31:39 +00:00
|
|
|
def HasF16C : Predicate<"Subtarget->hasF16C()">;
|
2011-10-11 06:44:02 +00:00
|
|
|
def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
|
2011-10-14 03:21:46 +00:00
|
|
|
def HasBMI : Predicate<"Subtarget->hasBMI()">;
|
2010-12-10 00:26:57 +00:00
|
|
|
def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
|
|
|
|
|
def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
|
2011-08-26 21:21:21 +00:00
|
|
|
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
|
2011-07-08 01:53:10 +00:00
|
|
|
def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
|
|
|
|
|
AssemblerPredicate<"!Mode64Bit">;
|
|
|
|
|
def In64BitMode : Predicate<"Subtarget->is64Bit()">,
|
|
|
|
|
AssemblerPredicate<"Mode64Bit">;
|
2009-08-03 08:12:53 +00:00
|
|
|
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
|
|
|
|
|
def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
|
2011-09-05 21:51:43 +00:00
|
|
|
def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">,
|
|
|
|
|
AssemblerPredicate<"ModeNaCl">;
|
|
|
|
|
def IsNaCl32 : Predicate<"Subtarget->isTargetNaCl32()">,
|
|
|
|
|
AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
|
|
|
|
|
def IsNaCl64 : Predicate<"Subtarget->isTargetNaCl64()">,
|
|
|
|
|
AssemblerPredicate<"ModeNaCl,Mode64Bit">;
|
|
|
|
|
def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">,
|
|
|
|
|
AssemblerPredicate<"!ModeNaCl">;
|
2009-08-06 11:23:24 +00:00
|
|
|
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
|
|
|
|
|
def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
|
|
|
|
|
def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
|
2009-08-06 09:11:19 +00:00
|
|
|
"TM.getCodeModel() != CodeModel::Kernel">;
|
2009-08-06 11:23:24 +00:00
|
|
|
def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
|
|
|
|
|
"TM.getCodeModel() == CodeModel::Kernel">;
|
2006-12-05 19:50:18 +00:00
|
|
|
def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
|
2010-03-25 00:10:31 +00:00
|
|
|
def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
|
2009-12-22 17:47:23 +00:00
|
|
|
def OptForSize : Predicate<"OptForSize">;
|
2008-09-26 23:41:32 +00:00
|
|
|
def OptForSpeed : Predicate<"!OptForSize">;
|
2009-01-02 05:35:45 +00:00
|
|
|
def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
|
2009-05-20 04:53:57 +00:00
|
|
|
def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
|
2005-12-20 22:59:51 +00:00
|
|
|
|
2005-12-17 01:24:02 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-07-31 08:04:03 +00:00
|
|
|
// X86 Instruction Format Definitions.
|
2005-12-17 01:24:02 +00:00
|
|
|
//
|
|
|
|
|
|
2007-07-31 08:04:03 +00:00
|
|
|
include "X86InstrFormats.td"
|
2003-08-03 21:54:21 +00:00
|
|
|
|
2005-11-18 01:04:42 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2011-04-17 21:38:24 +00:00
|
|
|
// Pattern fragments.
|
2005-11-18 01:04:42 +00:00
|
|
|
//
|
2006-01-06 00:43:03 +00:00
|
|
|
|
|
|
|
|
// X86 specific condition code. These correspond to CondCode in
|
2007-05-06 04:00:55 +00:00
|
|
|
// X86InstrInfo.h. They must be kept in synch.
|
2009-01-07 00:15:08 +00:00
|
|
|
def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
|
|
|
|
|
def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
|
|
|
|
|
def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
|
|
|
|
|
def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
|
|
|
|
|
def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
|
|
|
|
|
def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
|
|
|
|
|
def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
|
|
|
|
|
def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
|
|
|
|
|
def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
|
|
|
|
|
def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
|
2006-01-06 00:43:03 +00:00
|
|
|
def X86_COND_NO : PatLeaf<(i8 10)>;
|
2009-01-07 00:15:08 +00:00
|
|
|
def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
|
2006-01-06 00:43:03 +00:00
|
|
|
def X86_COND_NS : PatLeaf<(i8 12)>;
|
2009-01-07 00:15:08 +00:00
|
|
|
def X86_COND_O : PatLeaf<(i8 13)>;
|
|
|
|
|
def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
|
|
|
|
|
def X86_COND_S : PatLeaf<(i8 15)>;
|
2006-01-06 00:43:03 +00:00
|
|
|
|
2011-04-18 06:36:55 +00:00
|
|
|
let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
|
2011-04-20 03:19:42 +00:00
|
|
|
def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
|
|
|
|
|
def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
|
|
|
|
|
def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
|
2011-04-18 06:36:55 +00:00
|
|
|
}
|
|
|
|
|
|
2011-04-17 22:12:55 +00:00
|
|
|
def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
|
2005-11-18 01:04:42 +00:00
|
|
|
|
2011-04-17 22:05:17 +00:00
|
|
|
|
2011-04-17 22:12:55 +00:00
|
|
|
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
|
|
|
|
|
// unsigned field.
|
|
|
|
|
def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
|
2011-04-17 22:05:17 +00:00
|
|
|
|
2011-04-17 22:12:55 +00:00
|
|
|
def i64immZExt32SExt8 : ImmLeaf<i64, [{
|
|
|
|
|
return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
|
2010-10-13 13:31:20 +00:00
|
|
|
}]>;
|
|
|
|
|
|
2005-12-13 01:57:51 +00:00
|
|
|
// Helper fragments for loads.
|
2008-05-13 18:59:59 +00:00
|
|
|
// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
|
|
|
|
|
// known to be 32-bit aligned or better. Ditto for i8 to i16.
|
2008-10-15 06:50:19 +00:00
|
|
|
def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
|
|
|
if (ExtType == ISD::NON_EXTLOAD)
|
|
|
|
|
return true;
|
|
|
|
|
if (ExtType == ISD::EXTLOAD)
|
|
|
|
|
return LD->getAlignment() >= 2 && !LD->isVolatile();
|
2008-05-13 00:54:02 +00:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2010-03-03 01:52:59 +00:00
|
|
|
def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
|
2008-09-24 23:27:55 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
|
|
|
if (ExtType == ISD::EXTLOAD)
|
|
|
|
|
return LD->getAlignment() >= 2 && !LD->isVolatile();
|
|
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2008-10-15 06:50:19 +00:00
|
|
|
def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
|
|
|
if (ExtType == ISD::NON_EXTLOAD)
|
|
|
|
|
return true;
|
|
|
|
|
if (ExtType == ISD::EXTLOAD)
|
|
|
|
|
return LD->getAlignment() >= 4 && !LD->isVolatile();
|
2008-05-13 00:54:02 +00:00
|
|
|
return false;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2010-09-21 22:07:31 +00:00
|
|
|
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
|
|
|
|
|
def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
|
|
|
|
|
def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
|
|
|
|
|
def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
|
|
|
|
|
def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
|
2005-12-14 02:22:27 +00:00
|
|
|
|
2006-10-09 20:57:25 +00:00
|
|
|
def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
|
|
|
|
|
def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
|
|
|
|
|
def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
|
2010-10-05 06:37:31 +00:00
|
|
|
def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
|
|
|
|
|
def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
|
|
|
|
|
def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
|
2006-10-09 20:57:25 +00:00
|
|
|
|
|
|
|
|
def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
|
|
|
|
|
def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
|
|
|
|
|
def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
|
|
|
|
|
def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
|
|
|
|
|
def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
|
|
|
|
|
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
|
2010-10-05 06:37:31 +00:00
|
|
|
def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
|
|
|
|
|
def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
|
|
|
|
|
def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
|
|
|
|
|
def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
|
2006-10-09 20:57:25 +00:00
|
|
|
|
|
|
|
|
def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
|
|
|
|
|
def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
|
|
|
|
|
def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
|
|
|
|
|
def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
|
|
|
|
|
def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
|
|
|
|
|
def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
|
2010-10-05 06:37:31 +00:00
|
|
|
def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
|
|
|
|
|
def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
|
|
|
|
|
def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
|
|
|
|
|
def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
|
2006-02-21 02:24:38 +00:00
|
|
|
|
Don't fold and's into test instructions if they have multiple uses.
This compiles test-nofold.ll into:
_test:
movl $15, %ecx
andl 4(%esp), %ecx
testl %ecx, %ecx
movl $42, %eax
cmove %ecx, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl %eax, %ecx
andl $15, %ecx
testl $15, %eax
movl $42, %eax
cmove %ecx, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47330 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-19 17:37:35 +00:00
|
|
|
|
|
|
|
|
// An 'and' node with a single use.
|
|
|
|
|
def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
|
2008-03-04 00:40:35 +00:00
|
|
|
return N->hasOneUse();
|
Don't fold and's into test instructions if they have multiple uses.
This compiles test-nofold.ll into:
_test:
movl $15, %ecx
andl 4(%esp), %ecx
testl %ecx, %ecx
movl $42, %eax
cmove %ecx, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl %eax, %ecx
andl $15, %ecx
testl $15, %eax
movl $42, %eax
cmove %ecx, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47330 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-19 17:37:35 +00:00
|
|
|
}]>;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// An 'srl' node with a single use.
|
|
|
|
|
def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
|
|
|
|
|
return N->hasOneUse();
|
|
|
|
|
}]>;
|
|
|
|
|
// An 'trunc' node with a single use.
|
|
|
|
|
def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
|
|
|
|
|
return N->hasOneUse();
|
|
|
|
|
}]>;
|
Don't fold and's into test instructions if they have multiple uses.
This compiles test-nofold.ll into:
_test:
movl $15, %ecx
andl 4(%esp), %ecx
testl %ecx, %ecx
movl $42, %eax
cmove %ecx, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl %eax, %ecx
andl $15, %ecx
testl $15, %eax
movl $42, %eax
cmove %ecx, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47330 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-19 17:37:35 +00:00
|
|
|
|
2003-08-03 21:54:21 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-10-05 05:32:15 +00:00
|
|
|
// Instruction list.
|
2003-08-03 21:54:21 +00:00
|
|
|
//
|
|
|
|
|
|
2006-01-11 00:33:36 +00:00
|
|
|
// Nop
|
2009-07-23 23:39:34 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2008-01-10 07:59:24 +00:00
|
|
|
def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
|
|
|
|
|
"nop{w}\t$zero", []>, TB, OpSize;
|
2009-07-23 23:39:34 +00:00
|
|
|
def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
"nop{l}\t$zero", []>, TB;
|
2009-07-23 23:39:34 +00:00
|
|
|
}
|
2006-01-11 00:33:36 +00:00
|
|
|
|
2003-08-03 21:54:21 +00:00
|
|
|
|
2009-09-16 02:57:13 +00:00
|
|
|
// Constructing a stack frame.
|
2010-09-17 18:02:29 +00:00
|
|
|
def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
|
|
|
|
|
"enter\t$len, $lvl", []>;
|
2009-09-16 02:57:13 +00:00
|
|
|
|
2008-01-10 07:59:24 +00:00
|
|
|
let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
|
2004-08-10 20:17:41 +00:00
|
|
|
def LEAVE : I<0xC9, RawFrm,
|
2010-07-19 07:21:01 +00:00
|
|
|
(outs), (ins), "leave", []>, Requires<[In32BitMode]>;
|
2007-09-11 19:55:27 +00:00
|
|
|
|
2010-10-05 06:41:40 +00:00
|
|
|
let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
|
|
|
|
|
def LEAVE64 : I<0xC9, RawFrm,
|
|
|
|
|
(outs), (ins), "leave", []>, Requires<[In64BitMode]>;
|
|
|
|
|
|
2010-10-05 06:04:14 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-10-05 06:41:40 +00:00
|
|
|
// Miscellaneous Instructions.
|
2010-10-05 06:04:14 +00:00
|
|
|
//
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2008-01-10 07:59:24 +00:00
|
|
|
let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
|
2009-09-10 18:29:13 +00:00
|
|
|
let mayLoad = 1 in {
|
|
|
|
|
def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
|
|
|
|
|
OpSize;
|
|
|
|
|
def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
|
|
|
|
|
def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
|
|
|
|
|
OpSize;
|
|
|
|
|
def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
|
|
|
|
|
OpSize;
|
|
|
|
|
def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
|
|
|
|
|
def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
|
2010-10-05 06:47:35 +00:00
|
|
|
|
|
|
|
|
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
|
|
|
|
|
def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
|
|
|
|
|
Requires<[In32BitMode]>;
|
2009-09-10 18:29:13 +00:00
|
|
|
}
|
2003-08-03 21:54:21 +00:00
|
|
|
|
2009-09-10 18:29:13 +00:00
|
|
|
let mayStore = 1 in {
|
|
|
|
|
def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
|
|
|
|
|
OpSize;
|
2007-09-26 01:29:06 +00:00
|
|
|
def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
|
2009-09-10 18:29:13 +00:00
|
|
|
def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
|
|
|
|
|
OpSize;
|
|
|
|
|
def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
|
|
|
|
|
OpSize;
|
|
|
|
|
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
|
|
|
|
|
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
|
2007-04-17 09:20:00 +00:00
|
|
|
|
2010-10-20 23:40:27 +00:00
|
|
|
def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
|
2009-06-15 20:59:31 +00:00
|
|
|
"push{l}\t$imm", []>;
|
2010-10-20 23:40:27 +00:00
|
|
|
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
2010-05-03 20:45:05 +00:00
|
|
|
"push{w}\t$imm", []>, OpSize;
|
2010-10-20 23:40:27 +00:00
|
|
|
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
|
2009-06-15 20:59:31 +00:00
|
|
|
"push{l}\t$imm", []>;
|
2010-10-20 23:40:27 +00:00
|
|
|
|
2010-05-20 16:16:00 +00:00
|
|
|
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
|
|
|
|
|
def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
|
|
|
|
|
Requires<[In32BitMode]>;
|
2010-10-05 06:47:35 +00:00
|
|
|
|
|
|
|
|
}
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
}
|
2007-09-26 01:29:06 +00:00
|
|
|
|
2010-10-05 06:47:35 +00:00
|
|
|
let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
|
|
|
|
|
let mayLoad = 1 in {
|
|
|
|
|
def POP64r : I<0x58, AddRegFrm,
|
|
|
|
|
(outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
|
|
|
|
|
def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
|
|
|
|
|
def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
|
|
|
|
|
}
|
|
|
|
|
let mayStore = 1 in {
|
|
|
|
|
def PUSH64r : I<0x50, AddRegFrm,
|
|
|
|
|
(outs), (ins GR64:$reg), "push{q}\t$reg", []>;
|
|
|
|
|
def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
|
|
|
|
|
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
|
2011-07-06 17:23:46 +00:00
|
|
|
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
|
2010-10-05 06:47:35 +00:00
|
|
|
"push{q}\t$imm", []>;
|
2010-10-20 23:40:27 +00:00
|
|
|
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
2010-10-05 06:47:35 +00:00
|
|
|
"push{q}\t$imm", []>;
|
|
|
|
|
def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
|
|
|
|
|
"push{q}\t$imm", []>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
|
|
|
|
|
def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
|
|
|
|
|
Requires<[In64BitMode]>;
|
|
|
|
|
let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
|
|
|
|
|
def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
|
|
|
|
|
Requires<[In64BitMode]>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2010-06-23 20:00:58 +00:00
|
|
|
let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
|
|
|
|
|
mayLoad=1, neverHasSideEffects=1 in {
|
|
|
|
|
def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
|
|
|
|
|
Requires<[In32BitMode]>;
|
|
|
|
|
}
|
|
|
|
|
let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
|
|
|
|
|
mayStore=1, neverHasSideEffects=1 in {
|
|
|
|
|
def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
|
|
|
|
|
Requires<[In32BitMode]>;
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-05 06:52:26 +00:00
|
|
|
let Constraints = "$src = $dst" in { // GR32 = bswap GR32
|
|
|
|
|
def BSWAP32r : I<0xC8, AddRegFrm,
|
|
|
|
|
(outs GR32:$dst), (ins GR32:$src),
|
2010-10-20 23:40:27 +00:00
|
|
|
"bswap{l}\t$dst",
|
2010-10-05 06:52:26 +00:00
|
|
|
[(set GR32:$dst, (bswap GR32:$src))]>, TB;
|
2010-10-20 23:40:27 +00:00
|
|
|
|
2010-10-05 06:47:35 +00:00
|
|
|
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
|
2010-10-20 23:40:27 +00:00
|
|
|
"bswap{q}\t$dst",
|
2010-10-05 06:47:35 +00:00
|
|
|
[(set GR64:$dst, (bswap GR64:$src))]>, TB;
|
2010-10-05 06:52:26 +00:00
|
|
|
} // Constraints = "$src = $dst"
|
2004-10-03 20:35:00 +00:00
|
|
|
|
2007-12-14 02:13:44 +00:00
|
|
|
// Bit scan instructions.
|
|
|
|
|
let Defs = [EFLAGS] in {
|
2007-12-14 18:49:43 +00:00
|
|
|
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsf{w}\t{$src, $dst|$dst, $src}",
|
2010-04-28 23:20:40 +00:00
|
|
|
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
|
2007-12-14 02:13:44 +00:00
|
|
|
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsf{w}\t{$src, $dst|$dst, $src}",
|
2010-04-28 23:20:40 +00:00
|
|
|
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
|
|
|
|
|
OpSize;
|
2007-12-14 18:49:43 +00:00
|
|
|
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsf{l}\t{$src, $dst|$dst, $src}",
|
2010-03-28 05:07:17 +00:00
|
|
|
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
|
2007-12-14 02:13:44 +00:00
|
|
|
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsf{l}\t{$src, $dst|$dst, $src}",
|
2010-03-28 05:07:17 +00:00
|
|
|
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
|
2010-10-05 06:47:35 +00:00
|
|
|
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"bsf{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
|
|
|
|
|
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
|
|
|
"bsf{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
|
2007-12-14 02:13:44 +00:00
|
|
|
|
2007-12-14 18:49:43 +00:00
|
|
|
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsr{w}\t{$src, $dst|$dst, $src}",
|
2010-04-28 23:20:40 +00:00
|
|
|
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
|
2007-12-14 02:13:44 +00:00
|
|
|
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsr{w}\t{$src, $dst|$dst, $src}",
|
2010-04-28 23:20:40 +00:00
|
|
|
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
|
|
|
|
|
OpSize;
|
2007-12-14 18:49:43 +00:00
|
|
|
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsr{l}\t{$src, $dst|$dst, $src}",
|
2010-03-28 05:07:17 +00:00
|
|
|
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
|
2007-12-14 02:13:44 +00:00
|
|
|
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
2007-12-14 15:10:00 +00:00
|
|
|
"bsr{l}\t{$src, $dst|$dst, $src}",
|
2010-03-28 05:07:17 +00:00
|
|
|
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
|
2010-10-05 06:47:35 +00:00
|
|
|
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"bsr{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
|
|
|
|
|
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
|
|
|
"bsr{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
|
2007-12-14 02:13:44 +00:00
|
|
|
} // Defs = [EFLAGS]
|
|
|
|
|
|
2004-08-10 20:17:41 +00:00
|
|
|
|
2010-02-03 21:04:42 +00:00
|
|
|
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
|
|
|
|
|
let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
|
2011-09-09 05:40:53 +00:00
|
|
|
def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
|
|
|
|
|
def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
|
|
|
|
|
def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
|
2010-10-05 06:27:48 +00:00
|
|
|
def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
|
2010-02-03 21:04:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
|
|
|
|
|
let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
|
2011-09-09 05:40:53 +00:00
|
|
|
def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
|
2010-02-03 21:04:42 +00:00
|
|
|
let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
|
2011-09-09 05:40:53 +00:00
|
|
|
def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
|
2010-02-03 21:04:42 +00:00
|
|
|
let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
|
2011-09-09 05:40:53 +00:00
|
|
|
def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
|
2010-10-05 06:27:48 +00:00
|
|
|
let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
|
|
|
|
|
def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
|
2010-02-03 21:04:42 +00:00
|
|
|
|
2011-09-09 05:40:53 +00:00
|
|
|
def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
|
|
|
|
|
def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
|
|
|
|
|
def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
|
2010-10-05 06:27:48 +00:00
|
|
|
def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
|
2009-09-12 00:37:19 +00:00
|
|
|
|
2011-09-09 05:40:53 +00:00
|
|
|
def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
|
|
|
|
|
def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
|
|
|
|
|
def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
|
2010-10-05 06:27:48 +00:00
|
|
|
def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
|
2009-09-12 02:25:20 +00:00
|
|
|
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2003-08-03 21:54:21 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-10-05 05:32:15 +00:00
|
|
|
// Move Instructions.
|
2003-08-03 21:54:21 +00:00
|
|
|
//
|
2010-10-05 20:49:15 +00:00
|
|
|
|
2008-01-10 07:59:24 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{b}\t{$src, $dst|$dst, $src}", []>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{l}\t{$src, $dst|$dst, $src}", []>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
2008-01-10 07:59:24 +00:00
|
|
|
}
|
2008-06-18 08:13:07 +00:00
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{b}\t{$src, $dst|$dst, $src}",
|
2006-05-16 07:21:53 +00:00
|
|
|
[(set GR8:$dst, imm:$src)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{w}\t{$src, $dst|$dst, $src}",
|
2006-05-16 07:21:53 +00:00
|
|
|
[(set GR16:$dst, imm:$src)]>, OpSize;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{l}\t{$src, $dst|$dst, $src}",
|
2006-05-16 07:21:53 +00:00
|
|
|
[(set GR32:$dst, imm:$src)]>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
|
|
|
|
|
"movabs{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, imm:$src)]>;
|
|
|
|
|
def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
|
|
|
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, i64immSExt32:$src)]>;
|
2007-06-26 00:48:07 +00:00
|
|
|
}
|
2010-02-03 21:04:42 +00:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{b}\t{$src, $dst|$dst, $src}",
|
2005-12-10 00:48:20 +00:00
|
|
|
[(store (i8 imm:$src), addr:$dst)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{w}\t{$src, $dst|$dst, $src}",
|
2005-12-10 00:48:20 +00:00
|
|
|
[(store (i16 imm:$src), addr:$dst)]>, OpSize;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{l}\t{$src, $dst|$dst, $src}",
|
2005-12-10 00:48:20 +00:00
|
|
|
[(store (i32 imm:$src), addr:$dst)]>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
|
|
|
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(store i64immSExt32:$src, addr:$dst)]>;
|
2004-10-03 20:35:00 +00:00
|
|
|
|
2010-05-13 00:02:47 +00:00
|
|
|
/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
|
|
|
|
|
/// 32-bit offset from the PC. These are only valid in x86-32 mode.
|
2010-05-12 22:48:24 +00:00
|
|
|
def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{b}\t{$src, %al|AL, $src}", []>,
|
2010-07-19 06:14:44 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2010-05-12 22:48:24 +00:00
|
|
|
def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
|
2010-07-19 06:14:44 +00:00
|
|
|
Requires<[In32BitMode]>;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{l}\t{$src, %eax|EAX, $src}", []>,
|
2010-07-19 06:14:44 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2010-05-12 22:48:24 +00:00
|
|
|
def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{b}\t{%al, $dst|$dst, AL}", []>,
|
2010-07-19 06:14:44 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2010-05-12 22:48:24 +00:00
|
|
|
def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
|
2010-07-19 06:14:44 +00:00
|
|
|
Requires<[In32BitMode]>;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{l}\t{%eax, $dst|$dst, EAX}", []>,
|
2010-07-19 06:14:44 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2010-10-20 23:40:27 +00:00
|
|
|
|
2010-10-05 20:49:15 +00:00
|
|
|
// FIXME: These definitions are utterly broken
|
|
|
|
|
// Just leave them commented out for now because they're useless outside
|
|
|
|
|
// of the large code model, and most compilers won't generate the instructions
|
|
|
|
|
// in question.
|
|
|
|
|
/*
|
|
|
|
|
def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{q}\t{$src, %rax|RAX, $src}", []>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{q}\t{$src, %rax|RAX, $src}", []>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
|
2011-10-02 21:08:12 +00:00
|
|
|
"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
|
2010-10-05 20:49:15 +00:00
|
|
|
*/
|
|
|
|
|
|
2009-09-15 18:47:29 +00:00
|
|
|
|
2010-05-26 22:21:28 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
|
|
|
|
|
"mov{b}\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
|
def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|
|
|
|
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|
|
|
|
def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
|
|
|
"mov{l}\t{$src, $dst|$dst, $src}", []>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
2010-05-26 22:21:28 +00:00
|
|
|
}
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2010-02-27 23:47:46 +00:00
|
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{b}\t{$src, $dst|$dst, $src}",
|
2009-04-10 00:16:23 +00:00
|
|
|
[(set GR8:$dst, (loadi8 addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{w}\t{$src, $dst|$dst, $src}",
|
2009-04-10 00:16:23 +00:00
|
|
|
[(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{l}\t{$src, $dst|$dst, $src}",
|
2009-04-10 00:16:23 +00:00
|
|
|
[(set GR32:$dst, (loadi32 addr:$src))]>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
|
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, (load addr:$src))]>;
|
2007-08-30 05:49:43 +00:00
|
|
|
}
|
2004-10-03 20:35:00 +00:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{b}\t{$src, $dst|$dst, $src}",
|
2006-05-16 07:21:53 +00:00
|
|
|
[(store GR8:$src, addr:$dst)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{w}\t{$src, $dst|$dst, $src}",
|
2006-05-16 07:21:53 +00:00
|
|
|
[(store GR16:$src, addr:$dst)]>, OpSize;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
2007-07-31 20:11:57 +00:00
|
|
|
"mov{l}\t{$src, $dst|$dst, $src}",
|
2006-05-16 07:21:53 +00:00
|
|
|
[(store GR32:$src, addr:$dst)]>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
|
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(store GR64:$src, addr:$dst)]>;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
|
2009-04-27 16:41:36 +00:00
|
|
|
// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
|
|
|
|
|
// that they can be used for copying and storing h registers, which can't be
|
|
|
|
|
// encoded when a REX prefix is present.
|
2010-07-19 06:14:49 +00:00
|
|
|
let isCodeGenOnly = 1 in {
|
2009-04-15 00:04:23 +00:00
|
|
|
let neverHasSideEffects = 1 in
|
2009-04-15 19:48:57 +00:00
|
|
|
def MOV8rr_NOREX : I<0x88, MRMDestReg,
|
|
|
|
|
(outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
|
2009-04-15 00:04:23 +00:00
|
|
|
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
|
2009-04-30 00:58:57 +00:00
|
|
|
let mayStore = 1 in
|
2009-04-15 00:04:23 +00:00
|
|
|
def MOV8mr_NOREX : I<0x88, MRMDestMem,
|
|
|
|
|
(outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
|
|
|
|
|
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
|
2011-10-14 01:00:49 +00:00
|
|
|
let mayLoad = 1, neverHasSideEffects = 1,
|
2010-02-27 23:47:46 +00:00
|
|
|
canFoldAsLoad = 1, isReMaterializable = 1 in
|
2009-04-27 16:41:36 +00:00
|
|
|
def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
|
|
|
|
|
(outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
|
|
|
|
|
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
|
2010-07-19 06:14:49 +00:00
|
|
|
}
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
|
2007-09-25 01:57:46 +00:00
|
|
|
|
2004-02-28 22:02:05 +00:00
|
|
|
// Condition code ops, incl. set if equal/not equal/...
|
2008-01-10 07:59:24 +00:00
|
|
|
let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
|
2007-09-11 19:55:27 +00:00
|
|
|
def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
|
2008-01-10 07:59:24 +00:00
|
|
|
let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
|
2007-09-11 19:55:27 +00:00
|
|
|
def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
|
2004-02-28 22:02:05 +00:00
|
|
|
|
2010-03-09 22:50:40 +00:00
|
|
|
|
2010-10-05 20:49:15 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Bit tests instructions: BT, BTS, BTR, BTC.
|
2007-09-25 01:57:46 +00:00
|
|
|
|
2008-12-23 22:45:23 +00:00
|
|
|
let Defs = [EFLAGS] in {
|
2009-01-13 20:32:45 +00:00
|
|
|
def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
2008-12-23 22:45:23 +00:00
|
|
|
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
|
|
|
[(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
|
2009-01-13 20:32:45 +00:00
|
|
|
def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
2008-12-23 22:45:23 +00:00
|
|
|
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
|
|
|
[(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
|
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
|
|
|
[(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
|
2009-01-13 23:23:30 +00:00
|
|
|
|
|
|
|
|
// Unlike with the register+register form, the memory+register form of the
|
|
|
|
|
// bt instruction does not ignore the high bits of the index. From ISel's
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
// perspective, this is pretty bizarre. Make these instructions disassembly
|
|
|
|
|
// only for now.
|
|
|
|
|
|
|
|
|
|
def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
2010-10-20 23:40:27 +00:00
|
|
|
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
2009-01-13 23:23:30 +00:00
|
|
|
// [(X86bt (loadi16 addr:$src1), GR16:$src2),
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
// (implicit EFLAGS)]
|
|
|
|
|
[]
|
|
|
|
|
>, OpSize, TB, Requires<[FastBTMem]>;
|
|
|
|
|
def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
2010-10-20 23:40:27 +00:00
|
|
|
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
2009-01-13 23:23:30 +00:00
|
|
|
// [(X86bt (loadi32 addr:$src1), GR32:$src2),
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
// (implicit EFLAGS)]
|
|
|
|
|
[]
|
|
|
|
|
>, TB, Requires<[FastBTMem]>;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
|
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
|
|
|
// [(X86bt (loadi64 addr:$src1), GR64:$src2),
|
|
|
|
|
// (implicit EFLAGS)]
|
|
|
|
|
[]
|
|
|
|
|
>, TB;
|
2009-01-13 20:33:23 +00:00
|
|
|
|
|
|
|
|
def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|
|
|
|
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
|
|
|
[(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
|
|
|
|
|
OpSize, TB;
|
2009-01-13 20:33:23 +00:00
|
|
|
def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|
|
|
|
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
|
|
|
[(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
|
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
|
|
|
[(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
|
|
|
|
|
|
2009-01-13 20:33:23 +00:00
|
|
|
// Note that these instructions don't need FastBTMem because that
|
|
|
|
|
// only applies when the other operand is in a register. When it's
|
|
|
|
|
// an immediate, bt is still fast.
|
|
|
|
|
def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|
|
|
|
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
|
|
|
[(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
|
|
|
|
|
]>, OpSize, TB;
|
2009-01-13 20:33:23 +00:00
|
|
|
def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|
|
|
|
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
Now that tblgen can handle matching implicit defs of instructions
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
|
|
|
[(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
|
|
|
|
|
]>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
|
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
|
|
|
[(set EFLAGS, (X86bt (loadi64 addr:$src1),
|
|
|
|
|
i64immSExt8:$src2))]>, TB;
|
|
|
|
|
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
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|
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|
def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
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|
|
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"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
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def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
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"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
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|
|
def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
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|
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
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|
|
def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
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|
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"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
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|
def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
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|
|
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"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
|
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|
|
|
|
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|
|
|
|
"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
|
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|
|
|
|
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|
|
|
|
"btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
|
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
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|
|
|
|
def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|
|
|
|
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|
|
|
|
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
|
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
|
|
|
|
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
|
|
|
|
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
|
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|
|
|
|
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|
|
|
|
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
|
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|
|
|
|
"btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|
|
|
|
"btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
|
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
|
|
|
|
def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|
|
|
|
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|
|
|
|
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
|
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
|
|
|
|
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
|
|
|
|
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
|
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|
|
|
|
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|
|
|
|
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
|
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|
|
|
|
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|
|
|
|
def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|
|
|
|
"bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2010-10-05 20:49:15 +00:00
|
|
|
def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
|
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
2008-12-23 22:45:23 +00:00
|
|
|
} // Defs = [EFLAGS]
|
|
|
|
|
|
2007-07-14 14:06:15 +00:00
|
|
|
|
2008-02-21 06:45:13 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Atomic support
|
|
|
|
|
//
|
2008-03-01 13:37:02 +00:00
|
|
|
|
2010-07-22 02:48:34 +00:00
|
|
|
|
2008-04-19 01:20:30 +00:00
|
|
|
// Atomic swap. These are just normal xchg instructions. But since a memory
|
|
|
|
|
// operand is referenced, the atomicity is ensured.
|
2008-08-06 15:52:50 +00:00
|
|
|
let Constraints = "$val = $dst" in {
|
2010-10-05 06:22:35 +00:00
|
|
|
def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
2010-10-20 23:40:27 +00:00
|
|
|
"xchg{b}\t{$val, $ptr|$ptr, $val}",
|
2010-10-05 06:22:35 +00:00
|
|
|
[(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
|
2010-11-06 08:20:59 +00:00
|
|
|
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
|
2010-10-20 23:40:27 +00:00
|
|
|
"xchg{w}\t{$val, $ptr|$ptr, $val}",
|
|
|
|
|
[(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
|
2008-04-19 01:20:30 +00:00
|
|
|
OpSize;
|
2010-11-06 08:20:59 +00:00
|
|
|
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
|
2010-10-20 23:40:27 +00:00
|
|
|
"xchg{l}\t{$val, $ptr|$ptr, $val}",
|
2010-10-05 06:22:35 +00:00
|
|
|
[(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
|
2010-11-06 08:20:59 +00:00
|
|
|
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
|
2010-10-20 23:40:27 +00:00
|
|
|
"xchg{q}\t{$val, $ptr|$ptr, $val}",
|
2010-10-05 06:22:35 +00:00
|
|
|
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
|
|
|
|
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
|
|
|
|
|
"xchg{b}\t{$val, $src|$src, $val}", []>;
|
2010-10-05 06:22:35 +00:00
|
|
|
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
|
|
|
|
|
"xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
|
|
|
|
|
def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
|
|
|
|
|
"xchg{l}\t{$val, $src|$src, $val}", []>;
|
|
|
|
|
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
|
|
|
|
|
"xchg{q}\t{$val, $src|$src, $val}", []>;
|
2008-04-19 01:20:30 +00:00
|
|
|
}
|
|
|
|
|
|
2011-10-07 05:35:38 +00:00
|
|
|
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
|
2011-10-07 05:35:38 +00:00
|
|
|
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
|
|
|
|
|
"xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
|
|
|
|
|
// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
|
|
|
|
|
// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
|
|
|
|
|
def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
|
|
|
|
|
"xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
|
|
|
|
|
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
|
2011-10-02 21:08:12 +00:00
|
|
|
"xchg{q}\t{$src, %rax|RAX, $src}", []>;
|
2010-10-05 06:22:35 +00:00
|
|
|
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2008-03-01 13:37:02 +00:00
|
|
|
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
|
|
|
|
|
"xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
|
def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
|
|
|
|
"xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
|
|
|
def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
|
|
|
|
"xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
2010-10-05 06:22:35 +00:00
|
|
|
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2010-05-14 16:34:55 +00:00
|
|
|
let mayLoad = 1, mayStore = 1 in {
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
|
|
|
|
"xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
|
def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
|
|
|
|
"xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
|
|
|
def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|
|
|
|
"xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
2010-10-05 06:22:35 +00:00
|
|
|
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
|
|
|
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
|
|
2010-05-14 16:34:55 +00:00
|
|
|
}
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
|
|
|
|
def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
|
|
|
|
|
"cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
|
def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
|
|
|
|
"cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
|
|
|
def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
|
|
|
|
"cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
2010-10-05 06:22:35 +00:00
|
|
|
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2010-05-14 16:34:55 +00:00
|
|
|
let mayLoad = 1, mayStore = 1 in {
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
|
|
|
|
"cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
|
def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
|
|
|
|
"cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
|
|
|
def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|
|
|
|
"cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
2010-10-05 06:22:35 +00:00
|
|
|
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
|
|
|
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
2010-05-14 16:34:55 +00:00
|
|
|
}
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
2010-01-08 01:29:19 +00:00
|
|
|
let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
|
|
|
|
|
"cmpxchg8b\t$dst", []>, TB;
|
|
|
|
|
|
2010-10-05 06:22:35 +00:00
|
|
|
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
|
|
|
|
|
def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
|
2011-08-26 21:21:21 +00:00
|
|
|
"cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
|
2010-10-05 06:22:35 +00:00
|
|
|
|
|
|
|
|
|
2008-10-02 18:53:47 +00:00
|
|
|
|
2010-02-03 21:04:42 +00:00
|
|
|
// Lock instruction prefix
|
|
|
|
|
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
|
|
|
|
|
|
2010-11-23 11:23:24 +00:00
|
|
|
// Rex64 instruction prefix
|
|
|
|
|
def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
|
|
|
|
|
|
2010-11-27 20:29:45 +00:00
|
|
|
// Data16 instruction prefix
|
|
|
|
|
def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
|
|
|
|
|
|
2010-02-03 21:04:42 +00:00
|
|
|
// Repeat string operation instruction prefixes
|
|
|
|
|
// These uses the DF flag in the EFLAGS register to inc or dec ECX
|
|
|
|
|
let Defs = [ECX], Uses = [ECX,EFLAGS] in {
|
|
|
|
|
// Repeat (used with INS, OUTS, MOVS, LODS and STOS)
|
|
|
|
|
def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
|
|
|
|
|
// Repeat while not equal (used with CMPS and SCAS)
|
|
|
|
|
def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2009-09-16 22:59:28 +00:00
|
|
|
// String manipulation instructions
|
|
|
|
|
def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
|
|
|
|
|
def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
|
2010-10-05 06:22:35 +00:00
|
|
|
def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
|
|
|
|
def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
|
|
|
|
|
def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
|
|
|
|
|
def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Flag instructions
|
|
|
|
|
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
|
|
|
|
|
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
|
|
|
|
|
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
|
|
|
|
|
def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
|
|
|
|
|
def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
|
|
|
|
|
def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
|
|
|
|
|
def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
|
|
|
|
|
|
|
|
|
|
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
|
|
|
|
|
|
|
|
|
|
// Table lookup instructions
|
|
|
|
|
def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
|
|
|
|
|
|
2010-10-18 17:04:36 +00:00
|
|
|
// ASCII Adjust After Addition
|
|
|
|
|
// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
|
|
|
|
|
def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
|
|
|
|
|
|
|
|
|
|
// ASCII Adjust AX Before Division
|
|
|
|
|
// sets AL, AH and EFLAGS and uses AL and AH
|
|
|
|
|
def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
|
|
|
|
|
"aad\t$src", []>, Requires<[In32BitMode]>;
|
|
|
|
|
|
|
|
|
|
// ASCII Adjust AX After Multiply
|
|
|
|
|
// sets AL, AH and EFLAGS and uses AL
|
|
|
|
|
def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
|
|
|
|
|
"aam\t$src", []>, Requires<[In32BitMode]>;
|
|
|
|
|
|
2010-10-20 23:40:27 +00:00
|
|
|
// ASCII Adjust AL After Subtraction - sets
|
2010-10-18 17:04:36 +00:00
|
|
|
// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
|
|
|
|
|
def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
|
|
|
|
|
|
|
|
|
|
// Decimal Adjust AL after Addition
|
|
|
|
|
// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
|
|
|
|
|
def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
|
|
|
|
|
|
|
|
|
|
// Decimal Adjust AL after Subtraction
|
|
|
|
|
// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
|
|
|
|
|
def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
|
|
|
|
|
|
|
|
|
|
// Check Array Index Against Bounds
|
|
|
|
|
def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|
|
|
|
"bound\t{$src, $dst|$dst, $src}", []>, OpSize,
|
2010-10-20 23:40:27 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2010-10-18 17:04:36 +00:00
|
|
|
def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|
|
|
|
"bound\t{$src, $dst|$dst, $src}", []>,
|
2010-10-20 23:40:27 +00:00
|
|
|
Requires<[In32BitMode]>;
|
2010-10-18 17:04:36 +00:00
|
|
|
|
|
|
|
|
// Adjust RPL Field of Segment Selector
|
|
|
|
|
def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
|
2010-10-20 23:40:27 +00:00
|
|
|
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
|
2010-10-18 17:04:36 +00:00
|
|
|
def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
|
2010-10-20 23:40:27 +00:00
|
|
|
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
|
2009-09-18 19:59:53 +00:00
|
|
|
|
2011-10-03 17:28:23 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// MOVBE Instructions
|
|
|
|
|
//
|
|
|
|
|
let Predicates = [HasMOVBE] in {
|
|
|
|
|
def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
2011-10-10 18:34:56 +00:00
|
|
|
"movbe{w}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
|
2011-10-03 17:28:23 +00:00
|
|
|
def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
2011-10-10 18:34:56 +00:00
|
|
|
"movbe{l}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
|
2011-10-03 17:28:23 +00:00
|
|
|
def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
2011-10-10 18:34:56 +00:00
|
|
|
"movbe{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
|
2011-10-03 17:28:23 +00:00
|
|
|
def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
2011-10-10 18:34:56 +00:00
|
|
|
"movbe{w}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
|
2011-10-03 17:28:23 +00:00
|
|
|
def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
2011-10-10 18:34:56 +00:00
|
|
|
"movbe{l}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(store (bswap GR32:$src), addr:$dst)]>, T8;
|
2011-10-03 17:28:23 +00:00
|
|
|
def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
2011-10-10 18:34:56 +00:00
|
|
|
"movbe{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(store (bswap GR64:$src), addr:$dst)]>, T8;
|
2011-10-03 17:28:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// RDRAND Instruction
|
|
|
|
|
//
|
|
|
|
|
let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
|
|
|
|
|
def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
|
|
|
|
|
"rdrand{w}\t$dst", []>, OpSize, TB;
|
|
|
|
|
def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
|
|
|
|
|
"rdrand{l}\t$dst", []>, TB;
|
|
|
|
|
def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
|
|
|
|
|
"rdrand{q}\t$dst", []>, TB;
|
|
|
|
|
}
|
|
|
|
|
|
2011-10-11 06:44:02 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// LZCNT Instruction
|
|
|
|
|
//
|
|
|
|
|
let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
|
|
|
|
|
def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|
|
|
|
"lzcnt{w}\t{$src, $dst|$dst, $src}",
|
2011-10-13 06:18:52 +00:00
|
|
|
[(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
|
|
|
|
|
OpSize;
|
2011-10-11 06:44:02 +00:00
|
|
|
def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|
|
|
|
"lzcnt{w}\t{$src, $dst|$dst, $src}",
|
2011-10-13 06:18:52 +00:00
|
|
|
[(set GR16:$dst, (ctlz (loadi16 addr:$src))),
|
|
|
|
|
(implicit EFLAGS)]>, XS, OpSize;
|
2011-10-11 06:44:02 +00:00
|
|
|
|
|
|
|
|
def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
|
|
|
"lzcnt{l}\t{$src, $dst|$dst, $src}",
|
2011-10-13 06:18:52 +00:00
|
|
|
[(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
|
2011-10-11 06:44:02 +00:00
|
|
|
def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|
|
|
|
"lzcnt{l}\t{$src, $dst|$dst, $src}",
|
2011-10-13 06:18:52 +00:00
|
|
|
[(set GR32:$dst, (ctlz (loadi32 addr:$src))),
|
|
|
|
|
(implicit EFLAGS)]>, XS;
|
2011-10-11 06:44:02 +00:00
|
|
|
|
|
|
|
|
def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"lzcnt{q}\t{$src, $dst|$dst, $src}",
|
2011-10-13 06:18:52 +00:00
|
|
|
[(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
|
|
|
|
|
XS;
|
2011-10-11 06:44:02 +00:00
|
|
|
def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
|
|
|
"lzcnt{q}\t{$src, $dst|$dst, $src}",
|
2011-10-13 06:18:52 +00:00
|
|
|
[(set GR64:$dst, (ctlz (loadi64 addr:$src))),
|
|
|
|
|
(implicit EFLAGS)]>, XS;
|
2011-10-11 06:44:02 +00:00
|
|
|
}
|
|
|
|
|
|
2011-10-14 03:21:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2011-10-15 20:46:47 +00:00
|
|
|
// BMI Instructions
|
2011-10-14 03:21:46 +00:00
|
|
|
//
|
|
|
|
|
let Predicates = [HasBMI], Defs = [EFLAGS] in {
|
|
|
|
|
def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|
|
|
|
"tzcnt{w}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
|
|
|
|
|
OpSize;
|
|
|
|
|
def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|
|
|
|
"tzcnt{w}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR16:$dst, (cttz (loadi16 addr:$src))),
|
|
|
|
|
(implicit EFLAGS)]>, XS, OpSize;
|
|
|
|
|
|
|
|
|
|
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
|
|
|
"tzcnt{l}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
|
|
|
|
|
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|
|
|
|
"tzcnt{l}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR32:$dst, (cttz (loadi32 addr:$src))),
|
|
|
|
|
(implicit EFLAGS)]>, XS;
|
|
|
|
|
|
|
|
|
|
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
|
|
|
"tzcnt{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
|
|
|
|
|
XS;
|
|
|
|
|
def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
|
|
|
"tzcnt{q}\t{$src, $dst|$dst, $src}",
|
|
|
|
|
[(set GR64:$dst, (cttz (loadi64 addr:$src))),
|
|
|
|
|
(implicit EFLAGS)]>, XS;
|
|
|
|
|
}
|
|
|
|
|
|
2011-10-15 20:46:47 +00:00
|
|
|
multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
|
|
|
|
|
RegisterClass RC, X86MemOperand x86memop> {
|
|
|
|
|
def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
|
|
|
|
|
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>;
|
|
|
|
|
def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
|
|
|
|
|
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
let Predicates = [HasBMI], Defs = [EFLAGS] in {
|
|
|
|
|
defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>, T8, VEX_4V;
|
|
|
|
|
defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, T8, VEX_4V,
|
|
|
|
|
VEX_W;
|
|
|
|
|
defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>, T8, VEX_4V;
|
|
|
|
|
defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, T8, VEX_4V,
|
|
|
|
|
VEX_W;
|
|
|
|
|
defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>, T8, VEX_4V;
|
|
|
|
|
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, T8, VEX_4V,
|
|
|
|
|
VEX_W;
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-21 20:00:20 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-10-05 05:32:15 +00:00
|
|
|
// Subsystems.
|
2006-02-21 20:00:20 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2010-10-05 16:39:12 +00:00
|
|
|
include "X86InstrArithmetic.td"
|
2010-10-05 06:33:16 +00:00
|
|
|
include "X86InstrCMovSetCC.td"
|
2010-10-05 06:52:26 +00:00
|
|
|
include "X86InstrExtension.td"
|
2010-10-05 06:04:14 +00:00
|
|
|
include "X86InstrControl.td"
|
2010-10-05 07:00:12 +00:00
|
|
|
include "X86InstrShiftRotate.td"
|
2010-10-05 06:04:14 +00:00
|
|
|
|
2010-10-05 16:39:12 +00:00
|
|
|
// X87 Floating Point Stack.
|
|
|
|
|
include "X86InstrFPStack.td"
|
|
|
|
|
|
2010-02-09 23:52:19 +00:00
|
|
|
// SIMD support (SSE, MMX and AVX)
|
|
|
|
|
include "X86InstrFragmentsSIMD.td"
|
|
|
|
|
|
2010-07-23 00:54:35 +00:00
|
|
|
// FMA - Fused Multiply-Add support (requires FMA)
|
|
|
|
|
include "X86InstrFMA.td"
|
|
|
|
|
|
2010-10-05 05:32:15 +00:00
|
|
|
// SSE, MMX and 3DNow! vector support.
|
2008-04-25 18:19:54 +00:00
|
|
|
include "X86InstrSSE.td"
|
|
|
|
|
include "X86InstrMMX.td"
|
2010-10-02 23:06:23 +00:00
|
|
|
include "X86Instr3DNow.td"
|
|
|
|
|
|
2010-10-05 06:06:53 +00:00
|
|
|
include "X86InstrVMX.td"
|
|
|
|
|
|
2010-10-05 05:32:15 +00:00
|
|
|
// System instructions.
|
|
|
|
|
include "X86InstrSystem.td"
|
2010-10-05 06:04:14 +00:00
|
|
|
|
|
|
|
|
// Compiler Pseudo Instructions and Pat Patterns
|
|
|
|
|
include "X86InstrCompiler.td"
|
|
|
|
|
|
2010-10-30 17:36:36 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-11-01 23:07:52 +00:00
|
|
|
// Assembler Mnemonic Aliases
|
2010-10-30 17:36:36 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2010-11-01 21:06:34 +00:00
|
|
|
def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
|
|
|
|
|
|
2010-10-30 17:36:36 +00:00
|
|
|
def : MnemonicAlias<"cbw", "cbtw">;
|
|
|
|
|
def : MnemonicAlias<"cwd", "cwtd">;
|
|
|
|
|
def : MnemonicAlias<"cdq", "cltd">;
|
|
|
|
|
def : MnemonicAlias<"cwde", "cwtl">;
|
|
|
|
|
def : MnemonicAlias<"cdqe", "cltq">;
|
2010-10-30 18:07:17 +00:00
|
|
|
|
2010-11-12 18:54:56 +00:00
|
|
|
// lret maps to lretl, it is not ambiguous with lretq.
|
|
|
|
|
def : MnemonicAlias<"lret", "lretl">;
|
|
|
|
|
|
2011-02-17 23:36:39 +00:00
|
|
|
def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
|
|
|
|
|
|
2011-02-22 00:43:07 +00:00
|
|
|
def : MnemonicAlias<"loopz", "loope">;
|
|
|
|
|
def : MnemonicAlias<"loopnz", "loopne">;
|
|
|
|
|
|
2010-10-30 19:23:13 +00:00
|
|
|
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
|
2010-10-30 18:07:17 +00:00
|
|
|
def : MnemonicAlias<"popfd", "popfl">;
|
|
|
|
|
|
2010-10-31 18:43:46 +00:00
|
|
|
// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
|
|
|
|
|
// all modes. However: "push (addr)" and "push $42" should default to
|
|
|
|
|
// pushl/pushq depending on the current mode. Similar for "pop %bx"
|
2010-10-30 19:23:13 +00:00
|
|
|
def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"pushfd", "pushfl">;
|
|
|
|
|
|
2010-10-30 18:17:33 +00:00
|
|
|
def : MnemonicAlias<"repe", "rep">;
|
|
|
|
|
def : MnemonicAlias<"repz", "rep">;
|
|
|
|
|
def : MnemonicAlias<"repnz", "repne">;
|
|
|
|
|
|
2010-10-30 19:23:13 +00:00
|
|
|
def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
|
|
|
|
|
|
2010-10-30 18:14:54 +00:00
|
|
|
def : MnemonicAlias<"salb", "shlb">;
|
|
|
|
|
def : MnemonicAlias<"salw", "shlw">;
|
|
|
|
|
def : MnemonicAlias<"sall", "shll">;
|
|
|
|
|
def : MnemonicAlias<"salq", "shlq">;
|
|
|
|
|
|
2010-10-30 17:36:36 +00:00
|
|
|
def : MnemonicAlias<"smovb", "movsb">;
|
|
|
|
|
def : MnemonicAlias<"smovw", "movsw">;
|
|
|
|
|
def : MnemonicAlias<"smovl", "movsl">;
|
|
|
|
|
def : MnemonicAlias<"smovq", "movsq">;
|
|
|
|
|
|
|
|
|
|
def : MnemonicAlias<"ud2a", "ud2">;
|
|
|
|
|
def : MnemonicAlias<"verrw", "verr">;
|
|
|
|
|
|
2010-11-01 21:06:34 +00:00
|
|
|
// System instruction aliases.
|
|
|
|
|
def : MnemonicAlias<"iret", "iretl">;
|
|
|
|
|
def : MnemonicAlias<"sysret", "sysretl">;
|
|
|
|
|
|
|
|
|
|
def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
|
|
|
|
|
def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
|
|
|
|
|
|
2010-10-30 17:36:36 +00:00
|
|
|
|
2010-10-30 18:07:17 +00:00
|
|
|
// Floating point stack aliases.
|
|
|
|
|
def : MnemonicAlias<"fcmovz", "fcmove">;
|
|
|
|
|
def : MnemonicAlias<"fcmova", "fcmovnbe">;
|
|
|
|
|
def : MnemonicAlias<"fcmovnae", "fcmovb">;
|
|
|
|
|
def : MnemonicAlias<"fcmovna", "fcmovbe">;
|
|
|
|
|
def : MnemonicAlias<"fcmovae", "fcmovnb">;
|
2010-11-06 21:37:06 +00:00
|
|
|
def : MnemonicAlias<"fcomip", "fcompi">;
|
2010-10-30 18:07:17 +00:00
|
|
|
def : MnemonicAlias<"fildq", "fildll">;
|
|
|
|
|
def : MnemonicAlias<"fldcww", "fldcw">;
|
|
|
|
|
def : MnemonicAlias<"fnstcww", "fnstcw">;
|
|
|
|
|
def : MnemonicAlias<"fnstsww", "fnstsw">;
|
2010-11-06 21:37:06 +00:00
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|
def : MnemonicAlias<"fucomip", "fucompi">;
|
2010-10-30 18:07:17 +00:00
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|
def : MnemonicAlias<"fwait", "wait">;
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|
2010-10-30 17:56:50 +00:00
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|
|
class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
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|
: MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
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|
!strconcat(Prefix, NewCond, Suffix)>;
|
2010-10-30 17:51:45 +00:00
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|
|
/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
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|
|
/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
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|
|
/// example "setz" -> "sete".
|
2010-10-30 17:56:50 +00:00
|
|
|
multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
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|
def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
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def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
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def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
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def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
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def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
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def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
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def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
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def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
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def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
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def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
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def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
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def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
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def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
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|
def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
|
2010-10-30 17:51:45 +00:00
|
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|
}
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|
|
// Aliases for set<CC>
|
2010-10-30 17:56:50 +00:00
|
|
|
defm : IntegerCondCodeMnemonicAlias<"set", "">;
|
2010-10-30 17:51:45 +00:00
|
|
|
// Aliases for j<CC>
|
2010-10-30 17:56:50 +00:00
|
|
|
defm : IntegerCondCodeMnemonicAlias<"j", "">;
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|
|
// Aliases for cmov<CC>{w,l,q}
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|
|
defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
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|
defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
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|
|
defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
|
2010-10-30 17:36:36 +00:00
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|
|
|
2010-11-01 23:07:52 +00:00
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|
|
//===----------------------------------------------------------------------===//
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|
|
// Assembler Instruction Aliases
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|
//===----------------------------------------------------------------------===//
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|
2010-11-06 19:25:43 +00:00
|
|
|
// aad/aam default to base 10 if no operand is specified.
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|
|
def : InstAlias<"aad", (AAD8i8 10)>;
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|
def : InstAlias<"aam", (AAM8i8 10)>;
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|
2011-02-19 21:06:36 +00:00
|
|
|
// Disambiguate the mem/imm form of bt-without-a-suffix as btl.
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|
def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
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|
2010-11-06 07:31:43 +00:00
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|
|
// clr aliases.
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|
def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
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|
def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
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|
def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
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|
def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
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|
2010-11-06 22:41:18 +00:00
|
|
|
// div and idiv aliases for explicit A register.
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|
def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
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|
def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
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|
def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
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|
def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
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|
def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
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|
def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
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|
def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
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|
def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
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|
def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
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|
def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
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|
def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
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|
|
def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
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|
def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
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|
def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
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|
|
def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
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|
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|
def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
|
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|
|
|
|
2010-11-06 20:47:38 +00:00
|
|
|
// Various unary fpstack operations default to operating on on ST1.
|
|
|
|
|
// For example, "fxch" -> "fxch %st(1)"
|
2011-04-14 01:11:51 +00:00
|
|
|
def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
|
2010-11-06 20:47:38 +00:00
|
|
|
def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
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|
|
|
|
def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
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|
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|
|
def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
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|
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|
|
def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
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|
|
|
|
def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
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|
|
|
|
def : InstAlias<"fxch", (XCH_F ST1)>;
|
|
|
|
|
def : InstAlias<"fcomi", (COM_FIr ST1)>;
|
2010-11-06 21:37:06 +00:00
|
|
|
def : InstAlias<"fcompi", (COM_FIPr ST1)>;
|
2010-11-06 20:47:38 +00:00
|
|
|
def : InstAlias<"fucom", (UCOM_Fr ST1)>;
|
|
|
|
|
def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
|
|
|
|
|
def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
|
2010-11-06 21:37:06 +00:00
|
|
|
def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
|
2010-11-06 20:47:38 +00:00
|
|
|
|
|
|
|
|
// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
|
|
|
|
|
// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
|
|
|
|
|
// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
|
|
|
|
|
// gas.
|
2011-04-14 01:11:51 +00:00
|
|
|
multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
|
|
|
|
|
def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
|
|
|
|
|
(Inst RST:$op), EmitAlias>;
|
|
|
|
|
def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
|
|
|
|
|
(Inst ST0), EmitAlias>;
|
2010-11-06 20:47:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
defm : FpUnaryAlias<"fadd", ADD_FST0r>;
|
2011-04-14 01:11:51 +00:00
|
|
|
defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
|
2010-11-06 20:47:38 +00:00
|
|
|
defm : FpUnaryAlias<"fsub", SUB_FST0r>;
|
|
|
|
|
defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
|
|
|
|
|
defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
|
|
|
|
|
defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
|
|
|
|
|
defm : FpUnaryAlias<"fmul", MUL_FST0r>;
|
|
|
|
|
defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
|
|
|
|
|
defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
|
|
|
|
|
defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
|
|
|
|
|
defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
|
|
|
|
|
defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
|
2011-04-14 01:11:51 +00:00
|
|
|
defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
|
|
|
|
|
defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
|
2010-11-06 21:37:06 +00:00
|
|
|
defm : FpUnaryAlias<"fcompi", COM_FIPr>;
|
|
|
|
|
defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
|
2010-11-06 20:55:09 +00:00
|
|
|
|
2010-11-06 20:47:38 +00:00
|
|
|
|
|
|
|
|
// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
|
2010-12-30 22:10:49 +00:00
|
|
|
// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
|
|
|
|
|
// solely because gas supports it.
|
2011-04-14 01:11:51 +00:00
|
|
|
def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
|
2010-11-06 20:47:38 +00:00
|
|
|
def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
|
2011-05-22 22:31:57 +00:00
|
|
|
def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
|
2010-11-06 20:47:38 +00:00
|
|
|
def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
|
2010-12-30 22:10:49 +00:00
|
|
|
def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
|
2010-11-06 20:47:38 +00:00
|
|
|
def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
|
2010-11-06 19:57:21 +00:00
|
|
|
|
2010-12-30 22:10:49 +00:00
|
|
|
// We accept "fnstsw %eax" even though it only writes %ax.
|
2010-11-06 18:58:32 +00:00
|
|
|
def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
|
|
|
|
|
def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
|
|
|
|
|
def : InstAlias<"fnstsw" , (FNSTSW8r)>;
|
|
|
|
|
|
2010-11-06 07:48:45 +00:00
|
|
|
// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
|
|
|
|
|
// this is compatible with what GAS does.
|
|
|
|
|
def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
|
|
|
|
|
def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
|
|
|
|
|
|
2010-11-06 18:44:26 +00:00
|
|
|
// "imul <imm>, B" is an alias for "imul <imm>, B, B".
|
|
|
|
|
def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
|
|
|
|
|
def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
|
|
|
|
|
def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
|
|
|
|
|
def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
|
|
|
|
|
def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
|
|
|
|
|
def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
|
|
|
|
|
|
2010-11-06 18:52:40 +00:00
|
|
|
// inb %dx -> inb %al, %dx
|
|
|
|
|
def : InstAlias<"inb %dx", (IN8rr)>;
|
|
|
|
|
def : InstAlias<"inw %dx", (IN16rr)>;
|
|
|
|
|
def : InstAlias<"inl %dx", (IN32rr)>;
|
|
|
|
|
def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
|
2010-11-06 18:58:32 +00:00
|
|
|
def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
|
2010-11-06 18:52:40 +00:00
|
|
|
def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
|
|
|
|
|
|
2010-11-06 18:44:26 +00:00
|
|
|
|
2010-11-06 07:48:45 +00:00
|
|
|
// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
|
|
|
|
|
def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
|
|
|
|
|
def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
|
|
|
|
|
|
2010-11-06 22:35:34 +00:00
|
|
|
// Force mov without a suffix with a segment and mem to prefer the 'l' form of
|
|
|
|
|
// the move. All segment/mem forms are equivalent, this has the shortest
|
|
|
|
|
// encoding.
|
|
|
|
|
def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
|
|
|
|
|
def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
|
2010-11-06 07:48:45 +00:00
|
|
|
|
2010-11-06 18:44:26 +00:00
|
|
|
// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
|
|
|
|
|
def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
|
|
|
|
|
|
2010-11-21 08:18:57 +00:00
|
|
|
// Match 'movq GR64, MMX' as an alias for movd.
|
2011-04-13 23:36:21 +00:00
|
|
|
def : InstAlias<"movq $src, $dst",
|
2011-04-14 01:11:51 +00:00
|
|
|
(MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
|
2011-04-13 23:36:21 +00:00
|
|
|
def : InstAlias<"movq $src, $dst",
|
2011-04-14 01:11:51 +00:00
|
|
|
(MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
|
2010-11-21 08:18:57 +00:00
|
|
|
|
2010-11-06 07:48:45 +00:00
|
|
|
// movsd with no operands (as opposed to the SSE scalar move of a double) is an
|
|
|
|
|
// alias for movsl. (as in rep; movsd)
|
|
|
|
|
def : InstAlias<"movsd", (MOVSD)>;
|
|
|
|
|
|
2010-11-01 23:07:52 +00:00
|
|
|
// movsx aliases
|
2011-05-20 19:04:40 +00:00
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
|
|
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
|
2011-04-14 01:46:37 +00:00
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
|
|
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
|
|
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
|
|
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
|
|
|
|
|
def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
|
2010-11-01 23:07:52 +00:00
|
|
|
|
|
|
|
|
// movzx aliases
|
2011-05-20 19:04:40 +00:00
|
|
|
def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
|
|
|
|
|
def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
|
2011-04-14 01:46:37 +00:00
|
|
|
def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
|
|
|
|
|
def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
|
|
|
|
|
def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
|
|
|
|
|
def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
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2010-11-01 23:07:52 +00:00
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// Note: No GR32->GR64 movzx form.
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2010-11-06 18:52:40 +00:00
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// outb %dx -> outb %al, %dx
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def : InstAlias<"outb %dx", (OUT8rr)>;
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def : InstAlias<"outw %dx", (OUT16rr)>;
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def : InstAlias<"outl %dx", (OUT32rr)>;
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def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
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def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
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def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
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2010-11-06 18:44:26 +00:00
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// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
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// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
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// errors, since its encoding is the most compact.
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def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
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2010-11-06 22:25:39 +00:00
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// shld/shrd op,op -> shld op, op, 1
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def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
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def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
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def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
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def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
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def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
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def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
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def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
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def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
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def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
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def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
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def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
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def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
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/* FIXME: This is disabled because the asm matcher is currently incapable of
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* matching a fixed immediate like $1.
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2010-11-06 22:05:43 +00:00
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// "shl X, $1" is an alias for "shl X".
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multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
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2010-11-06 21:23:40 +00:00
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def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
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def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
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(!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
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}
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2010-11-06 22:05:43 +00:00
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defm : ShiftRotateByOneAlias<"rcl", "RCL">;
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defm : ShiftRotateByOneAlias<"rcr", "RCR">;
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defm : ShiftRotateByOneAlias<"rol", "ROL">;
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defm : ShiftRotateByOneAlias<"ror", "ROR">;
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2010-11-06 22:25:39 +00:00
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FIXME */
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2010-11-06 21:23:40 +00:00
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2010-11-06 08:20:59 +00:00
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// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
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def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
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def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
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def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
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def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
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// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
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def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
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def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
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def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
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def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
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2011-10-06 06:44:41 +00:00
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// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
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2011-10-07 05:35:38 +00:00
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def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
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def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
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def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
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def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;
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