2005-10-18 00:28:58 +00:00
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//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
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2005-08-16 17:14:42 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-08-16 17:14:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2005-10-16 05:39:50 +00:00
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// This file implements the PPCISelLowering class.
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2005-08-16 17:14:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:59:06 +00:00
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#include "PPCISelLowering.h"
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2006-11-16 22:43:37 +00:00
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#include "PPCMachineFunctionInfo.h"
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2006-11-17 22:10:59 +00:00
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#include "PPCPredicates.h"
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2005-10-14 23:59:06 +00:00
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#include "PPCTargetMachine.h"
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2006-04-17 05:28:54 +00:00
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#include "PPCPerfectShuffle.h"
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2007-09-07 04:06:50 +00:00
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#include "llvm/ADT/STLExtras.h"
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2006-02-01 07:19:44 +00:00
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#include "llvm/ADT/VectorExtras.h"
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2007-03-06 00:59:59 +00:00
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#include "llvm/CodeGen/CallingConvLower.h"
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2005-08-16 17:14:42 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2005-08-26 21:23:58 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-02-06 22:27:42 +00:00
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#include "llvm/CodeGen/PseudoSourceValue.h"
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2005-08-16 17:14:42 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2008-04-30 09:16:33 +00:00
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#include "llvm/CallingConv.h"
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2005-08-26 17:36:52 +00:00
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#include "llvm/Constants.h"
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2005-08-16 17:14:42 +00:00
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#include "llvm/Function.h"
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2006-03-26 10:06:40 +00:00
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#include "llvm/Intrinsics.h"
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2008-04-30 09:16:33 +00:00
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#include "llvm/ParameterAttributes.h"
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2006-02-01 07:19:44 +00:00
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#include "llvm/Support/MathExtras.h"
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2006-02-18 00:08:58 +00:00
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#include "llvm/Target/TargetOptions.h"
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2006-11-10 02:08:47 +00:00
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#include "llvm/Support/CommandLine.h"
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2005-08-16 17:14:42 +00:00
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using namespace llvm;
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2007-06-19 05:46:06 +00:00
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static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
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cl::desc("enable preincrement load/store generation on PPC (experimental)"),
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cl::Hidden);
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2006-11-10 02:08:47 +00:00
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2006-11-02 01:44:04 +00:00
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PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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2008-07-12 02:23:19 +00:00
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: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
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2005-08-16 17:14:42 +00:00
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2005-10-21 00:02:42 +00:00
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setPow2DivIsCheap();
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2005-08-16 17:14:42 +00:00
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2005-09-27 22:18:25 +00:00
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// Use _setjmp/_longjmp instead of setjmp/longjmp.
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2006-12-10 23:12:42 +00:00
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setUseUnderscoreSetJmp(true);
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setUseUnderscoreLongJmp(true);
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2005-09-27 22:18:25 +00:00
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2005-08-16 17:14:42 +00:00
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// Set up the register classes.
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2005-10-18 00:28:58 +00:00
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addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
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addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
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2005-08-16 17:14:42 +00:00
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2006-10-04 00:56:09 +00:00
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
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2008-01-23 20:39:46 +00:00
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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2006-10-04 00:56:09 +00:00
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setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
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2008-01-23 20:39:46 +00:00
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2008-01-17 19:59:44 +00:00
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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2006-11-10 23:58:45 +00:00
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// PowerPC has pre-inc load and store's.
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setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
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2006-11-09 19:11:50 +00:00
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setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
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2006-11-10 23:58:45 +00:00
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setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
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2006-11-09 19:11:50 +00:00
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setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
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2007-10-06 01:24:11 +00:00
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// Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
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setConvertAction(MVT::ppcf128, MVT::f64, Expand);
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setConvertAction(MVT::ppcf128, MVT::f32, Expand);
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2007-10-10 01:01:31 +00:00
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// This is used in the ppcf128->int sequence. Note it has different semantics
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// from FP_ROUND: that rounds to nearest, this rounds to zero.
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setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
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2007-10-06 01:24:11 +00:00
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2005-08-16 17:14:42 +00:00
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// PowerPC has no intrinsics for these particular operations
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2008-02-16 14:46:26 +00:00
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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2005-08-16 17:14:42 +00:00
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// PowerPC has no SREM/UREM instructions
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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2006-06-27 18:18:41 +00:00
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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2007-10-08 17:28:24 +00:00
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// Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
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2005-08-16 17:14:42 +00:00
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2007-10-11 23:21:31 +00:00
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// We don't support sin/cos/sqrt/fmod/pow
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2005-08-16 17:14:42 +00:00
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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2005-09-28 22:29:58 +00:00
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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2007-10-11 23:21:31 +00:00
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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2005-08-16 17:14:42 +00:00
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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2005-09-28 22:29:58 +00:00
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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2007-10-11 23:21:31 +00:00
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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2008-01-18 19:55:37 +00:00
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2008-01-31 00:41:03 +00:00
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setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
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2005-08-16 17:14:42 +00:00
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// If we're enabling GP optimizations, use hardware square root
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2005-09-02 18:33:05 +00:00
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if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
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2005-08-16 17:14:42 +00:00
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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}
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2006-03-05 05:08:37 +00:00
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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2006-01-14 03:14:10 +00:00
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// PowerPC does not have BSWAP, CTPOP or CTTZ
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setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
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2005-08-16 17:14:42 +00:00
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setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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2006-06-27 20:14:52 +00:00
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setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
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setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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2005-08-16 17:14:42 +00:00
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2006-01-11 21:21:00 +00:00
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// PowerPC does not have ROTR
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setOperationAction(ISD::ROTR, MVT::i32 , Expand);
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2005-08-16 17:14:42 +00:00
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// PowerPC does not have Select
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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2006-06-27 20:14:52 +00:00
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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2005-08-16 17:14:42 +00:00
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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2005-08-26 00:52:45 +00:00
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2005-08-26 17:36:52 +00:00
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// PowerPC wants to turn select_cc of FP into fsel when possible.
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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Codegen
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25848 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 08:17:29 +00:00
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2006-02-01 07:19:44 +00:00
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// PowerPC wants to optimize integer setcc a bit
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Codegen
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25848 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 08:17:29 +00:00
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setOperationAction(ISD::SETCC, MVT::i32, Custom);
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2005-08-31 19:09:57 +00:00
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2006-03-17 01:40:33 +00:00
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// PowerPC does not have BRCOND which requires SetCC
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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2006-10-30 08:02:39 +00:00
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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2005-08-16 17:14:42 +00:00
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2005-08-31 21:09:52 +00:00
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// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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2005-09-06 22:03:27 +00:00
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2005-08-17 00:40:22 +00:00
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// PowerPC does not have [U|S]INT_TO_FP
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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2005-12-23 05:13:35 +00:00
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
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2006-06-27 18:40:08 +00:00
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setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
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2005-12-23 05:13:35 +00:00
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2006-04-28 21:56:10 +00:00
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// We cannot sextinreg(i1). Expand to shifts.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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2007-02-22 14:56:36 +00:00
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2006-01-05 01:25:28 +00:00
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// Support label based line numbers.
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2008-06-30 20:59:49 +00:00
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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2006-01-05 01:47:43 +00:00
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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2007-12-21 12:19:44 +00:00
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setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
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setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
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setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
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setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
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2005-09-10 00:21:06 +00:00
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2005-12-10 02:36:00 +00:00
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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2005-11-17 18:26:56 +00:00
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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2007-07-11 17:19:51 +00:00
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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2005-12-10 02:36:00 +00:00
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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2006-04-22 18:53:45 +00:00
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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2006-06-16 21:01:35 +00:00
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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2007-07-11 17:19:51 +00:00
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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2006-06-16 21:01:35 +00:00
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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2006-01-27 21:09:22 +00:00
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// RET must be custom lowered, to meet ABI requirements
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setOperationAction(ISD::RET , MVT::Other, Custom);
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2007-07-27 12:58:54 +00:00
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2006-01-25 18:21:52 +00:00
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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2007-04-03 13:59:52 +00:00
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// VAARG is custom lowered with ELF 32 ABI
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if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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else
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setOperationAction(ISD::VAARG, MVT::Other, Expand);
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2006-01-15 09:02:48 +00:00
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// Use the default implementation.
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2006-01-25 18:21:52 +00:00
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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2006-01-15 09:02:48 +00:00
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setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
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2006-12-04 22:04:42 +00:00
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
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2006-11-16 22:43:37 +00:00
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
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2006-10-18 01:18:48 +00:00
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2008-06-25 08:15:39 +00:00
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setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i32 , Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32 , Custom);
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2008-04-19 01:30:48 +00:00
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setOperationAction(ISD::ATOMIC_SWAP , MVT::i32 , Custom);
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2008-04-19 02:30:38 +00:00
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if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
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2008-06-25 08:15:39 +00:00
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setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i64 , Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64 , Custom);
|
2008-04-19 02:30:38 +00:00
|
|
|
setOperationAction(ISD::ATOMIC_SWAP , MVT::i64 , Custom);
|
|
|
|
}
|
2008-04-19 01:30:48 +00:00
|
|
|
|
2006-03-26 10:06:40 +00:00
|
|
|
// We want to custom lower some of our intrinsics.
|
2006-03-28 00:40:33 +00:00
|
|
|
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
|
2006-03-26 10:06:40 +00:00
|
|
|
|
2006-06-16 17:34:12 +00:00
|
|
|
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
|
2005-10-18 00:28:58 +00:00
|
|
|
// They also have instructions for converting between i64 and fp.
|
2005-09-06 22:03:27 +00:00
|
|
|
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
|
2006-12-15 14:32:57 +00:00
|
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
|
2005-09-06 22:03:27 +00:00
|
|
|
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
|
2006-12-07 01:24:16 +00:00
|
|
|
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
|
2006-12-15 14:32:57 +00:00
|
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
|
|
|
|
|
2006-03-24 07:53:47 +00:00
|
|
|
// FIXME: disable this lowered code. This generates 64-bit register values,
|
|
|
|
// and we don't model the fact that the top part is clobbered by calls. We
|
|
|
|
// need to flag these together so that the value isn't live across a call.
|
|
|
|
//setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
|
|
|
|
|
2005-10-25 23:48:36 +00:00
|
|
|
// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
|
|
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
|
|
|
|
} else {
|
2005-11-17 07:30:41 +00:00
|
|
|
// PowerPC does not have FP_TO_UINT on 32-bit implementations.
|
2005-10-25 23:48:36 +00:00
|
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
|
2005-10-18 00:56:42 +00:00
|
|
|
}
|
|
|
|
|
2006-06-16 17:34:12 +00:00
|
|
|
if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
|
2007-10-19 04:08:28 +00:00
|
|
|
// 64-bit PowerPC implementations can support i64 types directly
|
2005-10-18 00:56:42 +00:00
|
|
|
addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
|
2005-10-18 00:28:58 +00:00
|
|
|
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
|
|
|
|
setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
|
2008-03-07 20:36:53 +00:00
|
|
|
// 64-bit PowerPC wants to expand i128 shifts itself.
|
|
|
|
setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
|
|
|
|
setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
|
2005-10-18 00:28:58 +00:00
|
|
|
} else {
|
2007-10-19 04:08:28 +00:00
|
|
|
// 32-bit PowerPC wants to expand i64 shifts itself.
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
|
|
|
|
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
|
2005-09-06 22:03:27 +00:00
|
|
|
}
|
2006-03-01 01:11:20 +00:00
|
|
|
|
2005-11-29 08:17:20 +00:00
|
|
|
if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
|
2006-03-31 19:52:36 +00:00
|
|
|
// First set operation action for all vector types to expand. Then we
|
|
|
|
// will selectively turn on ones that can be effectively codegen'd.
|
2008-06-06 12:08:01 +00:00
|
|
|
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
|
|
|
|
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
|
|
|
|
MVT VT = (MVT::SimpleValueType)i;
|
|
|
|
|
2006-04-16 01:37:57 +00:00
|
|
|
// add/sub are legal for all supported vector VT's.
|
2008-06-06 12:08:01 +00:00
|
|
|
setOperationAction(ISD::ADD , VT, Legal);
|
|
|
|
setOperationAction(ISD::SUB , VT, Legal);
|
2006-03-31 19:52:36 +00:00
|
|
|
|
2006-04-04 17:25:31 +00:00
|
|
|
// We promote all shuffles to v16i8.
|
2008-06-06 12:08:01 +00:00
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
|
|
|
|
AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
|
2006-04-16 01:37:57 +00:00
|
|
|
|
|
|
|
// We promote all non-typed operations to v4i32.
|
2008-06-06 12:08:01 +00:00
|
|
|
setOperationAction(ISD::AND , VT, Promote);
|
|
|
|
AddPromotedToType (ISD::AND , VT, MVT::v4i32);
|
|
|
|
setOperationAction(ISD::OR , VT, Promote);
|
|
|
|
AddPromotedToType (ISD::OR , VT, MVT::v4i32);
|
|
|
|
setOperationAction(ISD::XOR , VT, Promote);
|
|
|
|
AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
|
|
|
|
setOperationAction(ISD::LOAD , VT, Promote);
|
|
|
|
AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
|
|
|
|
setOperationAction(ISD::SELECT, VT, Promote);
|
|
|
|
AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
|
|
|
|
setOperationAction(ISD::STORE, VT, Promote);
|
|
|
|
AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
|
2006-03-31 19:52:36 +00:00
|
|
|
|
2006-04-16 01:37:57 +00:00
|
|
|
// No other operations are legal.
|
2008-06-06 12:08:01 +00:00
|
|
|
setOperationAction(ISD::MUL , VT, Expand);
|
|
|
|
setOperationAction(ISD::SDIV, VT, Expand);
|
|
|
|
setOperationAction(ISD::SREM, VT, Expand);
|
|
|
|
setOperationAction(ISD::UDIV, VT, Expand);
|
|
|
|
setOperationAction(ISD::UREM, VT, Expand);
|
|
|
|
setOperationAction(ISD::FDIV, VT, Expand);
|
|
|
|
setOperationAction(ISD::FNEG, VT, Expand);
|
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
|
|
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
|
|
|
|
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
|
|
|
|
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
|
|
|
|
setOperationAction(ISD::UDIVREM, VT, Expand);
|
|
|
|
setOperationAction(ISD::SDIVREM, VT, Expand);
|
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
|
|
|
|
setOperationAction(ISD::FPOW, VT, Expand);
|
|
|
|
setOperationAction(ISD::CTPOP, VT, Expand);
|
|
|
|
setOperationAction(ISD::CTLZ, VT, Expand);
|
|
|
|
setOperationAction(ISD::CTTZ, VT, Expand);
|
2006-03-31 19:52:36 +00:00
|
|
|
}
|
|
|
|
|
2006-04-04 17:25:31 +00:00
|
|
|
// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
|
|
|
|
// with merges, splats, etc.
|
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
|
|
|
|
|
2006-04-16 01:37:57 +00:00
|
|
|
setOperationAction(ISD::AND , MVT::v4i32, Legal);
|
|
|
|
setOperationAction(ISD::OR , MVT::v4i32, Legal);
|
|
|
|
setOperationAction(ISD::XOR , MVT::v4i32, Legal);
|
|
|
|
setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
|
|
|
|
setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
|
|
|
|
setOperationAction(ISD::STORE , MVT::v4i32, Legal);
|
|
|
|
|
2005-11-29 08:17:20 +00:00
|
|
|
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
|
2005-12-19 23:25:09 +00:00
|
|
|
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
|
2006-03-25 07:39:07 +00:00
|
|
|
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
|
|
|
|
addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
|
2006-01-29 06:32:58 +00:00
|
|
|
|
2006-03-31 19:52:36 +00:00
|
|
|
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
|
2006-04-18 03:24:30 +00:00
|
|
|
setOperationAction(ISD::MUL, MVT::v4i32, Custom);
|
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27789 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 03:43:48 +00:00
|
|
|
setOperationAction(ISD::MUL, MVT::v8i16, Custom);
|
2006-04-18 03:57:35 +00:00
|
|
|
setOperationAction(ISD::MUL, MVT::v16i8, Custom);
|
2006-03-20 01:53:53 +00:00
|
|
|
|
2006-03-19 06:55:52 +00:00
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
|
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
|
2006-03-24 07:48:08 +00:00
|
|
|
|
2006-04-02 00:43:36 +00:00
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
|
2006-03-24 07:48:08 +00:00
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
|
2005-11-29 08:17:20 +00:00
|
|
|
}
|
|
|
|
|
2006-06-27 17:34:57 +00:00
|
|
|
setShiftAmountType(MVT::i32);
|
2005-08-16 17:14:42 +00:00
|
|
|
setSetCCResultContents(ZeroOrOneSetCCResult);
|
2006-10-18 01:20:43 +00:00
|
|
|
|
2007-02-22 14:56:36 +00:00
|
|
|
if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
|
2006-10-18 01:20:43 +00:00
|
|
|
setStackPointerRegisterToSaveRestore(PPC::X1);
|
2007-02-22 14:56:36 +00:00
|
|
|
setExceptionPointerRegister(PPC::X3);
|
|
|
|
setExceptionSelectorRegister(PPC::X4);
|
|
|
|
} else {
|
2006-10-18 01:20:43 +00:00
|
|
|
setStackPointerRegisterToSaveRestore(PPC::R1);
|
2007-02-22 14:56:36 +00:00
|
|
|
setExceptionPointerRegister(PPC::R3);
|
|
|
|
setExceptionSelectorRegister(PPC::R4);
|
|
|
|
}
|
2005-08-16 17:14:42 +00:00
|
|
|
|
2006-03-01 04:57:39 +00:00
|
|
|
// We have target-specific dag combine patterns for the following nodes:
|
|
|
|
setTargetDAGCombine(ISD::SINT_TO_FP);
|
2006-03-01 05:50:56 +00:00
|
|
|
setTargetDAGCombine(ISD::STORE);
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
setTargetDAGCombine(ISD::BR_CC);
|
2006-07-10 20:56:58 +00:00
|
|
|
setTargetDAGCombine(ISD::BSWAP);
|
2006-03-01 04:57:39 +00:00
|
|
|
|
2007-10-19 00:59:18 +00:00
|
|
|
// Darwin long double math library functions have $LDBL128 appended.
|
|
|
|
if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
|
2008-01-10 10:28:30 +00:00
|
|
|
setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
|
2007-10-19 00:59:18 +00:00
|
|
|
setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
|
|
|
|
setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
|
2008-01-10 10:28:30 +00:00
|
|
|
setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
|
|
|
|
setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
|
2007-10-19 00:59:18 +00:00
|
|
|
}
|
|
|
|
|
2005-08-16 17:14:42 +00:00
|
|
|
computeRegisterProperties();
|
|
|
|
}
|
|
|
|
|
2008-02-28 22:31:51 +00:00
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
|
|
/// function arguments in the caller parameter area.
|
|
|
|
unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
|
|
|
|
TargetMachine &TM = getTargetMachine();
|
|
|
|
// Darwin passes everything on 4 byte boundary.
|
|
|
|
if (TM.getSubtarget<PPCSubtarget>().isDarwin())
|
|
|
|
return 4;
|
|
|
|
// FIXME Elf TBD
|
|
|
|
return 4;
|
|
|
|
}
|
|
|
|
|
2006-01-09 23:52:17 +00:00
|
|
|
const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
|
|
switch (Opcode) {
|
|
|
|
default: return 0;
|
2008-07-12 02:23:19 +00:00
|
|
|
case PPCISD::FSEL: return "PPCISD::FSEL";
|
|
|
|
case PPCISD::FCFID: return "PPCISD::FCFID";
|
|
|
|
case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
|
|
|
|
case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
|
|
|
|
case PPCISD::STFIWX: return "PPCISD::STFIWX";
|
|
|
|
case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
|
|
|
|
case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
|
|
|
|
case PPCISD::VPERM: return "PPCISD::VPERM";
|
|
|
|
case PPCISD::Hi: return "PPCISD::Hi";
|
|
|
|
case PPCISD::Lo: return "PPCISD::Lo";
|
|
|
|
case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
|
|
|
|
case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
|
|
|
|
case PPCISD::SRL: return "PPCISD::SRL";
|
|
|
|
case PPCISD::SRA: return "PPCISD::SRA";
|
|
|
|
case PPCISD::SHL: return "PPCISD::SHL";
|
|
|
|
case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
|
|
|
|
case PPCISD::STD_32: return "PPCISD::STD_32";
|
|
|
|
case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
|
|
|
|
case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
|
|
|
|
case PPCISD::MTCTR: return "PPCISD::MTCTR";
|
|
|
|
case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
|
|
|
|
case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
|
|
|
|
case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
|
|
|
|
case PPCISD::MFCR: return "PPCISD::MFCR";
|
|
|
|
case PPCISD::VCMP: return "PPCISD::VCMP";
|
|
|
|
case PPCISD::VCMPo: return "PPCISD::VCMPo";
|
|
|
|
case PPCISD::LBRX: return "PPCISD::LBRX";
|
|
|
|
case PPCISD::STBRX: return "PPCISD::STBRX";
|
|
|
|
case PPCISD::ATOMIC_LOAD_ADD: return "PPCISD::ATOMIC_LOAD_ADD";
|
|
|
|
case PPCISD::ATOMIC_CMP_SWAP: return "PPCISD::ATOMIC_CMP_SWAP";
|
|
|
|
case PPCISD::ATOMIC_SWAP: return "PPCISD::ATOMIC_SWAP";
|
|
|
|
case PPCISD::LARX: return "PPCISD::LARX";
|
|
|
|
case PPCISD::STCX: return "PPCISD::STCX";
|
|
|
|
case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
|
|
|
|
case PPCISD::MFFS: return "PPCISD::MFFS";
|
|
|
|
case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
|
|
|
|
case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
|
|
|
|
case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
|
|
|
|
case PPCISD::MTFSF: return "PPCISD::MTFSF";
|
|
|
|
case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
|
|
|
|
case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
|
2006-01-09 23:52:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-10 15:42:14 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
|
2008-03-10 15:42:14 +00:00
|
|
|
return MVT::i32;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Node matching predicates, for use by the tblgen matching code.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2005-08-26 17:36:52 +00:00
|
|
|
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
|
|
|
|
static bool isFloatingPointZero(SDOperand Op) {
|
|
|
|
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
|
2007-08-31 04:03:46 +00:00
|
|
|
return CFP->getValueAPF().isZero();
|
2006-10-09 20:57:25 +00:00
|
|
|
else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
|
2005-08-26 17:36:52 +00:00
|
|
|
// Maybe this has already been legalized into the constant pool?
|
|
|
|
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
|
2006-09-12 21:04:05 +00:00
|
|
|
if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
|
2007-08-31 04:03:46 +00:00
|
|
|
return CFP->getValueAPF().isZero();
|
2005-08-26 17:36:52 +00:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-04-06 17:23:16 +00:00
|
|
|
/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
|
|
|
|
/// true if Op is undef or if it matches the specified value.
|
|
|
|
static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
|
|
|
|
return Op.getOpcode() == ISD::UNDEF ||
|
|
|
|
cast<ConstantSDNode>(Op)->getValue() == Val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
|
|
|
|
/// VPKUHUM instruction.
|
2006-04-06 22:28:36 +00:00
|
|
|
bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
|
|
|
|
if (!isUnary) {
|
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i), i*2+1))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
for (unsigned i = 0; i != 8; ++i)
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
|
|
|
|
!isConstantOrUndef(N->getOperand(i+8), i*2+1))
|
|
|
|
return false;
|
|
|
|
}
|
2006-04-06 18:26:28 +00:00
|
|
|
return true;
|
2006-04-06 17:23:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
|
|
|
|
/// VPKUWUM instruction.
|
2006-04-06 22:28:36 +00:00
|
|
|
bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
|
|
|
|
if (!isUnary) {
|
|
|
|
for (unsigned i = 0; i != 16; i += 2)
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
|
|
|
|
!isConstantOrUndef(N->getOperand(i+1), i*2+3))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
for (unsigned i = 0; i != 8; i += 2)
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
|
|
|
|
!isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
|
|
|
|
!isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
|
|
|
|
!isConstantOrUndef(N->getOperand(i+9), i*2+3))
|
|
|
|
return false;
|
|
|
|
}
|
2006-04-06 18:26:28 +00:00
|
|
|
return true;
|
2006-04-06 17:23:16 +00:00
|
|
|
}
|
|
|
|
|
2006-04-06 22:02:42 +00:00
|
|
|
/// isVMerge - Common function, used to match vmrg* shuffles.
|
|
|
|
///
|
|
|
|
static bool isVMerge(SDNode *N, unsigned UnitSize,
|
|
|
|
unsigned LHSStart, unsigned RHSStart) {
|
2006-04-06 21:11:54 +00:00
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
|
|
|
|
N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
|
|
|
|
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
|
|
|
|
"Unsupported merge size!");
|
|
|
|
|
|
|
|
for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
|
|
|
|
for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
|
2006-04-06 22:02:42 +00:00
|
|
|
LHSStart+j+i*UnitSize) ||
|
2006-04-06 21:11:54 +00:00
|
|
|
!isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
|
2006-04-06 22:02:42 +00:00
|
|
|
RHSStart+j+i*UnitSize))
|
2006-04-06 21:11:54 +00:00
|
|
|
return false;
|
|
|
|
}
|
2006-04-06 22:02:42 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
|
|
|
|
/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
|
|
|
|
bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
|
|
|
|
if (!isUnary)
|
|
|
|
return isVMerge(N, UnitSize, 8, 24);
|
|
|
|
return isVMerge(N, UnitSize, 8, 8);
|
2006-04-06 21:11:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
|
|
|
|
/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
|
2006-04-06 22:02:42 +00:00
|
|
|
bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
|
|
|
|
if (!isUnary)
|
|
|
|
return isVMerge(N, UnitSize, 0, 16);
|
|
|
|
return isVMerge(N, UnitSize, 0, 0);
|
2006-04-06 21:11:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-04-06 18:26:28 +00:00
|
|
|
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
|
|
|
|
/// amount, otherwise return -1.
|
2006-04-06 22:28:36 +00:00
|
|
|
int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
|
2006-04-06 21:11:54 +00:00
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
|
|
|
|
N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
|
2006-04-06 18:26:28 +00:00
|
|
|
// Find the first non-undef value in the shuffle mask.
|
|
|
|
unsigned i;
|
|
|
|
for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
|
|
|
|
/*search*/;
|
|
|
|
|
|
|
|
if (i == 16) return -1; // all undef.
|
|
|
|
|
|
|
|
// Otherwise, check to see if the rest of the elements are consequtively
|
|
|
|
// numbered from this value.
|
|
|
|
unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
|
|
|
|
if (ShiftAmt < i) return -1;
|
|
|
|
ShiftAmt -= i;
|
|
|
|
|
2006-04-06 22:28:36 +00:00
|
|
|
if (!isUnary) {
|
|
|
|
// Check the rest of the elements to see if they are consequtive.
|
|
|
|
for (++i; i != 16; ++i)
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
|
|
|
|
return -1;
|
|
|
|
} else {
|
|
|
|
// Check the rest of the elements to see if they are consequtive.
|
|
|
|
for (++i; i != 16; ++i)
|
|
|
|
if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
|
|
|
|
return -1;
|
|
|
|
}
|
2006-04-06 18:26:28 +00:00
|
|
|
|
|
|
|
return ShiftAmt;
|
|
|
|
}
|
2006-03-20 06:33:01 +00:00
|
|
|
|
|
|
|
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a splat of a single element that is suitable for input to
|
|
|
|
/// VSPLTB/VSPLTH/VSPLTW.
|
2006-04-04 17:25:31 +00:00
|
|
|
bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
|
|
|
|
N->getNumOperands() == 16 &&
|
|
|
|
(EltSize == 1 || EltSize == 2 || EltSize == 4));
|
2006-03-20 06:51:10 +00:00
|
|
|
|
2006-03-20 06:37:44 +00:00
|
|
|
// This is a splat operation if each element of the permute is the same, and
|
|
|
|
// if the value doesn't reference the second vector.
|
2006-04-04 17:25:31 +00:00
|
|
|
unsigned ElementBase = 0;
|
2006-03-20 06:37:44 +00:00
|
|
|
SDOperand Elt = N->getOperand(0);
|
2006-04-04 17:25:31 +00:00
|
|
|
if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
|
|
|
|
ElementBase = EltV->getValue();
|
|
|
|
else
|
|
|
|
return false; // FIXME: Handle UNDEF elements too!
|
|
|
|
|
|
|
|
if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check that they are consequtive.
|
|
|
|
for (unsigned i = 1; i != EltSize; ++i) {
|
|
|
|
if (!isa<ConstantSDNode>(N->getOperand(i)) ||
|
|
|
|
cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-03-20 06:37:44 +00:00
|
|
|
assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
|
2006-04-04 17:25:31 +00:00
|
|
|
for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
|
2006-04-14 23:19:08 +00:00
|
|
|
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
|
2006-03-20 06:37:44 +00:00
|
|
|
assert(isa<ConstantSDNode>(N->getOperand(i)) &&
|
|
|
|
"Invalid VECTOR_SHUFFLE mask!");
|
2006-04-04 17:25:31 +00:00
|
|
|
for (unsigned j = 0; j != EltSize; ++j)
|
|
|
|
if (N->getOperand(i+j) != N->getOperand(j))
|
|
|
|
return false;
|
2006-03-20 06:37:44 +00:00
|
|
|
}
|
|
|
|
|
2006-04-04 17:25:31 +00:00
|
|
|
return true;
|
2006-03-20 06:33:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-30 07:51:22 +00:00
|
|
|
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
|
|
|
|
/// are -0.0.
|
|
|
|
bool PPC::isAllNegativeZeroVector(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
|
|
|
|
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
|
2007-08-31 04:03:46 +00:00
|
|
|
return CFP->getValueAPF().isNegZero();
|
2007-07-30 07:51:22 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-03-20 06:33:01 +00:00
|
|
|
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
|
|
|
|
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
|
2006-04-04 17:25:31 +00:00
|
|
|
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
|
|
|
|
assert(isSplatShuffleMask(N, EltSize));
|
|
|
|
return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
|
2006-03-20 06:33:01 +00:00
|
|
|
}
|
|
|
|
|
2006-04-12 17:37:20 +00:00
|
|
|
/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
|
2006-04-08 06:46:53 +00:00
|
|
|
/// by using a vspltis[bhw] instruction of the specified element size, return
|
|
|
|
/// the constant being splatted. The ByteSize field indicates the number of
|
|
|
|
/// bytes of each element [124] -> [bhw].
|
2006-04-12 17:37:20 +00:00
|
|
|
SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
|
2006-03-25 06:12:06 +00:00
|
|
|
SDOperand OpVal(0, 0);
|
2006-04-08 07:14:26 +00:00
|
|
|
|
|
|
|
// If ByteSize of the splat is bigger than the element size of the
|
|
|
|
// build_vector, then we have a case where we are checking for a splat where
|
|
|
|
// multiple elements of the buildvector are folded together into a single
|
|
|
|
// logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
|
|
|
|
unsigned EltSize = 16/N->getNumOperands();
|
|
|
|
if (EltSize < ByteSize) {
|
|
|
|
unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
|
|
|
|
SDOperand UniquedVals[4];
|
|
|
|
assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
|
|
|
|
|
|
|
|
// See if all of the elements in the buildvector agree across.
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
|
|
|
|
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
|
|
|
|
// If the element isn't a constant, bail fully out.
|
|
|
|
if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
|
|
|
|
|
|
|
|
|
|
|
|
if (UniquedVals[i&(Multiple-1)].Val == 0)
|
|
|
|
UniquedVals[i&(Multiple-1)] = N->getOperand(i);
|
|
|
|
else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
|
|
|
|
return SDOperand(); // no match.
|
|
|
|
}
|
|
|
|
|
|
|
|
// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
|
|
|
|
// either constant or undef values that are identical for each chunk. See
|
|
|
|
// if these chunks can form into a larger vspltis*.
|
|
|
|
|
|
|
|
// Check to see if all of the leading entries are either 0 or -1. If
|
|
|
|
// neither, then this won't fit into the immediate field.
|
|
|
|
bool LeadingZero = true;
|
|
|
|
bool LeadingOnes = true;
|
|
|
|
for (unsigned i = 0; i != Multiple-1; ++i) {
|
|
|
|
if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
|
|
|
|
|
|
|
|
LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
|
|
|
|
LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
|
|
|
|
}
|
|
|
|
// Finally, check the least significant entry.
|
|
|
|
if (LeadingZero) {
|
|
|
|
if (UniquedVals[Multiple-1].Val == 0)
|
|
|
|
return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
|
|
|
|
int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
|
|
|
|
if (Val < 16)
|
|
|
|
return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
|
|
|
|
}
|
|
|
|
if (LeadingOnes) {
|
|
|
|
if (UniquedVals[Multiple-1].Val == 0)
|
|
|
|
return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
|
|
|
|
int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
|
|
|
|
if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
|
|
|
|
return DAG.getTargetConstant(Val, MVT::i32);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-03-25 06:12:06 +00:00
|
|
|
// Check to see if this buildvec has a single non-undef value in its elements.
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
|
|
|
|
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
|
|
|
|
if (OpVal.Val == 0)
|
|
|
|
OpVal = N->getOperand(i);
|
|
|
|
else if (OpVal != N->getOperand(i))
|
2006-04-08 06:46:53 +00:00
|
|
|
return SDOperand();
|
2006-03-25 06:12:06 +00:00
|
|
|
}
|
|
|
|
|
2006-04-08 06:46:53 +00:00
|
|
|
if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
|
2006-03-25 06:12:06 +00:00
|
|
|
|
2006-03-28 04:15:58 +00:00
|
|
|
unsigned ValSizeInBytes = 0;
|
|
|
|
uint64_t Value = 0;
|
2006-03-25 06:12:06 +00:00
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
|
|
|
|
Value = CN->getValue();
|
2008-06-06 12:08:01 +00:00
|
|
|
ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
|
2006-03-25 06:12:06 +00:00
|
|
|
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
|
|
|
|
assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
|
2007-08-31 04:03:46 +00:00
|
|
|
Value = FloatToBits(CN->getValueAPF().convertToFloat());
|
2006-03-25 06:12:06 +00:00
|
|
|
ValSizeInBytes = 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the splat value is larger than the element value, then we can never do
|
|
|
|
// this splat. The only case that we could fit the replicated bits into our
|
|
|
|
// immediate field for would be zero, and we prefer to use vxor for it.
|
2006-04-08 06:46:53 +00:00
|
|
|
if (ValSizeInBytes < ByteSize) return SDOperand();
|
2006-03-25 06:12:06 +00:00
|
|
|
|
|
|
|
// If the element value is larger than the splat value, cut it in half and
|
|
|
|
// check to see if the two halves are equal. Continue doing this until we
|
|
|
|
// get to ByteSize. This allows us to handle 0x01010101 as 0x01.
|
|
|
|
while (ValSizeInBytes > ByteSize) {
|
|
|
|
ValSizeInBytes >>= 1;
|
|
|
|
|
|
|
|
// If the top half equals the bottom half, we're still ok.
|
2006-04-05 17:39:25 +00:00
|
|
|
if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
|
|
|
|
(Value & ((1 << (8*ValSizeInBytes))-1)))
|
2006-04-08 06:46:53 +00:00
|
|
|
return SDOperand();
|
2006-03-25 06:12:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Properly sign extend the value.
|
|
|
|
int ShAmt = (4-ByteSize)*8;
|
|
|
|
int MaskVal = ((int)Value << ShAmt) >> ShAmt;
|
|
|
|
|
2006-03-26 09:52:32 +00:00
|
|
|
// If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
|
2006-04-08 06:46:53 +00:00
|
|
|
if (MaskVal == 0) return SDOperand();
|
2006-03-25 06:12:06 +00:00
|
|
|
|
2006-04-08 06:46:53 +00:00
|
|
|
// Finally, if this value fits in a 5 bit sext field, return it
|
|
|
|
if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
|
|
|
|
return DAG.getTargetConstant(MaskVal, MVT::i32);
|
|
|
|
return SDOperand();
|
2006-03-25 06:12:06 +00:00
|
|
|
}
|
|
|
|
|
2006-11-08 02:15:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Addressing Mode Selection
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
|
|
|
|
/// or 64-bit immediate, and if the value can be accurately represented as a
|
|
|
|
/// sign extension from a 16-bit value. If so, this returns true and the
|
|
|
|
/// immediate.
|
|
|
|
static bool isIntS16Immediate(SDNode *N, short &Imm) {
|
|
|
|
if (N->getOpcode() != ISD::Constant)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Imm = (short)cast<ConstantSDNode>(N)->getValue();
|
|
|
|
if (N->getValueType(0) == MVT::i32)
|
|
|
|
return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
|
|
|
|
else
|
|
|
|
return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
|
|
|
|
}
|
|
|
|
static bool isIntS16Immediate(SDOperand Op, short &Imm) {
|
|
|
|
return isIntS16Immediate(Op.Val, Imm);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// SelectAddressRegReg - Given the specified addressed, check to see if it
|
|
|
|
/// can be represented as an indexed [r+r] operation. Returns false if it
|
|
|
|
/// can be more efficiently represented with [r+imm].
|
|
|
|
bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
|
|
|
|
SDOperand &Index,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
short imm = 0;
|
|
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
|
|
if (isIntS16Immediate(N.getOperand(1), imm))
|
|
|
|
return false; // r+i
|
|
|
|
if (N.getOperand(1).getOpcode() == PPCISD::Lo)
|
|
|
|
return false; // r+i
|
|
|
|
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
Index = N.getOperand(1);
|
|
|
|
return true;
|
|
|
|
} else if (N.getOpcode() == ISD::OR) {
|
|
|
|
if (isIntS16Immediate(N.getOperand(1), imm))
|
|
|
|
return false; // r+i can fold it if we can.
|
|
|
|
|
|
|
|
// If this is an or of disjoint bitfields, we can codegen this as an add
|
|
|
|
// (for better address arithmetic) if the LHS and RHS of the OR are provably
|
|
|
|
// disjoint.
|
2008-02-27 01:23:58 +00:00
|
|
|
APInt LHSKnownZero, LHSKnownOne;
|
|
|
|
APInt RHSKnownZero, RHSKnownOne;
|
|
|
|
DAG.ComputeMaskedBits(N.getOperand(0),
|
2008-02-27 21:12:32 +00:00
|
|
|
APInt::getAllOnesValue(N.getOperand(0)
|
|
|
|
.getValueSizeInBits()),
|
2008-02-27 01:23:58 +00:00
|
|
|
LHSKnownZero, LHSKnownOne);
|
2006-11-08 02:15:41 +00:00
|
|
|
|
2008-02-27 01:23:58 +00:00
|
|
|
if (LHSKnownZero.getBoolValue()) {
|
|
|
|
DAG.ComputeMaskedBits(N.getOperand(1),
|
2008-02-27 21:12:32 +00:00
|
|
|
APInt::getAllOnesValue(N.getOperand(1)
|
|
|
|
.getValueSizeInBits()),
|
2008-02-27 01:23:58 +00:00
|
|
|
RHSKnownZero, RHSKnownOne);
|
2006-11-08 02:15:41 +00:00
|
|
|
// If all of the bits are known zero on the LHS or RHS, the add won't
|
|
|
|
// carry.
|
2008-02-27 21:12:32 +00:00
|
|
|
if (~(LHSKnownZero | RHSKnownZero) == 0) {
|
2006-11-08 02:15:41 +00:00
|
|
|
Base = N.getOperand(0);
|
|
|
|
Index = N.getOperand(1);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns true if the address N can be represented by a base register plus
|
|
|
|
/// a signed 16-bit displacement [r+imm], and if it is not better
|
|
|
|
/// represented as reg+reg.
|
|
|
|
bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
|
|
|
|
SDOperand &Base, SelectionDAG &DAG){
|
|
|
|
// If this can be more profitably realized as r+r, fail.
|
|
|
|
if (SelectAddressRegReg(N, Disp, Base, DAG))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
|
|
short imm = 0;
|
|
|
|
if (isIntS16Immediate(N.getOperand(1), imm)) {
|
|
|
|
Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
|
|
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
|
|
|
|
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
|
|
} else {
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
}
|
|
|
|
return true; // [r+i]
|
|
|
|
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
|
|
|
|
// Match LOAD (ADD (X, Lo(G))).
|
|
|
|
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
|
|
|
|
&& "Cannot handle constant offsets yet!");
|
|
|
|
Disp = N.getOperand(1).getOperand(0); // The global address.
|
|
|
|
assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
|
|
|
|
Disp.getOpcode() == ISD::TargetConstantPool ||
|
|
|
|
Disp.getOpcode() == ISD::TargetJumpTable);
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
return true; // [&g+r]
|
|
|
|
}
|
|
|
|
} else if (N.getOpcode() == ISD::OR) {
|
|
|
|
short imm = 0;
|
|
|
|
if (isIntS16Immediate(N.getOperand(1), imm)) {
|
|
|
|
// If this is an or of disjoint bitfields, we can codegen this as an add
|
|
|
|
// (for better address arithmetic) if the LHS and RHS of the OR are
|
|
|
|
// provably disjoint.
|
2008-02-27 01:23:58 +00:00
|
|
|
APInt LHSKnownZero, LHSKnownOne;
|
|
|
|
DAG.ComputeMaskedBits(N.getOperand(0),
|
2008-03-24 23:16:37 +00:00
|
|
|
APInt::getAllOnesValue(N.getOperand(0)
|
|
|
|
.getValueSizeInBits()),
|
2008-02-27 01:23:58 +00:00
|
|
|
LHSKnownZero, LHSKnownOne);
|
2008-03-24 23:16:37 +00:00
|
|
|
|
2008-02-27 01:23:58 +00:00
|
|
|
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
|
2006-11-08 02:15:41 +00:00
|
|
|
// If all of the bits are known zero on the LHS or RHS, the add won't
|
|
|
|
// carry.
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
|
|
|
|
// Loading from a constant address.
|
|
|
|
|
|
|
|
// If this address fits entirely in a 16-bit sext immediate field, codegen
|
|
|
|
// this as "d, 0"
|
|
|
|
short Imm;
|
|
|
|
if (isIntS16Immediate(CN, Imm)) {
|
|
|
|
Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
|
|
|
|
Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
|
|
|
|
return true;
|
|
|
|
}
|
2007-02-17 06:44:03 +00:00
|
|
|
|
|
|
|
// Handle 32-bit sext immediates with LIS + addr mode.
|
|
|
|
if (CN->getValueType(0) == MVT::i32 ||
|
|
|
|
(int64_t)CN->getValue() == (int)CN->getValue()) {
|
2006-11-08 02:15:41 +00:00
|
|
|
int Addr = (int)CN->getValue();
|
|
|
|
|
|
|
|
// Otherwise, break this down into an LIS + disp.
|
2007-02-17 06:44:03 +00:00
|
|
|
Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
|
|
|
|
|
|
|
|
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
|
|
|
|
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
|
|
|
|
Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
|
2006-11-08 02:15:41 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Disp = DAG.getTargetConstant(0, getPointerTy());
|
|
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
|
|
|
|
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
|
|
else
|
|
|
|
Base = N;
|
|
|
|
return true; // [r+0]
|
|
|
|
}
|
|
|
|
|
|
|
|
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
|
|
|
|
/// represented as an indexed [r+r] operation.
|
|
|
|
bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
|
|
|
|
SDOperand &Index,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
// Check to see if we can easily represent this as an [r+r] address. This
|
|
|
|
// will fail if it thinks that the address is more profitably represented as
|
|
|
|
// reg+imm, e.g. where imm = 0.
|
|
|
|
if (SelectAddressRegReg(N, Base, Index, DAG))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the operand is an addition, always emit this as [r+r], since this is
|
|
|
|
// better (for code size, and execution, as the memop does the add for free)
|
|
|
|
// than emitting an explicit add.
|
|
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
Index = N.getOperand(1);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, do it the hard way, using R0 as the base register.
|
|
|
|
Base = DAG.getRegister(PPC::R0, N.getValueType());
|
|
|
|
Index = N;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// SelectAddressRegImmShift - Returns true if the address N can be
|
|
|
|
/// represented by a base register plus a signed 14-bit displacement
|
|
|
|
/// [r+imm*4]. Suitable for use by STD and friends.
|
|
|
|
bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
|
|
|
|
SDOperand &Base,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
// If this can be more profitably realized as r+r, fail.
|
|
|
|
if (SelectAddressRegReg(N, Disp, Base, DAG))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
|
|
short imm = 0;
|
|
|
|
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
|
|
|
|
Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
|
|
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
|
|
|
|
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
|
|
} else {
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
}
|
|
|
|
return true; // [r+i]
|
|
|
|
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
|
|
|
|
// Match LOAD (ADD (X, Lo(G))).
|
|
|
|
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
|
|
|
|
&& "Cannot handle constant offsets yet!");
|
|
|
|
Disp = N.getOperand(1).getOperand(0); // The global address.
|
|
|
|
assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
|
|
|
|
Disp.getOpcode() == ISD::TargetConstantPool ||
|
|
|
|
Disp.getOpcode() == ISD::TargetJumpTable);
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
return true; // [&g+r]
|
|
|
|
}
|
|
|
|
} else if (N.getOpcode() == ISD::OR) {
|
|
|
|
short imm = 0;
|
|
|
|
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
|
|
|
|
// If this is an or of disjoint bitfields, we can codegen this as an add
|
|
|
|
// (for better address arithmetic) if the LHS and RHS of the OR are
|
|
|
|
// provably disjoint.
|
2008-02-27 01:23:58 +00:00
|
|
|
APInt LHSKnownZero, LHSKnownOne;
|
|
|
|
DAG.ComputeMaskedBits(N.getOperand(0),
|
2008-03-24 23:16:37 +00:00
|
|
|
APInt::getAllOnesValue(N.getOperand(0)
|
|
|
|
.getValueSizeInBits()),
|
2008-02-27 01:23:58 +00:00
|
|
|
LHSKnownZero, LHSKnownOne);
|
|
|
|
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
|
2006-11-08 02:15:41 +00:00
|
|
|
// If all of the bits are known zero on the LHS or RHS, the add won't
|
|
|
|
// carry.
|
|
|
|
Base = N.getOperand(0);
|
|
|
|
Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
|
2007-02-17 06:57:26 +00:00
|
|
|
// Loading from a constant address. Verify low two bits are clear.
|
|
|
|
if ((CN->getValue() & 3) == 0) {
|
|
|
|
// If this address fits entirely in a 14-bit sext immediate field, codegen
|
|
|
|
// this as "d, 0"
|
|
|
|
short Imm;
|
|
|
|
if (isIntS16Immediate(CN, Imm)) {
|
|
|
|
Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
|
|
|
|
Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
|
|
|
|
return true;
|
|
|
|
}
|
2006-11-08 02:15:41 +00:00
|
|
|
|
2007-02-17 06:57:26 +00:00
|
|
|
// Fold the low-part of 32-bit absolute addresses into addr mode.
|
|
|
|
if (CN->getValueType(0) == MVT::i32 ||
|
|
|
|
(int64_t)CN->getValue() == (int)CN->getValue()) {
|
|
|
|
int Addr = (int)CN->getValue();
|
2006-11-08 02:15:41 +00:00
|
|
|
|
2007-02-17 06:57:26 +00:00
|
|
|
// Otherwise, break this down into an LIS + disp.
|
|
|
|
Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
|
|
|
|
|
|
|
|
Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
|
|
|
|
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
|
|
|
|
Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
|
|
|
|
return true;
|
|
|
|
}
|
2006-11-08 02:15:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Disp = DAG.getTargetConstant(0, getPointerTy());
|
|
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
|
|
|
|
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
|
|
else
|
|
|
|
Base = N;
|
|
|
|
return true; // [r+0]
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// getPreIndexedAddressParts - returns true by value, base pointer and
|
|
|
|
/// offset pointer and addressing mode by reference if the node's address
|
|
|
|
/// can be legally represented as pre-indexed load / store address.
|
|
|
|
bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
|
|
|
|
SDOperand &Offset,
|
2006-11-09 17:55:04 +00:00
|
|
|
ISD::MemIndexedMode &AM,
|
2006-11-08 02:15:41 +00:00
|
|
|
SelectionDAG &DAG) {
|
2006-11-10 02:08:47 +00:00
|
|
|
// Disabled by default for now.
|
|
|
|
if (!EnablePPCPreinc) return false;
|
2006-11-08 02:15:41 +00:00
|
|
|
|
|
|
|
SDOperand Ptr;
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT;
|
2006-11-08 02:15:41 +00:00
|
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
|
|
|
|
Ptr = LD->getBasePtr();
|
2008-01-30 00:15:11 +00:00
|
|
|
VT = LD->getMemoryVT();
|
2006-11-15 19:55:13 +00:00
|
|
|
|
2006-11-08 02:15:41 +00:00
|
|
|
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
|
2006-11-10 02:08:47 +00:00
|
|
|
ST = ST;
|
2006-11-14 01:38:31 +00:00
|
|
|
Ptr = ST->getBasePtr();
|
2008-01-30 00:15:11 +00:00
|
|
|
VT = ST->getMemoryVT();
|
2006-11-08 02:15:41 +00:00
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
|
2006-11-14 01:38:31 +00:00
|
|
|
// PowerPC doesn't have preinc load/store instructions for vectors.
|
2008-06-06 12:08:01 +00:00
|
|
|
if (VT.isVector())
|
2006-11-14 01:38:31 +00:00
|
|
|
return false;
|
|
|
|
|
2006-11-15 19:55:13 +00:00
|
|
|
// TODO: Check reg+reg first.
|
|
|
|
|
|
|
|
// LDU/STU use reg+imm*4, others use reg+imm.
|
|
|
|
if (VT != MVT::i64) {
|
|
|
|
// reg + imm
|
|
|
|
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
// reg + imm * 4.
|
|
|
|
if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
|
|
|
|
return false;
|
|
|
|
}
|
2006-11-11 00:08:42 +00:00
|
|
|
|
|
|
|
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
|
2006-11-15 19:55:13 +00:00
|
|
|
// PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
|
|
|
|
// sext i32 to i64 when addr mode is r+i.
|
2008-01-30 00:15:11 +00:00
|
|
|
if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
|
2006-11-11 00:08:42 +00:00
|
|
|
LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
|
|
isa<ConstantSDNode>(Offset))
|
|
|
|
return false;
|
2006-11-15 19:55:13 +00:00
|
|
|
}
|
2006-11-08 02:15:41 +00:00
|
|
|
|
2006-11-10 02:08:47 +00:00
|
|
|
AM = ISD::PRE_INC;
|
|
|
|
return true;
|
2006-11-08 02:15:41 +00:00
|
|
|
}
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// LowerOperation implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = Op.getValueType();
|
2006-04-14 06:01:58 +00:00
|
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
2006-09-12 21:04:05 +00:00
|
|
|
Constant *C = CP->getConstVal();
|
2006-06-16 21:01:35 +00:00
|
|
|
SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
|
|
|
|
SDOperand Zero = DAG.getConstant(0, PtrVT);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
const TargetMachine &TM = DAG.getTarget();
|
|
|
|
|
2006-06-16 21:01:35 +00:00
|
|
|
SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
|
|
|
|
SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
// If this is a non-darwin platform, we don't support non-static relo models
|
|
|
|
// yet.
|
|
|
|
if (TM.getRelocationModel() == Reloc::Static ||
|
|
|
|
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
|
|
|
|
// Generate non-pic code that has direct accesses to the constant pool.
|
|
|
|
// The address of the global is just (hi(&g)+lo(&g)).
|
2006-06-16 21:01:35 +00:00
|
|
|
return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2006-07-26 21:12:04 +00:00
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
2006-04-14 06:01:58 +00:00
|
|
|
// With PIC, the first instruction is actually "GR+hi(&G)".
|
2006-06-16 21:01:35 +00:00
|
|
|
Hi = DAG.getNode(ISD::ADD, PtrVT,
|
|
|
|
DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2006-06-16 21:01:35 +00:00
|
|
|
Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
|
2006-04-14 06:01:58 +00:00
|
|
|
return Lo;
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = Op.getValueType();
|
2006-04-22 18:53:45 +00:00
|
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
2006-06-16 21:01:35 +00:00
|
|
|
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
|
|
|
|
SDOperand Zero = DAG.getConstant(0, PtrVT);
|
2006-04-22 18:53:45 +00:00
|
|
|
|
|
|
|
const TargetMachine &TM = DAG.getTarget();
|
2006-06-16 21:01:35 +00:00
|
|
|
|
|
|
|
SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
|
|
|
|
SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
|
|
|
|
|
2006-04-22 18:53:45 +00:00
|
|
|
// If this is a non-darwin platform, we don't support non-static relo models
|
|
|
|
// yet.
|
|
|
|
if (TM.getRelocationModel() == Reloc::Static ||
|
|
|
|
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
|
|
|
|
// Generate non-pic code that has direct accesses to the constant pool.
|
|
|
|
// The address of the global is just (hi(&g)+lo(&g)).
|
2006-06-16 21:01:35 +00:00
|
|
|
return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
|
2006-04-22 18:53:45 +00:00
|
|
|
}
|
|
|
|
|
2006-07-26 21:12:04 +00:00
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
2006-04-22 18:53:45 +00:00
|
|
|
// With PIC, the first instruction is actually "GR+hi(&G)".
|
2006-06-16 21:01:35 +00:00
|
|
|
Hi = DAG.getNode(ISD::ADD, PtrVT,
|
2006-07-28 16:45:47 +00:00
|
|
|
DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
|
2006-04-22 18:53:45 +00:00
|
|
|
}
|
|
|
|
|
2006-06-16 21:01:35 +00:00
|
|
|
Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
|
2006-04-22 18:53:45 +00:00
|
|
|
return Lo;
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2007-07-11 17:19:51 +00:00
|
|
|
assert(0 && "TLS not implemented for PPC.");
|
2008-03-30 18:22:13 +00:00
|
|
|
return SDOperand(); // Not reached
|
2007-07-11 17:19:51 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = Op.getValueType();
|
2006-04-14 06:01:58 +00:00
|
|
|
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
|
|
|
|
GlobalValue *GV = GSDN->getGlobal();
|
2006-06-16 21:01:35 +00:00
|
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
|
2008-02-02 05:06:29 +00:00
|
|
|
// If it's a debug information descriptor, don't mess with it.
|
|
|
|
if (DAG.isVerifiedDebugInfoDesc(Op))
|
|
|
|
return GA;
|
2006-06-16 21:01:35 +00:00
|
|
|
SDOperand Zero = DAG.getConstant(0, PtrVT);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
const TargetMachine &TM = DAG.getTarget();
|
|
|
|
|
2006-06-16 21:01:35 +00:00
|
|
|
SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
|
|
|
|
SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
// If this is a non-darwin platform, we don't support non-static relo models
|
|
|
|
// yet.
|
|
|
|
if (TM.getRelocationModel() == Reloc::Static ||
|
|
|
|
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
|
|
|
|
// Generate non-pic code that has direct accesses to globals.
|
|
|
|
// The address of the global is just (hi(&g)+lo(&g)).
|
2006-06-16 21:01:35 +00:00
|
|
|
return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2006-07-26 21:12:04 +00:00
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
2006-04-14 06:01:58 +00:00
|
|
|
// With PIC, the first instruction is actually "GR+hi(&G)".
|
2006-06-16 21:01:35 +00:00
|
|
|
Hi = DAG.getNode(ISD::ADD, PtrVT,
|
|
|
|
DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2006-06-16 21:01:35 +00:00
|
|
|
Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
2006-12-11 23:22:45 +00:00
|
|
|
if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
|
2006-04-14 06:01:58 +00:00
|
|
|
return Lo;
|
|
|
|
|
|
|
|
// If the global is weak or external, we have to go through the lazy
|
|
|
|
// resolution stub.
|
2006-10-09 20:57:25 +00:00
|
|
|
return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
|
2006-04-14 06:01:58 +00:00
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
|
|
|
|
|
|
|
// If we're comparing for equality to zero, expose the fact that this is
|
|
|
|
// implented as a ctlz/srl pair on ppc, so that the dag combiner can
|
|
|
|
// fold the new nodes.
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
|
|
|
if (C->isNullValue() && CC == ISD::SETEQ) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.getOperand(0).getValueType();
|
2006-04-14 06:01:58 +00:00
|
|
|
SDOperand Zext = Op.getOperand(0);
|
2008-06-08 20:54:56 +00:00
|
|
|
if (VT.bitsLT(MVT::i32)) {
|
2006-04-14 06:01:58 +00:00
|
|
|
VT = MVT::i32;
|
|
|
|
Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
|
|
|
|
}
|
2008-06-06 12:08:01 +00:00
|
|
|
unsigned Log2b = Log2_32(VT.getSizeInBits());
|
2006-04-14 06:01:58 +00:00
|
|
|
SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
|
|
|
|
SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
|
|
|
|
DAG.getConstant(Log2b, MVT::i32));
|
|
|
|
return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
|
|
|
|
}
|
|
|
|
// Leave comparisons against 0 and -1 alone for now, since they're usually
|
|
|
|
// optimized. FIXME: revisit this when we can custom lower all setcc
|
|
|
|
// optimizations.
|
|
|
|
if (C->isAllOnesValue() || C->isNullValue())
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we have an integer seteq/setne, turn it into a compare against zero
|
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-14 05:28:08 +00:00
|
|
|
// by xor'ing the rhs with the lhs, which is faster than setting a
|
|
|
|
// condition register, reading it back out, and masking the correct bit. The
|
|
|
|
// normal approach here uses sub to do this instead of xor. Using xor exposes
|
|
|
|
// the result to other bit-twiddling opportunities.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT LHSVT = Op.getOperand(0).getValueType();
|
|
|
|
if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
|
|
|
|
MVT VT = Op.getValueType();
|
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-14 05:28:08 +00:00
|
|
|
SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
|
2006-04-14 06:01:58 +00:00
|
|
|
Op.getOperand(1));
|
|
|
|
return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
|
|
|
|
}
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
|
2007-04-03 13:59:52 +00:00
|
|
|
int VarArgsFrameIndex,
|
|
|
|
int VarArgsStackOffset,
|
|
|
|
unsigned VarArgsNumGPR,
|
|
|
|
unsigned VarArgsNumFPR,
|
|
|
|
const PPCSubtarget &Subtarget) {
|
|
|
|
|
|
|
|
assert(0 && "VAARG in ELF32 ABI not implemented yet!");
|
2008-03-30 18:22:13 +00:00
|
|
|
return SDOperand(); // Not reached
|
2007-04-03 13:59:52 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
|
2007-04-03 13:59:52 +00:00
|
|
|
int VarArgsFrameIndex,
|
|
|
|
int VarArgsStackOffset,
|
|
|
|
unsigned VarArgsNumGPR,
|
|
|
|
unsigned VarArgsNumFPR,
|
|
|
|
const PPCSubtarget &Subtarget) {
|
|
|
|
|
|
|
|
if (Subtarget.isMachoABI()) {
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
|
|
// memory location argument.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2007-04-03 13:59:52 +00:00
|
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
2008-02-06 22:27:42 +00:00
|
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
|
|
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
|
2007-04-03 13:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For ELF 32 ABI we follow the layout of the va_list struct.
|
|
|
|
// We suppose the given va_list is already allocated.
|
|
|
|
//
|
|
|
|
// typedef struct {
|
|
|
|
// char gpr; /* index into the array of 8 GPRs
|
|
|
|
// * stored in the register save area
|
|
|
|
// * gpr=0 corresponds to r3,
|
|
|
|
// * gpr=1 to r4, etc.
|
|
|
|
// */
|
|
|
|
// char fpr; /* index into the array of 8 FPRs
|
|
|
|
// * stored in the register save area
|
|
|
|
// * fpr=0 corresponds to f1,
|
|
|
|
// * fpr=1 to f2, etc.
|
|
|
|
// */
|
|
|
|
// char *overflow_arg_area;
|
|
|
|
// /* location on stack that holds
|
|
|
|
// * the next overflow argument
|
|
|
|
// */
|
|
|
|
// char *reg_save_area;
|
|
|
|
// /* where r3:r10 and f1:f8 (if saved)
|
|
|
|
// * are stored
|
|
|
|
// */
|
|
|
|
// } va_list[1];
|
|
|
|
|
|
|
|
|
|
|
|
SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
|
|
|
|
SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
|
|
|
|
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2007-04-03 13:59:52 +00:00
|
|
|
|
2008-02-06 22:27:42 +00:00
|
|
|
SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
|
2006-07-28 16:45:47 +00:00
|
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
2007-04-03 13:59:52 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
|
2008-02-06 22:27:42 +00:00
|
|
|
SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
|
2008-02-06 22:27:42 +00:00
|
|
|
SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
|
|
|
|
|
|
|
|
uint64_t FPROffset = 1;
|
|
|
|
SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
|
2007-04-03 13:59:52 +00:00
|
|
|
|
2008-02-06 22:27:42 +00:00
|
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
2007-04-03 13:59:52 +00:00
|
|
|
|
|
|
|
// Store first byte : number of int regs
|
|
|
|
SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
|
2008-02-06 22:27:42 +00:00
|
|
|
Op.getOperand(1), SV, 0);
|
|
|
|
uint64_t nextOffset = FPROffset;
|
2007-04-03 13:59:52 +00:00
|
|
|
SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
|
|
|
|
ConstFPROffset);
|
|
|
|
|
|
|
|
// Store second byte : number of float regs
|
2008-02-06 22:27:42 +00:00
|
|
|
SDOperand secondStore =
|
|
|
|
DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
|
|
|
|
nextOffset += StackOffset;
|
2007-04-03 13:59:52 +00:00
|
|
|
nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
|
|
|
|
|
|
|
|
// Store second word : arguments given on stack
|
2008-02-06 22:27:42 +00:00
|
|
|
SDOperand thirdStore =
|
|
|
|
DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
|
|
|
|
nextOffset += FrameOffset;
|
2007-04-03 13:59:52 +00:00
|
|
|
nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
|
|
|
|
|
|
|
|
// Store third word : arguments given in registers
|
2008-02-06 22:27:42 +00:00
|
|
|
return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
|
2007-04-03 13:59:52 +00:00
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2007-03-06 00:59:59 +00:00
|
|
|
#include "PPCGenCallingConv.inc"
|
|
|
|
|
2007-02-25 05:34:32 +00:00
|
|
|
/// GetFPR - Get the set of FP registers that should be allocated for arguments,
|
|
|
|
/// depending on which subtarget is selected.
|
|
|
|
static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
|
|
|
|
if (Subtarget.isMachoABI()) {
|
|
|
|
static const unsigned FPR[] = {
|
|
|
|
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
|
|
|
|
PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
|
|
|
|
};
|
|
|
|
return FPR;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static const unsigned FPR[] = {
|
|
|
|
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
|
2007-04-03 10:27:07 +00:00
|
|
|
PPC::F8
|
2007-02-25 05:34:32 +00:00
|
|
|
};
|
|
|
|
return FPR;
|
|
|
|
}
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
/// CalculateStackSlotSize - Calculates the size reserved for this argument on
|
|
|
|
/// the stack.
|
|
|
|
static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag,
|
|
|
|
bool isVarArg, unsigned PtrByteSize) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ArgVT = Arg.getValueType();
|
2008-04-30 09:16:33 +00:00
|
|
|
ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags();
|
2008-06-06 12:08:01 +00:00
|
|
|
unsigned ArgSize =ArgVT.getSizeInBits()/8;
|
2008-04-30 09:16:33 +00:00
|
|
|
if (Flags.isByVal())
|
|
|
|
ArgSize = Flags.getByValSize();
|
|
|
|
ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
|
|
|
|
|
|
|
|
return ArgSize;
|
|
|
|
}
|
|
|
|
|
2008-03-07 20:49:02 +00:00
|
|
|
SDOperand
|
|
|
|
PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
|
|
|
|
SelectionDAG &DAG,
|
|
|
|
int &VarArgsFrameIndex,
|
|
|
|
int &VarArgsStackOffset,
|
|
|
|
unsigned &VarArgsNumGPR,
|
|
|
|
unsigned &VarArgsNumFPR,
|
|
|
|
const PPCSubtarget &Subtarget) {
|
2006-05-16 18:18:50 +00:00
|
|
|
// TODO: add description of PPC stack frame format, or at least some docs.
|
|
|
|
//
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-12-31 04:13:23 +00:00
|
|
|
MachineRegisterInfo &RegInfo = MF.getRegInfo();
|
2006-08-11 17:18:05 +00:00
|
|
|
SmallVector<SDOperand, 8> ArgValues;
|
2006-05-16 18:18:50 +00:00
|
|
|
SDOperand Root = Op.getOperand(0);
|
2008-03-12 00:22:17 +00:00
|
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
2006-05-16 18:18:50 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-11-16 22:43:37 +00:00
|
|
|
bool isPPC64 = PtrVT == MVT::i64;
|
2007-02-25 05:34:32 +00:00
|
|
|
bool isMachoABI = Subtarget.isMachoABI();
|
2007-04-03 12:35:28 +00:00
|
|
|
bool isELF32_ABI = Subtarget.isELF32_ABI();
|
2008-04-30 09:16:33 +00:00
|
|
|
// Potential tail calls could cause overwriting of argument stack slots.
|
|
|
|
unsigned CC = MF.getFunction()->getCallingConv();
|
|
|
|
bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
|
2006-11-28 14:53:52 +00:00
|
|
|
unsigned PtrByteSize = isPPC64 ? 8 : 4;
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2007-02-25 05:34:32 +00:00
|
|
|
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
|
2008-04-30 09:16:33 +00:00
|
|
|
// Area that is at least reserved in caller of this function.
|
|
|
|
unsigned MinReservedArea = ArgOffset;
|
|
|
|
|
2006-06-26 22:48:35 +00:00
|
|
|
static const unsigned GPR_32[] = { // 32-bit registers.
|
2006-05-16 18:18:50 +00:00
|
|
|
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
|
|
|
|
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
|
|
|
|
};
|
2006-06-26 22:48:35 +00:00
|
|
|
static const unsigned GPR_64[] = { // 64-bit registers.
|
|
|
|
PPC::X3, PPC::X4, PPC::X5, PPC::X6,
|
|
|
|
PPC::X7, PPC::X8, PPC::X9, PPC::X10,
|
|
|
|
};
|
2007-02-25 05:34:32 +00:00
|
|
|
|
|
|
|
static const unsigned *FPR = GetFPR(Subtarget);
|
|
|
|
|
2006-05-16 18:18:50 +00:00
|
|
|
static const unsigned VR[] = {
|
|
|
|
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
|
|
|
|
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
|
|
|
|
};
|
2006-06-26 22:48:35 +00:00
|
|
|
|
2007-09-07 04:06:50 +00:00
|
|
|
const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
|
2007-04-03 10:27:07 +00:00
|
|
|
const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
|
2007-09-07 04:06:50 +00:00
|
|
|
const unsigned Num_VR_Regs = array_lengthof( VR);
|
2006-11-16 22:43:37 +00:00
|
|
|
|
|
|
|
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
|
|
|
|
|
2006-06-26 22:48:35 +00:00
|
|
|
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
|
2006-05-16 18:18:50 +00:00
|
|
|
|
2008-03-14 17:41:26 +00:00
|
|
|
// In 32-bit non-varargs functions, the stack space for vectors is after the
|
|
|
|
// stack space for non-vectors. We do not use this space unless we have
|
|
|
|
// too many vectors to fit in registers, something that only occurs in
|
|
|
|
// constructed examples:), but we have to walk the arglist to figure
|
|
|
|
// that out...for the pathological case, compute VecArgOffset as the
|
|
|
|
// start of the vector parameter area. Computing VecArgOffset is the
|
|
|
|
// entire point of the following loop.
|
|
|
|
// Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
|
|
|
|
// to handle Elf here.
|
|
|
|
unsigned VecArgOffset = ArgOffset;
|
|
|
|
if (!isVarArg && !isPPC64) {
|
|
|
|
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e;
|
|
|
|
++ArgNo) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
|
|
|
|
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
|
2008-03-21 09:14:45 +00:00
|
|
|
ISD::ArgFlagsTy Flags =
|
|
|
|
cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
|
2008-03-14 17:41:26 +00:00
|
|
|
|
2008-03-21 09:14:45 +00:00
|
|
|
if (Flags.isByVal()) {
|
2008-03-14 17:41:26 +00:00
|
|
|
// ObjSize is the true size, ArgSize rounded up to multiple of regs.
|
2008-03-21 09:14:45 +00:00
|
|
|
ObjSize = Flags.getByValSize();
|
2008-03-14 17:41:26 +00:00
|
|
|
unsigned ArgSize =
|
|
|
|
((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
|
|
|
|
VecArgOffset += ArgSize;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
switch(ObjectVT.getSimpleVT()) {
|
2008-03-14 17:41:26 +00:00
|
|
|
default: assert(0 && "Unhandled argument type!");
|
|
|
|
case MVT::i32:
|
|
|
|
case MVT::f32:
|
|
|
|
VecArgOffset += isPPC64 ? 8 : 4;
|
|
|
|
break;
|
|
|
|
case MVT::i64: // PPC64
|
|
|
|
case MVT::f64:
|
|
|
|
VecArgOffset += 8;
|
|
|
|
break;
|
|
|
|
case MVT::v4f32:
|
|
|
|
case MVT::v4i32:
|
|
|
|
case MVT::v8i16:
|
|
|
|
case MVT::v16i8:
|
|
|
|
// Nothing to do, we're only looking at Nonvector args here.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// We've found where the vector parameter area in memory is. Skip the
|
|
|
|
// first 12 parameters; these don't use that memory.
|
|
|
|
VecArgOffset = ((VecArgOffset+15)/16)*16;
|
|
|
|
VecArgOffset += 12*16;
|
|
|
|
|
2006-05-16 18:18:50 +00:00
|
|
|
// Add DAG nodes to load the arguments or copy them out of registers. On
|
2006-11-16 22:43:37 +00:00
|
|
|
// entry to a function on PPC, the arguments start after the linkage area,
|
|
|
|
// although the first ones are often in registers.
|
2007-03-13 15:02:46 +00:00
|
|
|
//
|
2007-04-03 12:35:28 +00:00
|
|
|
// In the ELF 32 ABI, GPRs and stack are double word align: an argument
|
2007-03-13 15:02:46 +00:00
|
|
|
// represented with two words (long long or double) must be copied to an
|
2008-04-13 13:40:22 +00:00
|
|
|
// even GPR_idx value or to an even ArgOffset value.
|
2007-03-13 15:02:46 +00:00
|
|
|
|
2008-03-07 20:27:40 +00:00
|
|
|
SmallVector<SDOperand, 8> MemOps;
|
2008-04-30 09:16:33 +00:00
|
|
|
unsigned nAltivecParamsAtEnd = 0;
|
2006-05-16 18:18:50 +00:00
|
|
|
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
|
|
|
|
SDOperand ArgVal;
|
|
|
|
bool needsLoad = false;
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
|
|
|
|
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
|
2006-11-29 13:37:09 +00:00
|
|
|
unsigned ArgSize = ObjSize;
|
2008-03-21 09:14:45 +00:00
|
|
|
ISD::ArgFlagsTy Flags =
|
|
|
|
cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
|
2007-03-13 15:02:46 +00:00
|
|
|
// See if next argument requires stack alignment in ELF
|
2008-04-15 08:08:50 +00:00
|
|
|
bool Align = Flags.isSplit();
|
2006-05-16 18:18:50 +00:00
|
|
|
|
2006-05-16 18:51:52 +00:00
|
|
|
unsigned CurArgOffset = ArgOffset;
|
2008-03-07 20:27:40 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
|
|
|
|
if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
|
|
|
|
ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
|
|
|
|
if (isVarArg || isPPC64) {
|
|
|
|
MinReservedArea = ((MinReservedArea+15)/16)*16;
|
|
|
|
MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
|
|
|
|
Op.getOperand(ArgNo+3),
|
|
|
|
isVarArg,
|
|
|
|
PtrByteSize);
|
|
|
|
} else nAltivecParamsAtEnd++;
|
|
|
|
} else
|
|
|
|
// Calculate min reserved area.
|
|
|
|
MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
|
|
|
|
Op.getOperand(ArgNo+3),
|
|
|
|
isVarArg,
|
|
|
|
PtrByteSize);
|
|
|
|
|
2008-03-07 20:27:40 +00:00
|
|
|
// FIXME alignment for ELF may not be right
|
|
|
|
// FIXME the codegen can be much improved in some cases.
|
|
|
|
// We do not have to keep everything in memory.
|
2008-03-21 09:14:45 +00:00
|
|
|
if (Flags.isByVal()) {
|
2008-03-07 20:27:40 +00:00
|
|
|
// ObjSize is the true size, ArgSize rounded up to multiple of registers.
|
2008-03-21 09:14:45 +00:00
|
|
|
ObjSize = Flags.getByValSize();
|
2008-03-07 20:27:40 +00:00
|
|
|
ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
|
2008-03-08 01:41:42 +00:00
|
|
|
// Double word align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
|
2008-03-08 01:41:42 +00:00
|
|
|
// Objects of size 1 and 2 are right justified, everything else is
|
|
|
|
// left justified. This means the memory address is adjusted forwards.
|
|
|
|
if (ObjSize==1 || ObjSize==2) {
|
|
|
|
CurArgOffset = CurArgOffset + (4 - ObjSize);
|
|
|
|
}
|
2008-03-07 20:27:40 +00:00
|
|
|
// The value of the object is its address.
|
|
|
|
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
|
|
|
|
ArgValues.push_back(FIN);
|
2008-03-08 01:41:42 +00:00
|
|
|
if (ObjSize==1 || ObjSize==2) {
|
|
|
|
if (GPR_idx != Num_GPR_Regs) {
|
|
|
|
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
|
|
|
|
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
|
|
|
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
|
|
|
|
SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
|
|
|
|
NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
|
|
|
|
MemOps.push_back(Store);
|
|
|
|
++GPR_idx;
|
|
|
|
if (isMachoABI) ArgOffset += PtrByteSize;
|
|
|
|
} else {
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
2008-03-07 20:27:40 +00:00
|
|
|
for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
|
|
|
|
// Store whatever pieces of the object are in registers
|
|
|
|
// to memory. ArgVal will be address of the beginning of
|
|
|
|
// the object.
|
|
|
|
if (GPR_idx != Num_GPR_Regs) {
|
|
|
|
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
|
|
|
|
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
|
|
|
|
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
|
|
|
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
|
|
|
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
|
|
|
MemOps.push_back(Store);
|
|
|
|
++GPR_idx;
|
|
|
|
if (isMachoABI) ArgOffset += PtrByteSize;
|
|
|
|
} else {
|
|
|
|
ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (ObjectVT.getSimpleVT()) {
|
2006-05-16 18:18:50 +00:00
|
|
|
default: assert(0 && "Unhandled argument type!");
|
|
|
|
case MVT::i32:
|
2008-03-07 20:49:02 +00:00
|
|
|
if (!isPPC64) {
|
|
|
|
// Double word align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
|
2008-03-07 20:49:02 +00:00
|
|
|
|
|
|
|
if (GPR_idx != Num_GPR_Regs) {
|
|
|
|
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
|
|
|
|
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
|
|
|
|
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
|
|
|
|
++GPR_idx;
|
|
|
|
} else {
|
|
|
|
needsLoad = true;
|
|
|
|
ArgSize = PtrByteSize;
|
|
|
|
}
|
|
|
|
// Stack align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (needsLoad && Align && isELF32_ABI)
|
2008-03-07 20:49:02 +00:00
|
|
|
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
|
|
|
|
// All int arguments reserve stack space in Macho ABI.
|
|
|
|
if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
|
|
|
|
break;
|
2006-05-16 18:18:50 +00:00
|
|
|
}
|
2008-03-07 20:49:02 +00:00
|
|
|
// FALLTHROUGH
|
2007-02-25 05:34:32 +00:00
|
|
|
case MVT::i64: // PPC64
|
2006-06-26 22:48:35 +00:00
|
|
|
if (GPR_idx != Num_GPR_Regs) {
|
2007-12-31 04:13:23 +00:00
|
|
|
unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
|
|
|
|
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
|
2006-06-26 22:48:35 +00:00
|
|
|
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
|
2008-03-07 20:49:02 +00:00
|
|
|
|
|
|
|
if (ObjectVT == MVT::i32) {
|
|
|
|
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
|
|
|
|
// value to MVT::i64 and then truncate to the correct register size.
|
2008-03-21 09:14:45 +00:00
|
|
|
if (Flags.isSExt())
|
2008-03-07 20:49:02 +00:00
|
|
|
ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
|
|
|
|
DAG.getValueType(ObjectVT));
|
2008-03-21 09:14:45 +00:00
|
|
|
else if (Flags.isZExt())
|
2008-03-07 20:49:02 +00:00
|
|
|
ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
|
|
|
|
DAG.getValueType(ObjectVT));
|
|
|
|
|
|
|
|
ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
|
|
|
|
}
|
|
|
|
|
2006-06-26 22:48:35 +00:00
|
|
|
++GPR_idx;
|
|
|
|
} else {
|
|
|
|
needsLoad = true;
|
|
|
|
}
|
2007-02-25 05:34:32 +00:00
|
|
|
// All int arguments reserve stack space in Macho ABI.
|
|
|
|
if (isMachoABI || needsLoad) ArgOffset += 8;
|
2006-06-26 22:48:35 +00:00
|
|
|
break;
|
2007-02-25 05:34:32 +00:00
|
|
|
|
2006-05-16 18:18:50 +00:00
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64:
|
2006-05-16 18:51:52 +00:00
|
|
|
// Every 4 bytes of argument space consumes one of the GPRs available for
|
|
|
|
// argument passing.
|
2007-03-13 15:02:46 +00:00
|
|
|
if (GPR_idx != Num_GPR_Regs && isMachoABI) {
|
2006-05-16 18:58:15 +00:00
|
|
|
++GPR_idx;
|
2006-11-18 01:57:19 +00:00
|
|
|
if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
|
2006-05-16 18:58:15 +00:00
|
|
|
++GPR_idx;
|
2006-05-16 18:51:52 +00:00
|
|
|
}
|
2006-05-16 18:58:15 +00:00
|
|
|
if (FPR_idx != Num_FPR_Regs) {
|
2006-05-16 18:18:50 +00:00
|
|
|
unsigned VReg;
|
|
|
|
if (ObjectVT == MVT::f32)
|
2007-12-31 04:13:23 +00:00
|
|
|
VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
|
2006-05-16 18:18:50 +00:00
|
|
|
else
|
2007-12-31 04:13:23 +00:00
|
|
|
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
|
|
|
|
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
|
2006-05-16 18:18:50 +00:00
|
|
|
ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
|
|
|
|
++FPR_idx;
|
|
|
|
} else {
|
|
|
|
needsLoad = true;
|
|
|
|
}
|
2007-02-25 05:34:32 +00:00
|
|
|
|
2007-03-13 15:02:46 +00:00
|
|
|
// Stack align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (needsLoad && Align && isELF32_ABI)
|
2007-03-13 15:02:46 +00:00
|
|
|
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
|
2007-02-25 05:34:32 +00:00
|
|
|
// All FP arguments reserve stack space in Macho ABI.
|
|
|
|
if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
|
2006-05-16 18:18:50 +00:00
|
|
|
break;
|
|
|
|
case MVT::v4f32:
|
|
|
|
case MVT::v4i32:
|
|
|
|
case MVT::v8i16:
|
|
|
|
case MVT::v16i8:
|
2008-03-12 00:22:17 +00:00
|
|
|
// Note that vector arguments in registers don't reserve stack space,
|
|
|
|
// except in varargs functions.
|
2006-05-16 18:58:15 +00:00
|
|
|
if (VR_idx != Num_VR_Regs) {
|
2007-12-31 04:13:23 +00:00
|
|
|
unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
|
|
|
|
RegInfo.addLiveIn(VR[VR_idx], VReg);
|
2006-05-16 18:18:50 +00:00
|
|
|
ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
|
2008-03-12 00:22:17 +00:00
|
|
|
if (isVarArg) {
|
|
|
|
while ((ArgOffset % 16) != 0) {
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
if (GPR_idx != Num_GPR_Regs)
|
|
|
|
GPR_idx++;
|
|
|
|
}
|
|
|
|
ArgOffset += 16;
|
|
|
|
GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
|
|
|
|
}
|
2006-05-16 18:18:50 +00:00
|
|
|
++VR_idx;
|
|
|
|
} else {
|
2008-03-14 17:41:26 +00:00
|
|
|
if (!isVarArg && !isPPC64) {
|
|
|
|
// Vectors go after all the nonvectors.
|
|
|
|
CurArgOffset = VecArgOffset;
|
|
|
|
VecArgOffset += 16;
|
|
|
|
} else {
|
|
|
|
// Vectors are aligned.
|
|
|
|
ArgOffset = ((ArgOffset+15)/16)*16;
|
|
|
|
CurArgOffset = ArgOffset;
|
|
|
|
ArgOffset += 16;
|
2008-03-12 00:49:20 +00:00
|
|
|
}
|
2006-05-16 18:18:50 +00:00
|
|
|
needsLoad = true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// We need to load the argument to a virtual register if we determined above
|
2008-02-13 07:35:30 +00:00
|
|
|
// that we ran out of physical registers of the appropriate type.
|
2006-05-16 18:18:50 +00:00
|
|
|
if (needsLoad) {
|
2008-02-13 07:35:30 +00:00
|
|
|
int FI = MFI->CreateFixedObject(ObjSize,
|
2008-04-30 09:16:33 +00:00
|
|
|
CurArgOffset + (ArgSize - ObjSize),
|
|
|
|
isImmutable);
|
2008-02-13 07:35:30 +00:00
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
|
|
|
|
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
|
2006-05-16 18:18:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ArgValues.push_back(ArgVal);
|
|
|
|
}
|
2008-03-07 20:27:40 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
// Set the size that is at least reserved in caller of this function. Tail
|
|
|
|
// call optimized function's reserved stack space needs to be aligned so that
|
|
|
|
// taking the difference between two stack areas will result in an aligned
|
|
|
|
// stack.
|
|
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
// Add the Altivec parameters at the end, if needed.
|
|
|
|
if (nAltivecParamsAtEnd) {
|
|
|
|
MinReservedArea = ((MinReservedArea+15)/16)*16;
|
|
|
|
MinReservedArea += 16*nAltivecParamsAtEnd;
|
|
|
|
}
|
|
|
|
MinReservedArea =
|
|
|
|
std::max(MinReservedArea,
|
|
|
|
PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
|
|
|
|
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
|
|
|
|
getStackAlignment();
|
|
|
|
unsigned AlignMask = TargetAlign-1;
|
|
|
|
MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
|
|
|
|
FI->setMinReservedArea(MinReservedArea);
|
|
|
|
|
2006-05-16 18:18:50 +00:00
|
|
|
// If the function takes variable number of arguments, make a frame index for
|
|
|
|
// the start of the first vararg value... for expansion of llvm.va_start.
|
|
|
|
if (isVarArg) {
|
2007-04-03 13:59:52 +00:00
|
|
|
|
|
|
|
int depth;
|
|
|
|
if (isELF32_ABI) {
|
|
|
|
VarArgsNumGPR = GPR_idx;
|
|
|
|
VarArgsNumFPR = FPR_idx;
|
|
|
|
|
|
|
|
// Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
|
|
|
|
// pointer.
|
2008-06-06 12:08:01 +00:00
|
|
|
depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
|
|
|
|
Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
|
|
|
|
PtrVT.getSizeInBits()/8);
|
2007-04-03 13:59:52 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
|
2007-04-03 13:59:52 +00:00
|
|
|
ArgOffset);
|
|
|
|
|
|
|
|
}
|
|
|
|
else
|
|
|
|
depth = ArgOffset;
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
|
2007-04-03 13:59:52 +00:00
|
|
|
depth);
|
2006-06-26 22:48:35 +00:00
|
|
|
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
2007-04-03 13:59:52 +00:00
|
|
|
|
|
|
|
// In ELF 32 ABI, the fixed integer arguments of a variadic function are
|
|
|
|
// stored to the VarArgsFrameIndex on the stack.
|
|
|
|
if (isELF32_ABI) {
|
|
|
|
for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
|
|
|
|
SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
|
|
|
|
SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
|
|
|
|
MemOps.push_back(Store);
|
|
|
|
// Increment the address by four for the next argument to store
|
2008-06-06 12:08:01 +00:00
|
|
|
SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
|
2007-04-03 13:59:52 +00:00
|
|
|
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-16 18:18:50 +00:00
|
|
|
// If this function is vararg, store any remaining integer argument regs
|
|
|
|
// to their spots on the stack so that they may be loaded by deferencing the
|
|
|
|
// result of va_next.
|
2006-05-16 18:58:15 +00:00
|
|
|
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
|
2006-11-18 01:57:19 +00:00
|
|
|
unsigned VReg;
|
|
|
|
if (isPPC64)
|
2007-12-31 04:13:23 +00:00
|
|
|
VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
|
2006-11-18 01:57:19 +00:00
|
|
|
else
|
2007-12-31 04:13:23 +00:00
|
|
|
VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
|
2006-11-18 01:57:19 +00:00
|
|
|
|
2007-12-31 04:13:23 +00:00
|
|
|
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
|
2006-06-26 22:48:35 +00:00
|
|
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
|
2006-10-13 21:14:26 +00:00
|
|
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
2006-05-16 18:18:50 +00:00
|
|
|
MemOps.push_back(Store);
|
|
|
|
// Increment the address by four for the next argument to store
|
2008-06-06 12:08:01 +00:00
|
|
|
SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
|
2006-06-26 22:48:35 +00:00
|
|
|
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
|
2006-05-16 18:18:50 +00:00
|
|
|
}
|
2007-04-03 13:59:52 +00:00
|
|
|
|
|
|
|
// In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
|
|
|
|
// on the stack.
|
|
|
|
if (isELF32_ABI) {
|
|
|
|
for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
|
|
|
|
SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
|
|
|
|
SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
|
|
|
|
MemOps.push_back(Store);
|
|
|
|
// Increment the address by eight for the next argument to store
|
2008-06-06 12:08:01 +00:00
|
|
|
SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
|
2007-04-03 13:59:52 +00:00
|
|
|
PtrVT);
|
|
|
|
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
|
|
|
|
unsigned VReg;
|
2007-12-31 04:13:23 +00:00
|
|
|
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
|
2007-04-03 13:59:52 +00:00
|
|
|
|
2007-12-31 04:13:23 +00:00
|
|
|
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
|
2007-04-03 13:59:52 +00:00
|
|
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
|
|
|
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
|
|
|
MemOps.push_back(Store);
|
|
|
|
// Increment the address by eight for the next argument to store
|
2008-06-06 12:08:01 +00:00
|
|
|
SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
|
2007-04-03 13:59:52 +00:00
|
|
|
PtrVT);
|
|
|
|
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
|
|
|
|
}
|
|
|
|
}
|
2006-05-16 18:18:50 +00:00
|
|
|
}
|
|
|
|
|
2008-03-07 20:27:40 +00:00
|
|
|
if (!MemOps.empty())
|
|
|
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
|
|
|
|
|
2006-05-16 18:18:50 +00:00
|
|
|
ArgValues.push_back(Root);
|
|
|
|
|
|
|
|
// Return the new list of results.
|
2008-06-30 10:19:09 +00:00
|
|
|
return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
|
|
|
|
ArgValues.size());
|
2006-05-16 18:18:50 +00:00
|
|
|
}
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
|
|
|
|
/// linkage area.
|
|
|
|
static unsigned
|
|
|
|
CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
|
|
|
|
bool isPPC64,
|
|
|
|
bool isMachoABI,
|
|
|
|
bool isVarArg,
|
|
|
|
unsigned CC,
|
|
|
|
SDOperand Call,
|
|
|
|
unsigned &nAltivecParamsAtEnd) {
|
|
|
|
// Count how many bytes are to be pushed on the stack, including the linkage
|
|
|
|
// area, and parameter passing area. We start with 24/48 bytes, which is
|
|
|
|
// prereserved space for [SP][CR][LR][3 x unused].
|
|
|
|
unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
|
|
|
|
unsigned NumOps = (Call.getNumOperands() - 5) / 2;
|
|
|
|
unsigned PtrByteSize = isPPC64 ? 8 : 4;
|
|
|
|
|
|
|
|
// Add up all the space actually used.
|
|
|
|
// In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
|
|
|
|
// they all go in registers, but we must reserve stack space for them for
|
|
|
|
// possible use by the caller. In varargs or 64-bit calls, parameters are
|
|
|
|
// assigned stack space in order, with padding so Altivec parameters are
|
|
|
|
// 16-byte aligned.
|
|
|
|
nAltivecParamsAtEnd = 0;
|
|
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
|
|
|
SDOperand Arg = Call.getOperand(5+2*i);
|
|
|
|
SDOperand Flag = Call.getOperand(5+2*i+1);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ArgVT = Arg.getValueType();
|
2008-04-30 09:16:33 +00:00
|
|
|
// Varargs Altivec parameters are padded to a 16 byte boundary.
|
|
|
|
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
|
|
|
|
ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
|
|
|
|
if (!isVarArg && !isPPC64) {
|
|
|
|
// Non-varargs Altivec parameters go after all the non-Altivec
|
|
|
|
// parameters; handle those later so we know how much padding we need.
|
|
|
|
nAltivecParamsAtEnd++;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
|
|
|
|
NumBytes = ((NumBytes+15)/16)*16;
|
|
|
|
}
|
|
|
|
NumBytes += CalculateStackSlotSize(Arg, Flag, isVarArg, PtrByteSize);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Allow for Altivec parameters at the end, if needed.
|
|
|
|
if (nAltivecParamsAtEnd) {
|
|
|
|
NumBytes = ((NumBytes+15)/16)*16;
|
|
|
|
NumBytes += 16*nAltivecParamsAtEnd;
|
|
|
|
}
|
|
|
|
|
|
|
|
// The prolog code of the callee may store up to 8 GPR argument registers to
|
|
|
|
// the stack, allowing va_start to index over them in memory if its varargs.
|
|
|
|
// Because we cannot tell if this is needed on the caller side, we have to
|
|
|
|
// conservatively assume that it is needed. As such, make sure we have at
|
|
|
|
// least enough stack space for the caller to store the 8 GPRs.
|
|
|
|
NumBytes = std::max(NumBytes,
|
|
|
|
PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
|
|
|
|
|
|
|
|
// Tail call needs the stack to be aligned.
|
|
|
|
if (CC==CallingConv::Fast && PerformTailCallOpt) {
|
|
|
|
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
|
|
|
|
getStackAlignment();
|
|
|
|
unsigned AlignMask = TargetAlign-1;
|
|
|
|
NumBytes = (NumBytes + AlignMask) & ~AlignMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NumBytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
|
|
|
|
/// adjusted to accomodate the arguments for the tailcall.
|
|
|
|
static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
|
|
|
|
unsigned ParamSize) {
|
|
|
|
|
|
|
|
if (!IsTailCall) return 0;
|
|
|
|
|
|
|
|
PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
|
|
|
|
unsigned CallerMinReservedArea = FI->getMinReservedArea();
|
|
|
|
int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
|
|
|
|
// Remember only if the new adjustement is bigger.
|
|
|
|
if (SPDiff < FI->getTailCallSPDelta())
|
|
|
|
FI->setTailCallSPDelta(SPDiff);
|
|
|
|
|
|
|
|
return SPDiff;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// IsEligibleForTailCallElimination - Check to see whether the next instruction
|
|
|
|
/// following the call is a return. A function is eligible if caller/callee
|
|
|
|
/// calling conventions match, currently only fastcc supports tail calls, and
|
|
|
|
/// the function CALL is immediatly followed by a RET.
|
|
|
|
bool
|
|
|
|
PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
|
|
|
|
SDOperand Ret,
|
|
|
|
SelectionDAG& DAG) const {
|
|
|
|
// Variable argument functions are not supported.
|
|
|
|
if (!PerformTailCallOpt ||
|
|
|
|
cast<ConstantSDNode>(Call.getOperand(2))->getValue() != 0) return false;
|
|
|
|
|
|
|
|
if (CheckTailCallReturnConstraints(Call, Ret)) {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
unsigned CallerCC = MF.getFunction()->getCallingConv();
|
|
|
|
unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
|
|
|
|
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
|
|
|
|
// Functions containing by val parameters are not supported.
|
|
|
|
for (unsigned i = 0; i != ((Call.getNumOperands()-5)/2); i++) {
|
|
|
|
ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Call.getOperand(5+2*i+1))
|
|
|
|
->getArgFlags();
|
|
|
|
if (Flags.isByVal()) return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand Callee = Call.getOperand(4);
|
|
|
|
// Non PIC/GOT tail calls are supported.
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// At the moment we can only do local tail calls (in same module, hidden
|
|
|
|
// or protected) if we are generating PIC.
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
|
|
return G->getGlobal()->hasHiddenVisibility()
|
|
|
|
|| G->getGlobal()->hasProtectedVisibility();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-05-17 19:00:46 +00:00
|
|
|
/// isCallCompatibleAddress - Return the immediate to use if the specified
|
|
|
|
/// 32-bit value is representable in the immediate field of a BxA instruction.
|
|
|
|
static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
|
|
|
|
if (!C) return 0;
|
|
|
|
|
|
|
|
int Addr = C->getValue();
|
|
|
|
if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
|
|
|
|
(Addr << 6 >> 6) != Addr)
|
|
|
|
return 0; // Top 6 bits have to be sext of immediate.
|
|
|
|
|
2007-10-22 19:46:19 +00:00
|
|
|
return DAG.getConstant((int)C->getValue() >> 2,
|
|
|
|
DAG.getTargetLoweringInfo().getPointerTy()).Val;
|
2006-05-17 19:00:46 +00:00
|
|
|
}
|
|
|
|
|
2008-05-13 00:00:25 +00:00
|
|
|
namespace {
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
struct TailCallArgumentInfo {
|
|
|
|
SDOperand Arg;
|
|
|
|
SDOperand FrameIdxOp;
|
|
|
|
int FrameIdx;
|
|
|
|
|
|
|
|
TailCallArgumentInfo() : FrameIdx(0) {}
|
|
|
|
};
|
|
|
|
|
2008-05-13 00:00:25 +00:00
|
|
|
}
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
|
|
|
|
static void
|
|
|
|
StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
|
|
|
|
SDOperand Chain,
|
|
|
|
const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
|
|
|
|
SmallVector<SDOperand, 8> &MemOpChains) {
|
|
|
|
for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
|
|
|
|
SDOperand Arg = TailCallArgs[i].Arg;
|
|
|
|
SDOperand FIN = TailCallArgs[i].FrameIdxOp;
|
|
|
|
int FI = TailCallArgs[i].FrameIdx;
|
|
|
|
// Store relative to framepointer.
|
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
|
2008-07-11 22:44:52 +00:00
|
|
|
PseudoSourceValue::getFixedStack(FI),
|
|
|
|
0));
|
2008-04-30 09:16:33 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
|
|
|
|
/// the appropriate stack slot for the tail call optimized function call.
|
|
|
|
static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
|
|
|
|
MachineFunction &MF,
|
|
|
|
SDOperand Chain,
|
|
|
|
SDOperand OldRetAddr,
|
|
|
|
SDOperand OldFP,
|
|
|
|
int SPDiff,
|
|
|
|
bool isPPC64,
|
|
|
|
bool isMachoABI) {
|
|
|
|
if (SPDiff) {
|
|
|
|
// Calculate the new stack slot for the return address.
|
|
|
|
int SlotSize = isPPC64 ? 8 : 4;
|
|
|
|
int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
|
|
|
|
isMachoABI);
|
|
|
|
int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
|
|
|
|
NewRetAddrLoc);
|
|
|
|
int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
|
|
|
|
isMachoABI);
|
|
|
|
int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
|
|
|
|
Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
|
2008-07-11 22:44:52 +00:00
|
|
|
PseudoSourceValue::getFixedStack(NewRetAddr), 0);
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
|
|
|
|
Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
|
2008-07-11 22:44:52 +00:00
|
|
|
PseudoSourceValue::getFixedStack(NewFPIdx), 0);
|
2008-04-30 09:16:33 +00:00
|
|
|
}
|
|
|
|
return Chain;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
|
|
|
|
/// the position of the argument.
|
|
|
|
static void
|
|
|
|
CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
|
|
|
|
SDOperand Arg, int SPDiff, unsigned ArgOffset,
|
|
|
|
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
|
|
|
|
int Offset = ArgOffset + SPDiff;
|
2008-06-06 12:08:01 +00:00
|
|
|
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
|
2008-04-30 09:16:33 +00:00
|
|
|
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI, VT);
|
|
|
|
TailCallArgumentInfo Info;
|
|
|
|
Info.Arg = Arg;
|
|
|
|
Info.FrameIdxOp = FIN;
|
|
|
|
Info.FrameIdx = FI;
|
|
|
|
TailCallArguments.push_back(Info);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
|
|
|
|
/// stack slot. Returns the chain as result and the loaded frame pointers in
|
|
|
|
/// LROpOut/FPOpout. Used when tail calling.
|
|
|
|
SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
|
|
|
|
int SPDiff,
|
|
|
|
SDOperand Chain,
|
|
|
|
SDOperand &LROpOut,
|
|
|
|
SDOperand &FPOpOut) {
|
|
|
|
if (SPDiff) {
|
|
|
|
// Load the LR and FP stack slot for later adjusting.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
|
2008-04-30 09:16:33 +00:00
|
|
|
LROpOut = getReturnAddrFrameIndex(DAG);
|
|
|
|
LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
|
|
|
|
Chain = SDOperand(LROpOut.Val, 1);
|
|
|
|
FPOpOut = getFramePointerFrameIndex(DAG);
|
|
|
|
FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
|
|
|
|
Chain = SDOperand(FPOpOut.Val, 1);
|
|
|
|
}
|
|
|
|
return Chain;
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
|
|
|
|
/// by "Src" to address "Dst" of size "Size". Alignment information is
|
|
|
|
/// specified by the specific parameter attribute. The copy will be passed as
|
|
|
|
/// a byval function parameter.
|
|
|
|
/// Sometimes what we are copying is the end of a larger object, the part that
|
|
|
|
/// does not fit in registers.
|
|
|
|
static SDOperand
|
|
|
|
CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
|
2008-03-21 09:14:45 +00:00
|
|
|
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
|
|
|
|
unsigned Size) {
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
|
|
|
SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
|
|
|
|
return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
|
|
|
|
NULL, 0, NULL, 0);
|
2008-03-04 23:17:14 +00:00
|
|
|
}
|
2007-02-25 05:34:32 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
|
|
|
|
/// tail calls.
|
|
|
|
static void
|
|
|
|
LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain,
|
|
|
|
SDOperand Arg, SDOperand PtrOff, int SPDiff,
|
|
|
|
unsigned ArgOffset, bool isPPC64, bool isTailCall,
|
|
|
|
bool isVector, SmallVector<SDOperand, 8> &MemOpChains,
|
|
|
|
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2008-04-30 09:16:33 +00:00
|
|
|
if (!isTailCall) {
|
|
|
|
if (isVector) {
|
|
|
|
SDOperand StackPtr;
|
|
|
|
if (isPPC64)
|
|
|
|
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
|
|
|
|
else
|
|
|
|
StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
|
|
|
|
DAG.getConstant(ArgOffset, PtrVT));
|
|
|
|
}
|
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
|
|
|
|
// Calculate and remember argument location.
|
|
|
|
} else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
|
|
|
|
TailCallArguments);
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
|
2008-03-19 21:39:28 +00:00
|
|
|
const PPCSubtarget &Subtarget,
|
|
|
|
TargetMachine &TM) {
|
2007-02-25 05:34:32 +00:00
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
2008-04-30 09:16:33 +00:00
|
|
|
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
|
|
|
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 &&
|
|
|
|
CC == CallingConv::Fast && PerformTailCallOpt;
|
2007-02-25 05:34:32 +00:00
|
|
|
SDOperand Callee = Op.getOperand(4);
|
|
|
|
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
|
|
|
|
|
|
|
|
bool isMachoABI = Subtarget.isMachoABI();
|
2007-04-03 12:35:28 +00:00
|
|
|
bool isELF32_ABI = Subtarget.isELF32_ABI();
|
2006-05-25 00:57:32 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-06-26 22:48:35 +00:00
|
|
|
bool isPPC64 = PtrVT == MVT::i64;
|
|
|
|
unsigned PtrByteSize = isPPC64 ? 8 : 4;
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
|
2006-05-16 22:56:08 +00:00
|
|
|
// args_to_use will accumulate outgoing args for the PPCISD::CALL case in
|
|
|
|
// SelectExpr to use to put the arguments in the appropriate registers.
|
|
|
|
std::vector<SDOperand> args_to_use;
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
// Mark this function as potentially containing a function that contains a
|
|
|
|
// tail call. As a consequence the frame pointer will be used for dynamicalloc
|
|
|
|
// and restoring the callers stack pointer in this functions epilog. This is
|
|
|
|
// done because by tail calling the called function might overwrite the value
|
|
|
|
// in this function's (MF) stack pointer stack slot 0(SP).
|
|
|
|
if (PerformTailCallOpt && CC==CallingConv::Fast)
|
|
|
|
MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
|
|
|
|
|
|
|
|
unsigned nAltivecParamsAtEnd = 0;
|
|
|
|
|
2006-05-16 22:56:08 +00:00
|
|
|
// Count how many bytes are to be pushed on the stack, including the linkage
|
2006-06-26 22:48:35 +00:00
|
|
|
// area, and parameter passing area. We start with 24/48 bytes, which is
|
2006-05-17 00:15:40 +00:00
|
|
|
// prereserved space for [SP][CR][LR][3 x unused].
|
2008-04-30 09:16:33 +00:00
|
|
|
unsigned NumBytes =
|
|
|
|
CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
|
|
|
|
Op, nAltivecParamsAtEnd);
|
2006-05-16 23:54:25 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
// Calculate by how many bytes the stack has to be adjusted in case of tail
|
|
|
|
// call optimization.
|
|
|
|
int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
|
2006-05-17 00:15:40 +00:00
|
|
|
|
|
|
|
// Adjust the stack pointer for the new arguments...
|
|
|
|
// These operations are automatically eliminated by the prolog/epilog pass
|
|
|
|
Chain = DAG.getCALLSEQ_START(Chain,
|
2006-06-26 22:48:35 +00:00
|
|
|
DAG.getConstant(NumBytes, PtrVT));
|
2008-03-05 23:31:27 +00:00
|
|
|
SDOperand CallSeqStart = Chain;
|
2006-05-17 00:15:40 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
// Load the return address and frame pointer so it can be move somewhere else
|
|
|
|
// later.
|
|
|
|
SDOperand LROp, FPOp;
|
|
|
|
Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
|
|
|
|
|
2006-05-17 00:15:40 +00:00
|
|
|
// Set up a copy of the stack pointer for use loading and storing any
|
|
|
|
// arguments that may not fit in the registers available for argument
|
|
|
|
// passing.
|
2006-06-26 22:48:35 +00:00
|
|
|
SDOperand StackPtr;
|
|
|
|
if (isPPC64)
|
|
|
|
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
|
|
|
|
else
|
|
|
|
StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
|
2006-05-17 00:15:40 +00:00
|
|
|
|
|
|
|
// Figure out which arguments are going to go in registers, and which in
|
|
|
|
// memory. Also, if this is a vararg function, floating point operations
|
|
|
|
// must be stored to our stack, and loaded into integer regs as well, if
|
|
|
|
// any integer regs are available for argument passing.
|
2007-02-25 05:34:32 +00:00
|
|
|
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
|
2006-05-17 06:01:33 +00:00
|
|
|
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2006-06-26 22:48:35 +00:00
|
|
|
static const unsigned GPR_32[] = { // 32-bit registers.
|
2006-05-17 06:01:33 +00:00
|
|
|
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
|
|
|
|
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
|
|
|
|
};
|
2006-06-26 22:48:35 +00:00
|
|
|
static const unsigned GPR_64[] = { // 64-bit registers.
|
|
|
|
PPC::X3, PPC::X4, PPC::X5, PPC::X6,
|
|
|
|
PPC::X7, PPC::X8, PPC::X9, PPC::X10,
|
|
|
|
};
|
2007-02-25 05:34:32 +00:00
|
|
|
static const unsigned *FPR = GetFPR(Subtarget);
|
|
|
|
|
2006-05-17 06:01:33 +00:00
|
|
|
static const unsigned VR[] = {
|
|
|
|
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
|
|
|
|
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
|
|
|
|
};
|
2007-09-07 04:06:50 +00:00
|
|
|
const unsigned NumGPRs = array_lengthof(GPR_32);
|
2007-04-03 10:27:07 +00:00
|
|
|
const unsigned NumFPRs = isMachoABI ? 13 : 8;
|
2007-09-07 04:06:50 +00:00
|
|
|
const unsigned NumVRs = array_lengthof( VR);
|
2006-05-17 06:01:33 +00:00
|
|
|
|
2006-06-26 22:48:35 +00:00
|
|
|
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
|
|
|
|
|
2006-05-17 06:01:33 +00:00
|
|
|
std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
|
2008-04-30 09:16:33 +00:00
|
|
|
SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
|
|
|
|
|
2006-08-11 17:38:39 +00:00
|
|
|
SmallVector<SDOperand, 8> MemOpChains;
|
2006-05-25 00:57:32 +00:00
|
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
2007-02-25 05:34:32 +00:00
|
|
|
bool inMem = false;
|
2006-05-25 00:57:32 +00:00
|
|
|
SDOperand Arg = Op.getOperand(5+2*i);
|
2008-03-21 09:14:45 +00:00
|
|
|
ISD::ArgFlagsTy Flags =
|
|
|
|
cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
|
2007-03-13 15:02:46 +00:00
|
|
|
// See if next argument requires stack alignment in ELF
|
2008-04-15 08:08:50 +00:00
|
|
|
bool Align = Flags.isSplit();
|
2007-03-13 15:02:46 +00:00
|
|
|
|
2006-05-17 00:15:40 +00:00
|
|
|
// PtrOff will be used to store the current argument to the stack if a
|
|
|
|
// register cannot be found for it.
|
2007-03-13 15:02:46 +00:00
|
|
|
SDOperand PtrOff;
|
|
|
|
|
2007-04-03 12:35:28 +00:00
|
|
|
// Stack align in ELF 32
|
2008-04-13 13:40:22 +00:00
|
|
|
if (isELF32_ABI && Align)
|
2007-03-13 15:02:46 +00:00
|
|
|
PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
|
|
|
|
StackPtr.getValueType());
|
|
|
|
else
|
|
|
|
PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
|
|
|
|
|
2006-06-26 22:48:35 +00:00
|
|
|
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
|
|
|
|
|
|
|
|
// On PPC64, promote integers to 64-bit values.
|
|
|
|
if (isPPC64 && Arg.getValueType() == MVT::i32) {
|
2008-03-21 09:14:45 +00:00
|
|
|
// FIXME: Should this use ANY_EXTEND if neither sext nor zext?
|
|
|
|
unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
|
2006-06-26 22:48:35 +00:00
|
|
|
Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
|
|
|
|
}
|
2008-03-04 23:17:14 +00:00
|
|
|
|
|
|
|
// FIXME Elf untested, what are alignment rules?
|
2008-03-07 20:27:40 +00:00
|
|
|
// FIXME memcpy is used way more than necessary. Correctness first.
|
2008-03-21 09:14:45 +00:00
|
|
|
if (Flags.isByVal()) {
|
|
|
|
unsigned Size = Flags.getByValSize();
|
2008-04-13 13:40:22 +00:00
|
|
|
if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
|
2008-03-07 20:27:40 +00:00
|
|
|
if (Size==1 || Size==2) {
|
|
|
|
// Very small objects are passed right-justified.
|
|
|
|
// Everything else is passed left-justified.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
|
2008-03-07 20:27:40 +00:00
|
|
|
if (GPR_idx != NumGPRs) {
|
|
|
|
SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
|
|
|
|
NULL, 0, VT);
|
|
|
|
MemOpChains.push_back(Load.getValue(1));
|
|
|
|
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
|
|
|
|
if (isMachoABI)
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
} else {
|
|
|
|
SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
|
|
|
|
SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
|
|
|
|
SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
|
|
|
|
CallSeqStart.Val->getOperand(0),
|
|
|
|
Flags, DAG, Size);
|
|
|
|
// This must go outside the CALLSEQ_START..END.
|
|
|
|
SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
|
|
|
|
CallSeqStart.Val->getOperand(1));
|
|
|
|
DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
|
|
|
|
Chain = CallSeqStart = NewCallSeqStart;
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
2008-03-17 02:13:43 +00:00
|
|
|
// Copy entire object into memory. There are cases where gcc-generated
|
|
|
|
// code assumes it is there, even if it could be put entirely into
|
|
|
|
// registers. (This is not what the doc says.)
|
|
|
|
SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
|
|
|
|
CallSeqStart.Val->getOperand(0),
|
|
|
|
Flags, DAG, Size);
|
|
|
|
// This must go outside the CALLSEQ_START..END.
|
|
|
|
SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
|
|
|
|
CallSeqStart.Val->getOperand(1));
|
|
|
|
DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
|
|
|
|
Chain = CallSeqStart = NewCallSeqStart;
|
|
|
|
// And copy the pieces of it that fit into registers.
|
2008-03-04 23:17:14 +00:00
|
|
|
for (unsigned j=0; j<Size; j+=PtrByteSize) {
|
|
|
|
SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
|
|
|
|
SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
|
|
|
|
if (GPR_idx != NumGPRs) {
|
|
|
|
SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
|
2008-03-05 23:31:27 +00:00
|
|
|
MemOpChains.push_back(Load.getValue(1));
|
2008-03-04 23:17:14 +00:00
|
|
|
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
|
|
|
|
if (isMachoABI)
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
} else {
|
2008-03-17 02:13:43 +00:00
|
|
|
ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
|
2008-03-07 20:27:40 +00:00
|
|
|
break;
|
2008-03-04 23:17:14 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (Arg.getValueType().getSimpleVT()) {
|
2006-05-17 00:15:40 +00:00
|
|
|
default: assert(0 && "Unexpected ValueType for argument!");
|
|
|
|
case MVT::i32:
|
2006-06-26 22:48:35 +00:00
|
|
|
case MVT::i64:
|
2007-03-13 15:02:46 +00:00
|
|
|
// Double word align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
|
2006-05-17 06:01:33 +00:00
|
|
|
if (GPR_idx != NumGPRs) {
|
|
|
|
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
|
2006-05-17 00:15:40 +00:00
|
|
|
} else {
|
2008-04-30 09:16:33 +00:00
|
|
|
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
|
|
|
|
isPPC64, isTailCall, false, MemOpChains,
|
|
|
|
TailCallArguments);
|
2007-02-25 05:34:32 +00:00
|
|
|
inMem = true;
|
2006-05-17 00:15:40 +00:00
|
|
|
}
|
2007-03-13 15:02:46 +00:00
|
|
|
if (inMem || isMachoABI) {
|
|
|
|
// Stack align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (isELF32_ABI && Align)
|
2007-03-13 15:02:46 +00:00
|
|
|
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
|
|
|
|
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
}
|
2006-05-17 00:15:40 +00:00
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64:
|
2006-05-17 06:01:33 +00:00
|
|
|
if (FPR_idx != NumFPRs) {
|
|
|
|
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
|
|
|
|
|
2006-05-17 00:15:40 +00:00
|
|
|
if (isVarArg) {
|
2006-10-13 21:14:26 +00:00
|
|
|
SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
|
2006-05-17 06:01:33 +00:00
|
|
|
MemOpChains.push_back(Store);
|
|
|
|
|
2006-05-17 00:15:40 +00:00
|
|
|
// Float varargs are always shadowed in available integer registers
|
2006-05-17 06:01:33 +00:00
|
|
|
if (GPR_idx != NumGPRs) {
|
2006-10-09 20:57:25 +00:00
|
|
|
SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
|
2006-05-17 06:01:33 +00:00
|
|
|
MemOpChains.push_back(Load.getValue(1));
|
2007-02-25 05:34:32 +00:00
|
|
|
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
|
|
|
|
Load));
|
2006-05-17 00:15:40 +00:00
|
|
|
}
|
2006-12-01 16:30:47 +00:00
|
|
|
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
|
2006-05-17 00:15:40 +00:00
|
|
|
SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
|
2006-06-26 22:48:35 +00:00
|
|
|
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
|
2006-10-09 20:57:25 +00:00
|
|
|
SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
|
2006-05-17 06:01:33 +00:00
|
|
|
MemOpChains.push_back(Load.getValue(1));
|
2007-02-25 05:34:32 +00:00
|
|
|
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
|
|
|
|
Load));
|
2006-05-16 22:56:08 +00:00
|
|
|
}
|
|
|
|
} else {
|
2006-05-17 00:15:40 +00:00
|
|
|
// If we have any FPRs remaining, we may also have GPRs remaining.
|
|
|
|
// Args passed in FPRs consume either 1 (f32) or 2 (f64) available
|
|
|
|
// GPRs.
|
2007-02-25 05:34:32 +00:00
|
|
|
if (isMachoABI) {
|
|
|
|
if (GPR_idx != NumGPRs)
|
|
|
|
++GPR_idx;
|
|
|
|
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
|
|
|
|
!isPPC64) // PPC64 has 64-bit GPR's obviously :)
|
|
|
|
++GPR_idx;
|
|
|
|
}
|
2006-05-16 22:56:08 +00:00
|
|
|
}
|
2006-05-17 00:15:40 +00:00
|
|
|
} else {
|
2008-04-30 09:16:33 +00:00
|
|
|
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
|
|
|
|
isPPC64, isTailCall, false, MemOpChains,
|
|
|
|
TailCallArguments);
|
2007-02-25 05:34:32 +00:00
|
|
|
inMem = true;
|
|
|
|
}
|
|
|
|
if (inMem || isMachoABI) {
|
2007-03-13 15:02:46 +00:00
|
|
|
// Stack align in ELF
|
2008-04-13 13:40:22 +00:00
|
|
|
if (isELF32_ABI && Align)
|
2007-03-13 15:02:46 +00:00
|
|
|
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
|
2007-02-25 05:34:32 +00:00
|
|
|
if (isPPC64)
|
|
|
|
ArgOffset += 8;
|
|
|
|
else
|
|
|
|
ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
|
2006-05-16 22:56:08 +00:00
|
|
|
}
|
2006-05-17 00:15:40 +00:00
|
|
|
break;
|
|
|
|
case MVT::v4f32:
|
|
|
|
case MVT::v4i32:
|
|
|
|
case MVT::v8i16:
|
|
|
|
case MVT::v16i8:
|
2008-03-12 00:22:17 +00:00
|
|
|
if (isVarArg) {
|
|
|
|
// These go aligned on the stack, or in the corresponding R registers
|
|
|
|
// when within range. The Darwin PPC ABI doc claims they also go in
|
|
|
|
// V registers; in fact gcc does this only for arguments that are
|
|
|
|
// prototyped, not for those that match the ... We do it for all
|
|
|
|
// arguments, seems to work.
|
|
|
|
while (ArgOffset % 16 !=0) {
|
|
|
|
ArgOffset += PtrByteSize;
|
|
|
|
if (GPR_idx != NumGPRs)
|
|
|
|
GPR_idx++;
|
|
|
|
}
|
|
|
|
// We could elide this store in the case where the object fits
|
|
|
|
// entirely in R registers. Maybe later.
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
|
|
|
|
DAG.getConstant(ArgOffset, PtrVT));
|
|
|
|
SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
|
|
|
|
MemOpChains.push_back(Store);
|
|
|
|
if (VR_idx != NumVRs) {
|
|
|
|
SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
|
|
|
|
MemOpChains.push_back(Load.getValue(1));
|
|
|
|
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
|
|
|
|
}
|
|
|
|
ArgOffset += 16;
|
|
|
|
for (unsigned i=0; i<16; i+=PtrByteSize) {
|
|
|
|
if (GPR_idx == NumGPRs)
|
|
|
|
break;
|
|
|
|
SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
|
|
|
|
DAG.getConstant(i, PtrVT));
|
|
|
|
SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
|
|
|
|
MemOpChains.push_back(Load.getValue(1));
|
|
|
|
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2008-04-30 09:16:33 +00:00
|
|
|
|
2008-03-14 17:41:26 +00:00
|
|
|
// Non-varargs Altivec params generally go in registers, but have
|
|
|
|
// stack space allocated at the end.
|
|
|
|
if (VR_idx != NumVRs) {
|
|
|
|
// Doesn't have GPR space allocated.
|
|
|
|
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
|
|
|
|
} else if (nAltivecParamsAtEnd==0) {
|
|
|
|
// We are emitting Altivec params in order.
|
2008-04-30 09:16:33 +00:00
|
|
|
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
|
|
|
|
isPPC64, isTailCall, true, MemOpChains,
|
|
|
|
TailCallArguments);
|
2008-03-12 00:22:17 +00:00
|
|
|
ArgOffset += 16;
|
|
|
|
}
|
2006-05-17 00:15:40 +00:00
|
|
|
break;
|
2006-05-16 22:56:08 +00:00
|
|
|
}
|
|
|
|
}
|
2008-03-14 17:41:26 +00:00
|
|
|
// If all Altivec parameters fit in registers, as they usually do,
|
|
|
|
// they get stack space following the non-Altivec parameters. We
|
|
|
|
// don't track this here because nobody below needs it.
|
|
|
|
// If there are more Altivec parameters than fit in registers emit
|
|
|
|
// the stores here.
|
|
|
|
if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
|
|
|
|
unsigned j = 0;
|
|
|
|
// Offset is aligned; skip 1st 12 params which go in V registers.
|
|
|
|
ArgOffset = ((ArgOffset+15)/16)*16;
|
|
|
|
ArgOffset += 12*16;
|
|
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
|
|
|
SDOperand Arg = Op.getOperand(5+2*i);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ArgType = Arg.getValueType();
|
2008-03-14 17:41:26 +00:00
|
|
|
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
|
|
|
|
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
|
|
|
|
if (++j > NumVRs) {
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand PtrOff;
|
|
|
|
// We are emitting Altivec params in order.
|
|
|
|
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
|
|
|
|
isPPC64, isTailCall, true, MemOpChains,
|
|
|
|
TailCallArguments);
|
2008-03-14 17:41:26 +00:00
|
|
|
ArgOffset += 16;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-17 06:01:33 +00:00
|
|
|
if (!MemOpChains.empty())
|
2006-08-11 17:38:39 +00:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&MemOpChains[0], MemOpChains.size());
|
2006-05-17 06:01:33 +00:00
|
|
|
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
|
|
// and flag operands which copy the outgoing args into the appropriate regs.
|
|
|
|
SDOperand InFlag;
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
|
|
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
|
|
|
|
InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
2007-02-25 05:34:32 +00:00
|
|
|
|
2007-04-03 12:35:28 +00:00
|
|
|
// With the ELF 32 ABI, set CR6 to true if this is a vararg call.
|
|
|
|
if (isVarArg && isELF32_ABI) {
|
2008-03-10 14:12:10 +00:00
|
|
|
SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
|
2007-02-25 05:34:32 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
// Emit a sequence of copyto/copyfrom virtual registers for arguments that
|
|
|
|
// might overwrite each other in case of tail call optimization.
|
|
|
|
if (isTailCall) {
|
|
|
|
SmallVector<SDOperand, 8> MemOpChains2;
|
|
|
|
// Do not flag preceeding copytoreg stuff together with the following stuff.
|
|
|
|
InFlag = SDOperand();
|
|
|
|
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
|
|
|
|
MemOpChains2);
|
|
|
|
if (!MemOpChains2.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&MemOpChains2[0], MemOpChains2.size());
|
|
|
|
|
|
|
|
// Store the return address to the appropriate stack slot.
|
|
|
|
Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
|
|
|
|
isPPC64, isMachoABI);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit callseq_end just before tailcall node.
|
|
|
|
if (isTailCall) {
|
|
|
|
SmallVector<SDOperand, 8> CallSeqOps;
|
|
|
|
SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
|
|
CallSeqOps.push_back(Chain);
|
|
|
|
CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
|
|
|
|
CallSeqOps.push_back(DAG.getIntPtrConstant(0));
|
|
|
|
if (InFlag.Val)
|
|
|
|
CallSeqOps.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
|
|
|
|
CallSeqOps.size());
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
std::vector<MVT> NodeTys;
|
2006-06-10 01:14:28 +00:00
|
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
|
|
|
2006-08-11 17:18:05 +00:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2007-02-27 13:01:19 +00:00
|
|
|
unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
|
2006-05-17 19:00:46 +00:00
|
|
|
|
|
|
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
|
|
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
|
|
|
// node so that legalize doesn't hack it.
|
2007-12-21 12:22:29 +00:00
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
|
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
|
2006-05-17 19:00:46 +00:00
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
|
|
|
|
else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
|
|
|
|
// If this is an absolute destination address, use the munged value.
|
|
|
|
Callee = SDOperand(Dest, 0);
|
|
|
|
else {
|
|
|
|
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
|
|
|
|
// to do the call, we can't use PPCISD::CALL.
|
2006-08-11 17:18:05 +00:00
|
|
|
SDOperand MTCTROps[] = {Chain, Callee, InFlag};
|
|
|
|
Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
|
2006-05-17 19:00:46 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2008-03-09 20:49:33 +00:00
|
|
|
// Copy the callee address into R12/X12 on darwin.
|
2007-02-25 05:34:32 +00:00
|
|
|
if (isMachoABI) {
|
2008-03-09 20:49:33 +00:00
|
|
|
unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
|
|
|
|
Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
|
2007-02-25 05:34:32 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
2006-05-17 06:01:33 +00:00
|
|
|
|
2006-05-17 19:00:46 +00:00
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::Other);
|
|
|
|
NodeTys.push_back(MVT::Flag);
|
|
|
|
Ops.push_back(Chain);
|
2007-02-25 05:34:32 +00:00
|
|
|
CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
|
2006-05-17 19:00:46 +00:00
|
|
|
Callee.Val = 0;
|
2008-04-30 09:16:33 +00:00
|
|
|
// Add CTR register as callee so a bctr can be emitted later.
|
|
|
|
if (isTailCall)
|
|
|
|
Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
|
2006-05-17 19:00:46 +00:00
|
|
|
}
|
|
|
|
|
2006-06-10 01:14:28 +00:00
|
|
|
// If this is a direct call, pass the chain and the callee.
|
2006-05-17 19:00:46 +00:00
|
|
|
if (Callee.Val) {
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
}
|
2008-04-30 09:16:33 +00:00
|
|
|
// If this is a tail call add stack pointer delta.
|
|
|
|
if (isTailCall)
|
|
|
|
Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
|
|
|
|
|
2006-06-10 01:14:28 +00:00
|
|
|
// Add argument registers to the end of the list so that they are known live
|
|
|
|
// into the call.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second.getValueType()));
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
// When performing tail call optimization the callee pops its arguments off
|
|
|
|
// the stack. Account for this here so these bytes can be pushed back on in
|
|
|
|
// PPCRegisterInfo::eliminateCallFramePseudoInstr.
|
|
|
|
int BytesCalleePops =
|
|
|
|
(CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
|
|
|
|
|
2006-06-10 01:14:28 +00:00
|
|
|
if (InFlag.Val)
|
|
|
|
Ops.push_back(InFlag);
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
// Emit tail call.
|
|
|
|
if (isTailCall) {
|
|
|
|
assert(InFlag.Val &&
|
|
|
|
"Flag must be set. Depend on flag being set in LowerRET");
|
|
|
|
Chain = DAG.getNode(PPCISD::TAILCALL,
|
|
|
|
Op.Val->getVTList(), &Ops[0], Ops.size());
|
|
|
|
return SDOperand(Chain.Val, Op.ResNo);
|
|
|
|
}
|
|
|
|
|
2006-08-11 17:18:05 +00:00
|
|
|
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
|
2006-06-10 01:14:28 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2007-11-13 00:44:25 +00:00
|
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
|
|
DAG.getConstant(NumBytes, PtrVT),
|
2008-04-30 09:16:33 +00:00
|
|
|
DAG.getConstant(BytesCalleePops, PtrVT),
|
2007-11-13 00:44:25 +00:00
|
|
|
InFlag);
|
|
|
|
if (Op.Val->getValueType(0) != MVT::Other)
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2008-03-19 21:39:28 +00:00
|
|
|
SmallVector<SDOperand, 16> ResultVals;
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2008-04-30 09:16:33 +00:00
|
|
|
unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
|
|
CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
|
2008-03-19 21:39:28 +00:00
|
|
|
CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC);
|
2006-05-17 06:01:33 +00:00
|
|
|
|
2008-03-19 21:39:28 +00:00
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
|
|
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = RVLocs[i];
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = VA.getValVT();
|
2008-03-19 21:39:28 +00:00
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
|
|
|
|
ResultVals.push_back(Chain.getValue(0));
|
|
|
|
InFlag = Chain.getValue(2);
|
2006-05-17 06:01:33 +00:00
|
|
|
}
|
2008-03-19 21:39:28 +00:00
|
|
|
|
2006-05-17 19:00:46 +00:00
|
|
|
// If the function returns void, just return the chain.
|
2008-03-19 21:39:28 +00:00
|
|
|
if (RVLocs.empty())
|
2006-05-17 19:00:46 +00:00
|
|
|
return Chain;
|
|
|
|
|
|
|
|
// Otherwise, merge everything together with a MERGE_VALUES node.
|
2008-03-19 21:39:28 +00:00
|
|
|
ResultVals.push_back(Chain);
|
2008-06-30 10:19:09 +00:00
|
|
|
SDOperand Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
|
|
|
|
ResultVals.size());
|
2006-05-16 22:56:08 +00:00
|
|
|
return Res.getValue(Op.ResNo);
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
|
|
|
|
TargetMachine &TM) {
|
2007-03-06 00:59:59 +00:00
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
2007-06-19 00:13:10 +00:00
|
|
|
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
|
|
|
|
CCState CCInfo(CC, isVarArg, TM, RVLocs);
|
2007-03-06 00:59:59 +00:00
|
|
|
CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
|
|
|
|
|
|
|
|
// If this is the first return lowered for this function, add the regs to the
|
|
|
|
// liveout set for the function.
|
2007-12-31 04:13:23 +00:00
|
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
2007-03-06 00:59:59 +00:00
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
2007-12-31 04:13:23 +00:00
|
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
2007-03-06 00:59:59 +00:00
|
|
|
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
|
|
|
|
if (Chain.getOpcode() == PPCISD::TAILCALL) {
|
|
|
|
SDOperand TailCall = Chain;
|
|
|
|
SDOperand TargetAddress = TailCall.getOperand(1);
|
|
|
|
SDOperand StackAdjustment = TailCall.getOperand(2);
|
|
|
|
|
|
|
|
assert(((TargetAddress.getOpcode() == ISD::Register &&
|
|
|
|
cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
|
|
|
|
TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
|
|
|
|
TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
|
|
|
|
isa<ConstantSDNode>(TargetAddress)) &&
|
|
|
|
"Expecting an global address, external symbol, absolute value or register");
|
|
|
|
|
|
|
|
assert(StackAdjustment.getOpcode() == ISD::Constant &&
|
|
|
|
"Expecting a const value");
|
|
|
|
|
|
|
|
SmallVector<SDOperand,8> Operands;
|
|
|
|
Operands.push_back(Chain.getOperand(0));
|
|
|
|
Operands.push_back(TargetAddress);
|
|
|
|
Operands.push_back(StackAdjustment);
|
|
|
|
// Copy registers used by the call. Last operand is a flag so it is not
|
|
|
|
// copied.
|
|
|
|
for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
|
|
|
|
Operands.push_back(Chain.getOperand(i));
|
|
|
|
}
|
|
|
|
return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0],
|
|
|
|
Operands.size());
|
|
|
|
}
|
|
|
|
|
2007-03-06 00:59:59 +00:00
|
|
|
SDOperand Flag;
|
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
|
|
|
|
Flag = Chain.getValue(1);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
2007-03-06 00:59:59 +00:00
|
|
|
|
|
|
|
if (Flag.Val)
|
|
|
|
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
|
|
|
|
else
|
|
|
|
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
|
2006-12-04 22:04:42 +00:00
|
|
|
const PPCSubtarget &Subtarget) {
|
|
|
|
// When we pop the dynamic allocation we need to restore the SP link.
|
|
|
|
|
|
|
|
// Get the corect type for pointers.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-12-04 22:04:42 +00:00
|
|
|
|
|
|
|
// Construct the stack pointer operand.
|
|
|
|
bool IsPPC64 = Subtarget.isPPC64();
|
|
|
|
unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
|
|
|
|
SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
|
|
|
|
|
|
|
|
// Get the operands for the STACKRESTORE.
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand SaveSP = Op.getOperand(1);
|
|
|
|
|
|
|
|
// Load the old link SP.
|
|
|
|
SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
|
|
|
|
|
|
|
|
// Restore the stack pointer.
|
|
|
|
Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
|
|
|
|
|
|
|
|
// Store the old link SP.
|
|
|
|
return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
|
|
|
|
}
|
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
|
2006-11-16 22:43:37 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2008-04-30 09:16:33 +00:00
|
|
|
bool IsPPC64 = PPCSubTarget.isPPC64();
|
|
|
|
bool isMachoABI = PPCSubTarget.isMachoABI();
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2008-04-30 09:16:33 +00:00
|
|
|
|
|
|
|
// Get current frame pointer save index. The users of this index will be
|
|
|
|
// primarily DYNALLOC instructions.
|
|
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
int RASI = FI->getReturnAddrSaveIndex();
|
|
|
|
|
|
|
|
// If the frame pointer save index hasn't been defined yet.
|
|
|
|
if (!RASI) {
|
|
|
|
// Find out what the fix offset of the frame pointer save area.
|
|
|
|
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
|
|
|
|
// Allocate the frame index for frame pointer save area.
|
|
|
|
RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
|
|
|
|
// Save the result.
|
|
|
|
FI->setReturnAddrSaveIndex(RASI);
|
|
|
|
}
|
|
|
|
return DAG.getFrameIndex(RASI, PtrVT);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
bool IsPPC64 = PPCSubTarget.isPPC64();
|
|
|
|
bool isMachoABI = PPCSubTarget.isMachoABI();
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-11-16 22:43:37 +00:00
|
|
|
|
|
|
|
// Get current frame pointer save index. The users of this index will be
|
|
|
|
// primarily DYNALLOC instructions.
|
|
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
2008-04-30 09:16:33 +00:00
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
// If the frame pointer save index hasn't been defined yet.
|
|
|
|
if (!FPSI) {
|
|
|
|
// Find out what the fix offset of the frame pointer save area.
|
2007-02-25 05:34:32 +00:00
|
|
|
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
|
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
// Allocate the frame index for frame pointer save area.
|
2007-02-25 05:34:32 +00:00
|
|
|
FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
|
2006-11-16 22:43:37 +00:00
|
|
|
// Save the result.
|
|
|
|
FI->setFramePointerSaveIndex(FPSI);
|
|
|
|
}
|
2008-04-30 09:16:33 +00:00
|
|
|
return DAG.getFrameIndex(FPSI, PtrVT);
|
|
|
|
}
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
|
|
|
|
SelectionDAG &DAG,
|
|
|
|
const PPCSubtarget &Subtarget) {
|
2006-11-16 22:43:37 +00:00
|
|
|
// Get the inputs.
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand Size = Op.getOperand(1);
|
|
|
|
|
|
|
|
// Get the corect type for pointers.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-11-16 22:43:37 +00:00
|
|
|
// Negate the size.
|
|
|
|
SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
|
|
|
|
DAG.getConstant(0, PtrVT), Size);
|
|
|
|
// Construct a node for the frame pointer save index.
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand FPSIdx = getFramePointerFrameIndex(DAG);
|
2006-11-16 22:43:37 +00:00
|
|
|
// Build a DYNALLOC node.
|
|
|
|
SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
|
|
|
|
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
|
|
|
|
return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
|
|
|
|
}
|
|
|
|
|
2008-06-25 08:15:39 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.Val->getValueType(0);
|
2008-04-19 01:30:48 +00:00
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand Ptr = Op.getOperand(1);
|
|
|
|
SDOperand Incr = Op.getOperand(2);
|
|
|
|
|
2008-07-12 02:23:19 +00:00
|
|
|
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
|
2008-04-19 01:30:48 +00:00
|
|
|
SDOperand Ops[] = {
|
2008-07-12 02:23:19 +00:00
|
|
|
Chain,
|
|
|
|
Ptr,
|
|
|
|
Incr,
|
2008-04-19 01:30:48 +00:00
|
|
|
};
|
2008-07-12 02:23:19 +00:00
|
|
|
return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3);
|
2008-04-19 01:30:48 +00:00
|
|
|
}
|
|
|
|
|
2008-06-25 08:15:39 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.Val->getValueType(0);
|
2008-04-19 01:30:48 +00:00
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand Ptr = Op.getOperand(1);
|
|
|
|
SDOperand NewVal = Op.getOperand(2);
|
|
|
|
SDOperand OldVal = Op.getOperand(3);
|
|
|
|
|
2008-07-12 02:23:19 +00:00
|
|
|
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
|
2008-04-19 01:30:48 +00:00
|
|
|
SDOperand Ops[] = {
|
2008-07-12 02:23:19 +00:00
|
|
|
Chain,
|
|
|
|
Ptr,
|
|
|
|
OldVal,
|
|
|
|
NewVal,
|
2008-04-19 01:30:48 +00:00
|
|
|
};
|
2008-07-12 02:23:19 +00:00
|
|
|
return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4);
|
2008-04-19 01:30:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.Val->getValueType(0);
|
2008-04-19 01:30:48 +00:00
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
SDOperand Ptr = Op.getOperand(1);
|
|
|
|
SDOperand NewVal = Op.getOperand(2);
|
|
|
|
|
2008-07-12 02:23:19 +00:00
|
|
|
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
|
2008-04-19 01:30:48 +00:00
|
|
|
SDOperand Ops[] = {
|
2008-07-12 02:23:19 +00:00
|
|
|
Chain,
|
|
|
|
Ptr,
|
|
|
|
NewVal,
|
2008-04-19 01:30:48 +00:00
|
|
|
};
|
2008-07-12 02:23:19 +00:00
|
|
|
return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3);
|
2008-04-19 01:30:48 +00:00
|
|
|
}
|
2006-11-16 22:43:37 +00:00
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
|
|
|
|
/// possible.
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
|
2006-04-14 06:01:58 +00:00
|
|
|
// Not FP? Not a fsel.
|
2008-06-06 12:08:01 +00:00
|
|
|
if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
|
|
|
|
!Op.getOperand(2).getValueType().isFloatingPoint())
|
2006-04-14 06:01:58 +00:00
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
|
|
|
|
|
|
// Cannot handle SETEQ/SETNE.
|
|
|
|
if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ResVT = Op.getValueType();
|
|
|
|
MVT CmpVT = Op.getOperand(0).getValueType();
|
2006-04-14 06:01:58 +00:00
|
|
|
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
|
|
|
|
SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
|
|
|
|
|
|
|
|
// If the RHS of the comparison is a 0.0, we don't need to do the
|
|
|
|
// subtraction at all.
|
|
|
|
if (isFloatingPointZero(RHS))
|
|
|
|
switch (CC) {
|
|
|
|
default: break; // SETUO etc aren't handled by fsel.
|
|
|
|
case ISD::SETULT:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOLT:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETLT:
|
|
|
|
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
|
|
|
|
case ISD::SETUGE:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOGE:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETGE:
|
|
|
|
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
|
|
|
|
LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
|
|
|
|
return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
|
|
|
|
case ISD::SETUGT:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOGT:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETGT:
|
|
|
|
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
|
|
|
|
case ISD::SETULE:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOLE:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETLE:
|
|
|
|
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
|
|
|
|
LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
|
|
|
|
return DAG.getNode(PPCISD::FSEL, ResVT,
|
|
|
|
DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
|
|
|
|
}
|
|
|
|
|
2007-10-15 20:14:52 +00:00
|
|
|
SDOperand Cmp;
|
2006-04-14 06:01:58 +00:00
|
|
|
switch (CC) {
|
|
|
|
default: break; // SETUO etc aren't handled by fsel.
|
|
|
|
case ISD::SETULT:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOLT:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETLT:
|
|
|
|
Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
|
|
|
|
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
|
|
|
|
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
|
|
|
|
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
|
|
|
|
case ISD::SETUGE:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOGE:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETGE:
|
|
|
|
Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
|
|
|
|
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
|
|
|
|
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
|
|
|
|
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
|
|
|
|
case ISD::SETUGT:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOGT:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETGT:
|
|
|
|
Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
|
|
|
|
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
|
|
|
|
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
|
|
|
|
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
|
|
|
|
case ISD::SETULE:
|
2006-05-24 00:06:44 +00:00
|
|
|
case ISD::SETOLE:
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETLE:
|
|
|
|
Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
|
|
|
|
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
|
|
|
|
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
|
|
|
|
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
|
|
|
|
}
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2007-11-28 18:44:47 +00:00
|
|
|
// FIXME: Split this code up when LegalizeDAGTypes lands.
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
assert(Op.getOperand(0).getValueType().isFloatingPoint());
|
2006-04-14 06:01:58 +00:00
|
|
|
SDOperand Src = Op.getOperand(0);
|
|
|
|
if (Src.getValueType() == MVT::f32)
|
|
|
|
Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
|
2008-07-19 16:26:02 +00:00
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
SDOperand Tmp;
|
2008-06-06 12:08:01 +00:00
|
|
|
switch (Op.getValueType().getSimpleVT()) {
|
2006-04-14 06:01:58 +00:00
|
|
|
default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
|
|
|
|
case MVT::i32:
|
|
|
|
Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
|
|
|
|
break;
|
|
|
|
}
|
2008-07-19 16:26:02 +00:00
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
// Convert the FP value to an int value through memory.
|
2007-10-15 20:14:52 +00:00
|
|
|
SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
|
2008-07-19 16:26:02 +00:00
|
|
|
|
2007-10-15 20:14:52 +00:00
|
|
|
// Emit a store to the stack slot.
|
|
|
|
SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
|
|
|
|
|
|
|
|
// Result is a load from the stack slot. If loading 4 bytes, make sure to
|
|
|
|
// add in a bias.
|
2006-04-14 06:01:58 +00:00
|
|
|
if (Op.getValueType() == MVT::i32)
|
2007-10-15 20:14:52 +00:00
|
|
|
FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
|
|
|
|
DAG.getConstant(4, FIPtr.getValueType()));
|
|
|
|
return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2007-10-10 01:01:31 +00:00
|
|
|
assert(Op.getValueType() == MVT::ppcf128);
|
|
|
|
SDNode *Node = Op.Val;
|
|
|
|
assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
|
2007-10-19 04:08:28 +00:00
|
|
|
assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
|
2007-10-10 01:01:31 +00:00
|
|
|
SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
|
|
|
|
SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
|
|
|
|
|
|
|
|
// This sequence changes FPSCR to do round-to-zero, adds the two halves
|
|
|
|
// of the long double, and puts FPSCR back the way it was. We do not
|
|
|
|
// actually model FPSCR.
|
2008-06-06 12:08:01 +00:00
|
|
|
std::vector<MVT> NodeTys;
|
2007-10-10 01:01:31 +00:00
|
|
|
SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
|
|
|
|
|
|
|
|
NodeTys.push_back(MVT::f64); // Return register
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
|
|
|
|
Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
|
|
|
|
MFFSreg = Result.getValue(0);
|
|
|
|
InFlag = Result.getValue(1);
|
|
|
|
|
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag
|
|
|
|
Ops[0] = DAG.getConstant(31, MVT::i32);
|
|
|
|
Ops[1] = InFlag;
|
|
|
|
Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
|
|
|
|
InFlag = Result.getValue(0);
|
|
|
|
|
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag
|
|
|
|
Ops[0] = DAG.getConstant(30, MVT::i32);
|
|
|
|
Ops[1] = InFlag;
|
|
|
|
Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
|
|
|
|
InFlag = Result.getValue(0);
|
|
|
|
|
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::f64); // result of add
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag
|
|
|
|
Ops[0] = Lo;
|
|
|
|
Ops[1] = Hi;
|
|
|
|
Ops[2] = InFlag;
|
|
|
|
Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
|
|
|
|
FPreg = Result.getValue(0);
|
|
|
|
InFlag = Result.getValue(1);
|
|
|
|
|
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::f64);
|
|
|
|
Ops[0] = DAG.getConstant(1, MVT::i32);
|
|
|
|
Ops[1] = MFFSreg;
|
|
|
|
Ops[2] = FPreg;
|
|
|
|
Ops[3] = InFlag;
|
|
|
|
Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
|
|
|
|
FPreg = Result.getValue(0);
|
|
|
|
|
|
|
|
// We know the low half is about to be thrown away, so just use something
|
|
|
|
// convenient.
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
2008-03-11 01:59:03 +00:00
|
|
|
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
|
|
|
|
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
|
|
|
|
return SDOperand();
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
if (Op.getOperand(0).getValueType() == MVT::i64) {
|
|
|
|
SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
|
|
|
|
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
|
|
|
|
if (Op.getValueType() == MVT::f32)
|
2008-01-17 07:00:52 +00:00
|
|
|
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
|
2006-04-14 06:01:58 +00:00
|
|
|
return FP;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(Op.getOperand(0).getValueType() == MVT::i32 &&
|
|
|
|
"Unhandled SINT_TO_FP type in custom expander!");
|
|
|
|
// Since we only generate this in 64-bit mode, we can take advantage of
|
|
|
|
// 64-bit registers. In particular, sign extend the input value into the
|
|
|
|
// 64-bit register with extsw, store the WHOLE 64-bit value into the stack
|
|
|
|
// then lfd it and fcfid it.
|
|
|
|
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
int FrameIdx = FrameInfo->CreateStackObject(8, 8);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-07-28 16:45:47 +00:00
|
|
|
SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
|
|
|
|
Op.getOperand(0));
|
|
|
|
|
|
|
|
// STD the extended value into the stack slot.
|
2008-07-11 22:44:52 +00:00
|
|
|
MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
|
|
|
|
MachineMemOperand::MOStore, 0, 8, 8);
|
2006-04-14 06:01:58 +00:00
|
|
|
SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
|
|
|
|
DAG.getEntryNode(), Ext64, FIdx,
|
2008-02-06 22:27:42 +00:00
|
|
|
DAG.getMemOperand(MO));
|
2006-04-14 06:01:58 +00:00
|
|
|
// Load the value as a double.
|
2006-10-09 20:57:25 +00:00
|
|
|
SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
// FCFID it and return it.
|
|
|
|
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
|
|
|
|
if (Op.getValueType() == MVT::f32)
|
2008-01-17 07:00:52 +00:00
|
|
|
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
|
2006-04-14 06:01:58 +00:00
|
|
|
return FP;
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
|
2008-01-18 19:55:37 +00:00
|
|
|
/*
|
|
|
|
The rounding mode is in bits 30:31 of FPSR, and has the following
|
|
|
|
settings:
|
|
|
|
00 Round to nearest
|
|
|
|
01 Round to 0
|
|
|
|
10 Round to +inf
|
|
|
|
11 Round to -inf
|
|
|
|
|
|
|
|
FLT_ROUNDS, on the other hand, expects the following:
|
|
|
|
-1 Undefined
|
|
|
|
0 Round to 0
|
|
|
|
1 Round to nearest
|
|
|
|
2 Round to +inf
|
|
|
|
3 Round to -inf
|
|
|
|
|
|
|
|
To perform the conversion, we do:
|
|
|
|
((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
|
|
|
|
*/
|
|
|
|
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.getValueType();
|
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
|
|
|
std::vector<MVT> NodeTys;
|
2008-01-18 19:55:37 +00:00
|
|
|
SDOperand MFFSreg, InFlag;
|
|
|
|
|
|
|
|
// Save FP Control Word to register
|
|
|
|
NodeTys.push_back(MVT::f64); // return register
|
|
|
|
NodeTys.push_back(MVT::Flag); // unused in this context
|
|
|
|
SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
|
|
|
|
|
|
|
|
// Save FP register to stack slot
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
|
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
|
|
|
|
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
|
|
|
|
StackSlot, NULL, 0);
|
|
|
|
|
|
|
|
// Load FP Control Word from low 32 bits of stack slot.
|
|
|
|
SDOperand Four = DAG.getConstant(4, PtrVT);
|
|
|
|
SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
|
|
|
|
SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
|
|
|
|
|
|
|
|
// Transform as necessary
|
|
|
|
SDOperand CWD1 =
|
|
|
|
DAG.getNode(ISD::AND, MVT::i32,
|
|
|
|
CWD, DAG.getConstant(3, MVT::i32));
|
|
|
|
SDOperand CWD2 =
|
|
|
|
DAG.getNode(ISD::SRL, MVT::i32,
|
|
|
|
DAG.getNode(ISD::AND, MVT::i32,
|
|
|
|
DAG.getNode(ISD::XOR, MVT::i32,
|
|
|
|
CWD, DAG.getConstant(3, MVT::i32)),
|
|
|
|
DAG.getConstant(3, MVT::i32)),
|
|
|
|
DAG.getConstant(1, MVT::i8));
|
|
|
|
|
|
|
|
SDOperand RetVal =
|
|
|
|
DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
return DAG.getNode((VT.getSizeInBits() < 16 ?
|
2008-01-18 19:55:37 +00:00
|
|
|
ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.getValueType();
|
|
|
|
unsigned BitWidth = VT.getSizeInBits();
|
2008-03-07 20:36:53 +00:00
|
|
|
assert(Op.getNumOperands() == 3 &&
|
|
|
|
VT == Op.getOperand(1).getValueType() &&
|
|
|
|
"Unexpected SHL!");
|
2006-04-14 06:01:58 +00:00
|
|
|
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
// Expand into a bunch of logical ops. Note that these ops
|
2006-04-14 06:01:58 +00:00
|
|
|
// depend on the PPC behavior for oversized shift amounts.
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
SDOperand Lo = Op.getOperand(0);
|
|
|
|
SDOperand Hi = Op.getOperand(1);
|
|
|
|
SDOperand Amt = Op.getOperand(2);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT AmtVT = Amt.getValueType();
|
2008-03-07 20:36:53 +00:00
|
|
|
|
|
|
|
SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
|
|
|
|
DAG.getConstant(BitWidth, AmtVT), Amt);
|
|
|
|
SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
|
|
|
|
SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
|
|
|
|
SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
|
|
|
|
SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
|
|
|
|
DAG.getConstant(-BitWidth, AmtVT));
|
|
|
|
SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
|
|
|
|
SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
|
|
|
|
SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
SDOperand OutOps[] = { OutLo, OutHi };
|
2008-07-02 17:40:58 +00:00
|
|
|
return DAG.getMergeValues(OutOps, 2);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.getValueType();
|
|
|
|
unsigned BitWidth = VT.getSizeInBits();
|
2008-03-07 20:36:53 +00:00
|
|
|
assert(Op.getNumOperands() == 3 &&
|
|
|
|
VT == Op.getOperand(1).getValueType() &&
|
|
|
|
"Unexpected SRL!");
|
2006-04-14 06:01:58 +00:00
|
|
|
|
2008-03-07 20:36:53 +00:00
|
|
|
// Expand into a bunch of logical ops. Note that these ops
|
2006-04-14 06:01:58 +00:00
|
|
|
// depend on the PPC behavior for oversized shift amounts.
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
SDOperand Lo = Op.getOperand(0);
|
|
|
|
SDOperand Hi = Op.getOperand(1);
|
|
|
|
SDOperand Amt = Op.getOperand(2);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT AmtVT = Amt.getValueType();
|
2008-03-07 20:36:53 +00:00
|
|
|
|
|
|
|
SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
|
|
|
|
DAG.getConstant(BitWidth, AmtVT), Amt);
|
|
|
|
SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
|
|
|
|
SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
|
|
|
|
SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
|
|
|
|
SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
|
|
|
|
DAG.getConstant(-BitWidth, AmtVT));
|
|
|
|
SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
|
|
|
|
SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
|
|
|
|
SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
SDOperand OutOps[] = { OutLo, OutHi };
|
2008-07-02 17:40:58 +00:00
|
|
|
return DAG.getMergeValues(OutOps, 2);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT = Op.getValueType();
|
|
|
|
unsigned BitWidth = VT.getSizeInBits();
|
2008-03-07 20:36:53 +00:00
|
|
|
assert(Op.getNumOperands() == 3 &&
|
|
|
|
VT == Op.getOperand(1).getValueType() &&
|
|
|
|
"Unexpected SRA!");
|
2006-04-14 06:01:58 +00:00
|
|
|
|
2008-03-07 20:36:53 +00:00
|
|
|
// Expand into a bunch of logical ops, followed by a select_cc.
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
SDOperand Lo = Op.getOperand(0);
|
|
|
|
SDOperand Hi = Op.getOperand(1);
|
|
|
|
SDOperand Amt = Op.getOperand(2);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT AmtVT = Amt.getValueType();
|
2008-03-07 20:36:53 +00:00
|
|
|
|
|
|
|
SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
|
|
|
|
DAG.getConstant(BitWidth, AmtVT), Amt);
|
|
|
|
SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
|
|
|
|
SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
|
|
|
|
SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
|
|
|
|
SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
|
|
|
|
DAG.getConstant(-BitWidth, AmtVT));
|
|
|
|
SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
|
|
|
|
SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
|
|
|
|
SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
|
2006-04-14 06:01:58 +00:00
|
|
|
Tmp4, Tmp6, ISD::SETLE);
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
SDOperand OutOps[] = { OutLo, OutHi };
|
2008-07-02 17:40:58 +00:00
|
|
|
return DAG.getMergeValues(OutOps, 2);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Vector related lowering.
|
|
|
|
//
|
|
|
|
|
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 19:07:14 +00:00
|
|
|
// If this is a vector of constants or undefs, get the bits. A bit in
|
|
|
|
// UndefBits is set if the corresponding element of the vector is an
|
|
|
|
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
|
|
|
|
// zero. Return true if this is not an array of constants, false if it is.
|
|
|
|
//
|
|
|
|
static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
|
|
|
|
uint64_t UndefBits[2]) {
|
|
|
|
// Start with zero'd results.
|
|
|
|
VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
|
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 19:07:14 +00:00
|
|
|
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
|
|
|
|
SDOperand OpVal = BV->getOperand(i);
|
|
|
|
|
|
|
|
unsigned PartNo = i >= e/2; // In the upper 128 bits?
|
2006-04-16 01:01:29 +00:00
|
|
|
unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
|
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 19:07:14 +00:00
|
|
|
|
|
|
|
uint64_t EltBits = 0;
|
|
|
|
if (OpVal.getOpcode() == ISD::UNDEF) {
|
|
|
|
uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
|
|
|
|
UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
|
|
|
|
continue;
|
|
|
|
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
|
|
|
|
EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
|
|
|
|
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
|
|
|
|
assert(CN->getValueType(0) == MVT::f32 &&
|
|
|
|
"Only one legal FP vector type!");
|
2007-08-31 04:03:46 +00:00
|
|
|
EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
|
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 19:07:14 +00:00
|
|
|
} else {
|
|
|
|
// Nonconstant element.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
|
|
|
|
}
|
|
|
|
|
|
|
|
//printf("%llx %llx %llx %llx\n",
|
|
|
|
// VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
|
|
|
|
return false;
|
|
|
|
}
|
2006-03-20 06:33:01 +00:00
|
|
|
|
2006-04-16 01:01:29 +00:00
|
|
|
// If this is a splat (repetition) of a value across the whole vector, return
|
|
|
|
// the smallest size that splats it. For example, "0x01010101010101..." is a
|
|
|
|
// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
|
|
|
|
// SplatSize = 1 byte.
|
|
|
|
static bool isConstantSplat(const uint64_t Bits128[2],
|
|
|
|
const uint64_t Undef128[2],
|
|
|
|
unsigned &SplatBits, unsigned &SplatUndef,
|
|
|
|
unsigned &SplatSize) {
|
|
|
|
|
|
|
|
// Don't let undefs prevent splats from matching. See if the top 64-bits are
|
|
|
|
// the same as the lower 64-bits, ignoring undefs.
|
|
|
|
if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
|
|
|
|
return false; // Can't be a splat if two pieces don't match.
|
|
|
|
|
|
|
|
uint64_t Bits64 = Bits128[0] | Bits128[1];
|
|
|
|
uint64_t Undef64 = Undef128[0] & Undef128[1];
|
|
|
|
|
|
|
|
// Check that the top 32-bits are the same as the lower 32-bits, ignoring
|
|
|
|
// undefs.
|
|
|
|
if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
|
|
|
|
return false; // Can't be a splat if two pieces don't match.
|
|
|
|
|
|
|
|
uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
|
|
|
|
uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
|
|
|
|
|
|
|
|
// If the top 16-bits are different than the lower 16-bits, ignoring
|
|
|
|
// undefs, we have an i32 splat.
|
|
|
|
if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
|
|
|
|
SplatBits = Bits32;
|
|
|
|
SplatUndef = Undef32;
|
|
|
|
SplatSize = 4;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
|
|
|
|
uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
|
|
|
|
|
|
|
|
// If the top 8-bits are different than the lower 8-bits, ignoring
|
|
|
|
// undefs, we have an i16 splat.
|
|
|
|
if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
|
|
|
|
SplatBits = Bits16;
|
|
|
|
SplatUndef = Undef16;
|
|
|
|
SplatSize = 2;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we have an 8-bit splat.
|
|
|
|
SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
|
|
|
|
SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
|
|
|
|
SplatSize = 1;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-04-17 06:00:21 +00:00
|
|
|
/// BuildSplatI - Build a canonical splati of Val with an element size of
|
|
|
|
/// SplatSize. Cast the result to VT.
|
2008-06-06 12:08:01 +00:00
|
|
|
static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT,
|
2006-04-17 06:00:21 +00:00
|
|
|
SelectionDAG &DAG) {
|
|
|
|
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
|
2006-12-01 01:45:39 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
static const MVT VTys[] = { // canonical VT to use for each size.
|
2006-04-17 06:00:21 +00:00
|
|
|
MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
|
|
|
|
};
|
2006-12-01 01:45:39 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
|
2006-12-01 01:45:39 +00:00
|
|
|
|
|
|
|
// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
|
|
|
|
if (Val == -1)
|
|
|
|
SplatSize = 1;
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT CanonicalVT = VTys[SplatSize-1];
|
2006-04-17 06:00:21 +00:00
|
|
|
|
|
|
|
// Build a canonical splat for this value.
|
2008-06-06 12:08:01 +00:00
|
|
|
SDOperand Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
|
2006-08-11 17:38:39 +00:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2008-06-06 12:08:01 +00:00
|
|
|
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
|
2006-08-11 17:38:39 +00:00
|
|
|
SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
|
|
|
|
&Ops[0], Ops.size());
|
2006-12-01 01:45:39 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
|
2006-04-17 06:00:21 +00:00
|
|
|
}
|
|
|
|
|
2006-04-18 03:24:30 +00:00
|
|
|
/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
|
2006-04-17 06:58:41 +00:00
|
|
|
/// specified intrinsic ID.
|
2006-04-18 03:24:30 +00:00
|
|
|
static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
|
|
|
|
SelectionDAG &DAG,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT DestVT = MVT::Other) {
|
2006-04-18 03:24:30 +00:00
|
|
|
if (DestVT == MVT::Other) DestVT = LHS.getValueType();
|
|
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
|
2006-04-17 06:58:41 +00:00
|
|
|
DAG.getConstant(IID, MVT::i32), LHS, RHS);
|
|
|
|
}
|
|
|
|
|
2006-04-18 03:24:30 +00:00
|
|
|
/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
|
|
|
|
/// specified intrinsic ID.
|
|
|
|
static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
|
|
|
|
SDOperand Op2, SelectionDAG &DAG,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT DestVT = MVT::Other) {
|
2006-04-18 03:24:30 +00:00
|
|
|
if (DestVT == MVT::Other) DestVT = Op0.getValueType();
|
|
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
|
|
|
|
DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-04-17 17:55:10 +00:00
|
|
|
/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
|
|
|
|
/// amount. The result has the specified value type.
|
|
|
|
static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT, SelectionDAG &DAG) {
|
2006-04-17 17:55:10 +00:00
|
|
|
// Force LHS/RHS to be the right type.
|
|
|
|
LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
|
|
|
|
RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
|
2008-07-21 10:20:31 +00:00
|
|
|
|
2006-08-11 17:38:39 +00:00
|
|
|
SDOperand Ops[16];
|
2006-04-17 17:55:10 +00:00
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
2008-07-21 10:20:31 +00:00
|
|
|
Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
|
2006-04-17 17:55:10 +00:00
|
|
|
SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
|
2006-08-11 17:38:39 +00:00
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
|
2006-04-17 17:55:10 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, VT, T);
|
|
|
|
}
|
|
|
|
|
2006-04-14 05:19:18 +00:00
|
|
|
// If this is a case we can't handle, return null and let the default
|
|
|
|
// expansion code take care of it. If we CAN select this case, and if it
|
|
|
|
// selects to a single instruction, return Op. Otherwise, if we can codegen
|
|
|
|
// this case more efficiently than a constant pool load, lower it to the
|
|
|
|
// sequence of ops that should be used.
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2006-04-14 05:19:18 +00:00
|
|
|
// If this is a vector of constants or undefs, get the bits. A bit in
|
|
|
|
// UndefBits is set if the corresponding element of the vector is an
|
|
|
|
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
|
|
|
|
// zero.
|
|
|
|
uint64_t VectorBits[2];
|
|
|
|
uint64_t UndefBits[2];
|
|
|
|
if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
|
|
|
|
return SDOperand(); // Not a constant vector.
|
|
|
|
|
2006-04-16 01:01:29 +00:00
|
|
|
// If this is a splat (repetition) of a value across the whole vector, return
|
|
|
|
// the smallest size that splats it. For example, "0x01010101010101..." is a
|
|
|
|
// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
|
|
|
|
// SplatSize = 1 byte.
|
|
|
|
unsigned SplatBits, SplatUndef, SplatSize;
|
|
|
|
if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
|
|
|
|
bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
|
|
|
|
|
|
|
|
// First, handle single instruction cases.
|
|
|
|
|
|
|
|
// All zeros?
|
|
|
|
if (SplatBits == 0) {
|
|
|
|
// Canonicalize all zero vectors to be v4i32.
|
|
|
|
if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
|
|
|
|
SDOperand Z = DAG.getConstant(0, MVT::i32);
|
|
|
|
Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
|
|
|
|
Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
|
|
|
|
}
|
|
|
|
return Op;
|
2006-04-14 05:19:18 +00:00
|
|
|
}
|
2006-04-16 01:01:29 +00:00
|
|
|
|
|
|
|
// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
|
|
|
|
int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
|
2006-04-17 06:00:21 +00:00
|
|
|
if (SextVal >= -16 && SextVal <= 15)
|
|
|
|
return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
|
2006-04-16 01:01:29 +00:00
|
|
|
|
2006-04-17 18:09:22 +00:00
|
|
|
|
|
|
|
// Two instruction sequences.
|
|
|
|
|
2006-04-17 06:00:21 +00:00
|
|
|
// If this value is in the range [-32,30] and is even, use:
|
|
|
|
// tmp = VSPLTI[bhw], result = add tmp, tmp
|
|
|
|
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
|
2008-07-10 16:33:38 +00:00
|
|
|
SDOperand Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
|
|
|
|
Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
|
2006-04-17 06:00:21 +00:00
|
|
|
}
|
2006-04-14 05:19:18 +00:00
|
|
|
|
|
|
|
// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
|
2006-04-17 06:58:41 +00:00
|
|
|
// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
|
2006-04-14 05:19:18 +00:00
|
|
|
// for fneg/fabs.
|
2006-04-17 06:58:41 +00:00
|
|
|
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
|
2006-04-14 05:19:18 +00:00
|
|
|
// Make -1 and vspltisw -1:
|
2006-04-17 06:58:41 +00:00
|
|
|
SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
|
2006-04-14 05:19:18 +00:00
|
|
|
|
|
|
|
// Make the VSLW intrinsic, computing 0x8000_0000.
|
2006-04-18 03:24:30 +00:00
|
|
|
SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
|
|
|
|
OnesV, DAG);
|
2006-04-14 05:19:18 +00:00
|
|
|
|
2006-04-17 06:58:41 +00:00
|
|
|
// xor by OnesV to invert it.
|
|
|
|
Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
|
2006-04-14 05:19:18 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
|
|
|
|
}
|
2006-04-17 06:58:41 +00:00
|
|
|
|
|
|
|
// Check to see if this is a wide variety of vsplti*, binop self cases.
|
|
|
|
unsigned SplatBitSize = SplatSize*8;
|
2007-03-27 16:33:08 +00:00
|
|
|
static const signed char SplatCsts[] = {
|
2006-04-17 06:58:41 +00:00
|
|
|
-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
|
2006-04-17 18:09:22 +00:00
|
|
|
-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
|
2006-04-17 06:58:41 +00:00
|
|
|
};
|
2006-11-29 19:58:49 +00:00
|
|
|
|
2007-09-07 04:06:50 +00:00
|
|
|
for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
|
2006-04-17 06:58:41 +00:00
|
|
|
// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
|
|
|
|
// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
|
|
|
|
int i = SplatCsts[idx];
|
|
|
|
|
|
|
|
// Figure out what shift amount will be used by altivec if shifted by i in
|
|
|
|
// this splat size.
|
|
|
|
unsigned TypeShiftAmt = i & (SplatBitSize-1);
|
|
|
|
|
|
|
|
// vsplti + shl self.
|
|
|
|
if (SextVal == (i << (int)TypeShiftAmt)) {
|
2006-11-29 19:58:49 +00:00
|
|
|
SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
|
2006-04-17 06:58:41 +00:00
|
|
|
static const unsigned IIDs[] = { // Intrinsic to use for each size.
|
|
|
|
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
|
|
|
|
Intrinsic::ppc_altivec_vslw
|
|
|
|
};
|
2006-11-29 19:58:49 +00:00
|
|
|
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
|
2006-04-17 06:58:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// vsplti + srl self.
|
|
|
|
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
|
2006-11-29 19:58:49 +00:00
|
|
|
SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
|
2006-04-17 06:58:41 +00:00
|
|
|
static const unsigned IIDs[] = { // Intrinsic to use for each size.
|
|
|
|
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
|
|
|
|
Intrinsic::ppc_altivec_vsrw
|
|
|
|
};
|
2006-11-29 19:58:49 +00:00
|
|
|
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
|
2006-04-17 06:58:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// vsplti + sra self.
|
|
|
|
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
|
2006-11-29 19:58:49 +00:00
|
|
|
SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
|
2006-04-17 06:58:41 +00:00
|
|
|
static const unsigned IIDs[] = { // Intrinsic to use for each size.
|
|
|
|
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
|
|
|
|
Intrinsic::ppc_altivec_vsraw
|
|
|
|
};
|
2006-11-29 19:58:49 +00:00
|
|
|
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
|
2006-04-17 06:58:41 +00:00
|
|
|
}
|
|
|
|
|
2006-04-17 17:55:10 +00:00
|
|
|
// vsplti + rol self.
|
|
|
|
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
|
|
|
|
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
|
2006-11-29 19:58:49 +00:00
|
|
|
SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
|
2006-04-17 17:55:10 +00:00
|
|
|
static const unsigned IIDs[] = { // Intrinsic to use for each size.
|
|
|
|
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
|
|
|
|
Intrinsic::ppc_altivec_vrlw
|
|
|
|
};
|
2006-11-29 19:58:49 +00:00
|
|
|
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
|
2006-04-17 17:55:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// t = vsplti c, result = vsldoi t, t, 1
|
|
|
|
if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
|
|
|
|
SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
|
|
|
|
return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
|
|
|
|
}
|
|
|
|
// t = vsplti c, result = vsldoi t, t, 2
|
|
|
|
if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
|
|
|
|
SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
|
|
|
|
return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
|
|
|
|
}
|
|
|
|
// t = vsplti c, result = vsldoi t, t, 3
|
|
|
|
if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
|
|
|
|
SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
|
|
|
|
return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
|
|
|
|
}
|
2006-04-17 06:58:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Three instruction sequences.
|
|
|
|
|
2006-04-17 18:09:22 +00:00
|
|
|
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
|
|
|
|
if (SextVal >= 0 && SextVal <= 31) {
|
2006-11-29 19:58:49 +00:00
|
|
|
SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
|
|
|
|
SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
|
2007-10-14 01:58:32 +00:00
|
|
|
LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
|
2006-11-29 19:58:49 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
|
2006-04-17 18:09:22 +00:00
|
|
|
}
|
|
|
|
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
|
|
|
|
if (SextVal >= -31 && SextVal <= 0) {
|
2006-11-29 19:58:49 +00:00
|
|
|
SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
|
|
|
|
SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
|
2007-10-14 01:58:32 +00:00
|
|
|
LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
|
2006-11-29 19:58:49 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
|
2006-04-17 06:58:41 +00:00
|
|
|
}
|
2006-04-14 05:19:18 +00:00
|
|
|
}
|
2006-04-16 01:01:29 +00:00
|
|
|
|
2006-04-14 05:19:18 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-04-17 05:28:54 +00:00
|
|
|
/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
|
|
|
|
/// the specified operations to build the shuffle.
|
|
|
|
static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
|
|
|
|
SDOperand RHS, SelectionDAG &DAG) {
|
|
|
|
unsigned OpNum = (PFEntry >> 26) & 0x0F;
|
|
|
|
unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
|
|
|
|
unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
|
|
|
|
|
|
|
|
enum {
|
2006-05-16 04:20:24 +00:00
|
|
|
OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
|
2006-04-17 05:28:54 +00:00
|
|
|
OP_VMRGHW,
|
|
|
|
OP_VMRGLW,
|
|
|
|
OP_VSPLTISW0,
|
|
|
|
OP_VSPLTISW1,
|
|
|
|
OP_VSPLTISW2,
|
|
|
|
OP_VSPLTISW3,
|
|
|
|
OP_VSLDOI4,
|
|
|
|
OP_VSLDOI8,
|
2006-05-24 17:04:05 +00:00
|
|
|
OP_VSLDOI12
|
2006-04-17 05:28:54 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
if (OpNum == OP_COPY) {
|
|
|
|
if (LHSID == (1*9+2)*9+3) return LHS;
|
|
|
|
assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
|
|
|
|
return RHS;
|
|
|
|
}
|
|
|
|
|
2006-04-17 17:55:10 +00:00
|
|
|
SDOperand OpLHS, OpRHS;
|
|
|
|
OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
|
|
|
|
OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
|
|
|
|
|
2006-04-17 05:28:54 +00:00
|
|
|
unsigned ShufIdxs[16];
|
|
|
|
switch (OpNum) {
|
|
|
|
default: assert(0 && "Unknown i32 permute!");
|
|
|
|
case OP_VMRGHW:
|
|
|
|
ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
|
|
|
|
ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
|
|
|
|
ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
|
|
|
|
ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
|
|
|
|
break;
|
|
|
|
case OP_VMRGLW:
|
|
|
|
ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
|
|
|
|
ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
|
|
|
|
ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
|
|
|
|
ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
|
|
|
|
break;
|
|
|
|
case OP_VSPLTISW0:
|
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
|
|
|
ShufIdxs[i] = (i&3)+0;
|
|
|
|
break;
|
|
|
|
case OP_VSPLTISW1:
|
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
|
|
|
ShufIdxs[i] = (i&3)+4;
|
|
|
|
break;
|
|
|
|
case OP_VSPLTISW2:
|
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
|
|
|
ShufIdxs[i] = (i&3)+8;
|
|
|
|
break;
|
|
|
|
case OP_VSPLTISW3:
|
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
|
|
|
ShufIdxs[i] = (i&3)+12;
|
|
|
|
break;
|
|
|
|
case OP_VSLDOI4:
|
2006-04-17 17:55:10 +00:00
|
|
|
return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
|
2006-04-17 05:28:54 +00:00
|
|
|
case OP_VSLDOI8:
|
2006-04-17 17:55:10 +00:00
|
|
|
return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
|
2006-04-17 05:28:54 +00:00
|
|
|
case OP_VSLDOI12:
|
2006-04-17 17:55:10 +00:00
|
|
|
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
|
2006-04-17 05:28:54 +00:00
|
|
|
}
|
2006-08-11 17:38:39 +00:00
|
|
|
SDOperand Ops[16];
|
2006-04-17 05:28:54 +00:00
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
2008-07-21 10:20:31 +00:00
|
|
|
Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
|
2006-04-17 05:28:54 +00:00
|
|
|
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
|
2006-08-11 17:38:39 +00:00
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
|
2006-04-17 05:28:54 +00:00
|
|
|
}
|
|
|
|
|
2006-04-14 05:19:18 +00:00
|
|
|
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
|
|
|
|
/// is a shuffle we can handle in a single instruction, return it. Otherwise,
|
|
|
|
/// return the code it can be lowered into. Worst case, it can always be
|
|
|
|
/// lowered into a vperm.
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2006-04-14 05:19:18 +00:00
|
|
|
SDOperand V1 = Op.getOperand(0);
|
|
|
|
SDOperand V2 = Op.getOperand(1);
|
|
|
|
SDOperand PermMask = Op.getOperand(2);
|
|
|
|
|
|
|
|
// Cases that are handled by instructions that take permute immediates
|
|
|
|
// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
|
|
|
|
// selected by the instruction selector.
|
|
|
|
if (V2.getOpcode() == ISD::UNDEF) {
|
|
|
|
if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
|
|
|
|
PPC::isSplatShuffleMask(PermMask.Val, 2) ||
|
|
|
|
PPC::isSplatShuffleMask(PermMask.Val, 4) ||
|
|
|
|
PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
|
|
|
|
PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
|
|
|
|
PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
|
|
|
|
PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
|
|
|
|
PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
|
|
|
|
PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
|
|
|
|
PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
|
|
|
|
PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
|
|
|
|
PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
|
|
|
|
return Op;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Altivec has a variety of "shuffle immediates" that take two vector inputs
|
|
|
|
// and produce a fixed permutation. If any of these match, do not lower to
|
|
|
|
// VPERM.
|
|
|
|
if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
|
|
|
|
PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
|
|
|
|
PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
|
|
|
|
PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
|
|
|
|
PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
|
|
|
|
PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
|
|
|
|
PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
|
|
|
|
PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
|
|
|
|
PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
|
|
|
|
return Op;
|
|
|
|
|
2006-04-17 05:28:54 +00:00
|
|
|
// Check to see if this is a shuffle of 4-byte values. If so, we can use our
|
|
|
|
// perfect shuffle table to emit an optimal matching sequence.
|
|
|
|
unsigned PFIndexes[4];
|
|
|
|
bool isFourElementShuffle = true;
|
|
|
|
for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
|
|
|
|
unsigned EltNo = 8; // Start out undef.
|
|
|
|
for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
|
|
|
|
if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
|
|
|
|
continue; // Undef, ignore it.
|
|
|
|
|
|
|
|
unsigned ByteSource =
|
|
|
|
cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
|
|
|
|
if ((ByteSource & 3) != j) {
|
|
|
|
isFourElementShuffle = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (EltNo == 8) {
|
|
|
|
EltNo = ByteSource/4;
|
|
|
|
} else if (EltNo != ByteSource/4) {
|
|
|
|
isFourElementShuffle = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
PFIndexes[i] = EltNo;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this shuffle can be expressed as a shuffle of 4-byte elements, use the
|
|
|
|
// perfect shuffle vector to determine if it is cost effective to do this as
|
|
|
|
// discrete instructions, or whether we should use a vperm.
|
|
|
|
if (isFourElementShuffle) {
|
|
|
|
// Compute the index in the perfect shuffle table.
|
|
|
|
unsigned PFTableIndex =
|
|
|
|
PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
|
|
|
|
|
|
|
|
unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
|
|
|
|
unsigned Cost = (PFEntry >> 30);
|
|
|
|
|
|
|
|
// Determining when to avoid vperm is tricky. Many things affect the cost
|
|
|
|
// of vperm, particularly how many times the perm mask needs to be computed.
|
|
|
|
// For example, if the perm mask can be hoisted out of a loop or is already
|
|
|
|
// used (perhaps because there are multiple permutes with the same shuffle
|
|
|
|
// mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
|
|
|
|
// the loop requires an extra register.
|
|
|
|
//
|
|
|
|
// As a compromise, we only emit discrete instructions if the shuffle can be
|
|
|
|
// generated in 3 or fewer operations. When we have loop information
|
|
|
|
// available, if this block is within a loop, we should avoid using vperm
|
|
|
|
// for 3-operation perms and use a constant pool load instead.
|
|
|
|
if (Cost < 3)
|
|
|
|
return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
|
|
|
|
}
|
2006-04-14 05:19:18 +00:00
|
|
|
|
|
|
|
// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
|
|
|
|
// vector that will get spilled to the constant pool.
|
|
|
|
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
|
|
|
|
|
|
|
|
// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
|
|
|
|
// that it is in input element units, not in bytes. Convert now.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT EltVT = V1.getValueType().getVectorElementType();
|
|
|
|
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
|
2006-04-14 05:19:18 +00:00
|
|
|
|
2006-08-11 17:38:39 +00:00
|
|
|
SmallVector<SDOperand, 16> ResultMask;
|
2006-04-14 05:19:18 +00:00
|
|
|
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
|
2006-04-15 23:48:05 +00:00
|
|
|
unsigned SrcElt;
|
|
|
|
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
|
|
|
|
SrcElt = 0;
|
|
|
|
else
|
|
|
|
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
|
2006-04-14 05:19:18 +00:00
|
|
|
|
|
|
|
for (unsigned j = 0; j != BytesPerElement; ++j)
|
|
|
|
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
|
|
|
|
MVT::i8));
|
|
|
|
}
|
|
|
|
|
2006-08-11 17:38:39 +00:00
|
|
|
SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
|
|
|
|
&ResultMask[0], ResultMask.size());
|
2006-04-14 05:19:18 +00:00
|
|
|
return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
|
|
|
|
}
|
|
|
|
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
|
|
|
|
/// altivec comparison. If it is, return true and fill in Opc/isDot with
|
|
|
|
/// information about the intrinsic.
|
|
|
|
static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
|
|
|
|
bool &isDot) {
|
|
|
|
unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
|
|
|
|
CompareOpc = -1;
|
|
|
|
isDot = false;
|
|
|
|
switch (IntrinsicID) {
|
|
|
|
default: return false;
|
|
|
|
// Comparison predicates.
|
2006-04-14 06:01:58 +00:00
|
|
|
case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
|
2005-10-02 06:37:13 +00:00
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
// Normal Comparisons.
|
|
|
|
case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
|
2005-09-06 22:03:27 +00:00
|
|
|
}
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
|
|
|
|
/// lower, do it, otherwise return null.
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
// If this is a lowered altivec predicate compare, CompareOpc is set to the
|
|
|
|
// opcode number of the comparison.
|
|
|
|
int CompareOpc;
|
|
|
|
bool isDot;
|
|
|
|
if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
|
|
|
|
return SDOperand(); // Don't custom lower most intrinsics.
|
2006-04-14 06:01:58 +00:00
|
|
|
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
// If this is a non-dot comparison, make the VCMP node and we are done.
|
2006-04-14 06:01:58 +00:00
|
|
|
if (!isDot) {
|
|
|
|
SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
|
|
|
|
Op.getOperand(1), Op.getOperand(2),
|
|
|
|
DAG.getConstant(CompareOpc, MVT::i32));
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create the PPCISD altivec 'dot' comparison node.
|
2006-08-11 17:18:05 +00:00
|
|
|
SDOperand Ops[] = {
|
|
|
|
Op.getOperand(2), // LHS
|
|
|
|
Op.getOperand(3), // RHS
|
|
|
|
DAG.getConstant(CompareOpc, MVT::i32)
|
|
|
|
};
|
2008-06-06 12:08:01 +00:00
|
|
|
std::vector<MVT> VTs;
|
2006-04-14 06:01:58 +00:00
|
|
|
VTs.push_back(Op.getOperand(2).getValueType());
|
|
|
|
VTs.push_back(MVT::Flag);
|
2006-08-11 17:18:05 +00:00
|
|
|
SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
// Now that we have the comparison, emit a copy from the CR to a GPR.
|
|
|
|
// This is flagged to the above dot comparison.
|
|
|
|
SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
|
|
|
|
DAG.getRegister(PPC::CR6, MVT::i32),
|
|
|
|
CompNode.getValue(1));
|
|
|
|
|
|
|
|
// Unpack the result based on how the target uses it.
|
|
|
|
unsigned BitNo; // Bit # of CR6.
|
|
|
|
bool InvertBit; // Invert result?
|
|
|
|
switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
|
|
|
|
default: // Can't happen, don't crash on invalid number though.
|
|
|
|
case 0: // Return the value of the EQ bit of CR6.
|
|
|
|
BitNo = 0; InvertBit = false;
|
2006-03-24 07:53:47 +00:00
|
|
|
break;
|
2006-04-14 06:01:58 +00:00
|
|
|
case 1: // Return the inverted value of the EQ bit of CR6.
|
|
|
|
BitNo = 0; InvertBit = true;
|
2005-08-31 21:09:52 +00:00
|
|
|
break;
|
2006-04-14 06:01:58 +00:00
|
|
|
case 2: // Return the value of the LT bit of CR6.
|
|
|
|
BitNo = 2; InvertBit = false;
|
|
|
|
break;
|
|
|
|
case 3: // Return the inverted value of the LT bit of CR6.
|
|
|
|
BitNo = 2; InvertBit = true;
|
Codegen
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25848 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 08:17:29 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
// Shift the bit into the low position.
|
|
|
|
Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
|
|
|
|
DAG.getConstant(8-(3-BitNo), MVT::i32));
|
|
|
|
// Isolate the bit.
|
|
|
|
Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
|
|
|
|
DAG.getConstant(1, MVT::i32));
|
|
|
|
|
|
|
|
// If we are supposed to, toggle the bit.
|
|
|
|
if (InvertBit)
|
|
|
|
Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
|
2006-03-26 10:06:40 +00:00
|
|
|
DAG.getConstant(1, MVT::i32));
|
2006-04-14 06:01:58 +00:00
|
|
|
return Flags;
|
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
2006-04-14 06:01:58 +00:00
|
|
|
// Create a stack slot that is 16-byte aligned.
|
|
|
|
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-07-28 16:45:47 +00:00
|
|
|
SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
// Store the input value into Value#0 of the stack slot.
|
2006-10-05 23:01:46 +00:00
|
|
|
SDOperand Store = DAG.getStore(DAG.getEntryNode(),
|
2006-10-13 21:14:26 +00:00
|
|
|
Op.getOperand(0), FIdx, NULL, 0);
|
2006-04-14 06:01:58 +00:00
|
|
|
// Load it out.
|
2006-10-09 20:57:25 +00:00
|
|
|
return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
|
2006-04-14 06:01:58 +00:00
|
|
|
}
|
|
|
|
|
2008-03-04 23:17:14 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
|
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27789 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 03:43:48 +00:00
|
|
|
if (Op.getValueType() == MVT::v4i32) {
|
|
|
|
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
|
|
|
|
|
|
|
|
SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
|
|
|
|
SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
|
|
|
|
|
|
|
|
SDOperand RHSSwap = // = vrlw RHS, 16
|
|
|
|
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
|
|
|
|
|
|
|
|
// Shrinkify inputs to v8i16.
|
|
|
|
LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
|
|
|
|
RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
|
|
|
|
RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
|
|
|
|
|
|
|
|
// Low parts multiplied together, generating 32-bit results (we ignore the
|
|
|
|
// top parts).
|
|
|
|
SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
|
|
|
|
LHS, RHS, DAG, MVT::v4i32);
|
|
|
|
|
|
|
|
SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
|
|
|
|
LHS, RHSSwap, Zero, DAG, MVT::v4i32);
|
|
|
|
// Shift the high parts up 16 bits.
|
|
|
|
HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
|
|
|
|
return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
|
|
|
|
} else if (Op.getValueType() == MVT::v8i16) {
|
|
|
|
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
|
|
|
|
|
2006-04-18 04:28:57 +00:00
|
|
|
SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
|
|
|
|
|
|
|
|
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
|
|
|
|
LHS, RHS, Zero, DAG);
|
2006-04-18 03:57:35 +00:00
|
|
|
} else if (Op.getValueType() == MVT::v16i8) {
|
|
|
|
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
|
|
|
|
|
|
|
|
// Multiply the even 8-bit parts, producing 16-bit sums.
|
|
|
|
SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
|
|
|
|
LHS, RHS, DAG, MVT::v8i16);
|
|
|
|
EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
|
|
|
|
|
|
|
|
// Multiply the odd 8-bit parts, producing 16-bit sums.
|
|
|
|
SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
|
|
|
|
LHS, RHS, DAG, MVT::v8i16);
|
|
|
|
OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
|
|
|
|
|
|
|
|
// Merge the results together.
|
2006-08-11 17:38:39 +00:00
|
|
|
SDOperand Ops[16];
|
2006-04-18 03:57:35 +00:00
|
|
|
for (unsigned i = 0; i != 8; ++i) {
|
2006-08-11 17:38:39 +00:00
|
|
|
Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
|
|
|
|
Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
|
2006-04-18 03:57:35 +00:00
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
|
2006-08-11 17:38:39 +00:00
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
|
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27789 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 03:43:48 +00:00
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown mul to lower!");
|
|
|
|
abort();
|
|
|
|
}
|
2006-04-18 03:24:30 +00:00
|
|
|
}
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
|
|
///
|
|
|
|
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
switch (Op.getOpcode()) {
|
|
|
|
default: assert(0 && "Wasn't expecting to be able to lower this!");
|
|
|
|
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
|
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
2007-07-11 17:19:51 +00:00
|
|
|
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
|
2006-04-22 18:53:45 +00:00
|
|
|
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
2007-04-03 13:59:52 +00:00
|
|
|
case ISD::VASTART:
|
|
|
|
return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
|
|
|
|
VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
|
|
|
|
|
|
|
|
case ISD::VAARG:
|
|
|
|
return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
|
|
|
|
VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
|
|
|
|
|
2006-06-21 00:34:03 +00:00
|
|
|
case ISD::FORMAL_ARGUMENTS:
|
2007-04-03 13:59:52 +00:00
|
|
|
return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
|
|
|
|
VarArgsStackOffset, VarArgsNumGPR,
|
|
|
|
VarArgsNumFPR, PPCSubTarget);
|
|
|
|
|
2008-03-19 21:39:28 +00:00
|
|
|
case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
|
|
|
|
getTargetMachine());
|
2007-03-06 00:59:59 +00:00
|
|
|
case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
|
2006-12-04 22:04:42 +00:00
|
|
|
case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
|
2007-02-25 05:34:32 +00:00
|
|
|
case ISD::DYNAMIC_STACKALLOC:
|
|
|
|
return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
|
2008-04-19 01:30:48 +00:00
|
|
|
|
2008-06-25 08:15:39 +00:00
|
|
|
case ISD::ATOMIC_LOAD_ADD: return LowerAtomicLOAD_ADD(Op, DAG);
|
|
|
|
case ISD::ATOMIC_CMP_SWAP: return LowerAtomicCMP_SWAP(Op, DAG);
|
2008-04-19 01:30:48 +00:00
|
|
|
case ISD::ATOMIC_SWAP: return LowerAtomicSWAP(Op, DAG);
|
2006-03-26 10:06:40 +00:00
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
|
|
|
|
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
|
|
|
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
|
2007-10-10 01:01:31 +00:00
|
|
|
case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
|
2008-01-31 00:41:03 +00:00
|
|
|
case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
// Lower 64-bit shifts.
|
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20 03:47:40 +00:00
|
|
|
case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
|
|
|
|
case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
|
|
|
|
case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
|
2006-04-14 06:01:58 +00:00
|
|
|
|
|
|
|
// Vector-related lowering.
|
|
|
|
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
|
|
|
|
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
|
|
|
|
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
|
|
|
|
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
|
2006-04-18 03:24:30 +00:00
|
|
|
case ISD::MUL: return LowerMUL(Op, DAG);
|
2007-01-29 22:58:52 +00:00
|
|
|
|
2007-12-08 06:59:59 +00:00
|
|
|
// Frame & Return address.
|
|
|
|
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
|
2007-03-01 13:11:38 +00:00
|
|
|
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
|
2005-08-31 20:23:54 +00:00
|
|
|
}
|
2005-08-26 00:52:45 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2008-07-04 11:47:58 +00:00
|
|
|
SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
|
2007-11-28 18:44:47 +00:00
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default: assert(0 && "Wasn't expecting to be able to lower this!");
|
2008-07-19 16:26:02 +00:00
|
|
|
case ISD::FP_TO_SINT: {
|
|
|
|
SDOperand Res = LowerFP_TO_SINT(SDOperand(N, 0), DAG);
|
|
|
|
// Use MERGE_VALUES to drop the chain result value and get a node with one
|
|
|
|
// result. This requires turning off getMergeValues simplification, since
|
|
|
|
// otherwise it will give us Res back.
|
|
|
|
return DAG.getMergeValues(&Res, 1, false).Val;
|
|
|
|
}
|
2007-11-28 18:44:47 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Other Lowering Code
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2005-08-26 21:23:58 +00:00
|
|
|
MachineBasicBlock *
|
2008-01-30 18:18:23 +00:00
|
|
|
PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) {
|
2006-11-27 23:37:22 +00:00
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
2008-07-12 02:23:19 +00:00
|
|
|
|
|
|
|
// To "insert" these instructions we actually have to insert their
|
|
|
|
// control-flow patterns.
|
2005-08-26 21:23:58 +00:00
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
2008-07-07 23:14:23 +00:00
|
|
|
MachineFunction::iterator It = BB;
|
2005-08-26 21:23:58 +00:00
|
|
|
++It;
|
2008-07-12 02:23:19 +00:00
|
|
|
|
2008-07-07 23:14:23 +00:00
|
|
|
MachineFunction *F = BB->getParent();
|
2008-07-12 02:23:19 +00:00
|
|
|
|
|
|
|
if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
|
|
|
|
MI->getOpcode() == PPC::SELECT_CC_I8 ||
|
|
|
|
MI->getOpcode() == PPC::SELECT_CC_F4 ||
|
|
|
|
MI->getOpcode() == PPC::SELECT_CC_F8 ||
|
|
|
|
MI->getOpcode() == PPC::SELECT_CC_VRRC) {
|
|
|
|
|
|
|
|
// The incoming instruction knows the destination vreg to set, the
|
|
|
|
// condition code register to branch on, the true/false values to
|
|
|
|
// select between, and a branch opcode to use.
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// TrueVal = ...
|
|
|
|
// cmpTY ccX, r1, r2
|
|
|
|
// bCC copy1MBB
|
|
|
|
// fallthrough --> copy0MBB
|
|
|
|
MachineBasicBlock *thisMBB = BB;
|
|
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
unsigned SelectPred = MI->getOperand(4).getImm();
|
|
|
|
BuildMI(BB, TII->get(PPC::BCC))
|
|
|
|
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
|
|
|
|
F->insert(It, copy0MBB);
|
|
|
|
F->insert(It, sinkMBB);
|
|
|
|
// Update machine-CFG edges by transferring all successors of the current
|
|
|
|
// block to the new block which will contain the Phi node for the select.
|
|
|
|
sinkMBB->transferSuccessors(BB);
|
|
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
|
|
BB->addSuccessor(copy0MBB);
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// copy0MBB:
|
|
|
|
// %FalseValue = ...
|
|
|
|
// # fallthrough to sinkMBB
|
|
|
|
BB = copy0MBB;
|
|
|
|
|
|
|
|
// Update machine-CFG edges
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// sinkMBB:
|
|
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
|
|
// ...
|
|
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
|
|
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
|
|
|
}
|
|
|
|
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 ||
|
|
|
|
MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) {
|
|
|
|
bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64;
|
|
|
|
|
|
|
|
unsigned dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned ptrA = MI->getOperand(1).getReg();
|
|
|
|
unsigned ptrB = MI->getOperand(2).getReg();
|
|
|
|
unsigned incr = MI->getOperand(3).getReg();
|
|
|
|
|
|
|
|
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(It, loopMBB);
|
|
|
|
F->insert(It, exitMBB);
|
|
|
|
exitMBB->transferSuccessors(BB);
|
|
|
|
|
|
|
|
MachineRegisterInfo &RegInfo = F->getRegInfo();
|
|
|
|
unsigned TmpReg = RegInfo.createVirtualRegister(
|
|
|
|
is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
|
|
|
|
(const TargetRegisterClass *) &PPC::G8RCRegClass);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loopMBB
|
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
|
|
|
|
// loopMBB:
|
|
|
|
// l[wd]arx dest, ptr
|
|
|
|
// add r0, dest, incr
|
|
|
|
// st[wd]cx. r0, ptr
|
|
|
|
// bne- loopMBB
|
|
|
|
// fallthrough --> exitMBB
|
|
|
|
BB = loopMBB;
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
|
|
|
|
.addReg(ptrA).addReg(ptrB);
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), TmpReg)
|
|
|
|
.addReg(incr).addReg(dest);
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
|
|
|
|
.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
|
|
|
|
BuildMI(BB, TII->get(PPC::BCC))
|
|
|
|
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
|
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
BB->addSuccessor(exitMBB);
|
|
|
|
|
|
|
|
// exitMBB:
|
|
|
|
// ...
|
|
|
|
BB = exitMBB;
|
|
|
|
}
|
|
|
|
else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
|
|
|
|
MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
|
|
|
|
bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
|
|
|
|
|
|
|
|
unsigned dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned ptrA = MI->getOperand(1).getReg();
|
|
|
|
unsigned ptrB = MI->getOperand(2).getReg();
|
|
|
|
unsigned oldval = MI->getOperand(3).getReg();
|
|
|
|
unsigned newval = MI->getOperand(4).getReg();
|
|
|
|
|
|
|
|
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(It, loopMBB);
|
|
|
|
F->insert(It, exitMBB);
|
|
|
|
exitMBB->transferSuccessors(BB);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loopMBB
|
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
|
|
|
|
// loopMBB:
|
|
|
|
// l[wd]arx dest, ptr
|
|
|
|
// cmp[wd] dest, oldval
|
|
|
|
// bne- exitMBB
|
|
|
|
// st[wd]cx. newval, ptr
|
|
|
|
// bne- loopMBB
|
|
|
|
// fallthrough --> exitMBB
|
|
|
|
BB = loopMBB;
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
|
|
|
|
.addReg(ptrA).addReg(ptrB);
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
|
|
|
|
.addReg(oldval).addReg(dest);
|
|
|
|
BuildMI(BB, TII->get(PPC::BCC))
|
|
|
|
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(exitMBB);
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
|
|
|
|
.addReg(newval).addReg(ptrA).addReg(ptrB);
|
|
|
|
BuildMI(BB, TII->get(PPC::BCC))
|
|
|
|
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
|
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
BB->addSuccessor(exitMBB);
|
|
|
|
|
|
|
|
// exitMBB:
|
|
|
|
// ...
|
|
|
|
BB = exitMBB;
|
|
|
|
}
|
|
|
|
else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32 ||
|
|
|
|
MI->getOpcode() == PPC::ATOMIC_SWAP_I64) {
|
|
|
|
bool is64bit = MI->getOpcode() == PPC::ATOMIC_SWAP_I64;
|
|
|
|
|
|
|
|
unsigned dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned ptrA = MI->getOperand(1).getReg();
|
|
|
|
unsigned ptrB = MI->getOperand(2).getReg();
|
|
|
|
unsigned newval = MI->getOperand(3).getReg();
|
|
|
|
|
|
|
|
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(It, loopMBB);
|
|
|
|
F->insert(It, exitMBB);
|
|
|
|
exitMBB->transferSuccessors(BB);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loopMBB
|
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
|
|
|
|
// loopMBB:
|
|
|
|
// l[wd]arx dest, ptr
|
|
|
|
// st[wd]cx. newval, ptr
|
|
|
|
// bne- loopMBB
|
|
|
|
// fallthrough --> exitMBB
|
|
|
|
BB = loopMBB;
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
|
|
|
|
.addReg(ptrA).addReg(ptrB);
|
|
|
|
BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
|
|
|
|
.addReg(newval).addReg(ptrA).addReg(ptrB);
|
|
|
|
BuildMI(BB, TII->get(PPC::BCC))
|
|
|
|
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
|
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
BB->addSuccessor(exitMBB);
|
|
|
|
|
|
|
|
// exitMBB:
|
|
|
|
// ...
|
|
|
|
BB = exitMBB;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
assert(0 && "Unexpected instr type to insert");
|
|
|
|
}
|
2005-08-26 21:23:58 +00:00
|
|
|
|
2008-07-07 23:14:23 +00:00
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
2005-08-26 21:23:58 +00:00
|
|
|
return BB;
|
|
|
|
}
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Target Optimization Hooks
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-03-01 04:57:39 +00:00
|
|
|
SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
|
|
|
|
DAGCombinerInfo &DCI) const {
|
|
|
|
TargetMachine &TM = getTargetMachine();
|
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default: break;
|
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
like:
long long test(long long X, int Y) {
return 1ULL << Y;
}
long long test2(long long X, int Y) {
return -1LL << Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-19 05:22:59 +00:00
|
|
|
case PPCISD::SHL:
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
|
|
|
|
if (C->getValue() == 0) // 0 << V -> 0.
|
|
|
|
return N->getOperand(0);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case PPCISD::SRL:
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
|
|
|
|
if (C->getValue() == 0) // 0 >>u V -> 0.
|
|
|
|
return N->getOperand(0);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case PPCISD::SRA:
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
|
|
|
|
if (C->getValue() == 0 || // 0 >>s V -> 0.
|
|
|
|
C->isAllOnesValue()) // -1 >>s V -> -1.
|
|
|
|
return N->getOperand(0);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2006-03-01 04:57:39 +00:00
|
|
|
case ISD::SINT_TO_FP:
|
2006-06-16 17:34:12 +00:00
|
|
|
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
|
|
|
|
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
|
|
|
|
// We allow the src/dst to be either f32/f64, but the intermediate
|
|
|
|
// type must be i64.
|
2007-10-23 23:20:14 +00:00
|
|
|
if (N->getOperand(0).getValueType() == MVT::i64 &&
|
|
|
|
N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
SDOperand Val = N->getOperand(0).getOperand(0);
|
|
|
|
if (Val.getValueType() == MVT::f32) {
|
|
|
|
Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
|
|
|
|
DCI.AddToWorklist(Val.Val);
|
|
|
|
}
|
|
|
|
|
|
|
|
Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
|
2006-03-01 04:57:39 +00:00
|
|
|
DCI.AddToWorklist(Val.Val);
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
|
2006-03-01 04:57:39 +00:00
|
|
|
DCI.AddToWorklist(Val.Val);
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
if (N->getValueType(0) == MVT::f32) {
|
2008-01-17 07:00:52 +00:00
|
|
|
Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
|
|
|
|
DAG.getIntPtrConstant(0));
|
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
|
|
|
DCI.AddToWorklist(Val.Val);
|
|
|
|
}
|
|
|
|
return Val;
|
|
|
|
} else if (N->getOperand(0).getValueType() == MVT::i32) {
|
|
|
|
// If the intermediate type is i32, we can avoid the load/store here
|
|
|
|
// too.
|
2006-03-01 04:57:39 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2006-03-01 05:50:56 +00:00
|
|
|
case ISD::STORE:
|
|
|
|
// Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
|
|
|
|
if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
|
2008-01-18 16:54:56 +00:00
|
|
|
!cast<StoreSDNode>(N)->isTruncatingStore() &&
|
2006-03-01 05:50:56 +00:00
|
|
|
N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
|
2007-10-23 23:20:14 +00:00
|
|
|
N->getOperand(1).getValueType() == MVT::i32 &&
|
|
|
|
N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
|
2006-03-01 05:50:56 +00:00
|
|
|
SDOperand Val = N->getOperand(1).getOperand(0);
|
|
|
|
if (Val.getValueType() == MVT::f32) {
|
|
|
|
Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
|
|
|
|
DCI.AddToWorklist(Val.Val);
|
|
|
|
}
|
|
|
|
Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
|
|
|
|
DCI.AddToWorklist(Val.Val);
|
|
|
|
|
|
|
|
Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
|
|
|
|
N->getOperand(2), N->getOperand(3));
|
|
|
|
DCI.AddToWorklist(Val.Val);
|
|
|
|
return Val;
|
|
|
|
}
|
2006-07-10 20:56:58 +00:00
|
|
|
|
|
|
|
// Turn STORE (BSWAP) -> sthbrx/stwbrx.
|
|
|
|
if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
|
|
|
|
N->getOperand(1).Val->hasOneUse() &&
|
|
|
|
(N->getOperand(1).getValueType() == MVT::i32 ||
|
|
|
|
N->getOperand(1).getValueType() == MVT::i16)) {
|
|
|
|
SDOperand BSwapOp = N->getOperand(1).getOperand(0);
|
|
|
|
// Do an any-extend to 32-bits if this is a half-word input.
|
|
|
|
if (BSwapOp.getValueType() == MVT::i16)
|
|
|
|
BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
|
|
|
|
|
|
|
|
return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
|
|
|
|
N->getOperand(2), N->getOperand(3),
|
|
|
|
DAG.getValueType(N->getOperand(1).getValueType()));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ISD::BSWAP:
|
|
|
|
// Turn BSWAP (LOAD) -> lhbrx/lwbrx.
|
2006-10-09 20:57:25 +00:00
|
|
|
if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
|
2006-07-10 20:56:58 +00:00
|
|
|
N->getOperand(0).hasOneUse() &&
|
|
|
|
(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
|
|
|
|
SDOperand Load = N->getOperand(0);
|
2006-10-09 20:57:25 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(Load);
|
2006-07-10 20:56:58 +00:00
|
|
|
// Create the byte-swapping load.
|
2008-06-06 12:08:01 +00:00
|
|
|
std::vector<MVT> VTs;
|
2006-07-10 20:56:58 +00:00
|
|
|
VTs.push_back(MVT::i32);
|
|
|
|
VTs.push_back(MVT::Other);
|
2008-02-06 22:27:42 +00:00
|
|
|
SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
|
2006-08-11 17:18:05 +00:00
|
|
|
SDOperand Ops[] = {
|
2006-10-09 20:57:25 +00:00
|
|
|
LD->getChain(), // Chain
|
|
|
|
LD->getBasePtr(), // Ptr
|
2008-02-06 22:27:42 +00:00
|
|
|
MO, // MemOperand
|
2006-08-11 17:18:05 +00:00
|
|
|
DAG.getValueType(N->getValueType(0)) // VT
|
|
|
|
};
|
|
|
|
SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
|
2006-07-10 20:56:58 +00:00
|
|
|
|
|
|
|
// If this is an i16 load, insert the truncate.
|
|
|
|
SDOperand ResVal = BSLoad;
|
|
|
|
if (N->getValueType(0) == MVT::i16)
|
|
|
|
ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
|
|
|
|
|
|
|
|
// First, combine the bswap away. This makes the value produced by the
|
|
|
|
// load dead.
|
|
|
|
DCI.CombineTo(N, ResVal);
|
|
|
|
|
|
|
|
// Next, combine the load away, we give it a bogus result value but a real
|
|
|
|
// chain result. The result value is dead because the bswap is dead.
|
|
|
|
DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
|
|
|
|
|
|
|
|
// Return N so it doesn't get rechecked!
|
|
|
|
return SDOperand(N, 0);
|
|
|
|
}
|
|
|
|
|
2006-03-01 05:50:56 +00:00
|
|
|
break;
|
Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 06:02:07 +00:00
|
|
|
case PPCISD::VCMP: {
|
|
|
|
// If a VCMPo node already exists with exactly the same operands as this
|
|
|
|
// node, use its result instead of this node (VCMPo computes both a CR6 and
|
|
|
|
// a normal output).
|
|
|
|
//
|
|
|
|
if (!N->getOperand(0).hasOneUse() &&
|
|
|
|
!N->getOperand(1).hasOneUse() &&
|
|
|
|
!N->getOperand(2).hasOneUse()) {
|
|
|
|
|
|
|
|
// Scan all of the users of the LHS, looking for VCMPo's that match.
|
|
|
|
SDNode *VCMPoNode = 0;
|
|
|
|
|
|
|
|
SDNode *LHSN = N->getOperand(0).Val;
|
|
|
|
for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
|
|
|
|
UI != E; ++UI)
|
2008-04-07 10:06:32 +00:00
|
|
|
if ((*UI).getUser()->getOpcode() == PPCISD::VCMPo &&
|
|
|
|
(*UI).getUser()->getOperand(1) == N->getOperand(1) &&
|
|
|
|
(*UI).getUser()->getOperand(2) == N->getOperand(2) &&
|
|
|
|
(*UI).getUser()->getOperand(0) == N->getOperand(0)) {
|
|
|
|
VCMPoNode = UI->getUser();
|
Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 06:02:07 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-04-18 18:28:22 +00:00
|
|
|
// If there is no VCMPo node, or if the flag value has a single use, don't
|
|
|
|
// transform this.
|
|
|
|
if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Look at the (necessarily single) use of the flag value. If it has a
|
|
|
|
// chain, this transformation is more complex. Note that multiple things
|
|
|
|
// could use the value result, which we should ignore.
|
|
|
|
SDNode *FlagUser = 0;
|
|
|
|
for (SDNode::use_iterator UI = VCMPoNode->use_begin();
|
|
|
|
FlagUser == 0; ++UI) {
|
|
|
|
assert(UI != VCMPoNode->use_end() && "Didn't find user!");
|
2008-04-07 10:06:32 +00:00
|
|
|
SDNode *User = UI->getUser();
|
2006-04-18 18:28:22 +00:00
|
|
|
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
|
|
|
|
if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
|
|
|
|
FlagUser = User;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the user is a MFCR instruction, we know this is safe. Otherwise we
|
|
|
|
// give up for right now.
|
|
|
|
if (FlagUser->getOpcode() == PPCISD::MFCR)
|
Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 06:02:07 +00:00
|
|
|
return SDOperand(VCMPoNode, 0);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
case ISD::BR_CC: {
|
|
|
|
// If this is a branch on an altivec predicate comparison, lower this so
|
|
|
|
// that we don't have to do a MFCR: instead, branch directly on CR6. This
|
|
|
|
// lowering is done pre-legalize, because the legalizer lowers the predicate
|
|
|
|
// compare down to code that is difficult to reassemble.
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
|
|
|
|
SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
|
|
|
|
int CompareOpc;
|
|
|
|
bool isDot;
|
|
|
|
|
|
|
|
if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
|
|
|
|
isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
|
|
|
|
getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
|
|
|
|
assert(isDot && "Can't compare against a vector result!");
|
|
|
|
|
|
|
|
// If this is a comparison against something other than 0/1, then we know
|
|
|
|
// that the condition is never/always true.
|
|
|
|
unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
|
|
|
|
if (Val != 0 && Val != 1) {
|
|
|
|
if (CC == ISD::SETEQ) // Cond never true, remove branch.
|
|
|
|
return N->getOperand(0);
|
|
|
|
// Always !=, turn it into an unconditional branch.
|
|
|
|
return DAG.getNode(ISD::BR, MVT::Other,
|
|
|
|
N->getOperand(0), N->getOperand(4));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
|
|
|
|
|
|
|
|
// Create the PPCISD altivec 'dot' comparison node.
|
2008-06-06 12:08:01 +00:00
|
|
|
std::vector<MVT> VTs;
|
2006-08-11 17:18:05 +00:00
|
|
|
SDOperand Ops[] = {
|
|
|
|
LHS.getOperand(2), // LHS of compare
|
|
|
|
LHS.getOperand(3), // RHS of compare
|
|
|
|
DAG.getConstant(CompareOpc, MVT::i32)
|
|
|
|
};
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
VTs.push_back(LHS.getOperand(2).getValueType());
|
|
|
|
VTs.push_back(MVT::Flag);
|
2006-08-11 17:18:05 +00:00
|
|
|
SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
|
|
|
|
// Unpack the result based on how the target uses it.
|
2006-11-17 22:10:59 +00:00
|
|
|
PPC::Predicate CompOpc;
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
|
|
|
|
default: // Can't happen, don't crash on invalid number though.
|
|
|
|
case 0: // Branch on the value of the EQ bit of CR6.
|
2006-11-17 22:10:59 +00:00
|
|
|
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
break;
|
|
|
|
case 1: // Branch on the inverted value of the EQ bit of CR6.
|
2006-11-17 22:10:59 +00:00
|
|
|
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
break;
|
|
|
|
case 2: // Branch on the value of the LT bit of CR6.
|
2006-11-17 22:10:59 +00:00
|
|
|
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
break;
|
|
|
|
case 3: // Branch on the inverted value of the LT bit of CR6.
|
2006-11-17 22:10:59 +00:00
|
|
|
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
|
|
|
|
DAG.getConstant(CompOpc, MVT::i32),
|
2006-11-17 22:37:34 +00:00
|
|
|
DAG.getRegister(PPC::CR6, MVT::i32),
|
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
|
|
|
N->getOperand(4), CompNode.getValue(1));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2006-03-01 04:57:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-04-14 06:01:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Inline Assembly Support
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-04-02 06:26:07 +00:00
|
|
|
void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
|
2008-02-13 22:28:48 +00:00
|
|
|
const APInt &Mask,
|
2008-02-13 00:35:47 +00:00
|
|
|
APInt &KnownZero,
|
|
|
|
APInt &KnownOne,
|
2007-06-22 14:59:07 +00:00
|
|
|
const SelectionDAG &DAG,
|
2006-04-02 06:26:07 +00:00
|
|
|
unsigned Depth) const {
|
2008-02-13 00:35:47 +00:00
|
|
|
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
|
2006-04-02 06:26:07 +00:00
|
|
|
switch (Op.getOpcode()) {
|
|
|
|
default: break;
|
2006-07-10 20:56:58 +00:00
|
|
|
case PPCISD::LBRX: {
|
|
|
|
// lhbrx is known to have the top bits cleared out.
|
|
|
|
if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
|
|
|
|
KnownZero = 0xFFFF0000;
|
|
|
|
break;
|
|
|
|
}
|
2006-04-02 06:26:07 +00:00
|
|
|
case ISD::INTRINSIC_WO_CHAIN: {
|
|
|
|
switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
|
|
|
|
default: break;
|
|
|
|
case Intrinsic::ppc_altivec_vcmpbfp_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpeqfp_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequb_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequh_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpequw_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgefp_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtfp_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsb_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsh_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtsw_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtub_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtuh_p:
|
|
|
|
case Intrinsic::ppc_altivec_vcmpgtuw_p:
|
|
|
|
KnownZero = ~1U; // All bits but the low one are known to be zero.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-03-25 02:14:49 +00:00
|
|
|
/// getConstraintType - Given a constraint, return the type of
|
2006-02-07 20:16:30 +00:00
|
|
|
/// constraint it is for this target.
|
|
|
|
PPCTargetLowering::ConstraintType
|
2007-03-25 02:14:49 +00:00
|
|
|
PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
|
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default: break;
|
|
|
|
case 'b':
|
|
|
|
case 'r':
|
|
|
|
case 'f':
|
|
|
|
case 'v':
|
|
|
|
case 'y':
|
|
|
|
return C_RegisterClass;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
2006-02-07 20:16:30 +00:00
|
|
|
}
|
|
|
|
|
2006-11-02 01:44:04 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
|
|
PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT) const {
|
2006-01-31 19:20:21 +00:00
|
|
|
if (Constraint.size() == 1) {
|
2006-11-02 01:44:04 +00:00
|
|
|
// GCC RS6000 Constraint Letters
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
case 'b': // R1-R31
|
|
|
|
case 'r': // R0-R31
|
|
|
|
if (VT == MVT::i64 && PPCSubTarget.isPPC64())
|
|
|
|
return std::make_pair(0U, PPC::G8RCRegisterClass);
|
|
|
|
return std::make_pair(0U, PPC::GPRCRegisterClass);
|
|
|
|
case 'f':
|
|
|
|
if (VT == MVT::f32)
|
|
|
|
return std::make_pair(0U, PPC::F4RCRegisterClass);
|
|
|
|
else if (VT == MVT::f64)
|
|
|
|
return std::make_pair(0U, PPC::F8RCRegisterClass);
|
|
|
|
break;
|
2006-01-31 19:20:21 +00:00
|
|
|
case 'v':
|
2006-11-02 01:44:04 +00:00
|
|
|
return std::make_pair(0U, PPC::VRRCRegisterClass);
|
|
|
|
case 'y': // crrc
|
|
|
|
return std::make_pair(0U, PPC::CRRCRegisterClass);
|
2006-01-31 19:20:21 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-11-02 01:44:04 +00:00
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
2006-01-31 19:20:21 +00:00
|
|
|
}
|
2006-02-07 00:47:13 +00:00
|
|
|
|
2006-11-02 01:44:04 +00:00
|
|
|
|
2007-08-25 00:47:38 +00:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
|
|
|
void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
|
|
|
|
std::vector<SDOperand>&Ops,
|
2008-04-26 23:02:14 +00:00
|
|
|
SelectionDAG &DAG) const {
|
2007-08-25 00:47:38 +00:00
|
|
|
SDOperand Result(0,0);
|
2006-02-07 00:47:13 +00:00
|
|
|
switch (Letter) {
|
|
|
|
default: break;
|
|
|
|
case 'I':
|
|
|
|
case 'J':
|
|
|
|
case 'K':
|
|
|
|
case 'L':
|
|
|
|
case 'M':
|
|
|
|
case 'N':
|
|
|
|
case 'O':
|
|
|
|
case 'P': {
|
2007-05-15 01:31:05 +00:00
|
|
|
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
|
2007-08-25 00:47:38 +00:00
|
|
|
if (!CST) return; // Must be an immediate to match.
|
2007-05-15 01:31:05 +00:00
|
|
|
unsigned Value = CST->getValue();
|
2006-02-07 00:47:13 +00:00
|
|
|
switch (Letter) {
|
|
|
|
default: assert(0 && "Unknown constraint letter!");
|
|
|
|
case 'I': // "I" is a signed 16-bit constant.
|
2007-05-15 01:31:05 +00:00
|
|
|
if ((short)Value == (int)Value)
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
|
|
|
|
case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
|
2007-05-15 01:31:05 +00:00
|
|
|
if ((short)Value == 0)
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
|
2007-05-15 01:31:05 +00:00
|
|
|
if ((Value >> 16) == 0)
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
case 'M': // "M" is a constant that is greater than 31.
|
2007-05-15 01:31:05 +00:00
|
|
|
if (Value > 31)
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
case 'N': // "N" is a positive constant that is an exact power of two.
|
2007-05-15 01:31:05 +00:00
|
|
|
if ((int)Value > 0 && isPowerOf2_32(Value))
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
case 'O': // "O" is the constant zero.
|
2007-05-15 01:31:05 +00:00
|
|
|
if (Value == 0)
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
|
2007-05-15 01:31:05 +00:00
|
|
|
if ((short)-Value == (int)-Value)
|
2007-08-25 00:47:38 +00:00
|
|
|
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
2006-10-31 19:40:43 +00:00
|
|
|
break;
|
2006-02-07 00:47:13 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-08-25 00:47:38 +00:00
|
|
|
if (Result.Val) {
|
|
|
|
Ops.push_back(Result);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2006-02-07 00:47:13 +00:00
|
|
|
// Handle standard constraint letters.
|
2007-08-25 00:47:38 +00:00
|
|
|
TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
|
2006-02-07 00:47:13 +00:00
|
|
|
}
|
2006-03-13 23:20:37 +00:00
|
|
|
|
2007-03-30 23:15:24 +00:00
|
|
|
// isLegalAddressingMode - Return true if the addressing mode represented
|
|
|
|
// by AM is legal for this target, for a load/store of the specified type.
|
|
|
|
bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
|
|
|
|
const Type *Ty) const {
|
|
|
|
// FIXME: PPC does not allow r+i addressing modes for vectors!
|
|
|
|
|
|
|
|
// PPC allows a sign-extended 16-bit immediate field.
|
|
|
|
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// No global is ever allowed as a base.
|
|
|
|
if (AM.BaseGV)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// PPC only support r+r,
|
|
|
|
switch (AM.Scale) {
|
|
|
|
case 0: // "r+i" or just "i", depending on HasBaseReg.
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
|
|
|
|
return false;
|
|
|
|
// Otherwise we have r+r or r+i.
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
|
|
|
|
return false;
|
|
|
|
// Allow 2*r as r+r.
|
|
|
|
break;
|
2007-04-09 22:10:05 +00:00
|
|
|
default:
|
|
|
|
// No other scales are supported.
|
|
|
|
return false;
|
2007-03-30 23:15:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-03-13 23:20:37 +00:00
|
|
|
/// isLegalAddressImmediate - Return true if the integer value can be used
|
2007-03-12 23:29:01 +00:00
|
|
|
/// as the offset of the target addressing mode for load / store of the
|
|
|
|
/// given type.
|
|
|
|
bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
|
2006-03-13 23:20:37 +00:00
|
|
|
// PPC allows a sign-extended 16-bit immediate field.
|
|
|
|
return (V > -(1 << 16) && V < (1 << 16)-1);
|
|
|
|
}
|
2006-08-28 01:02:49 +00:00
|
|
|
|
|
|
|
bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
|
2007-03-30 23:15:24 +00:00
|
|
|
return false;
|
2006-08-28 01:02:49 +00:00
|
|
|
}
|
2007-03-01 13:11:38 +00:00
|
|
|
|
2007-12-08 06:59:59 +00:00
|
|
|
SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
// Depths > 0 not supported yet!
|
|
|
|
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
|
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
2008-04-30 09:16:33 +00:00
|
|
|
|
2007-12-08 06:59:59 +00:00
|
|
|
// Just load the return address off the stack.
|
2008-04-30 09:16:33 +00:00
|
|
|
SDOperand RetAddrFI = getReturnAddrFrameIndex(DAG);
|
|
|
|
|
|
|
|
// Make sure the function really does not optimize away the store of the RA
|
|
|
|
// to the stack.
|
|
|
|
FuncInfo->setLRStoreRequired();
|
2007-12-08 06:59:59 +00:00
|
|
|
return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
|
2007-03-01 13:11:38 +00:00
|
|
|
// Depths > 0 not supported yet!
|
|
|
|
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
|
|
|
|
return SDOperand();
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
2007-03-01 13:11:38 +00:00
|
|
|
bool isPPC64 = PtrVT == MVT::i64;
|
|
|
|
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
|
|
|
|
&& MFI->getStackSize();
|
|
|
|
|
|
|
|
if (isPPC64)
|
|
|
|
return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
|
2007-08-30 00:59:19 +00:00
|
|
|
MVT::i64);
|
2007-03-01 13:11:38 +00:00
|
|
|
else
|
|
|
|
return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
|
|
|
|
MVT::i32);
|
|
|
|
}
|