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5704 Commits

Author SHA1 Message Date
Evan Cheng
63d3300da1 - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 08:01:21 +00:00
Chris Lattner
c04b423f14 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26950 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 07:33:46 +00:00
Evan Cheng
2da953f77a Fix PSHUF* and SHUF* jit code emission problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26949 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 07:10:28 +00:00
Chris Lattner
9d86a9dff2 This has been implemented. Tweak it into another note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26944 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:33:23 +00:00
Chris Lattner
ecfe55e65b When possible, custom lower 32-bit SINT_TO_FP to this: 
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:30:33 +00:00
Chris Lattner
e5ba580ab0 Add support for "ri" addressing modes where the immediate is a 14-bit field 
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:26:03 +00:00
Chris Lattner
6df1154644 fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26941 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 04:18:34 +00:00
Evan Cheng
b9df0ca67b Some splat and shuffle support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 02:53:00 +00:00
Evan Cheng
a9f2a717e9 Add a couple more pseudo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26939 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 02:52:03 +00:00
Chris Lattner
eb8b09f69f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 01:44:36 +00:00
Evan Cheng
4a7da36546 Didn't mean to check this in. No MMX support yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26933 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 23:04:23 +00:00
Evan Cheng
48090aa814 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 23:01:21 +00:00
Chris Lattner
9b3bd467d0 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:51:05 +00:00
Chris Lattner
f3ce43210a Don't emit pseudo instructions! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26926 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:19:37 +00:00
Nate Begeman
c0a8b6df2a Update readme 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26924 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 18:58:20 +00:00
Chris Lattner
13feb58aa1 Print absolute memory references like this: 
lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26922 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 17:21:13 +00:00
Evan Cheng
7ab54047e7 Combine 2 entries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26921 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:18:26 +00:00
Evan Cheng
50a6d8c835 Add a note about x86 register coallescing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26920 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:12:57 +00:00
Evan Cheng
82521dd838 - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:09:35 +00:00
Chris Lattner
8151914321 With Evan's latest tblgen patch, this code is obsolete, thanks Evan! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 06:37:40 +00:00
Chris Lattner
8593f9891d When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:51:38 +00:00
Chris Lattner
ef040dd4a3 minor note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26912 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:47:09 +00:00
Evan Cheng
811ec1c92a x86 ISD::SCALAR_TO_VECTOR support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26911 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:33:35 +00:00
Evan Cheng
5c791c8ba4 Junk unused vector register classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26910 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:30:59 +00:00
Chris Lattner
d97964457e Handle constant addresses more efficiently, folding the low bits into the 
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 22:38:22 +00:00
Chris Lattner
23baa1b310 remove dead variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 22:37:23 +00:00
Chris Lattner
bd83afd3cd Fix a couple of bugs in permute/splat generate, thanks to Nate for actually 
figuring these out! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 18:26:51 +00:00
Chris Lattner
e376e00247 reenable this hack, the tblgen version isn't quite ready 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 17:54:43 +00:00
Chris Lattner
32f57d9e26 Fix the pattern for VADDUWM, add i32 splat 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 17:51:58 +00:00
Evan Cheng
e63d746ef6 Use tblgen'd VECTOR_SHUFFLE selection code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 08:14:16 +00:00
Chris Lattner
dd4d2d0e40 Add support for generating vspltw, instead of a vperm instruction with a 
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:51:10 +00:00
Chris Lattner
88a99ef7cc Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26897 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:37:44 +00:00
Chris Lattner
ef819f8fbb fix duplicate definition errors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26896 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:33:01 +00:00
Chris Lattner
39afef3150 Add a build_vector node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26895 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:18:01 +00:00
Chris Lattner
3c0f9cc90c Check in some intermediate code that adds a skeleton for matching vsplt* 
instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:15:45 +00:00
Evan Cheng
ba753c61b7 Move a few things around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26893 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:04:52 +00:00
Chris Lattner
fa818d0b8b add vector_shuffle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26891 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 05:40:45 +00:00
Chris Lattner
08e25de4d3 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 05:05:55 +00:00
Chris Lattner
556aae0df0 add vsplat instructions, fix sched description for vperm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 04:47:33 +00:00
Chris Lattner
f1d0b2beda Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. 
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:53 +00:00
Chris Lattner
2bc6dc27e9 Claim to have v16i8 for perm masks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26886 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:02 +00:00
Chris Lattner
abdff1ee6d add the vperm instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:00:56 +00:00
Chris Lattner
8bcf926277 add a note with a testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26877 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 22:27:41 +00:00
Chris Lattner
28097d086f Add a note about the MUL -> FMADD vector bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26874 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 22:08:08 +00:00
Evan Cheng
c12e6c488e Vector undef's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26870 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 09:38:54 +00:00
Chris Lattner
b2177b9405 Custom lower SCALAR_TO_VECTOR into lve*x. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:55:52 +00:00
Chris Lattner
ab515b09bf PPC doesn't have SCALAR_TO_VECTOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26865 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:17:19 +00:00
Chris Lattner
528180ed7b add support for vector undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:10:09 +00:00
Evan Cheng
d3864b5743 Remind us of exit value substitution 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26862 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:09:23 +00:00
Evan Cheng
5fef51e9aa Turning on LSR by default 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26861 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:08:49 +00:00
Evan Cheng
0def9c3d7d Remember which tests are hurt by LSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26860 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:08:11 +00:00
Chris Lattner
a17409dfd6 minor fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:43:01 +00:00
Chris Lattner
28b1a0b532 notes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:33:30 +00:00
Chris Lattner
0a7bff01d0 we don't use lmw/stmw. When we want them they are easy enough to add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26853 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 04:33:37 +00:00
Chris Lattner
a064d28843 rename these nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 01:13:28 +00:00
Evan Cheng
2246f8449f Use the generic vector register classes VR64 / VR128 rather than V4F32, 
V8I16, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26838 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-18 01:23:20 +00:00
Nate Begeman
79691bc1f3 Fix subfic to match subc by default instead of sub so that it is correctly 
cost-modeled as producing a flag.  This fixes the test I just added for neg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 22:41:37 +00:00
Evan Cheng
df57fa0c7d Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26833 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 20:31:41 +00:00
Evan Cheng
06a8aa14b3 Move some pattern fragments to the right files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26831 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 19:55:52 +00:00
Chris Lattner
89fad2c3b2 Disable x86 fastcc from passing args in registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26824 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 17:27:47 +00:00
Chris Lattner
1c636e9d98 Parameterize the number of integer arguments to pass in registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26818 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 05:10:20 +00:00
Evan Cheng
8586b953a0 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26817 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 02:36:22 +00:00
Evan Cheng
5bd4d48c24 Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. 
ADD32ri8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26816 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 02:25:01 +00:00
Evan Cheng
7f31ad39fb - Nuke 16-bit SBB instructions. We'll never use them. 
- Nuke a bogus comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26815 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 02:24:04 +00:00
Nate Begeman
81e8097377 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 01:40:33 +00:00
Chris Lattner
e261c474ca remove dead variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26813 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 23:52:08 +00:00
Evan Cheng
2771d21c50 A new entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26810 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:44:22 +00:00
Nate Begeman
1ad9b3a3cc Notes on how to kill the eeevil brtwoway, and make ppc branch selector 
more target independant, generate better code, and be less conservative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26809 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:37:48 +00:00
Chris Lattner
be80fc8d09 Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26808 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:35:59 +00:00
Chris Lattner
ed51169cd8 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26807 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:25:55 +00:00
Chris Lattner
9c09c9ec9d teach the ppc backend how to spill/reload vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:24:02 +00:00
Chris Lattner
419ed53006 add callee saved vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26805 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:07:06 +00:00
Evan Cheng
2221de9cc1 Bug fix: condition inverted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26804 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:02:48 +00:00
Evan Cheng
714554d707 Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:47:42 +00:00
Chris Lattner
8aa777d5ea in functions that use a lot of callee saved regs, this can be more than 
5 instructions away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26801 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:31:45 +00:00
Chris Lattner
335fd3c7c2 Add support for copying registers. still needed: spilling and reloading them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 20:03:58 +00:00
Nate Begeman
2df992883b Another case we could do better on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26795 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 18:50:44 +00:00
Chris Lattner
4bb1895072 Save/restore VRSAVE once per function, not once per block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26793 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 18:25:23 +00:00
Chris Lattner
c29e12674b add support for the bitconvert node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26789 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 01:29:53 +00:00
Nate Begeman
133decdceb Update scheduling info for vrsave instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26776 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-15 05:25:05 +00:00
Chris Lattner
cbd3cdd239 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26762 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-14 19:31:24 +00:00
Chris Lattner
a08610c8a5 Fix an off by one error that caused PPC LLC failures last night. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26758 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-14 17:56:49 +00:00
Chris Lattner
ad5a3a0265 transformation implemented 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26754 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-14 06:57:34 +00:00
Evan Cheng
9c543b2299 PPC LSR pass should use target lowering hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26743 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:56:51 +00:00
Evan Cheng
c4c6257c1a Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:20:37 +00:00
Evan Cheng
e617b085fe Update 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26741 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:19:10 +00:00
Evan Cheng
30b37b5f29 Add LSR hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:18:16 +00:00
Chris Lattner
872421553e Handle builtins that directly correspond to GCC builtins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26737 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:09:05 +00:00
Chris Lattner
1877ec9b02 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 21:52:10 +00:00
Jim Laskey
f4321a3a43 Handle the removal of the debug chain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26729 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 13:07:37 +00:00
Chris Lattner
2e8a77ff42 remove two implemented items 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26728 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 06:52:22 +00:00
Chris Lattner
64ce964673 Fix a couple of bugs that broke the alpha tester build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26722 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:23:59 +00:00
Chris Lattner
3faad495bc Handle cracked instructions in dispatch group formation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26721 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:20:04 +00:00
Chris Lattner
fd97734f36 Mark instructions that are cracked by the PPC970 decoder as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:15:10 +00:00
Chris Lattner
88d211f823 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-12 09:13:49 +00:00
Chris Lattner
9c2c38674a blr is a branch too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26710 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-11 21:49:49 +00:00
Chris Lattner
74cfb7d7b3 add an example 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26709 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-11 20:20:40 +00:00
Chris Lattner
c20995e070 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26708 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-11 20:17:08 +00:00
Chris Lattner
e928a72772 teach the JIT to encode vector registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26697 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 20:19:50 +00:00
Evan Cheng
627fb57e19 Add option -enable-x86-lsr to enable x86 loop strength reduction pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26665 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 21:51:28 +00:00
Chris Lattner
82c78b2f7e add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26661 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 20:13:21 +00:00
Andrew Lenharth
ddc877ccae these are copies too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26653 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 18:18:51 +00:00
Chris Lattner
79cdfa3ee2 remove some now-dead code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26652 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 18:07:49 +00:00
Andrew Lenharth
e5b71d0715 fcopysign for mixed mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26651 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:56:33 +00:00
Andrew Lenharth
d26b8f97c4 relax fcopysign 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26649 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:47:22 +00:00
Andrew Lenharth
283f22275a alpha and llvm have different oppinions on which arg is the sign bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26647 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:41:50 +00:00
Andrew Lenharth
017c556efc Alpha Scheduling classes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26643 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:16:45 +00:00
Andrew Lenharth
13beebb25b fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26641 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 14:58:25 +00:00
Andrew Lenharth
97d74aac35 fcopysign support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26640 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 14:57:36 +00:00
Chris Lattner
04f9674857 Add support for 'special' llvm globals like debug info and static ctors/dtors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26628 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 06:14:35 +00:00
Chris Lattner
181b9c6a2a a couple of miscellaneous things. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26625 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 01:39:46 +00:00
Jim Laskey
7075d6f2f2 Add #line support for CBE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26621 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 19:31:15 +00:00
Duraid Madina
1ffd41ab99 doo de doo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26614 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 06:18:46 +00:00
Chris Lattner
b0d21ef20c Change the interface for getting a target HazardRecognizer to be more clean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 04:25:59 +00:00
Chris Lattner
49f398b96a add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26605 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 00:25:47 +00:00
Evan Cheng
9925642ec5 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26604 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 23:34:23 +00:00
Evan Cheng
ff909926e2 Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest. 
and variable value.
Similarly for memcpy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 23:29:39 +00:00
Chris Lattner
9a571ba823 Two things: 
1. Don't emit debug info, or other llvm.metadata to the .cbe.c file.
2. Mark static ctors/dtors as such, so that bugpoint works on C++ code
   compiled with the new CFE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26602 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 22:58:23 +00:00
Jim Laskey
7809811e4e Use "llvm.metadata" section for debug globals. Filter out these globals in the 
asm printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26599 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 22:00:35 +00:00
Chris Lattner
b84225b080 add another missing store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26595 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 16:26:48 +00:00
Chris Lattner
ab5801cb28 add a couple more load/store instrs, add a newline to the end of file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26594 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 16:19:46 +00:00
Nate Begeman
3acbe5d4f0 This kinda sorta implements "things that have to lead a dispatch group". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26591 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 08:30:27 +00:00
Chris Lattner
2046371e70 add some new instructions to the classifier. With this, we correctly insert 
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26590 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 07:14:55 +00:00
Chris Lattner
7ce64852e8 add some comments that describe what we model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26588 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 06:44:19 +00:00
Chris Lattner
c664418820 Implement a very very simple hazard recognizer for LSU rejects and ctr set/read 
flushes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26587 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 06:32:48 +00:00
Chris Lattner
5a63c47fb5 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26585 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 04:42:59 +00:00
Chris Lattner
549f27d235 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26583 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 02:46:26 +00:00
Evan Cheng
d594881a28 - Emit subsections_via_symbols for Darwin. 
- Conditionalize Dwarf debugging output (Darwin only for now).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26582 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 02:23:26 +00:00
Evan Cheng
3c992d291b Enable Dwarf debugging info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26581 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 02:02:57 +00:00
Chris Lattner
bbf1c72d51 implement TII::insertNoop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 23:49:55 +00:00
Chris Lattner
5b0fe7d91d add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26549 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 20:00:08 +00:00
Chris Lattner
9601a86a64 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should 
implement copysign as a native op if they have it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 05:08:37 +00:00
Chris Lattner
a4929df2da add a note for something evan noticed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26539 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 01:15:18 +00:00
Chris Lattner
9f17be690e Implemented. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26536 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 23:33:44 +00:00
Chris Lattner
ad01993194 Add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26523 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 08:44:51 +00:00
Evan Cheng
f42f516984 Add an entry 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26520 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 07:49:50 +00:00
Evan Cheng
62bec2ca4c MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of 
rep/stos and rep/mov if the count is not a constant. We could do
  rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.

Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26517 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 02:48:56 +00:00
Chris Lattner
b27b69f283 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26513 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 01:19:34 +00:00
Evan Cheng
8df346b4e8 Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26512 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 01:12:00 +00:00
Chris Lattner
a8309ae1cb Split the valuetypes out of Target.td into ValueTypes.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26490 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 01:55:26 +00:00
Chris Lattner
41edaa0529 remove the read/write port/io intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 00:19:58 +00:00
Chris Lattner
89188a1096 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26472 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-02 22:34:38 +00:00
Chris Lattner
0f6ab6ff97 Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 07:14:48 +00:00
Chris Lattner
00d18f0879 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 06:36:20 +00:00
Chris Lattner
5126984b1d Compile this: 
void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 05:50:56 +00:00
Chris Lattner
8c13d0a573 Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 04:57:39 +00:00
Evan Cheng
d30bf01e90 Vector op lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 01:11:20 +00:00
Evan Cheng
f338dd881f New type v2f32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26435 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 01:06:22 +00:00
Evan Cheng
aafc1412b1 Another entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26430 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 23:38:49 +00:00
Evan Cheng
8c03fe4aca Don't match x << 1 to LEAL. It's better to emit x + x. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26429 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 21:13:57 +00:00
Chris Lattner
bf751e2d6f Add a subtarget feature for the stfiwx instruction. I know the G5 has it, 
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 07:08:22 +00:00
Chris Lattner
f4c8575c27 remove implemented item 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 06:36:04 +00:00
Nate Begeman
6e53ceb0d4 readme updates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 22:08:36 +00:00
Chris Lattner
a34544d96c Don't print constant initializers, they may span lines now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26403 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 20:09:23 +00:00
Jim Laskey
dae29989cf Removed dependency on how operands are printed (want multi-line.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26399 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 10:29:04 +00:00
Evan Cheng
140a4c4868 ConstantPoolIndex is now the displacement portion of the address (rather 
than base).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26382 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-26 09:12:34 +00:00
Evan Cheng
a09bd8190c Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP 
and 2005-05-12-Int64ToFP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26380 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-26 08:28:12 +00:00
Evan Cheng
51a9ed9b41 * Cleaned up addressing mode matching code. 
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 10:09:08 +00:00
Evan Cheng
53f280a30e Updates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26375 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 10:04:07 +00:00
Evan Cheng
71fb834b50 * Allow mul, shl nodes to be codegen'd as LEA (if appropriate). 
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26374 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 10:02:21 +00:00
Evan Cheng
c4ee50c6b9 ConstantPoolIndex is now the displacement field of addressing mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26373 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:56:50 +00:00
Evan Cheng
bbbb2fbbde Added a common about the need for X86ISD::Wrapper. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:55:19 +00:00
Evan Cheng
404cb4f9fa Added an offset field to ConstantPoolSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:54:52 +00:00
Evan Cheng
cb4a38e75d Fix an obvious bug exposed when we are doing 
ADD X, 4
==>
MOV32ri $X+4, ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26366 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 01:37:02 +00:00
Chris Lattner
2c003e26e5 Add memory printing support for PPC. Input memory operands now work with 
inline asms! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26365 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 20:27:40 +00:00
Chris Lattner
e5d8861126 Implement selection of inline asm memory operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 02:13:12 +00:00
Evan Cheng
d0839f3071 PPC JIT relocation model should be DynamicNoPIC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26338 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 22:18:07 +00:00
Evan Cheng
020d2e8e7a - Clean up the lowering and selection code of ConstantPool, GlobalAddress, 
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 20:41:18 +00:00
Chris Lattner
e3f01570c1 Implement the PPC inline asm "L" modifier. This allows us to compile: 
long long test(long long X) {
  __asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
  return X;
}

to:
        foo r2 r3 r2 r3


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26333 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 19:31:10 +00:00
Chris Lattner
e650a6b3f4 "." isn't enough to get a private label on linux, use ".L". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26327 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 05:25:02 +00:00
Chris Lattner
205065ae0c add a small and simple case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26326 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 05:17:43 +00:00
Evan Cheng
3032410f9b A couple of new entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26325 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 02:50:21 +00:00
Evan Cheng
a0ea0539e3 PIC related bug fixes. 
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 02:43:52 +00:00
Evan Cheng
224ec39cab X86 codegen tweak to use lea in another case: 
Suppose base == %eax and it has multiple uses, then instead of
  movl %eax, %ecx
  addl $8, %ecx
use
  leal 8(%eax), %ecx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26323 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 00:13:58 +00:00
Evan Cheng
f1616dadad Missing .globl for weak / link-once .text symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26321 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 23:59:57 +00:00
Evan Cheng
4c1aa86657 - Added option -relocation-model to set relocation model. Valid values include static, pic, 
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 20:19:42 +00:00
Jim Laskey
0420f2aaf9 Coordinate activities with llvm-gcc4 and dwarf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26314 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 19:02:11 +00:00
Evan Cheng
470a6adc78 Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 02:26:30 +00:00
Chris Lattner
1efa40f6a4 split register class handling from explicit physreg handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 00:56:39 +00:00
Chris Lattner
4217ca8dc1 Updates to match change of getRegForInlineAsmConstraint prototype 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 23:11:00 +00:00
Evan Cheng
4e4c71e423 One more round of reorg so sabre doesn't freak out. :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26303 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 20:00:20 +00:00
Evan Cheng
beb07e117d A big more cleaning up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 19:30:30 +00:00
Evan Cheng
bf156d1ae6 Moving things to their proper places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 19:26:52 +00:00
Evan Cheng
ffcb95beab Split instruction info into multiple files, one for each of x87, MMX, and SSE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26300 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 19:13:53 +00:00
Chris Lattner
a1532bc283 missed optzn 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26299 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 18:29:44 +00:00
Chris Lattner
2deb87f201 The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter 
instructions are expensive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26298 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 18:04:32 +00:00
Evan Cheng
747a90d887 Added separate alias instructions for SSE logical ops that operate on non-packed types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26297 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 02:24:38 +00:00
Evan Cheng
7dbc0a3351 Added MMX and XMM packed integer move instructions, movd and movq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26296 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 01:39:57 +00:00
Evan Cheng
933be3318b Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64. 
Added generic vector types: VR64 and VR128.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 01:38:21 +00:00
Evan Cheng
aea20f50e5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-20 22:34:53 +00:00
Evan Cheng
755ee8f9aa Some updates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26292 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-20 19:58:27 +00:00
Evan Cheng
45af8fd8c2 If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take 
advantage of fisttpll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26288 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 07:26:17 +00:00
Evan Cheng
2b15271571 Added fisttp for fp to int conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26283 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 02:36:28 +00:00
Evan Cheng
6428302f3d Disable PIC for JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26281 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 01:49:25 +00:00
Evan Cheng
5e8b5558f7 Jit does not support PIC yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26278 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:57:10 +00:00
Evan Cheng
7ccced634a x86 / Darwin PIC support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:15:05 +00:00
Evan Cheng
d2ee218b49 Moved PICEnabled to include/llvm/Target/TargetOptions.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26272 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:08:58 +00:00
Chris Lattner
c2fe97e726 unbreak the build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26260 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 07:09:27 +00:00
Evan Cheng
5298bcc722 Unbreak x86 be 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26259 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 07:01:52 +00:00
Nate Begeman
551bf3f800 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 05:43:56 +00:00
Chris Lattner
a648df2871 add note about div by power of 2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26253 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 04:20:13 +00:00
Nate Begeman
9c3c2e9686 Whoops, didn't mean to check this in yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26250 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 00:56:19 +00:00
Nate Begeman
c22f357b78 Add a missing and useful pat frag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26249 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 00:51:06 +00:00
Evan Cheng
7634ac4a9b Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers" 
issue. Need to do more experiments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26247 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 00:04:28 +00:00
Nate Begeman
4c5dcf54ff Kill the x86 pattern isel. boom. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 00:03:04 +00:00
Evan Cheng
dc8acb6420 Remove the entry about using movapd for SSE reg-reg moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26245 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 00:00:58 +00:00
Evan Cheng
39d1761c70 pxor (for FLD0SS) encoding was missing the OpSize prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 23:59:30 +00:00
Chris Lattner
6a6eb7b622 Remove the skeleton target, it doesn't produce useful code and there are 
other small targets that do that can be learned from.  They also have
the added advantage of being tested :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 23:14:50 +00:00
Evan Cheng
fe5cb19405 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This 
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26241 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 22:45:17 +00:00
Evan Cheng
19ade3bf9c Use movaps / movapd to spill / restore V4F4 / V2F8 registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26240 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 21:20:26 +00:00
Nate Begeman
368e18d56a Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 21:11:51 +00:00
Evan Cheng
77dea9b3c3 MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26234 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 19:34:41 +00:00
Duraid Madina
00d3d44b75 distinguish between objects and register names, now we can have stuff 
with names like "f84", "in6" etc etc.

this should fix one or two tests


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26232 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 13:12:57 +00:00
Evan Cheng
298ebf2bd8 If the false case is the current basic block, then this is a self loop. 
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 08:27:56 +00:00
Evan Cheng
d51425a82d Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg 
transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26226 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 01:50:02 +00:00
Evan Cheng
18a8452f3d A bit more memset / memcpy optimization. 
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 00:21:07 +00:00
Evan Cheng
fe1c31204e Remove an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26222 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 22:14:34 +00:00
Chris Lattner
5946fef1db new test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26217 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 19:52:06 +00:00
Chris Lattner
45090476be Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires 
it, because this:

.bss
X:
.byte 0

results in the assembler warning: "initialization in bss segment".  Annoying.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26204 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 07:07:14 +00:00
Chris Lattner
6fa1f57c66 Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc. 
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26202 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 06:41:34 +00:00
Evan Cheng
2354f5a46b Remove an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26197 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 01:56:48 +00:00
Evan Cheng
17ef92eda7 Use .zerofill on x86/darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26196 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 01:56:23 +00:00
Evan Cheng
f3f0a9c587 cvtsd2ss / cvtss2sd encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26193 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 00:31:03 +00:00
Evan Cheng
7335f9beea movaps, movapd encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26192 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 00:11:37 +00:00
Chris Lattner
ae302ab9cb new note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26186 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 22:19:54 +00:00
Chris Lattner
0d7db6f79a If we have zero initialized data with external linkage, use .zerofill to 
emit it (instead of .space), saving a bit of space in the .o file.

For example:
int foo[100];
int bar[100] = {};

when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space.  The X86 backend can also do this on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26185 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 22:18:23 +00:00
Evan Cheng
ee50a1ae27 Don't special case XS, XD prefixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26183 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 21:52:51 +00:00
Evan Cheng
576c141921 Bug fix: XS, XD prefixes were being emitted twice. 
XMM registers were not being handled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26182 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 21:45:24 +00:00
Chris Lattner
33d5082779 Make sure that weak functions are aligned properly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26181 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 20:42:33 +00:00
Evan Cheng
ddf7532442 Duh 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26180 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 20:37:37 +00:00
Evan Cheng
968c178172 Remove -disable-x86-sse 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26179 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 20:30:14 +00:00
Evan Cheng
a03a5dc7ce Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:38:30 +00:00
Evan Cheng
952b7d6a1e Add a entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26173 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:25:32 +00:00
Evan Cheng
87ed716d21 Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and 
maxStoresPerMemMove. Although the last one is not used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26172 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:25:08 +00:00
Evan Cheng
82eaf628b4 Enable SSE (for the right subtargets) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26169 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:07:58 +00:00
Chris Lattner
f9a05329a1 Another hack due to allowing multiple symbols with the same name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26150 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 22:22:42 +00:00
Andrew Lenharth
40ec5037fa improved zap discovery 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26148 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 18:52:29 +00:00
Chris Lattner
94dd29216c Switch targets over to using SelectionDAG::getCALLSEQ_START to create 
CALLSEQ_START nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26143 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 09:00:43 +00:00
Chris Lattner
45b3976db7 Switch to using getCALLSEQ_START instead of using our own creation calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26142 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 08:55:29 +00:00
Nate Begeman
789fd42320 Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/ 
PowerPC/and-imm.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26136 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-12 09:09:52 +00:00
Duraid Madina
b20f97959e fix storing booleans (grawp missed this one) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26120 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-11 07:33:17 +00:00
Duraid Madina
631a140054 now short immediates will get matched (previously constants were all 
triggering movl 64bit imm fat instructions)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26119 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-11 07:32:15 +00:00
Evan Cheng
2486af1b53 Prevent certain nodes that have already been selected from being folded into 
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26117 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-11 02:05:36 +00:00
Evan Cheng
23addc061c Nicer code. :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26111 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-10 22:46:26 +00:00
Evan Cheng
f597dc78f8 Added X86 isel debugging stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26110 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-10 22:24:32 +00:00
Chris Lattner
ad7a3e6208 Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr 
intrinsics.

Autogen frameindex matcher


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26107 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-10 07:35:42 +00:00
Chris Lattner
f613fcb741 Update to new-style flags usage, simplifying the .td file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26106 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-10 06:58:25 +00:00
Evan Cheng
c57e5c17bc Remove a completed entry; add a new entry about fisttp op 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26105 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-10 05:48:15 +00:00
Evan Cheng
7d82d607c5 Match tblgen change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 22:12:53 +00:00
Chris Lattner
f262766619 Done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26091 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 20:00:19 +00:00