Jim Grosbach
06ef444e5c
Add operand encoding bits for SMC and SVC in ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062
More encoding cleanup. Also add register Rd operands for indirect branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7
Simplify some ARM encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5
Add a FIXME. The ADR instruction is a bit odd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03
Add MC encodings for VCVT* instrunctions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
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wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509
Fix encoding for compares. No Rd register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70
Add ARM mode operand encoding information for ADDE/SUBE instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:00:52 +00:00
Rafael Espindola
6d8628061b
Fix another case where we were preferring instructions with large
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immediates instead of 8 bits ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
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8 bit constants can be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 13:31:20 +00:00
Eric Christopher
ede42b0a22
Start handling more global variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 09:11:46 +00:00
Evan Cheng
14ce175216
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 01:54:21 +00:00
Bill Wendling
6932643a37
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
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just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b
Add encodings for VCVT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
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arithmetic-with-carry-in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f
Add VCMPZ and VABS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254
Refactor VCMP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044
Add the rest of the ARM so_reg encoding options (register shifted register)
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and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:53:58 +00:00
Bill Wendling
5a1fd8cf68
Add encodings for VNMUL[SD].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab
Add encodings for VDIV and VMUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:22:27 +00:00
Evan Cheng
3f490f3469
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:19:28 +00:00
Jim Grosbach
2a6a93d542
Move the ARM so_imm encoding into a custom operand encoder and remove the
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explicit handling of the instructions referencing it from the MC code
emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:18:08 +00:00
Bill Wendling
52061f83e7
Refactor some of the encoding logic into a base class. This keeps us from having
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to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6
Add encoding for VSUB and VCMP.
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Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b
Encoding for VADDD. Plus a test for the VFP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6
Split out the "size" field from the encoding. The newer documentation has it as
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a separate bit in the coding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5
Fix thinko in arm fast isel alloca rewrite.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6
Encoding for ARM-mode VADD.F32 instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 21:22:40 +00:00
Eric Christopher
52b45056b2
Combine these together - should probably have some text associated
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that says what why what we just asserted is wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 19:44:17 +00:00
Nick Lewycky
65b65d6ca4
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 18:18:03 +00:00
Jim Grosbach
f59818b81a
Add MOVi ARM encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 18:09:12 +00:00
Dan Gohman
320afb8c81
Initial va_arg support for x86-64. Patch by David Meyer!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 18:00:49 +00:00
Jim Grosbach
8e157302f4
Nuke unused wrapper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
d0eeeeb558
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
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The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:15:00 +00:00
Jim Grosbach
0de6ab3c43
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278
PR8359: The ARM backend may end up allocating registers D16 to D31 when
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"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941
Rework alloca handling so that we can load or store from casted
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address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57
Handle a wider arrangement of loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27
More ARM scheduling itinerary fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43
Second set of ARM/MC/ELF changes.
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Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f
Proper VST scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b
Use a sane mechanism for that assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9
We're not going to handle dynamic allocas anywhere else.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e
Make sure that the call stack adjustments have default operands. Also
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leave custom lowerings for later.
Fixes some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:20:02 +00:00
Jakob Stoklund Olesen
4f9af2ef65
PowerPC varargs functions store live-in registers on the stack. Make sure we use
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virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:43:09 +00:00
Eric Christopher
8ff9a9da0a
Found a bug turning this on by default. Disable again for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd
Fix help text.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6
Change flag from Enable to Disable since we're enabled by default.
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Also don't use fast-isel on non-darwin since it's untested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:05:22 +00:00
Andrew Trick
1a2cf3b4d9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 19:02:04 +00:00
Jim Grosbach
62547267f0
More binary encoding stuff, taking advantage of the new "by name" operand
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matching in tblgen to do the predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e
Turn on arm fast isel by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9
Copy and pasteo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43
Whitespace cleanup in ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:38:55 +00:00
Eric Christopher
6a880d6ba8
Add srem libcall support to ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:37:26 +00:00
Eric Christopher
7bdc4de4e7
Add i8 sdiv support for ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:31:54 +00:00
Eric Christopher
3bbd396853
Implement select handling for ARM fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:27:59 +00:00
Chris Lattner
60cb528246
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
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it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 05:44:40 +00:00
Michael J. Spencer
335b806c62
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 05:29:15 +00:00
Michael J. Spencer
92bf38c956
X86: MinGW should always use libgcc on Windows.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 23:11:06 +00:00
Michael J. Spencer
1802a9f8fe
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 22:04:34 +00:00
Michael J. Spencer
ec38de2ca8
Fix Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 22:04:20 +00:00
Chris Lattner
749dc72bdc
fix the expansion of va_arg instruction on PPC to know the arg
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alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 18:34:00 +00:00
Michael J. Spencer
c0c8df3cea
Fix Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 11:00:50 +00:00
Evan Cheng
10dc63feeb
Add VLD4 scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 04:07:58 +00:00
Evan Cheng
84f69e8436
Finish vld3 and vld4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:45:34 +00:00
Evan Cheng
40bb6836f6
Complete vld2 instruction itineries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:26:12 +00:00
Evan Cheng
8ae6ffacdd
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:15:04 +00:00
Evan Cheng
d2ca813549
Correct some load / store instruction itinerary mistakes:
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1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:03:04 +00:00
Bill Wendling
0aa38b9381
Check to make sure that the iterator isn't at the beginning of the basic block
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before decrementing. <rdar://problem/8529919>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 00:03:48 +00:00
Chris Lattner
0d9a0865c6
add jit support for the new psuedo instructions I added for
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the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 23:59:27 +00:00
Chris Lattner
8dae787db4
machine a mutable machineinstr down into emitInstruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 23:54:01 +00:00
Eric Christopher
e93417bcc8
Fix the store part of this as well. Fixes smg2000.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 23:52:16 +00:00
Jim Grosbach
56ac907c57
Implement a few more binary encoding bits. Still very early stage proof-of-
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concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 21:45:55 +00:00
Cameron Esfahani
ec37b00b17
Recommit 116056, now with the missing file...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 19:24:18 +00:00
Jim Grosbach
3e09413c2c
Reapply 116059, this time without the fatfingered pasto at the top.
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''const'ify getMachineOpValue() and associated helpers.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:45:54 +00:00
Jim Grosbach
2cee75a254
Reverting 116059. Bots are unhappy with it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:28:40 +00:00
Andrew Trick
5900201aa7
reverting 116056: win64_params.ll may need to be conditionalized?
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:22:42 +00:00
Jim Grosbach
461caba214
'const'ify getMachineOpValue() and associated helpers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 16:52:44 +00:00
Cameron Esfahani
d7b8d91d4a
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 10:31:30 +00:00
Bob Wilson
7d24705f65
Change register allocation order for ARM VFP and NEON registers to put the
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callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 06:15:13 +00:00
Chris Lattner
d043529b34
fix a subtle bug I introduced in my refactoring, where we stopped preferring
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the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 05:12:14 +00:00
Chris Lattner
15df55d8c2
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
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reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 03:57:25 +00:00
Chris Lattner
99ae6659da
reapply the patch reverted in r116033:
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"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 03:54:52 +00:00
Daniel Dunbar
b88b00ba2b
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
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'add'", which seems to have broken just about everything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:32 +00:00
Daniel Dunbar
b38109fc2d
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
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on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:29 +00:00
Daniel Dunbar
32f0cdba30
Revert "reimplement the second half of the or/add optimization. We should now",
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which depends on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:26 +00:00
Eric Christopher
7a56f33583
Move to thumb2 loads, fixes a problem with incoming registers
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as thumb1.
Fixes lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:13:17 +00:00
Chris Lattner
cd3167b281
reimplement the second half of the or/add optimization. We should now
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only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:05:10 +00:00
Jim Grosbach
58f38bfa24
Enable binary encoding of some simple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Chris Lattner
05e27c5786
Use the new TB_NOT_REVERSABLE flag instead of special
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casing FsMOVAPDrr/FsMOVAPSrr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:03:02 +00:00
Chris Lattner
a228376185
simplify some map operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:57:02 +00:00
Chris Lattner
122e2ea043
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
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is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:36:18 +00:00
Evan Cheng
344d9db970
Code refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:12:15 +00:00
Chris Lattner
45a1cb26a3
Reduce casting in various tables by defining the table
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with the right types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:08:41 +00:00
Chris Lattner
afcd543a55
simplify code: don't build up vector only to assert it is empty.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:26:19 +00:00
Owen Anderson
ce665bd2e2
Now with fewer extraneous semicolons!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:25:06 +00:00
Jim Grosbach
d6d4b42ba4
Trivial MC code emitter shell. No instruction forms actually handled yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:12:50 +00:00
Jim Grosbach
9af82ba42b
Include the auto-generated bits for machine encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:57:55 +00:00
Eric Christopher
df1f5a924e
Remember to promote load/store types for stack to register size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:40:18 +00:00
Chris Lattner
9649e9acdd
convert test to use the existing classes that the multipatterns
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use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:31:03 +00:00
Chris Lattner
00e94baf4e
convert cmp to use a multipattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:56:25 +00:00
Evan Cheng
835580fc3a
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:50:20 +00:00
Jim Grosbach
ae93ed1dd7
ARM instruction don't have instruction prefixes, so remove the helper functions
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for them from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:41:30 +00:00
Chris Lattner
9e94000c16
reduce redundancy between pattern copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:14:23 +00:00
Chris Lattner
a2b8b16c7e
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:06:24 +00:00
Owen Anderson
154c5c46fc
Improve comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115966 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:05:18 +00:00
Chris Lattner
a3208e122c
convert adc/sbb to a multipattern. Because the adde/sube nodes
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are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:01:55 +00:00
Owen Anderson
9966306aa7
Add initialization routines for Target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:50:11 +00:00
Jakob Stoklund Olesen
8456c4f957
Fix obvious mistake pointed out by Michael Spencer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:47:10 +00:00
Kalle Raiskila
218c98c284
Add the missing cases to the type->registerclass conversion function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:32:42 +00:00
Kalle Raiskila
8a52fa674b
Implement two virtual functions in SPUTargetLowering.
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Before the implementation of isLegalAddressingMode, some rare cases
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a
bad TargetLowering, or if the bug is elsewhere and this patch just
hides it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:24:35 +00:00
Eric Christopher
ee56ea6243
Use the correct register class for load instructions - fixes
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compilation of MultiSource/Benchmarks/Bullet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:50:44 +00:00
Eric Christopher
5d18d92aad
Use the correct register class here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:39:19 +00:00
Eric Christopher
338c253d7e
Use the thumb2 conditional move instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:31:49 +00:00
Eric Christopher
1107734e22
Remove in-progress assertion, add TODO.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:14:08 +00:00
Evan Cheng
5a50ceeaea
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:50:48 +00:00
Chris Lattner
b046810fe4
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
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allowing us to convert ADD over. deletes 160 lines of .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:37:01 +00:00
Chris Lattner
521ff704a1
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
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Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:26:27 +00:00
Chris Lattner
4b181c87de
Convert 'and' to single instance of a multipattern
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which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:10:20 +00:00
Jim Grosbach
a4257162be
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:53:56 +00:00
Chris Lattner
511c686f76
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
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This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:43:39 +00:00
Jim Grosbach
3bbdcea49a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:42:42 +00:00
Chris Lattner
1bb9adae4c
add a bunch of classes for other common patterns.
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As usual, no change in generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:35:28 +00:00
Chris Lattner
2b8d30d080
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6
Constrain the offset register to a *_NOSP register class when inserting LEA
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instructions.
This unbreaks the machine code verifier and fixes PR8317.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf
add the pattern operator to match to X86TypeInfo, use this to
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convert AND64ri32 to use BinOpRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
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This function looks like it is about ready to be generated by TebleGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:56:46 +00:00
Jim Grosbach
fa7fb64fad
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7
First in a sequence of ARM/MC/*ELF* specific work.
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Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:36:46 +00:00
Jim Grosbach
3c38f96af2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
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"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:22:32 +00:00
Jim Grosbach
65dc30340c
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
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pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:16:16 +00:00
Jim Grosbach
7cd2729d2a
Add a 'pattern' arg to the ARM PseudoNeonI class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 20:36:55 +00:00
Jim Grosbach
4dea941c8d
target operand flag values aren't a bitmask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 16:51:55 +00:00
Evan Cheng
a0792de66c
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 06:27:31 +00:00
Chris Lattner
b2fc409827
enhance X86TypeInfo to include information about the encoding and
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operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:55:42 +00:00
Chris Lattner
3ab0b59aad
add a class for _REV nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:35:22 +00:00
Chris Lattner
08808f9733
sink more intelligence into the ITy base class. Now it knows
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that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:28:38 +00:00
Chris Lattner
44402c0701
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 05:20:57 +00:00
Chris Lattner
da4b361726
with tblgen suitably extended, we can now get the load node from typeinfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 04:58:43 +00:00
Chris Lattner
417b54354b
lets go all meta and define new X86 type wrappers that declare the associated
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gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:45:24 +00:00
Chris Lattner
ff27af206e
introduce a new BinOpRM class and use it to factor AND*rm. This points out
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that I need a heavier handed approach to get ultimate factorization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:30:49 +00:00
Chris Lattner
c7252ce743
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
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where !cast is just as short.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:19:21 +00:00
Chris Lattner
78caacc226
replace stuff like:
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let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:05:18 +00:00
Chris Lattner
8d978a75b4
allow !strconcat to take more than two operands to eliminate
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!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:58:18 +00:00
Eric Christopher
e540a6f94a
Comment out fastisel debugging message.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:50:58 +00:00
Chris Lattner
20b2499a7c
associate the instruction suffix letter with the integer gpr
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register class, and use this to simplify use of BinOpRR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:43:04 +00:00
Chris Lattner
e00047c906
introduce a new BinOpRR class, and convert 4 and instructions to use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:32:05 +00:00
Eric Christopher
022b7fb045
Random cleanup and make the intermediate register in fptosi a
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32-bit fp reg, not 64-bit.
Fixes SingleSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:13:24 +00:00
Chris Lattner
6dbbff9172
Move cmov pseudo instructions to InstrCompiler,
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convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:09:10 +00:00
Chris Lattner
25cbf504fe
Use #NAME# to have the CMOV multiclass define things with the same names as before
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(e.g. CMOVBE16rr instead of CMOVBErr16).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:00:14 +00:00
Chris Lattner
df72eaef3d
enhance tblgen to support anonymous defm's, use this to
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simplify the X86 CMOVmr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:51:56 +00:00
Chris Lattner
286997c745
convert cmov mr patterns to use a multipattern. Death to redundancy
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and verbosity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:42:54 +00:00
Chris Lattner
d350e4757e
switch CMOVBE to the multipattern:
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21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:23:58 +00:00
Chris Lattner
e583c892d8
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
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not getting marked as mayStore. This fixes llvm-gcc bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:16:48 +00:00
Chris Lattner
b484213d1b
add a multiclass for cmov's, but don't start using it yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 22:01:02 +00:00
Chris Lattner
d244699067
use a multipattern to define setcc instructions:
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X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 21:34:29 +00:00
Chris Lattner
2c383d8c4d
move SETB pseudos into the same place in InstrCompiler.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 21:18:04 +00:00
Chris Lattner
508fc4708b
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
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gross hack (having the asmmatcher handle the alias).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 21:09:45 +00:00
Chris Lattner
748a2fe917
distribute the rest of the contents of X86Instr64bit.td out to
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the right places. X86Instr64bit.td now dies, long live x86-64!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:49:15 +00:00
Chris Lattner
10701928ff
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:35:37 +00:00
Chris Lattner
5bbbcdb1d8
continue moving 64-bit stuff into X86InstrArithmetic.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:23:31 +00:00
Jim Grosbach
d86609fca4
Increase the number of bits used internally by the ARM target to represent the
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addressing mode from four to five.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 18:14:55 +00:00
Chris Lattner
64227940e7
move 64-bit add and adc to InstrArithmetic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 16:59:08 +00:00
Chris Lattner
c7d4655b57
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 16:52:25 +00:00
Chris Lattner
6367cfc470
split the 32-bit integer arithmetic instructions out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 16:39:12 +00:00
Chris Lattner
5249ff34fb
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 07:13:35 +00:00
Chris Lattner
5f58e84af8
move 32-bit shift and rotates out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 07:00:12 +00:00
Chris Lattner
2c065e1c86
add new file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:52:35 +00:00
Chris Lattner
8917cd3d67
move sign and zero extensions out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:52:26 +00:00
Chris Lattner
d8cc2722a4
move some instructions from Instr64Bit -> InstrInfo.
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bswap32 doesn't read eflags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:47:35 +00:00
Chris Lattner
5673e1d314
move CMOV_FR32 and friends to InstrCompiler, since they are
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pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:41:40 +00:00
Chris Lattner
41efbfaa66
move various pattern matching support goop out of X86Instr64Bit, to live
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with the 32-bit stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115602 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:37:31 +00:00
Chris Lattner
35649fc3dd
split conditional moves and setcc's out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:33:16 +00:00
Chris Lattner
d3f033d969
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:27:48 +00:00
Chris Lattner
010496c6a7
move the atomic pseudo instructions out to X86InstrCompiler.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:22:35 +00:00
Chris Lattner
8af88ef157
move more pseudo instructions out to X86InstrCompiler.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:10:16 +00:00
Chris Lattner
d071b83b5d
move VMX instructions out to their own file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:06:53 +00:00
Chris Lattner
87be16a9e1
continue moving stuff out to X86InstrSystem.td. Move
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control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:04:14 +00:00
Michael J. Spencer
f000a7a212
fix MSVC 2010 build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:00:43 +00:00
Michael J. Spencer
2bbb769091
Cleanup Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:00:33 +00:00
Chris Lattner
434c7cb8a1
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 05:32:15 +00:00
Jim Grosbach
33caa07cc5
Re-apply r115363 and r115366 now that r115525 has removed the un-needed header
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that caused the circular dependencies on Linux.
Built OK for me on OSX and Linux (Ubuntu) with configure/make and CMake. Will
keep an eye on the bots....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 00:34:11 +00:00
Bill Wendling
6cf6c79e82
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
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it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-04 20:24:01 +00:00
Jim Grosbach
c5ccf73dee
Remove unneeded header
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-04 17:53:40 +00:00
Jan Wen Voung
083cf1574f
Add hook in MCSection to decide when to use "optimized nops", for each
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section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-04 17:32:41 +00:00
Anton Korobeynikov
e7beda183d
va_args support for Win64.
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Patch by Cameron!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 22:52:07 +00:00
Anton Korobeynikov
6af61ca789
Properly emit stack probe on win64 (for non-mingw targets).
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Based on the patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115479 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 22:02:38 +00:00
Eli Friedman
d32d85e5ba
Add 3DNowA instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115477 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 20:23:13 +00:00
Chris Lattner
591d76ea5a
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 19:09:13 +00:00
Rafael Espindola
0febc4657b
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
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so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:59:45 +00:00
Chris Lattner
cc07d7116a
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:42:30 +00:00
Chris Lattner
f132fa0e74
what the heck, add support for the rest of the 3dNow! binary operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:24:18 +00:00
Chris Lattner
548abfcbd6
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:08:05 +00:00
Evan Cheng
ec45f60cab
Major changes to Cortex-A9 itinerary.
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1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 02:03:59 +00:00
Chris Lattner
7330d97069
stub out a header to put 3dNow! instructions into.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 23:06:23 +00:00
Chris Lattner
d476914607
fix a regression introduced in r115243, in which the instruction
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backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 21:32:15 +00:00
Nick Lewycky
d0669493b8
Wind these directories back too. File adds and removes are properly represented
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in patches. :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 01:16:59 +00:00
Nick Lewycky
0e7fdf5f09
Continue reverting r115363.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 01:08:17 +00:00
Nick Lewycky
c57707dd87
Revert patches r115363 r115367 r115391 due to build breakage:
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llvm[2]: Updated LibDeps.txt because dependencies changed
llvm[2]: Checking for cyclic dependencies between LLVM libraries.
find-cycles.pl: Circular dependency between *.a files:
find-cycles.pl: libLLVMMSP430AsmPrinter.a libLLVMMSP430CodeGen.a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 01:06:42 +00:00
Jim Grosbach
0e69aff03a
Update CMake files for recent AsmPrinter->InstPrinter changes. Can someone who
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is more familiar with CMake please review?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 00:39:56 +00:00
Eric Christopher
890dbbec57
Start on lowering global addresses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 00:32:44 +00:00
Jim Grosbach
443e625d8a
PrintSpecial() can go away now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:27:48 +00:00
Eric Christopher
c9932f6f60
Stub out constant GV handling, fixes C++ eh tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:24:42 +00:00
Jim Grosbach
78890f41f4
Nuke the rest of the :comment references
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:21:38 +00:00
Jim Grosbach
adde5da638
Nuke a bunch of no-longer-needed comment-only asm strings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:09:33 +00:00
Jim Grosbach
7722980950
Now that the asmprinter itself isn't in the subdir, rename 'AsmPrinter' to
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'InstPrinter' to fall into line with the other MC-ized assembly printer
using targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:57:18 +00:00
Evan Cheng
055028215d
Fix r115332: correctly model AGU / NEON mux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:52:29 +00:00
Owen Anderson
e3cc84a43d
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
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stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:45:50 +00:00
Jim Grosbach
6314ef9e81
Move the asmprinter and MC lowering out of the AsmPrinter (soon to be
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InstPrinter) subdir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:45:38 +00:00
Jim Grosbach
7ac1609a3b
Rename the AsmPrinter directory to InstPrinter for those targets that have
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been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:39:28 +00:00
Evan Cheng
ef0ccad725
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 21:48:06 +00:00
Evan Cheng
df9da6a033
Add operand cycles for vldr / vstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 21:40:30 +00:00
Eric Christopher
e6ca6771e3
Direct calls only for arm fast isel for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 21:33:12 +00:00
Evan Cheng
cae6a12a99
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:50:58 +00:00
Eric Christopher
45547b844d
Fix thinko on store instructions. Fixes test_indvars failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:46:04 +00:00
Owen Anderson
00d4f48168
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:33:47 +00:00
Owen Anderson
aa9f0a57d0
Provide an option to restore old-style if-conversion heuristics for Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:28:06 +00:00
Evan Cheng
7c3423f413
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 19:41:46 +00:00
Jim Grosbach
bffa1a5cf3
grammar
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 14:57:48 +00:00
Benjamin Kramer
b0f96facd6
Delete token *after* reading from it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115311 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 12:25:27 +00:00
Kalle Raiskila
8258135c90
Zap some redundant 'ori $?, $?, 0' from SPU.
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Also remove some code that died in the process.
One now non-existant ori is checked for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 09:20:01 +00:00
Eric Christopher
14df88282b
Implement double return values in calls. Fixes
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SingleSource/Regression/C/casts.c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 00:00:11 +00:00
Dale Johannesen
0488fb649a
Massive rewrite of MMX:
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The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Owen Anderson
b3c04ec956
Temporarily add a flag to make it easier to compare the new-style ARM if
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conversion heuristics to the old-style ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115239 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:48:38 +00:00
Jim Grosbach
ddcf859851
Clean up asm writer usage for x86 and msp430 to flag that the writer should
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use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:40:25 +00:00
Eric Christopher
086378597d
Movement and cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 22:34:19 +00:00
Eric Christopher
f9764fa14f
Start of generalized call support for ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 20:49:44 +00:00
Jim Grosbach
a3fbadfcd8
Nuke a few more unused asm strings
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 19:53:58 +00:00
Jim Grosbach
3787a40e03
Move getPointerSize() to the base class since it's not dependent on MachO
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vs. ELF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:45:51 +00:00
Jim Grosbach
af2a8b21f1
Remove extraneous ';'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:19:17 +00:00
Chris Lattner
905f2e0669
preemptively add the rest of the non-n fpstack instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:11:29 +00:00
Jim Grosbach
71d933a49e
The asm strings are never used at all, so just nuke 'em entirely.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:56:53 +00:00
Chris Lattner
9ee4aed3b6
implement support for finit, PR8258
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:42:53 +00:00
Chris Lattner
0bb83a84d4
add support for fstcw, PR8259
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:39:29 +00:00
Kevin Enderby
8ebf66236e
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
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for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:38:07 +00:00
Jim Grosbach
2f24c4ece0
80 column fix
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 15:25:22 +00:00
Jason W Kim
a4c27248b5
Fix two tiny issues (ARM does not need COFF) and comment sanity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 14:58:19 +00:00
Jim Grosbach
f73fd7278f
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:21:00 +00:00
Jim Grosbach
87dc3aa2d8
Remove misplaced ';'. Make buildbots happy, hopefully.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:20:34 +00:00
Rafael Espindola
a8c02c3bdd
Correctly produce R_X86_64_32 or R_X86_64_32S.
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With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:11:42 +00:00