Thomas Harte
9b7ca6f271
Implements the basics of EORI, ORI, ANDI, SUBI and ADDI.
...
Also corrects the BSR return address.
2019-04-16 19:50:10 -04:00
Thomas Harte
8ce018dbab
Adds the necessary runtime support for AND, EOR and OR.
2019-04-16 15:17:40 -04:00
Thomas Harte
180062c58c
Finishes fleshing out [ADD/SUB]Q.
2019-04-16 14:28:31 -04:00
Thomas Harte
37656f14d8
Adds basic addressing modes for [ADD/SUB]Q.
2019-04-16 11:19:45 -04:00
Thomas Harte
dec5535e54
Implements (arguably: fixes) BSR.
2019-04-15 23:20:36 -04:00
Thomas Harte
1f0e3b157a
Corrects a couple of JSR and JMP addressing modes.
2019-04-15 22:37:11 -04:00
Thomas Harte
d802e83f49
Fills in further MOVEs.
2019-04-15 22:25:22 -04:00
Thomas Harte
ebcae25762
Adjusts JSR behaviour and further extends MOVE.
2019-04-15 22:02:52 -04:00
Thomas Harte
5330267d16
Implements BCLR.
2019-04-15 18:11:02 -04:00
Thomas Harte
892476973b
Attempts RO{X}[L/R].
2019-04-15 17:31:58 -04:00
Thomas Harte
84f4a25bc9
Completes TST.
2019-04-15 16:28:20 -04:00
Thomas Harte
1460a88bb3
Takes a run at JSR and RTS.
2019-04-15 15:14:38 -04:00
Thomas Harte
d25ab35d58
Finally gets setw
usage correct.
2019-04-15 12:41:56 -04:00
Thomas Harte
a223cd90a1
Adds predecrement TSTs, increases QL running time, reduces logging.
2019-04-15 12:36:08 -04:00
Thomas Harte
aef92ba29c
Corrects immediate shift count.
2019-04-15 12:25:45 -04:00
Thomas Harte
328d297490
Implements the first few addressing modes for TST.
2019-04-15 10:03:52 -04:00
Thomas Harte
3d240f3f18
Corrects decoding of DBcc.
2019-04-15 09:49:23 -04:00
Thomas Harte
45f35236a7
Corrects decoding of ADDA and SUBA.
2019-04-15 09:44:06 -04:00
Thomas Harte
fba210f7ce
Corrects MOVE.l Dn, (An)[+].
2019-04-15 09:30:49 -04:00
Thomas Harte
8a09e5fc16
Implements Scc.
2019-04-14 22:39:13 -04:00
Thomas Harte
75d8824e6b
Eliminates implicit type conversion.
2019-04-14 21:02:28 -04:00
Thomas Harte
325af677d3
Implements MOVEM to M with an implicit type conversion.
2019-04-14 20:53:27 -04:00
Thomas Harte
1003e70b5e
Implements MOVEM to R.
2019-04-14 20:02:18 -04:00
Thomas Harte
d70229201d
Advances right up to the lack of MOVEM actions being the final piece.
2019-04-14 14:45:29 -04:00
Thomas Harte
823f91605b
Still slow pedalling slightly, adds further MOVEM storage.
2019-04-14 14:31:13 -04:00
Thomas Harte
53f75034fc
Commits at least to decoding MOVEM.
2019-04-14 14:09:28 -04:00
Thomas Harte
78649a5b54
Fleshes out MOVE, (XXX) a little further.
2019-04-12 17:16:03 -04:00
Thomas Harte
f48db625a0
Corrects write-back and zero flag for ADD/SUB.l.
2019-04-12 16:41:00 -04:00
Thomas Harte
2ba66c4457
Corrects MOVEA, adds extra test safeguards.
2019-04-12 16:10:17 -04:00
Thomas Harte
2c78ea1a4e
Completes conversion away from magic constants.
2019-04-12 15:48:29 -04:00
Thomas Harte
73f50ac44e
Commits further to elimination of magic constants.
2019-04-12 13:45:28 -04:00
Thomas Harte
9ce48953c1
Improves debugging printout.
2019-04-12 13:45:03 -04:00
Thomas Harte
1098cd0c6b
Begins rooting out magic constants.
2019-04-11 22:31:17 -04:00
Thomas Harte
652ebd143c
Corrects addressing mode support for LEA.
2019-04-11 11:58:34 -04:00
Thomas Harte
8e9d7c0f40
Corrects register-relative address calculation.
2019-04-10 23:09:03 -04:00
Thomas Harte
a64948a2ba
Permits zero-bus-op non-terminals.
2019-04-10 22:42:43 -04:00
Thomas Harte
43f619a081
Implements ASL, ASR, LSL and LSR.
2019-04-10 22:31:04 -04:00
Thomas Harte
a07de97df4
Implements the fixed part of register shifts.
2019-04-09 22:12:37 -04:00
Thomas Harte
85d25068a8
Attempts a full implementation of memory shifts.
2019-04-09 22:04:25 -04:00
Thomas Harte
7a0319cfe5
Kicks the work of dealing with ASL/etc into the runtime.
2019-04-09 21:48:08 -04:00
Thomas Harte
f750671f33
Stepping gingerly onwards, adds a double-decoding test.
...
As a result of that, collapses BRA into Bcc. Which provisionally looks correct.
2019-04-09 16:54:41 -04:00
Thomas Harte
7886fe677a
Cleans up commenting.
2019-04-08 22:51:18 -04:00
Thomas Harte
73c027f8e3
Implements CMPA and CMPM. [Provisionally] completing the CMPs.
2019-04-08 22:40:38 -04:00
Thomas Harte
eda88cc462
Implements MOVE to CCR.
2019-04-07 22:24:17 -04:00
Thomas Harte
652f4ebfed
Implements CLR, NEG, NEGX and NOT.
2019-04-07 22:07:39 -04:00
Thomas Harte
06a2f59bd0
Implements DBcc.
2019-04-06 23:21:01 -04:00
Thomas Harte
03f365e696
Corrects source/destination order of CMP setup.
2019-04-06 20:00:15 -04:00
Thomas Harte
49a22674ba
Corrects MOVE destinations.
2019-04-06 18:33:53 -04:00
Thomas Harte
ec494511ec
Implements CMP.
2019-04-06 10:41:19 -04:00
Thomas Harte
af02ce9c6e
Attempts to correct various instances of PC-relative addressing.
2019-04-05 23:49:13 -04:00
Thomas Harte
56e42859ab
Ensures the supervisor flag is updated properly on MOVE to SR.
2019-04-05 23:21:50 -04:00
Thomas Harte
2d153359f8
Adds BTST.
2019-04-04 21:43:22 -04:00
Thomas Harte
068ce23716
Adds a few more MOVEs.
2019-04-04 19:49:19 -04:00
Thomas Harte
03be2e3652
Adds decoding of ADDA and SUBA.
2019-04-03 22:39:01 -04:00
Thomas Harte
4ef2c0bed8
Completes ADD and SUB.
2019-04-03 21:41:59 -04:00
Thomas Harte
bfd405613c
Reuse of addresses is also no longer implicit.
2019-04-03 21:27:11 -04:00
Thomas Harte
73e1c8c780
Corrects now-unimplemented ADD/SUB.
2019-04-03 19:43:54 -04:00
Thomas Harte
689ba1d4a2
Effective address adjustments now have to be explicit.
2019-04-03 19:13:10 -04:00
Thomas Harte
39b9d00550
Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification.
2019-04-02 21:50:58 -04:00
Thomas Harte
64f99d83a4
Takes a stab at offering ADD, ADDA, SUB and SUBA operations.
...
Not yet decoded.
2019-04-01 21:21:26 -04:00
Thomas Harte
8f1faefa1c
Implements further MOVEs and fixes a potential error in program formation.
2019-03-31 22:34:28 -04:00
Thomas Harte
a9ceef5c37
Improves communication slightly.
2019-03-31 22:27:33 -04:00
Thomas Harte
c6f977ed4b
Corrects CMPI and documentation; implements JMP.
2019-03-31 21:13:26 -04:00
Thomas Harte
cb240cd32a
Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
2019-03-30 23:11:39 -04:00
Thomas Harte
bc6349f823
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-29 23:40:54 -04:00
Thomas Harte
a93a1ae40f
Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq.
2019-03-29 23:13:41 -04:00
Thomas Harte
25254255fe
Implements a few additional MOVEs.
2019-03-27 21:26:04 -04:00
Thomas Harte
42634b500c
Implements LEA.
2019-03-26 22:07:28 -04:00
Thomas Harte
be4b38c76a
Adds BRA and Bcc.
2019-03-25 22:54:49 -04:00
Thomas Harte
7163b1132c
Takes a run at CMPI.
...
Also factors out a couple of mode things, clarifies on where things from the
prefetch are assembled to, and switches to ordering implemented instructions
alphabetically.
2019-03-24 23:05:57 -04:00
Thomas Harte
3ccec1c996
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 18:20:54 -04:00
Thomas Harte
47359dc8f1
Adds tests for MOVE.l (An), Dn, and thereby correct their implementation.
2019-03-23 21:41:47 -04:00
Thomas Harte
43532c8455
Starts to make incursions into MOVE[A].l.
2019-03-23 21:03:52 -04:00
Thomas Harte
d7c3d4ce52
Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
2019-03-22 23:27:48 -04:00
Thomas Harte
ed7060a105
Made an initial stab at completing MOVEA.w.
...
I think I'm probably peeking into the prefetch queue incorrectly.
2019-03-22 21:43:51 -04:00
Thomas Harte
db0da4b741
Improves get/set state.
2019-03-22 19:34:17 -04:00
Thomas Harte
c9c16968bb
Implements MOVEA as distinct from MOVE.
...
At least as far as MOVE is implemented, that is.
2019-03-22 19:25:53 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
f679145bd1
Makes a further push into the MOVEs.
...
With some quick notation shortening.
2019-03-20 23:21:02 -04:00
Thomas Harte
eeb161ec51
Converts the prefetch queue into a 32-bit quantity.
2019-03-19 21:33:52 -04:00
Thomas Harte
21cb7307d0
Adds MOVE #, Dn
and MOVEA An, An
.
...
As well as the scheduling for `(d16,PC), Dd` and `MOVE (d8,As,Xn), Dd` other than the .ls.
2019-03-19 11:53:37 -04:00
Thomas Harte
412a1eb7ee
Takes an initial run at (An)+, -(An), (d16,An) and (d8,An,Xn) addressing modes.
...
With only MOVEs from those to a data register implemented so far.
2019-03-18 22:51:32 -04:00
Thomas Harte
1d801acf72
Switched to a better ABCD fix.
2019-03-17 22:04:32 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
53b3d9cf9d
Implements a few more MOVE variants, plus MOVEA.
2019-03-17 14:34:16 -04:00
Thomas Harte
c3ebbfb10e
Implements all MOVE Dn, Dn
.
2019-03-16 23:14:18 -04:00
Thomas Harte
58f035e31a
Makes error more communicative.
2019-03-16 23:05:12 -04:00
Thomas Harte
a8f1d98d40
Small further adjustments; seems likely to be correct now.
2019-03-16 23:01:56 -04:00
Thomas Harte
cf6fa98433
Corrects detection of terminal micro-ops.
2019-03-16 22:50:44 -04:00
Thomas Harte
937b3ca81d
Attempts properly to honour the bus-op and microcycle contract.
2019-03-16 22:36:09 -04:00
Thomas Harte
d0c5cf0d2d
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-16 21:47:46 -04:00
Thomas Harte
4cbf2bef82
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp.
...
As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 19:41:07 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
bb04981280
I'm still dithering on address management, but this seeks fully to implement ABCD and SUBD bus programs.
2019-03-13 21:08:13 -04:00
Thomas Harte
57898ed6dd
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-12 22:46:31 -04:00
Thomas Harte
33b53e7605
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-11 22:47:58 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
98aa597510
A theoretical 68000 could now perform its /RESET. That's all though.
2019-03-10 17:42:13 -04:00
Thomas Harte
de56d48b2f
Embraces a more communicative 68000 bus.
2019-03-10 17:27:34 -04:00
Thomas Harte
4aeb9a7c56
Genericises RegisterPair.
2019-03-09 21:16:11 -05:00
Thomas Harte
b9b52b7c8b
Begins some very early sketching out of a 68000.
2019-03-09 00:00:23 -05:00
Thomas Harte
d97348dd38
Eliminates dangling uses of printf
.
2019-03-02 18:07:05 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
364859467f
Corrects Rockwell and WDC references.
...
Also shuffles the NES CPU type up into the top position, so this is a strict progression in terms of functionality.
2018-09-27 22:36:45 -04:00
Thomas Harte
8787d85e64
Eliminates #undefs as being (i) unnecessary, now this is a source file; and (ii) incomplete in any case.
2018-08-17 22:24:42 -04:00
Thomas Harte
0e7f54f375
Implements STP and WAI, and ensures all unimplemented 65C02 instructions are NOP for all 65C02s.
2018-08-17 21:49:06 -04:00
Thomas Harte
b3bdfa9f46
Corrected: it's three-cycle 65C02 branches that ignore interrupts, not two.
2018-08-16 20:47:49 -04:00
Thomas Harte
592ec69d36
Causes the 65C02 not to accept interrupts immediately after untaken branches.
2018-08-15 22:42:04 -04:00
Thomas Harte
60e00ddd02
Correction: the test for not skipping an operand fetch requires a 65C02.
2018-08-15 22:07:17 -04:00
Thomas Harte
6806193dc2
Ensures that "Read/Modify/Write instructions absolute indexed in same page" take only six cycles on a 65C02.
2018-08-15 19:17:37 -04:00
Thomas Harte
c35dca783f
Ensures that page-crossing indexing no longer causes an extra read of an invalid address on the 65C02.
...
It rereads the last byte of the instruction stream instead.
2018-08-15 18:47:53 -04:00
Thomas Harte
901e0d65b9
Documents all 6502 micro-operations.
...
Also makes sure 1-cycle NOPs really, definitely are one cycle only on a 65C02 and eliminates OperationCopyOperandFromA as a redundant copy of OperationSTA.
2018-08-14 22:17:53 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
1eca4463b3
Ensures NMI can no longer usurp BRK on 65C02s.
2018-08-14 19:33:48 -04:00
Thomas Harte
be01203cc1
Starts to expand the range of supported 6502s.
...
This fully implements the NES 6502 because, well, it's virtually no extra work, and ensures that RDY takes effect on write cycles on 65C02s.
2018-08-13 22:17:22 -04:00
Thomas Harte
4b91910fab
Removes erroneous addition.
2018-08-10 23:27:09 -04:00
Thomas Harte
878c63dcd2
Ensures ADC and SBC decimal take an extra cycle on the 65C02.
2018-08-10 22:52:55 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
8b50ab2593
Corrects (zero) behaviour.
2018-08-10 21:12:55 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
6f838fe190
Implements INA and DEA.
2018-08-08 22:30:19 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
e46bde35f5
Implements BBS and BBR.
2018-08-07 21:52:17 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
5c881bd19d
Implements PLX, PLY, PHX and PHY.
2018-08-06 22:00:23 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
633af4d404
The operations table is now per-instance.
2018-08-06 20:47:14 -04:00
Thomas Harte
76a73c835c
Forces 6502 consumers to declare which model — the original, 65C02 or 65SC02.
...
All present machines use a regular 6502.
2018-08-06 20:06:07 -04:00
Thomas Harte
0b14850467
Corrects some comments.
2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1
Differentiates reasons for a read to be four cycles.
...
Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
2018-06-20 21:34:21 -04:00
Thomas Harte
ad9b0cd4e3
Eliminates all endashes.
2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
45be1c19df
Resolves undefined behaviour of a signed shift left.
2018-03-22 21:59:39 -04:00
Thomas Harte
0e73ba4b3e
Introduces proper 5/3 SCF/CCF behaviour for the Z80.
...
While also `const`ing a bunch of things.
2018-03-09 09:47:00 -05:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
74dfe56d2b
Expands documentation of NMI setting.
...
Given that it was previously incorrect, explains logic behind request_status_ and last_request_status_ setting. Also takes the opportunity to ensure that NMI is 'sampled' at the same time as IRQ; whether the next thing should be the NMI routine now occurs one cycle before the end of any instruction. That's an assumption for now. Testing to come.
2018-03-02 11:10:02 -05:00
Thomas Harte
b02e4fbbf6
Corrects NMI receipt to be genuinely edge triggered.
...
Previously a caller that signalled NMI set multiple times would trigger multiple NMIs.
2018-03-01 22:04:56 -05:00
Thomas Harte
23c47e21de
Proceeds the ColecoVision to booting.
2018-02-24 18:14:38 -05:00
Thomas Harte
7dfbe4bb93
Ensures proper Boolean startup values for IFF1 and IFF2.
2017-11-29 20:32:55 -05:00
Thomas Harte
5aef81cf24
Commutes cross-platform #pragma mark
s to //MARK:
s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
cb0f58ab7a
Corrects order-of-initialisation errors in the CPC (again), TextureBuilder, TextureTarget, Z80, MFM parser and binary tape player.
2017-11-10 22:57:03 -05:00
Thomas Harte
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
Thomas Harte
c0055a5a5f
Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
2017-11-09 22:04:49 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
ad9df4bb90
Commutes uint8_t *
, uint16_t *
, uint32_t *
, size_t
, off_t
and long
to functional-style casts.
2017-10-21 22:30:15 -04:00
Thomas Harte
e983854e71
Converts all uint8_t
and uint16_t
casts to the functional style.
2017-10-21 21:50:53 -04:00
Thomas Harte
ab2bcb939f
Separates 6502Base into its constituent parts.
2017-09-04 11:08:33 -04:00
Thomas Harte
45499050b6
Separates Z80Base.cpp into its component classes.
2017-09-04 11:04:01 -04:00
Thomas Harte
a1e200cc65
Further strips back the amount exposed in Z80-related headers.
...
Almost all opcode table generation macros and code now resides neatly in the world of .CPP.
2017-09-01 22:19:16 -04:00
Thomas Harte
e6ac939ae0
Reintroduces missing noexcept specifier.
2017-09-01 20:51:31 -04:00
Thomas Harte
b034d4e6f8
Refactors the Z80 to separate out interface and implementation.
...
Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
2017-09-01 20:50:24 -04:00
Thomas Harte
de218611e4
Corrects possible confusion as documentation recommends Cycles(0) as default, but then gives Cycles(1).
2017-09-01 20:49:24 -04:00
Thomas Harte
b306776ba9
Removes from 6502.hpp all remaining implementation details, making it purely an interface document.
...
Though those details remain visible to files including 6502.hpp through necessity.
2017-09-01 19:46:29 -04:00
Thomas Harte
4af333d5ec
Tidies the 6502 template and folder hierarchy.
...
Specifically: there's now just the one .h file at the top level, giving a clear indication of what a user should read. That separates implementation from interface. It also devolves a lot more to the base class because doing so makes debug builds less of a hassle. The all-RAM 6502 has been shuffled off into a subfolder, to indicate that it's not something you necessarily need know about. Also general documentation improvements have been applied: incorrect citing of the recurring-template pattern has been removed and the meaning of the two BusHandler methods has now accrued at the bus handler.
2017-08-31 22:10:27 -04:00
Thomas Harte
fab6908129
Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
2017-08-26 23:18:11 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
Thomas Harte
95d360251d
Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
2017-08-24 21:32:33 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
e1aded0d95
Allows Z80 users to opt out of support for the bus request line. Which both now do.
2017-08-21 20:43:12 -04:00
Thomas Harte
6315c22b80
Removed repeated checking of bus_request_line_. It's now checked only after each outward perform_machine_cycle
.
2017-08-20 12:39:45 -04:00
Thomas Harte
42b5b66305
Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
2017-08-16 11:56:52 -04:00
Thomas Harte
039811ce6a
Switched the Z80 to being something a machine has, not something a machine is.
2017-08-02 22:09:59 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles
as the thing called and returned, rather than const [Half]Cycles &
as it's explicitly defined to be only one int
in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
9ef232157b
Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for
intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles.
2017-07-27 21:38:50 -04:00
Thomas Harte
8848ebbd4f
Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
2017-07-27 21:10:14 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
60e374dca3
Merge branch 'master' into Memptr
2017-07-27 07:54:25 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
847e49ccdf
Corrected timestamp reporting by the all-RAM Z80.
2017-07-26 19:47:39 -04:00
Thomas Harte
81a3899381
Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
2017-07-26 19:42:00 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
966b5e6372
Adapted the Z80's perform_machine_cycle
to return Cycles
.
2017-07-25 22:25:44 -04:00
Thomas Harte
279c369a1f
Switched to Cycles as the result from the 6502 perform_bus_operation
, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
2017-07-25 22:21:09 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver
and sought to ensure that proper run_for
s are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
677ed463f0
Updated comment per new method name.
2017-07-24 21:19:49 -04:00
Thomas Harte
9bff787ee1
Corrected for the new, non-integral type.
2017-07-24 21:05:07 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles
and HalfCycles
as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
Thomas Harte
ace8e30818
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
2017-07-23 22:21:39 -04:00
Thomas Harte
ec3aa06caf
Removed dangling reference.
2017-07-23 22:16:00 -04:00
Thomas Harte
ba088e5545
Adapted the Z80 into a clock receiver, which also vends Cycles
rather than a raw int within its PartialMachineCycle
struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first.
2017-07-23 22:15:04 -04:00
Thomas Harte
2ff157cf7a
Switched CRTMachine over to use Cycles
as an explicit statement of units, and followed through on the effects of that.
2017-07-22 22:17:29 -04:00
Thomas Harte
83628b285b
Experimentally turned the 6502 into a clock receiver. No problem encountered.
2017-07-22 21:52:21 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr
instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
540a03f75c
Exposed the memptr register.
2017-07-21 22:31:42 -04:00
Thomas Harte
9b72c445a7
Fixed indexing type.
2017-07-21 21:19:46 -04:00
Thomas Harte
aec4fd066b
I think I've definitively decided against this model of timing.
2017-06-22 21:32:14 -04:00
Thomas Harte
95a6b0f85c
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-22 21:09:26 -04:00
Thomas Harte
b7c978e078
Added getters for most of the input lines, and attempted to round out the ZX81's wait logic.
2017-06-22 20:11:19 -04:00
Thomas Harte
f0398a6db8
Added wait state hooks to the interrupt programs, and added an is_wait query on PartialMachineCycle.
2017-06-22 20:07:47 -04:00
Thomas Harte
7eeac3b586
Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation.
2017-06-21 21:11:00 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
2017-06-21 20:32:08 -04:00
Thomas Harte
45f442ea63
Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.
2017-06-21 19:08:48 -04:00
Thomas Harte
db743c90d8
Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.
2017-06-21 18:58:44 -04:00
Thomas Harte
10cc94f581
Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.
2017-06-21 18:47:00 -04:00
Thomas Harte
108da64562
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
2017-06-20 22:25:00 -04:00
Thomas Harte
f85b46286e
Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.
2017-06-20 22:20:58 -04:00
Thomas Harte
184b371649
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
2017-06-20 21:48:50 -04:00
Thomas Harte
b0375bb037
Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.
2017-06-20 21:32:23 -04:00
Thomas Harte
48942848e7
Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.
2017-06-20 21:15:56 -04:00
Thomas Harte
27ac342928
Corrected conditional call timing, and its test.
2017-06-20 20:57:23 -04:00
Thomas Harte
25aba16ef8
Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.
2017-06-19 22:20:23 -04:00
Thomas Harte
a0d0f383c8
Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.
2017-06-19 22:07:36 -04:00
Thomas Harte
cc8f316941
Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).
2017-06-19 20:51:28 -04:00
Thomas Harte
b684254908
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
2017-06-19 20:33:34 -04:00
Thomas Harte
ba15371948
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
2017-06-19 19:47:00 -04:00
Thomas Harte
73dbaebbc1
Fixed timing of EX (SP), HL/IX.
2017-06-19 19:25:53 -04:00
Thomas Harte
e3244eb68e
Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes.
2017-06-19 07:39:46 -04:00
Thomas Harte
85c6fb1430
Explained refresh cycles to the all-RAM Z80.
2017-06-19 07:36:11 -04:00
Thomas Harte
54e4643396
Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.
2017-06-19 07:34:23 -04:00
Thomas Harte
85c5c4405a
Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
2017-06-19 07:30:01 -04:00
Thomas Harte
d668879ba6
Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
2017-06-18 22:03:13 -04:00
Thomas Harte
cb140aa06e
Managed to navigate back to building.
2017-06-18 21:00:44 -04:00
Thomas Harte
6a769d3953
Finally dipped below the 20 error threshold that the compiler tops out at.
2017-06-18 20:34:46 -04:00
Thomas Harte
3be8ffd826
Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors.
2017-06-18 20:31:12 -04:00
Thomas Harte
bb910e14a4
Dealt with the CB page.
2017-06-18 18:01:33 -04:00
Thomas Harte
69ebbe019a
Completed ED page conversion. Rolling onwards...
2017-06-18 17:56:48 -04:00
Thomas Harte
0d39672d32
Fixing typos here and there, persuaded the first half of the ED table to compile.
2017-06-18 17:48:54 -04:00
Thomas Harte
0d1231980a
Advanced to getting specific warnings in the ed-page table. So that's progress.
2017-06-18 17:25:15 -04:00
Thomas Harte
82a015892b
Started adapting to the newly-segmented world.
2017-06-18 17:18:01 -04:00
Thomas Harte
194b7f60c5
Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.
2017-06-18 17:08:50 -04:00
Thomas Harte
ebc7356db5
Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.
2017-06-18 12:21:27 -04:00
Thomas Harte
e1a2580b2a
Renamed BusOperation to MachineCycle::Operation.
2017-06-17 21:53:45 -04:00
Thomas Harte
efc7f9df37
Combined I and R into a register pair.
2017-06-17 18:18:28 -04:00
Thomas Harte
aed2827e7b
Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
2017-06-12 22:22:00 -04:00
Thomas Harte
b9dbb6bcf8
Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.
2017-06-12 18:55:04 -04:00
Thomas Harte
d12e50eb02
Corrected "should I adjust history?" tests.
2017-06-11 16:41:34 -04:00
Thomas Harte
db30f53ab0
Added the capacity to back-date interrupt line changes within a machine cycle, so that machines which time themselves entirely within perform_machine_cycle can still be cycle accurate on those changes.
2017-06-11 13:31:02 -04:00
Thomas Harte
b55579c348
Fixed usage of flush
: the subclass version is definitively used.
2017-06-06 17:52:44 -04:00
Thomas Harte
3df6eba237
Fixed: my HALT line wasn't actually halting. NOPs followed, but the PC just kept counting.
2017-06-05 10:35:03 -04:00
Thomas Harte
e940e02126
Added a short circuit to set_interrupt_line, mostly to make breakpoints slightly more convenient to place.
2017-06-05 09:37:19 -04:00
Thomas Harte
7f743c6fb0
Got explicit about permitted type conversions.
2017-06-04 18:40:59 -04:00
Thomas Harte
096551ab3e
Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.
2017-06-04 18:32:23 -04:00
Thomas Harte
c485c460f7
Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
2017-06-04 18:08:35 -04:00
Thomas Harte
d2637123c4
Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
2017-06-04 17:55:19 -04:00
Thomas Harte
0eebfdb4cc
Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f
Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
2017-06-04 15:07:07 -04:00
Thomas Harte
a2f01b4a46
Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.
2017-06-04 14:59:18 -04:00
Thomas Harte
f5c910beb7
Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE.
2017-06-04 14:18:04 -04:00
Thomas Harte
4e014ca748
Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?
2017-06-04 14:13:38 -04:00
Thomas Harte
1a811b1ab1
Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
2017-06-03 22:19:35 -04:00
Thomas Harte
c26349624c
This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
2017-06-03 22:00:57 -04:00
Thomas Harte
b642d9f712
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
Thomas Harte
b304c3a4b9
Eliminated the 6502's reliance on the micro-op scheduler.
2017-06-03 20:30:07 -04:00
Thomas Harte
3ceef2005b
Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private.
2017-06-03 19:17:34 -04:00
Thomas Harte
24c84ca6f5
Commented out as-yet-unimplemented features.
2017-06-03 19:10:23 -04:00
Thomas Harte
7898f643ac
Added bus request/acknowledge logic.
2017-06-03 19:09:47 -04:00
Thomas Harte
7bd45d308a
Error was simply failure of the interrupt-mode setter. Fixed.
2017-06-03 18:58:13 -04:00
Thomas Harte
b3da16911f
Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
2017-06-03 18:42:54 -04:00
Thomas Harte
8c41a0f0ed
Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
2017-06-03 17:41:45 -04:00
Thomas Harte
a2ec902773
Made an attempt at implementing all three modes of IRQ.
2017-06-03 17:07:05 -04:00
Thomas Harte
1c0130fd02
Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute.
2017-06-03 12:19:25 -04:00
Thomas Harte
3e3d6f97f4
Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation.
2017-06-03 12:16:21 -04:00
Thomas Harte
9c3bda0111
Attempted to round out NMI handling.
2017-06-03 11:30:12 -04:00
Thomas Harte
d14902700a
Minor syntax and wiring fixes.
2017-06-01 22:33:05 -04:00
Thomas Harte
c95c32a9fe
Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
2017-06-01 22:31:04 -04:00
Thomas Harte
35e045d7a7
Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little.
2017-06-01 22:16:22 -04:00
Thomas Harte
084e1f3d51
Added a latching of interrupt status before each bus operation, and reset and power-on inputs.
2017-06-01 21:40:08 -04:00
Thomas Harte
5b43cefb85
Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts.
2017-06-01 20:34:52 -04:00
Thomas Harte
aab637c9e7
Made check_address_for_trap inlineable.
2017-06-01 18:28:34 -04:00
Thomas Harte
7d9b197383
Pulled the .get() call for fetch-decode-execute out of the main loop.
2017-06-01 18:28:04 -04:00
Thomas Harte
c9dd267ec1
Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP.
2017-05-31 22:51:32 -04:00
Thomas Harte
a5254989f8
Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase.
2017-05-31 20:15:56 -04:00
Thomas Harte
494ce073b5
Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
2017-05-31 19:58:57 -04:00
Thomas Harte
b99e4210ba
Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods.
2017-05-31 19:57:03 -04:00
Thomas Harte
d3b74cbc91
Set proper initial value for number_of_cycles_.
2017-05-31 19:55:51 -04:00
Thomas Harte
2f7f11e2e5
Added diagnosis props.
2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-30 22:41:23 -04:00
Thomas Harte
b5c1773d59
Eliminated another conditional. Albeit a very predictable one.
2017-05-30 22:15:43 -04:00
Thomas Harte
dfb5057342
Moved repetition group conditions explicitly into the switch statement.
2017-05-30 22:12:10 -04:00
Thomas Harte
7bddd294c9
Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run.
2017-05-30 21:03:02 -04:00
Thomas Harte
01f7394f7f
Corrected 6502 scheduling when flushing the pipeline.
2017-05-30 20:58:07 -04:00
Thomas Harte
5aa8b03349
Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
2017-05-30 20:36:53 -04:00
Thomas Harte
b5ad910b81
Merge branch 'Z80' into StraightPointer
2017-05-30 19:25:38 -04:00
Thomas Harte
da65bae86e
Switched to supplying the bus operation by reference, go guarantee that it isn't null.
2017-05-30 19:24:58 -04:00
Thomas Harte
a0189a6fe1
Switched to following the current program via address.
2017-05-30 18:49:40 -04:00
Thomas Harte
c6185baa99
Fixed R incrementation and attempted to make the status flags cheaper to write to.
2017-05-29 22:23:19 -04:00
Thomas Harte
9d29cefe75
Evicted manual memory management.
2017-05-29 21:44:33 -04:00
Thomas Harte
35f535b9a3
Noodled around with initial state.
2017-05-29 19:25:08 -04:00
Thomas Harte
8bfaa487ce
Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
2017-05-29 17:13:24 -04:00
Thomas Harte
0d067d2f01
Adjusted OTI/etc timing; 23 failures outstanding.
2017-05-29 16:54:45 -04:00
Thomas Harte
d66755fd1e
Corrected INI/D[r] timing. Down to 45 failures.
2017-05-29 16:50:52 -04:00
Thomas Harte
d290e3d99e
Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
2017-05-29 16:35:00 -04:00