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2978 Commits

Author SHA1 Message Date
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:16:10 +00:00
David Greene
bef8768bd0 Simplify operand padding by keying off tabs in the asm stream. If 
padding is disabled, tabs get replaced by spaces except in the case of
the first operand, where the tab is output to line up the operands after
the mnemonics.

Add some better comments and eliminate redundant code.

Fix some testcases to not assume tabs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77740 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 21:57:10 +00:00
Chris Lattner
a87dea4f8c switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:48:30 +00:00
Evan Cheng
ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:35:56 +00:00
Chris Lattner
82987bfe9b fix PR4650: we only track sizes for certain objects, so only put something 
into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77679 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 16:17:13 +00:00
Evan Cheng
ee42fd309e When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 23:29:25 +00:00
David Goodwin
8f65253236 Darwin assembler now recognizes "orn", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:51:41 +00:00
David Goodwin
7c92f3ac99 Darwin assembler now supports "rrx", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:38:40 +00:00
David Goodwin
d8c95b5ac2 Cleanup and include code selection for some frame index cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 18:56:48 +00:00
Evan Cheng
37b7387da9 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 08:33:02 +00:00
Dan Gohman
a4714e025d Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 01:56:29 +00:00
Evan Cheng
8770f747a9 tbb / tbh instructions only branch forward, not backwards. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:20:20 +00:00
Evan Cheng
d600522608 Add VFP3 D registers to the DPR register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:03:41 +00:00
Bob Wilson
b7d0c90c44 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 16:39:22 +00:00
Chris Lattner
b8f396bdbb fix PR4584 with a trivial patch now that the pieces are in place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 05:20:33 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 02:18:14 +00:00
Eric Christopher
c841fe5fd1 Add a couple more tests for the ptest intrinsics to make sure we're 
grabbing them all correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:51:15 +00:00
Eric Christopher
71c6753d03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:28:05 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
David Goodwin
6340632d3b Remove support for ORN to workaround <rdar://problem/7096522>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:51:25 +00:00
David Goodwin
5743854f47 Add workaround for <rdar://problem/7098328>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:15:38 +00:00
Chris Lattner
3e23d42dee fix testcase for previous patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77338 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:04:18 +00:00
Chris Lattner
bf15e433b9 Fix PR4639, a ELF-TLS regression from some of my refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:57:51 +00:00
David Goodwin
3583df7676 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:06:49 +00:00
Evan Cheng
bae20a6353 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 07:38:35 +00:00
Evan Cheng
6495f63945 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 05:48:47 +00:00
David Goodwin
1f0962756d ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 23:34:12 +00:00
David Goodwin
af0d08d55c Add ".w" suffix for wide thumb-2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:31:55 +00:00
Sanjiv Gupta
c3ee7960d9 Test case to check that separate section is created for a global variable specified with section attribute. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77195 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:20:41 +00:00
Chris Lattner
a759135168 update testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 15:52:58 +00:00
Chris Lattner
abb477f663 put normal data into .data instead of .data.rel on elf systems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77116 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 03:06:11 +00:00
Chris Lattner
30c4a3b9a8 finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal 
for now.  Make the section switching directives more consistent
by not including \n and including \t for them all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 01:24:18 +00:00
Chris Lattner
e3577da6d9 simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit 
and make it more aggressive, we now put:

const int G2 __attribute__((weak)) = 42;

into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:51:36 +00:00
Bob Wilson
8bb9e48752 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:39:34 +00:00
Chris Lattner
10cf6a6a4b add the most expedient hack to fix PR4619, along with a testcase. 
Thanks to Rafael for the great example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77083 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 17:57:37 +00:00
Evan Cheng
b140f4907c I've lost my mind. PR4572 has not been fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77031 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 01:11:46 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Evan Cheng
b2fa93dc1c Remove a duplicated test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77020 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:24:40 +00:00
Evan Cheng
caca2b659f Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 22:42:45 +00:00
Evan Cheng
0bc116192d Fix these tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 22:42:22 +00:00
Eric Christopher
a1a491c094 Move insertps tests to sse41 combo test file, convert to filecheck 
format and add an extract/insert test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 19:24:26 +00:00
Evan Cheng
f631a68cf8 Convert a test to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 06:01:46 +00:00
Chris Lattner
013e6b6309 Remove SectionKind::Small*. This was only used on mips, and is apparently 
a sad mistake that is regretted. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 03:11:51 +00:00
Richard Osborne
e23e0976c7 Add tests for handling of globals and tls on the XCore. These currently fail 
but pass when run against r76652.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:38:20 +00:00
Dan Gohman
d2cb3d2c32 Remove the IA-64 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:30:09 +00:00
Evan Cheng
eee839dd3c Thumb2 does not allow the use of "pc" register as part of the load / store address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 23:09:51 +00:00
Evan Cheng
d3d9d66dd2 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 18:27:47 +00:00
Chris Lattner
d58fb250bb merge one more sse41 test into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76853 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:49:39 +00:00
Chris Lattner
052876957c merge another sse41 test into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:43:48 +00:00
Chris Lattner
ca6883b007 merge sse41-pmovx.ll into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:39:09 +00:00
Chris Lattner
5fe2b03779 change a test to run in filecheck style. Rename it to be a general 
dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file.  Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the 
reg and mem forms of these instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:33:02 +00:00
Eric Christopher
1e5cdea9d7 Support insertps via the intrinsic and add a couple of simple 
testcases to make sure it's being generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 02:22:41 +00:00
Eric Christopher
3091719b90 Add test for pinsrd and pinsrb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76840 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 01:58:04 +00:00
Dan Gohman
608ad24ac3 Revert r75663 (and r76805), as it is causing regressions on powerpc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76823 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 00:09:46 +00:00
Dan Gohman
41d0b9d952 x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76817 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 23:26:55 +00:00
Dan Gohman
1c88efff02 Add -march=ppc32 lines so that this test doesn't ever default to ppc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76805 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:08:31 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Dan Gohman
784025039f Make the grep line in this test more specific, to avoid 
unintended matches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76802 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:02:42 +00:00
Evan Cheng
1e0c1588b1 Ignore undef uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76799 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 21:51:42 +00:00
Duncan Sands
ed4b2dc313 Revert commit 76707, it was breaking the llvm-gcc build 
on linux platforms.  The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 10:35:05 +00:00
Chris Lattner
828f704c10 set the ELF "small" flag on objects that end up in .rodata.cst4 consistently, 
updating a mips testcase to expect it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76707 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 00:41:56 +00:00
Evan Cheng
47b1e2afd0 Remove a big test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76669 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 22:52:04 +00:00
Evan Cheng
3ecadc816d Do not select tSXTB / tSXTH in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 18:15:26 +00:00
Chris Lattner
74625023a8 convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76591 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 17:36:24 +00:00
Chris Lattner
99bd8bf8a2 add a testcase for the pic16 section handling stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 16:48:20 +00:00
Evan Cheng
5d885023fe Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 09:15:00 +00:00
Chris Lattner
634d61b135 remove a very large testcase for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76537 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 06:28:36 +00:00
Evan Cheng
d101a72d79 Fix a dagga combiner bug: avoid creating illegal constant. 
Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76535 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 05:40:15 +00:00
Evan Cheng
af9e7a7c20 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:31:12 +00:00
Evan Cheng
c95be59371 Cross RC coalescing is now on by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:22:59 +00:00
David Greene
76081c4ef7 Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes 
next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 22:02:59 +00:00
Evan Cheng
87faa1fc67 Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:46:42 +00:00
Evan Cheng
33d0474bf5 Use TII->findCommutedOpIndices to find the commute operands (rather than guessing). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76472 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:16:08 +00:00
Evan Cheng
753480ad20 Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76458 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 19:47:55 +00:00
Dan Gohman
f241174421 Revert the addition of hasNoPointerOverflow to GEPOperator. 
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.

Remove a few optimizations that depended on this flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76437 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 17:43:30 +00:00
Chris Lattner
401e10c4fb implement a new magic global "llvm.compiler.used" which is like llvm.used, but 
doesn't cause ".no_dead_strip" to be emitted on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76399 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:14:25 +00:00
Evan Cheng
ba8dc03935 Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76398 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:10:07 +00:00
Jakob Stoklund Olesen
45d34fe358 Fix http://llvm.org/bugs/show_bug.cgi?id=4583 
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76373 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-19 19:09:59 +00:00
Evan Cheng
438d9900c0 Catch more coalescing opportunities. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76282 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 04:52:23 +00:00
Evan Cheng
5248468473 Enable cross register class coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 02:10:10 +00:00
Evan Cheng
59959cd966 Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76258 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:42:51 +00:00
Evan Cheng
47e9fab158 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76248 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:13:25 +00:00
Chris Lattner
a9af7e626c rename test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 18:05:55 +00:00
Eli Friedman
a64eb92fe3 Make promotion in operation legalization for SETCC work correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76153 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 05:16:04 +00:00
Anton Korobeynikov
b8e9ac834a Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 23:26:06 +00:00
Dale Johannesen
423ccfe51d Assume an inline asm might be a call, so we get 
stack alignment right when it is.  This is not
ideal but conservatively correct.  Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76120 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 22:34:45 +00:00
Jakob Stoklund Olesen
57e599a46b Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands. 
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:58:34 +00:00
Evan Cheng
5f15992b77 Changed my mind. We now allow remat of instructions whose defs have subreg indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76100 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:15:00 +00:00
Evan Cheng
2b48ab947c With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76094 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 18:44:05 +00:00
Anton Korobeynikov
ebfe2b2722 Make xfail proper 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:53:47 +00:00
Anton Korobeynikov
c975180624 Temporary disable 16 bit bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov
6ff3f2c710 Add bswap patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov
54681eca69 Fix logic inversion for RI-mode address selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:31:14 +00:00
Anton Korobeynikov
9419a0d13d Unbreak the test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76051 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:49 +00:00
Anton Korobeynikov
bb8a04806d Expand 32-bit bitconverts via memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:29 +00:00
Anton Korobeynikov
f2fd8ea1c9 Fix incomin arg stack frame offset in case we need to generate stack frame 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:29:57 +00:00
Anton Korobeynikov
5dd38de2c2 Revert the commit, it just hides the real bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov
75eef89ddb Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov
8bd0db7615 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:18:17 +00:00
Anton Korobeynikov
6fe326c713 Implement 'large' PIC model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov
48e8b3cc58 Implement shifts properly (hopefilly - finally!) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov
0a42d2b437 Properly handle divides. As a bonus - implement memory versions of them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov
014d4639d8 32 bit shifts have only 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov
1ed1e3ecd4 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov
720e3b00b8 Add support for 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:09:35 +00:00
Anton Korobeynikov
980d5503c3 Emit proper lowering of load from arg stack slot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:42 +00:00
Anton Korobeynikov
c772c4408e Implement dynamic allocas 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:15 +00:00
Anton Korobeynikov
c16cdc5de7 Add jump tables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:07:50 +00:00
Anton Korobeynikov
759205d1ac Add rotates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:49 +00:00
Anton Korobeynikov
cfca8b1f62 Add patterns for integer negate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:27 +00:00
Anton Korobeynikov
8c993e1632 Provide proper patterns for and with imm instructions. Tune the tests accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:00 +00:00
Anton Korobeynikov
25af73303f Add 32 bit and reg-imm and disable invalid patterns for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:32 +00:00
Anton Korobeynikov
747052c1a5 Add z9 and z10 target processors. Mark z10-only instructions as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:00 +00:00
Anton Korobeynikov
22836d1b31 Proper lower 'small' results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:58:24 +00:00
Anton Korobeynikov
eb68f1c661 Completel forgot about unconditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:52 +00:00
Anton Korobeynikov
bad769f11a Lower addresses of globals 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75960 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:27 +00:00
Anton Korobeynikov
ed1a6d4cad Test (incomplete) for easy muls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75959 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:03 +00:00
Anton Korobeynikov
8d1837d9be Provide "wide" muls and divs/rems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75958 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:56:42 +00:00
Anton Korobeynikov
ecf22d5bdc Tests for cmp / br_cc / select_cc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:53:15 +00:00
Anton Korobeynikov
ef5decab53 Emit callee-saved regs spills / restores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov
ba249e41f3 Some preliminary call lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov
3c98c616c5 Prologue / epilogue emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov
51f613fb2b Add simple frame index elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:25 +00:00
Anton Korobeynikov
81c0325cdf Provide proper test :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75938 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:48:59 +00:00
Anton Korobeynikov
711d5b68e0 Add address computation stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov
c8301d17a8 Add mem-imm stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:14 +00:00
Anton Korobeynikov
961bb6f430 Add stores and truncstores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:45:00 +00:00
Anton Korobeynikov
dc28955b3f Add patterns for various extloads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:44:30 +00:00
Anton Korobeynikov
9e4816e09f Add shifts and reg-imm address matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:43:18 +00:00
Anton Korobeynikov
a51752cbea Add bunch of 32-bit patterns... Uffff :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:42:31 +00:00
Anton Korobeynikov
da308c9a67 Add bunch of reg-imm movs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:34:50 +00:00
Anton Korobeynikov
89edcd0927 Provide masked reg-imm 'or' and 'and' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:57 +00:00
Anton Korobeynikov
c79629536a Fix test running lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:21 +00:00
Anton Korobeynikov
e6220fb230 Add reg-reg and pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:49 +00:00
Anton Korobeynikov
bdc9081693 Add sub reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:16 +00:00
Anton Korobeynikov
b573f99ab7 Add xor reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:31:28 +00:00
Anton Korobeynikov
26ba0b1ec5 Add or reg-reg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:53 +00:00
Anton Korobeynikov
0676d2887a Add add reg-reg and reg-imm patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:15 +00:00
Anton Korobeynikov
1cc9dc7267 Add simple reg-reg and reg-imm moves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:29:38 +00:00
Anton Korobeynikov
87a24e3ee4 Minimal lowering for formal_arguments / ret 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:59 +00:00
Anton Korobeynikov
b24f97dd74 Add testsuite dir for systemz stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:22 +00:00
Richard Osborne
db9e697725 Combine an unaligned store of unaligned load into a memmove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 12:50:48 +00:00
Richard Osborne
ccb7e96ef0 Expand unaligned 32 bit loads from an address which is a constant 
offset from a 32 bit aligned base as follows:

  ldw low, base[offset >> 2]
  ldw high, base[(offset >> 2) + 1]
  shr low_shifted, low, (offset & 0x3) * 8
  shl high_shifted, high, 32 - (offset & 0x3) * 8
  or result, low_shifted, high_shifted

Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662 Custom lower unaligned 32 bit stores and loads into libcalls. This is 
a big code size win since before they were expanding to upto 16
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:21:18 +00:00
Evan Cheng
378445303b Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 09:20:10 +00:00
Evan Cheng
a499effd3b ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill situations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75838 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 21:39:50 +00:00
Richard Osborne
1d05b237a5 Fix pattern for LD16S_3r, add basic tests to check load / store instructions 
are being properly selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 17:06:59 +00:00
Richard Osborne
3af282f16a Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 15:46:56 +00:00
Chris Lattner
4fb63d088b fix an arm codegen bug (the same as PR4482 on ppc) where available_externally 
symbols were not getting stubs.  While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 04:12:33 +00:00
Chris Lattner
392db3e11d get the PPC stub temporary label from the mangler instead of 
using horrible string hacking.  This gives us a different label,
but it's just an assembler temporary, so the name doesn't matter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 02:56:53 +00:00