Jim Grosbach
458f2dc5d1
imm12 operands aren't Thumb2 only, so rename the printer helper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:00:01 +00:00
Owen Anderson
162875a9f3
Add correct instruction encodings for vbic, vorn, and vmvn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:43:52 +00:00
Rafael Espindola
4921e2356e
Add a virtual destructor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:38:32 +00:00
Owen Anderson
8c71eff594
Provide correct NEON encodings for vand, veor, and vorr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:28:30 +00:00
Owen Anderson
d0c5b6170f
Add NEON encoding tests for vcgt and vacgt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:03:59 +00:00
Rafael Espindola
cecbc3d282
Add support for emitting ARM file attributes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:50:35 +00:00
Owen Anderson
10c15e5d58
Add tests for NEON encodings of vcge and vacge.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:49:32 +00:00
Owen Anderson
4fe20bbd66
Add a warning about our inability to test the encoding of vceq with immediate zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:33:02 +00:00
Eric Christopher
a4633f5d74
Move rejection of NEON parameters earlier in fast isel call processing,
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note that we can actually handle some f64 arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:37:17 +00:00
Chandler Carruth
19e57025d4
Move the remaining attribute macros to systematic names based on the attribute
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name and prefixed with 'LLVM_'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:40:19 +00:00
Chandler Carruth
100c267249
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
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until other LLVM projects using these are cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:10:43 +00:00
Evan Cheng
5c2d428f43
Enable ARM fastcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:19:37 +00:00
Evan Cheng
dd9dd6f857
Latency between CPSR def and branch is zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:04:38 +00:00
Jim Grosbach
a9a968d1ef
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:48:29 +00:00
Gabor Greif
41f31ef28e
fix memory-layout assumption which only holds on little-endian systems
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:16:11 +00:00
Jim Grosbach
f8da5f5dfa
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 22:12:16 +00:00
Evan Cheng
b179b46cc5
Transfer implicit ops when forming load multiple and return instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 21:29:58 +00:00
Owen Anderson
9b26497273
Add correct NEON encodings for vqdmlal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:35:48 +00:00
Jim Grosbach
385e136dce
Add the encoding information for the rest of the ARM mode multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:15:30 +00:00
Owen Anderson
92205842ca
Provide correct encodings for NEON vmlal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:05:25 +00:00
Evan Cheng
1f8b40d51c
Silence compiler warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:57:05 +00:00
Owen Anderson
18341e9e31
Provide correct NEON encodings for vmla.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:54:37 +00:00
Jim Grosbach
3870b750e6
More ARM multiply instuction binary encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:35:16 +00:00
Evan Cheng
76f920d316
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:23:05 +00:00
Jim Grosbach
929a7056d8
Parameterize a bit of ARM encoding information, simplifying some instruction
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definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:42:06 +00:00
Jim Grosbach
9463d0e400
More ARM multiply instruction encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:16:17 +00:00
Wesley Peck
eecb858ca8
Making the e_machine configurable by the target backend in ELFObjectWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 15:52:49 +00:00
Eric Christopher
4f512efee9
Add some basic ret instruction support to arm fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:28:00 +00:00
Jim Grosbach
f50af8b5b8
ARM binary encoding for some of the multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:52:30 +00:00
Jim Grosbach
3686046a2c
ARM binary encodings for MVN variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:19:32 +00:00
Jim Grosbach
3fea19105d
ARM Binary encoding information for BFC/BFI instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:03:21 +00:00
Eric Christopher
1778772d1b
These don't need to be virtual.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 21:47:51 +00:00
Owen Anderson
90d4cf9314
Move the encoding logic for Q registers into getMachineOpValue().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:49:13 +00:00
Owen Anderson
d451f888b8
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
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half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:21:49 +00:00
Eric Christopher
5b924809e4
Handle storing args to the stack for calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:09:54 +00:00
Eric Christopher
212ae937bb
More load/store refactoring, call reg+offset simplification from within
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the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:40:30 +00:00
Jim Grosbach
3ab5658a12
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:38:40 +00:00
Owen Anderson
1e93466c3a
Add correct NEON encodings for vhadd and vrhadd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:55:04 +00:00
Owen Anderson
9d50559bae
Add correct encodings for NEON vaddw.s* and vaddw.u*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:20:25 +00:00
Owen Anderson
e0e6dc3f4e
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:09:17 +00:00
Duncan Sands
dbbd99faf1
The return value of this call is not used, so no point
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in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:06:28 +00:00
Andrew Trick
5b7a825ec5
putback r116983 and fix simple-fp-encoding.ll tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:40:16 +00:00
Owen Anderson
d9707e3d85
Revert r116983, which is breaking all the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:11:16 +00:00
Evan Cheng
d6865de2d2
Add missing scheduling itineraries for transfers between core registers and VFP registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 01:12:00 +00:00
Owen Anderson
d7795540d0
Implement correct encodings for NEON vadd, both integer and floating point.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:48:00 +00:00
Eric Christopher
2d8f6fe610
Custom lower f64 args passed in integer registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:01:47 +00:00
Bill Wendling
01aabdac44
Add encoding for moving a value between two ARM core registers and a doublework
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extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 23:37:40 +00:00
Bill Wendling
7d31a169af
Add encodings for movement between ARM core registers and single-precision
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registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:44:54 +00:00
Dale Johannesen
e4d31593c5
Fix crash introduced in 116852. 8573915.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:03:37 +00:00
Chandler Carruth
1cd9708f5c
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
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#includes in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:27:02 +00:00
Eric Christopher
3659ac22c0
Fix a TODO by removing some unnecesary copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:02:24 +00:00
Jim Grosbach
b8e67fc92b
Fix backwards conditional.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 01:10:01 +00:00
Jim Grosbach
8b95c3ebfb
Add dynamic realignment when rematerializing the base register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 00:02:50 +00:00
Jim Grosbach
f6d7df6f21
Nuke a commented out bit that got missed a while back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:48:47 +00:00
Jim Grosbach
e4ad387a5a
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
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setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:27:08 +00:00
Jim Grosbach
8155ea4c3a
Update comments to remove obsolete references.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 21:34:47 +00:00
Dale Johannesen
575cd148ce
Enable using vdup for vector constants which are splat of
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integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 20:00:17 +00:00
Evan Cheng
2312842de0
Re-enable register pressure aware machine licm with fixes. Hoist() may have
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erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 18:58:51 +00:00
Daniel Dunbar
9869413802
Revert r116781 "- Add a hook for target to determine whether an instruction def
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is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:14:24 +00:00
Evan Cheng
11e8b74a7a
- Add a hook for target to determine whether an instruction def is
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"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:55:07 +00:00
Bob Wilson
3454ed9545
Support alignment for NEON vld-lane and vst-lane instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:16:32 +00:00
Jim Grosbach
70987fbc60
ARM encoding information for [SU]SAT* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 23:35:38 +00:00
Eric Christopher
6e5367d6a3
Revert r116220 - thus turning arm fast isel back on by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 22:53:53 +00:00
Bill Wendling
b41ee96d76
Don't recompute MachineRegisterInfo in the Optimize* method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 21:22:31 +00:00
Jim Grosbach
5c57639c28
For Thumb2, try to use frame pointer references for stack slots even when a
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base register is available. rdar://8525298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:39:46 +00:00
Jim Grosbach
0f0127f4a6
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
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offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:48:59 +00:00
Jim Grosbach
e038a206df
Grammar tweak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:38:50 +00:00
Eric Christopher
4cf34c6c04
Remove the check for invalid calling conventions. Testing shows that they're
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working just fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 06:49:12 +00:00
Eric Christopher
fa87d66752
Lift arg promotion from the X86 backend. This should be unified at some point.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 02:17:53 +00:00
Eric Christopher
404be0c04f
Now that we handle all allocas via a non-SP reg offset remove all of the
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special case handling for ARM::SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 11:08:44 +00:00
Eric Christopher
ec8bf972f5
Allow more load types to be materialized through the allocas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 06:07:26 +00:00
Eric Christopher
d56d61af01
Optimize GEP off of intermediate allocas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:51:42 +00:00
Eric Christopher
7208dbf2d5
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:42:53 +00:00
Eric Christopher
dc0b0ef6cd
Turn on AddOperator folding in GEP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:41:46 +00:00
Eric Christopher
45c607134b
Use the i12 immediate versions of the load instructions - they're handled
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more in the post-passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:40:27 +00:00
Rafael Espindola
f230df9af4
Add a MCObjectFormat class so that code common to all targets that use a
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single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 18:23:53 +00:00
Eric Christopher
47650ece37
Fix some funky formatting that got through.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 01:10:35 +00:00
Bill Wendling
07fda9f9b6
ARMCodeEmitter::emitMiscInstruction is dead. Long live
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ARMCodeEmitter::emitMiscInstruction!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:35:12 +00:00
Eric Christopher
c9a91fdaf9
Make sure offset is 0 for load/store register to the stack call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:07:10 +00:00
Eric Christopher
00ed59a968
Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 22:49:28 +00:00
Eric Christopher
315030ca74
Fix else if -> if in store machinery.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 22:32:37 +00:00
Bill Wendling
2695d8edd1
Reformatting. No functionalogicality changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:50:45 +00:00
Eric Christopher
a322425642
Refactor ARM fast-isel reg + offset to be a base + offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:32:12 +00:00
Jim Grosbach
5ad01c7728
Encoding information for the various ARM saturating add/sub instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 19:49:46 +00:00
Jim Grosbach
84760885e1
ARM binary encoding information for RSB and RSC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:42:41 +00:00
Jim Grosbach
fd52906478
Don't mark argument value stores as immutable, as otherwise the post-RA
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scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:34:47 +00:00
Bob Wilson
01b35c25de
Use simple RegState::Define flag instead of getDefRegState(true).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:25:59 +00:00
Eric Christopher
2896df897c
Expand GEP handling for constant offsets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:02:07 +00:00
Jim Grosbach
6bdc8ae291
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
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an explicit def. Make sure to capture that properly. rdar://8556556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 17:35:17 +00:00
Jim Grosbach
8abe32af38
ARM mode encoding information for UBFX and SBFX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 17:15:16 +00:00
Bob Wilson
1dd5a2f4e1
Remove unused ARMISD::AND selection DAG node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 04:34:40 +00:00
Bob Wilson
cfbece50f6
ARM instructions that are both predicated and set the condition codes
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have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 03:23:44 +00:00
Jim Grosbach
197a8df640
Encoding info for extension instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 02:29:58 +00:00
Jim Grosbach
58456c0b04
Add missing Rd encoding for MOVs instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 23:28:31 +00:00
Jim Grosbach
7032f922b1
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
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and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
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pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69
MOVi16 and MOVT ARM mode encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 18:54:27 +00:00
Jim Grosbach
2d294f564b
Simplify encoding information and add 'dst' operand info for TAILJMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 17:24:28 +00:00
Oscar Fuentes
7bd698153d
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
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creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 15:54:46 +00:00
Eric Christopher
eae8439771
Handle more complex GEP based loads and add a few TODOs to deal with
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GEP + alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 09:29:41 +00:00
Bill Wendling
bbbdcd453d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
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here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 02:33:26 +00:00
Bill Wendling
946a2740a5
Add encoding for 'fmstat'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436
- Add encodings for multiply add/subtract instructions in all their glory.
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- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:02:08 +00:00
Jim Grosbach
bd38acfa6f
Regenerate. No functional change, just cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 00:15:18 +00:00
Jim Grosbach
55561d1882
Detabify and clean up 80 column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:47:11 +00:00
Jim Grosbach
95369599c6
A few 80 column fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:34:31 +00:00
Jim Grosbach
3a37866e53
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:12:26 +00:00
Jim Grosbach
b4b07b93ea
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c
Add operand encoding bits for SMC and SVC in ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062
More encoding cleanup. Also add register Rd operands for indirect branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7
Simplify some ARM encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5
Add a FIXME. The ADR instruction is a bit odd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03
Add MC encodings for VCVT* instrunctions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
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wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509
Fix encoding for compares. No Rd register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70
Add ARM mode operand encoding information for ADDE/SUBE instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:00:52 +00:00
Eric Christopher
ede42b0a22
Start handling more global variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 09:11:46 +00:00
Evan Cheng
14ce175216
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 01:54:21 +00:00
Bill Wendling
6932643a37
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
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just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b
Add encodings for VCVT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
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arithmetic-with-carry-in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f
Add VCMPZ and VABS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254
Refactor VCMP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044
Add the rest of the ARM so_reg encoding options (register shifted register)
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and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:53:58 +00:00
Bill Wendling
5a1fd8cf68
Add encodings for VNMUL[SD].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab
Add encodings for VDIV and VMUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:22:27 +00:00
Jim Grosbach
2a6a93d542
Move the ARM so_imm encoding into a custom operand encoder and remove the
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explicit handling of the instructions referencing it from the MC code
emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:18:08 +00:00
Bill Wendling
52061f83e7
Refactor some of the encoding logic into a base class. This keeps us from having
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to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6
Add encoding for VSUB and VCMP.
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Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b
Encoding for VADDD. Plus a test for the VFP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6
Split out the "size" field from the encoding. The newer documentation has it as
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a separate bit in the coding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5
Fix thinko in arm fast isel alloca rewrite.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6
Encoding for ARM-mode VADD.F32 instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 21:22:40 +00:00
Jim Grosbach
f59818b81a
Add MOVi ARM encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 18:09:12 +00:00
Jim Grosbach
8e157302f4
Nuke unused wrapper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:53:25 +00:00
Jim Grosbach
0de6ab3c43
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278
PR8359: The ARM backend may end up allocating registers D16 to D31 when
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"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941
Rework alloca handling so that we can load or store from casted
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address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57
Handle a wider arrangement of loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27
More ARM scheduling itinerary fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43
Second set of ARM/MC/ELF changes.
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Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f
Proper VST scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b
Use a sane mechanism for that assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9
We're not going to handle dynamic allocas anywhere else.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e
Make sure that the call stack adjustments have default operands. Also
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leave custom lowerings for later.
Fixes some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:20:02 +00:00
Eric Christopher
8ff9a9da0a
Found a bug turning this on by default. Disable again for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd
Fix help text.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6
Change flag from Enable to Disable since we're enabled by default.
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Also don't use fast-isel on non-darwin since it's untested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:05:22 +00:00
Jim Grosbach
62547267f0
More binary encoding stuff, taking advantage of the new "by name" operand
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matching in tblgen to do the predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e
Turn on arm fast isel by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9
Copy and pasteo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43
Whitespace cleanup in ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:38:55 +00:00
Eric Christopher
6a880d6ba8
Add srem libcall support to ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:37:26 +00:00
Eric Christopher
7bdc4de4e7
Add i8 sdiv support for ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:31:54 +00:00
Eric Christopher
3bbd396853
Implement select handling for ARM fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:27:59 +00:00
Evan Cheng
10dc63feeb
Add VLD4 scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 04:07:58 +00:00
Evan Cheng
84f69e8436
Finish vld3 and vld4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:45:34 +00:00
Evan Cheng
40bb6836f6
Complete vld2 instruction itineries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:26:12 +00:00
Evan Cheng
8ae6ffacdd
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:15:04 +00:00
Evan Cheng
d2ca813549
Correct some load / store instruction itinerary mistakes:
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1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:03:04 +00:00
Bill Wendling
0aa38b9381
Check to make sure that the iterator isn't at the beginning of the basic block
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before decrementing. <rdar://problem/8529919>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 00:03:48 +00:00
Eric Christopher
e93417bcc8
Fix the store part of this as well. Fixes smg2000.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 23:52:16 +00:00
Jim Grosbach
56ac907c57
Implement a few more binary encoding bits. Still very early stage proof-of-
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concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 21:45:55 +00:00
Jim Grosbach
3e09413c2c
Reapply 116059, this time without the fatfingered pasto at the top.
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''const'ify getMachineOpValue() and associated helpers.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:45:54 +00:00
Jim Grosbach
2cee75a254
Reverting 116059. Bots are unhappy with it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:28:40 +00:00
Jim Grosbach
461caba214
'const'ify getMachineOpValue() and associated helpers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 16:52:44 +00:00
Bob Wilson
7d24705f65
Change register allocation order for ARM VFP and NEON registers to put the
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callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 06:15:13 +00:00
Eric Christopher
7a56f33583
Move to thumb2 loads, fixes a problem with incoming registers
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as thumb1.
Fixes lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:13:17 +00:00
Jim Grosbach
58f38bfa24
Enable binary encoding of some simple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Evan Cheng
344d9db970
Code refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:12:15 +00:00
Jim Grosbach
d6d4b42ba4
Trivial MC code emitter shell. No instruction forms actually handled yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:12:50 +00:00
Jim Grosbach
9af82ba42b
Include the auto-generated bits for machine encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:57:55 +00:00
Eric Christopher
df1f5a924e
Remember to promote load/store types for stack to register size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:40:18 +00:00
Jim Grosbach
ae93ed1dd7
ARM instruction don't have instruction prefixes, so remove the helper functions
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for them from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:41:30 +00:00
Eric Christopher
ee56ea6243
Use the correct register class for load instructions - fixes
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compilation of MultiSource/Benchmarks/Bullet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:50:44 +00:00
Eric Christopher
5d18d92aad
Use the correct register class here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:39:19 +00:00
Eric Christopher
338c253d7e
Use the thumb2 conditional move instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:31:49 +00:00
Eric Christopher
1107734e22
Remove in-progress assertion, add TODO.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:14:08 +00:00
Evan Cheng
5a50ceeaea
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:50:48 +00:00
Jim Grosbach
a4257162be
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:53:56 +00:00
Jim Grosbach
3bbdcea49a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:42:42 +00:00
Jim Grosbach
fa7fb64fad
remove trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7
First in a sequence of ARM/MC/*ELF* specific work.
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Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:36:46 +00:00
Jim Grosbach
3c38f96af2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
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"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:22:32 +00:00
Jim Grosbach
65dc30340c
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
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pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 21:16:16 +00:00
Jim Grosbach
7cd2729d2a
Add a 'pattern' arg to the ARM PseudoNeonI class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 20:36:55 +00:00
Jim Grosbach
4dea941c8d
target operand flag values aren't a bitmask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 16:51:55 +00:00
Evan Cheng
a0792de66c
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
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allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 06:27:31 +00:00
Chris Lattner
78caacc226
replace stuff like:
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let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:05:18 +00:00
Eric Christopher
e540a6f94a
Comment out fastisel debugging message.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:50:58 +00:00
Eric Christopher
022b7fb045
Random cleanup and make the intermediate register in fptosi a
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32-bit fp reg, not 64-bit.
Fixes SingleSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:13:24 +00:00
Jim Grosbach
d86609fca4
Increase the number of bits used internally by the ARM target to represent the
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addressing mode from four to five.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 18:14:55 +00:00
Michael J. Spencer
f000a7a212
fix MSVC 2010 build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:00:43 +00:00
Michael J. Spencer
2bbb769091
Cleanup Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:00:33 +00:00
Rafael Espindola
0febc4657b
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
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so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:59:45 +00:00
Evan Cheng
ec45f60cab
Major changes to Cortex-A9 itinerary.
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1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 02:03:59 +00:00
Eric Christopher
890dbbec57
Start on lowering global addresses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 00:32:44 +00:00
Jim Grosbach
443e625d8a
PrintSpecial() can go away now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:27:48 +00:00
Eric Christopher
c9932f6f60
Stub out constant GV handling, fixes C++ eh tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:24:42 +00:00
Jim Grosbach
78890f41f4
Nuke the rest of the :comment references
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:21:38 +00:00
Jim Grosbach
adde5da638
Nuke a bunch of no-longer-needed comment-only asm strings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 23:09:33 +00:00
Evan Cheng
055028215d
Fix r115332: correctly model AGU / NEON mux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:52:29 +00:00
Owen Anderson
e3cc84a43d
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
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stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:45:50 +00:00
Jim Grosbach
7ac1609a3b
Rename the AsmPrinter directory to InstPrinter for those targets that have
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been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 22:39:28 +00:00
Evan Cheng
ef0ccad725
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 21:48:06 +00:00
Evan Cheng
df9da6a033
Add operand cycles for vldr / vstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 21:40:30 +00:00
Eric Christopher
e6ca6771e3
Direct calls only for arm fast isel for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 21:33:12 +00:00
Evan Cheng
cae6a12a99
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:50:58 +00:00
Eric Christopher
45547b844d
Fix thinko on store instructions. Fixes test_indvars failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:46:04 +00:00
Owen Anderson
00d4f48168
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:33:47 +00:00
Owen Anderson
aa9f0a57d0
Provide an option to restore old-style if-conversion heuristics for Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:28:06 +00:00
Evan Cheng
7c3423f413
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 19:41:46 +00:00
Jim Grosbach
bffa1a5cf3
grammar
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 14:57:48 +00:00
Eric Christopher
14df88282b
Implement double return values in calls. Fixes
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SingleSource/Regression/C/casts.c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 00:00:11 +00:00
Owen Anderson
b3c04ec956
Temporarily add a flag to make it easier to compare the new-style ARM if
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conversion heuristics to the old-style ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115239 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:48:38 +00:00
Eric Christopher
086378597d
Movement and cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 22:34:19 +00:00
Eric Christopher
f9764fa14f
Start of generalized call support for ARM fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 20:49:44 +00:00
Jim Grosbach
a3fbadfcd8
Nuke a few more unused asm strings
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 19:53:58 +00:00
Jim Grosbach
3787a40e03
Move getPointerSize() to the base class since it's not dependent on MachO
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vs. ELF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:45:51 +00:00
Jim Grosbach
af2a8b21f1
Remove extraneous ';'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:19:17 +00:00
Jim Grosbach
71d933a49e
The asm strings are never used at all, so just nuke 'em entirely.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:56:53 +00:00
Kevin Enderby
8ebf66236e
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
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for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 16:38:07 +00:00
Jim Grosbach
2f24c4ece0
80 column fix
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 15:25:22 +00:00
Jason W Kim
a4c27248b5
Fix two tiny issues (ARM does not need COFF) and comment sanity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 14:58:19 +00:00
Jim Grosbach
f73fd7278f
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:21:00 +00:00
Jim Grosbach
87dc3aa2d8
Remove misplaced ';'. Make buildbots happy, hopefully.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 03:20:34 +00:00
Jason W Kim
afd1cc2578
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:45:56 +00:00
Jim Grosbach
7ebc863c15
Go ahead and jump!
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Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:18:06 +00:00
Jason W Kim
d4d4f4f488
I added a new file ARMAsmBackend which stubs out in similar ways to
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the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:17:26 +00:00
Jim Grosbach
a4e97de71d
Now that the pseudos that needed this are all custom lowered, we can go back
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to an empty PrintSpecial()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 02:02:22 +00:00
Jim Grosbach
2317e40539
Nuke it from orbit. It's the only way to be sure.
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(Kill the dead non-MC asm printer for the ARM target.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 01:57:53 +00:00
Evan Cheng
0e55fd61ae
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 01:08:25 +00:00
Eric Christopher
a9a7a1a9a5
Refactor arm fast isel libcall handling so that pieces can be used
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for generic call handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115105 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 23:11:09 +00:00
Evan Cheng
3881cb7a5d
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 22:42:35 +00:00
Eric Christopher
8cf6c60710
Add a convenience variable so I'm not chasing all over looking for
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a context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 22:24:45 +00:00
Jim Grosbach
828916203a
Add specializations of addrmode2 that allow differentiating those forms
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which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 19:03:54 +00:00
Bob Wilson
7122ba7efb
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 17:54:10 +00:00
Jim Grosbach
be91232900
Add braces for legibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 17:32:29 +00:00
Jim Grosbach
b454cdaebc
One Printer to rule them all, One Printer to find them,
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 15:23:40 +00:00
Gabor Greif
05642a3eba
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 10:12:08 +00:00
Chris Lattner
7c51a3172c
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:50:45 +00:00
Chris Lattner
7036f8be4d
change the protocol TargetAsmPArser::MatchInstruction method to take an
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MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:42:58 +00:00
Eric Christopher
229207aa2e
Rework comparison handling to set a register on true/false. This avoids
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problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:14:47 +00:00
Eric Christopher
f8476e6742
Remove unnecessary set ahead of time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:50:57 +00:00
Evan Cheng
5d42c567c9
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:49:25 +00:00
Eric Christopher
98de5b4603
Remove assert, add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:49:09 +00:00
Evan Cheng
7e1bf305cf
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:27:46 +00:00
Evan Cheng
63d66eed16
Add support to model pipeline bypass / forwarding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 23:50:49 +00:00
Eric Christopher
744c7c8e1b
32-bit constant ints only for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 22:47:54 +00:00
Oscar Fuentes
3609eb0de2
Removed a bunch of unnecessary target_link_libraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 22:39:14 +00:00
Owen Anderson
654d5440a4
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:57:50 +00:00
Eric Christopher
fd60980eb2
Integer materialization needed the same thinko change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:55:34 +00:00
Nick Lewycky
a6136b7156
Resolve this GCC warning:
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ARMTargetMachine.cpp:53: error: control reaches end of non-void function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:40:26 +00:00
Anton Korobeynikov
4f922f2cca
User proper libcall names & condcodes while compiling for ARM EABI.
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Patch by Evzen Muller!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:39:26 +00:00
Owen Anderson
b20b85168c
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
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Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 18:32:13 +00:00
Jim Grosbach
2d0f53bd63
Factor out dbg_value comment printing and teach MC asm printing to use it.
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This should make the arm-linux self-host buildbot happy again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 17:05:56 +00:00
Oscar Fuentes
38e1390c29
Add ARM Disassembler to the CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 11:48:19 +00:00
Eric Christopher
a99c3e9acd
80-col fixups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 04:18:29 +00:00
Bob Wilson
02aba73a9e
Add a command line option "-arm-strict-align" to disallow unaligned memory
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accesses for ARM targets that would otherwise allow it. Radar 8465431.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 04:09:35 +00:00
Eric Christopher
7ed8ec94d9
Rework builtin handling and call setup. The builtin handling
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now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 01:21:42 +00:00
Eric Christopher
5371cabfc2
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 00:35:33 +00:00
Eric Christopher
f5732c4ee5
Fix fp constant loads to have a destination register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 00:35:09 +00:00
Jim Grosbach
385cc5eede
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 22:28:11 +00:00
Jim Grosbach
5acb3de8b7
ARM-mode eh.sjlj.longjmp MC lowering
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 21:47:04 +00:00
Jim Grosbach
376ce97bac
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 21:28:44 +00:00
Daniel Dunbar
3b9569e70d
Hard to imagine there are still people using inferior compilers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 20:12:58 +00:00
Rafael Espindola
fd9493d74e
Odd additional stub framework for the ARM MC ELF emission.
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llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 18:31:37 +00:00
Eric Christopher
1127c720ed
Insert missing coherency in comment. Add a quick check for hardware
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divide support also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:08:12 +00:00
Eric Christopher
43b62beb4c
Mass rename for Jim.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:02:23 +00:00
Evan Cheng
5981fc6788
Fix IIC_iEXTAr itinerary class of Cortex-A9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:09:28 +00:00
Evan Cheng
27fdcd1c95
Remove a unused instruction itinerary class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:06:02 +00:00
Evan Cheng
576a3968a2
Fix zero and sign extension instructions scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 00:49:35 +00:00
Evan Cheng
bd30ce4311
More pseudo instruction scheduling itinerary fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:41:41 +00:00
Evan Cheng
5be3922321
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:03:46 +00:00
Jim Grosbach
433a5785cc
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 20:47:58 +00:00
Evan Cheng
fff606d7b2
Enable code placement optimization pass for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:07:23 +00:00
Evan Cheng
de0e11c8f3
Fix a potential null dereference bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 05:18:35 +00:00
Owen Anderson
f523e476c2
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Bob Wilson
2a6e616142
Set alignment operand for NEON VST instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:42:37 +00:00
Jim Grosbach
453900814e
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:33:56 +00:00
Jim Grosbach
b327e13740
#+4 --> #4 for consistency with other asm output
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:32:38 +00:00
Jim Grosbach
45d6c1777c
Fix formatting of output .s code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:03:26 +00:00
Owen Anderson
71e416ac3a
Add isConditionalMove bits to X86 and ARM instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:57:01 +00:00
Bob Wilson
40ff01a030
Set alignment operand for NEON VLD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 21:43:54 +00:00
Jim Grosbach
b2dda4bd34
never mind. I can't read, apparently
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:42:17 +00:00
Evan Cheng
676e258366
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:42:03 +00:00
Jim Grosbach
24e6f2f802
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
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constant. Hopefully the non-Darwin bots will like it...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:32:40 +00:00
Jim Grosbach
5c49b69609
explicit 'unsigned long' on constant value. Hopefully make bots happier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 19:08:04 +00:00
Benjamin Kramer
c8ab9eb066
Unbreak build. Jim, please review.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 18:57:26 +00:00
Jim Grosbach
2e6ae13bf6
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 18:05:37 +00:00
Jim Grosbach
16c9a64c28
nuke unused var
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 17:58:00 +00:00
Evan Cheng
108c872466
If there are multiple unconditional branches terminating a block, eliminate all
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but the first one. Those will never be executed. There was logic to do this
but it was faulty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 06:54:40 +00:00
Jim Grosbach
637d89fe0e
Add support for ELF PLT references for ARM MC asm printing. Adding a
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new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 23:27:36 +00:00
Jim Grosbach
b6ec8cae3c
Enable a few additional asserts in MC instruction lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 23:01:28 +00:00
Bob Wilson
b68987e4bf
Change VDUPLANE DAG combiner to just return the result instead of calling
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CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:27:30 +00:00
Bob Wilson
0b8ccb8252
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
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of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:09:21 +00:00
Jim Grosbach
f0633e48eb
add FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:55:15 +00:00
Jim Grosbach
bfbe187593
Remove a few commented out bits
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 20:32:34 +00:00
Jim Grosbach
00d01f1a42
Add PrintSpecial() handling for in ARM MC instruction printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 18:37:14 +00:00
Jim Grosbach
a2244cb387
Add MC instruction printer support for ARM and Thumb1 jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:39:48 +00:00
Jim Grosbach
205a5fa8e4
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 17:15:35 +00:00
Jim Grosbach
1b935a3d2e
Clean up comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 16:45:13 +00:00
Evan Cheng
691e64a54c
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:49:07 +00:00
Jim Grosbach
882ef2b76a
Add start of support for MC instruction printer of ARM jump tables. Filling in
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the rest of it is next up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:28:16 +00:00
Owen Anderson
8614167572
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
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irrelevant, but add a new test for the new, improved functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:51:46 +00:00
Chris Lattner
52a261b3c1
fix a long standing wart: all the ComplexPattern's were being
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passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:31:19 +00:00
Chris Lattner
fc448ff89b
convert a couple more places to use the new getStore()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:51:21 +00:00
Bob Wilson
65ffec49f7
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
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and store intrinsics are represented with MemIntrinsicSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 17:56:22 +00:00
Jim Grosbach
532baa5d53
Fix errant printing of [v]ldm instructions that aren't a pop
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 16:45:31 +00:00
Gabor Greif
8ff9bb189c
Fix buglet when the TST instruction directly uses the AND result.
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I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 13:30:57 +00:00
Gabor Greif
04ac81d5db
Move the search for the appropriate AND instruction
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into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 12:01:15 +00:00
Chris Lattner
d1c24ed81c
convert the targets off the non-MachinePointerInfo of getLoad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:44:06 +00:00
Chris Lattner
e72f2027e9
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
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instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4
convert targets to the new MF.getMachineMemOperand interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 04:39:43 +00:00
Jim Grosbach
1dc335a79f
Simplify ARM callee-saved register handling by removing the distinction
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between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:32:20 +00:00
Michael J. Spencer
895dda6fb5
Fix build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 17:54:37 +00:00
Eric Christopher
c109556a0a
Thumb opcodes for thumb calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 02:32:38 +00:00
Eric Christopher
6dab137b88
Add addrmode5 fp load support. Swap float/thumb operand adding to handle
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thumb with floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:59:37 +00:00
Eric Christopher
b74558ad3e
Floating point stores have a 3rd addressing mode type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:23:38 +00:00
Jim Grosbach
988ce097b7
factor out a simple helper function to create a label for PC-relative
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instructions (PICADD, PICLDR, et.al.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:05:05 +00:00
Jim Grosbach
d30cfde935
PC-relative pseudo instructions are lowered and printed directly. Any encounter
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with one in the generic printing code is an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:04:53 +00:00
Benjamin Kramer
92aa1f7123
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:48:07 +00:00
Jim Grosbach
fbd1873041
Add MC-inst handling for tPICADD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:41:53 +00:00
Bob Wilson
75f0288b7d
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
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value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
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and shift instructions on ARM. Update the tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Eric Christopher
a5b1e68107
Rework arm fast isel branch and compare code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
74d7e6c64e
Hook up verbose asm comment printing for SOImm operands in MC printer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:33:25 +00:00
Jim Grosbach
196b48b708
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:25:10 +00:00
Jim Grosbach
568eeedea7
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:46:17 +00:00
Jim Grosbach
c686e33d12
handle the upper16/lower16 target operand flags on symbol references for MC
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instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:25:25 +00:00
Jim Grosbach
a28abbe245
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 16:25:52 +00:00
Jim Grosbach
b74ca9d631
MC-ization of the PICLDR pseudo. Next up, adding the other variants
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(PICLDRB, et. al.) and PICSTR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:43:25 +00:00
Jim Grosbach
1d51c41a45
Make sure to promote single precision floats to double before extracting them
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from the APFloat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:37:30 +00:00
Bob Wilson
de0ae8f83d
Remove support for "dregpair" operand modifier, now that it is no longer being
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used for anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:55:00 +00:00
Bob Wilson
823611bfba
When expanding ARM pseudo registers, copy the existing predicate operands
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instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:25:37 +00:00
Jim Grosbach
a8e47b3319
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
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unnecessary dtor for MCOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 03:45:21 +00:00
Bob Wilson
ea606bb76b
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:32 +00:00
Bob Wilson
9d4ebc0eb8
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
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register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:02 +00:00
Jim Grosbach
765c4d9477
Add support for the 'lane' modifier on vdup operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 22:13:23 +00:00
Jakob Stoklund Olesen
06f264e504
Remember VLDMQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:11 +00:00