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544 Commits

Author SHA1 Message Date
Lauro Ramos Venancio
da4842e266 Define StaticCtorsSection and StaticDtorsSection for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32763 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-28 13:13:00 +00:00
Lauro Ramos Venancio
301009a0fc Implement SELECT_CC (f32/f64) for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32762 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-28 13:11:14 +00:00
Rafael Espindola
6547c55988 remove duplicated line 
bug noticed by Lauro


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32761 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio
a8f9f4af54 This patch defines extloadi1 and fixes an internal compiler error on 
arm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32760 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-26 19:30:42 +00:00
Chris Lattner
1a199de813 Fix for ARM weak symbols, patch by Lauro Ramos Venancio! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32740 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-21 22:59:58 +00:00
Chris Lattner
95b2c7da5e eliminate static ctors for Statistic objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32703 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-19 22:59:26 +00:00
Rafael Espindola
3ef39ca6a1 macros -> Inline functions 
Lauros's patch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32656 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-18 11:07:09 +00:00
Rafael Espindola
15404d060b move ExtWeakSymbols to AsmPrinter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32648 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-18 03:37:18 +00:00
Rafael Espindola
8897a7b02e avoid using a constant table when a constant can be used inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32580 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-14 18:58:37 +00:00
Rafael Espindola
15f17a7c47 Avoid creating invalid sub/add instructions on the prolog/epilog 
patch by Lauro


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32577 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-14 13:31:27 +00:00
Rafael Espindola
a898ce687a more general matching of the MVN instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 17:10:13 +00:00
Rafael Espindola
2426775c81 don't use "ordinary" addressing mode 1 when mvn is appropriate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32482 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 14:03:29 +00:00
Rafael Espindola
f64945d83c use MVN to handle small negative constants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32459 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 01:03:11 +00:00
Rafael Espindola
450856d01b add mvn 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32454 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-12 00:37:38 +00:00
Rafael Espindola
4dfab986ab add note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32452 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-11 23:56:10 +00:00
Rafael Espindola
796cbd87b4 .align is in bits 
.comm is in bytes
:-(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32408 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-10 02:53:14 +00:00
Rafael Espindola
0ec729ef2d %progbits not @progbits 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32376 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-08 22:06:02 +00:00
Rafael Espindola
1366626e08 add \"aw\",@progbits" to ctors and dtors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32373 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-08 21:24:58 +00:00
Rafael Espindola
a43f3d4c96 fix truncstorei1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32364 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-08 18:41:21 +00:00
Rafael Espindola
1c411dee4f fix alignment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32337 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-07 22:38:06 +00:00
Bill Wendling
f5da13367f What should be the last unnecessary <iostream>s in the library. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-07 22:21:48 +00:00
Rafael Espindola
7367d05cb7 make sure that we don't use a common symbol if a section was specified 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-07 18:33:58 +00:00
Chris Lattner
ac0b6ae358 Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-06 17:46:33 +00:00
Rafael Espindola
392b1b2ef3 print weak references 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32276 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-06 13:35:10 +00:00
Chris Lattner
d17aa4b1f1 These asm printers shouldn't use assembly/writer.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32262 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-06 06:13:25 +00:00
Rafael Espindola
97815c6b9c expand memmove and memcpy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32226 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-05 17:57:23 +00:00
Rafael Espindola
462af9a2e0 add support for the "r" asm constraint 
patch by Lauro Ramos Venancio


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32224 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-05 17:37:31 +00:00
Rafael Espindola
204b0c2ca0 add support for weak linkage 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32222 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-05 17:00:17 +00:00
Evan Cheng
c0f64ffab9 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-27 23:37:22 +00:00
Rafael Espindola
f819a4999a implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 13:58:55 +00:00
Evan Cheng
0d53826f36 Match tblegen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 20:34:28 +00:00
Rafael Espindola
6e8c6493f0 initial implementation of addressing mode 2 
TODO: fix lea_addri


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 17:07:32 +00:00
Chris Lattner
3751844b39 remove dead/redundant vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31435 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:48:56 +00:00
Rafael Espindola
f05696c1b5 revert previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31411 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:08:28 +00:00
Rafael Espindola
115bfcb574 add createCFGSimplificationPass to ARMTargetMachine::addInstSelector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31400 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:39:25 +00:00
Rafael Espindola
e931a37a4e move ARMCondCodeToString to ARMAsmPrinter.cpp 
remove unused variables from lowerCall


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31378 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 15:00:02 +00:00
Rafael Espindola
560a8d0512 print null values in bss 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31349 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 14:26:44 +00:00
Rafael Espindola
9dca7ad78f implement zextload bool and truncstore bool 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31348 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 14:13:27 +00:00
Rafael Espindola
b191e0ab51 add support for calling functions when the caller has variable sized objects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31312 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 13:03:26 +00:00
Evan Cheng
c35497fc2a All targets expand BR_JT for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 08:02:39 +00:00
Rafael Espindola
7ae68ab3bc initial support for frame pointers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 13:31:26 +00:00
Rafael Espindola
0e5e3aacbe expand ISD::VACOPY 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31170 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 20:15:21 +00:00
Rafael Espindola
3d7d39ab15 fix warning about missing newline at end of file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31162 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 17:07:11 +00:00
Chris Lattner
578e64a041 implement uncond branch insertion, mark branches with isBranch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31160 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 16:47:57 +00:00
Rafael Espindola
c391d16b49 implement STRB and STRH 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31138 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-23 20:34:27 +00:00
Rafael Espindola
d8ed7f8cde expand ISD::MEMSET 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31137 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-23 20:08:22 +00:00
Reid Spencer
b83eb6447b For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31063 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-20 07:07:24 +00:00
Rafael Espindola
2435786414 use Pat to implement extloadi8 and extloadi16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31052 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 17:05:03 +00:00
Rafael Espindola
20793115a8 implement undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31049 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 13:45:00 +00:00
Rafael Espindola
b97809c9a7 print common symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31048 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 13:30:40 +00:00
Rafael Espindola
3692c7ac17 implement extloadi8 and extloadi16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31047 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 12:45:04 +00:00
Rafael Espindola
6495bdd8d2 expand SIGN_EXTEND_INREG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31046 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 12:06:50 +00:00
Rafael Espindola
4749aa4ea3 expand brind so that we don't have to implement jump tables right now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31045 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 10:56:43 +00:00
Rafael Espindola
71d94d8817 add blx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31037 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 16:21:43 +00:00
Rafael Espindola
70673a1a90 add isTerminatortto b and bcond 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31036 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 16:20:57 +00:00
Rafael Espindola
5f1b698aeb implement CallingConv::Fast as CallingConv::C 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31034 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 12:03:07 +00:00
Rafael Espindola
226f8bc38c expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 21:05:33 +00:00
Rafael Espindola
04d88ffdb5 add the FPUnaryOp and DFPUnaryOp classes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31013 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 20:45:22 +00:00
Rafael Espindola
c01c87c8ba add FABSS and FABSD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31012 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 20:33:13 +00:00
Rafael Espindola
3f3a6f6c3b remove extra [] in stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31008 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 18:29:14 +00:00
Rafael Espindola
32bd5f4f6a initial implementation of addressing mode 5 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31002 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 18:04:53 +00:00
Rafael Espindola
0d479ecbb1 add the immediate to the Offset in eliminateFrameIndex 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30998 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 14:34:02 +00:00
Rafael Espindola
f621abca9e add FSTD and FSTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30996 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 13:36:07 +00:00
Rafael Espindola
199dd67c50 add FCPYS and FCPYD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30995 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 13:13:23 +00:00
Rafael Espindola
a605be69c3 add fdivs e fdivd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30988 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 21:50:04 +00:00
Rafael Espindola
0505be03ad expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30987 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 21:10:32 +00:00
Rafael Espindola
27e469ef13 define the DFPBinOp class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30981 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 18:39:22 +00:00
Rafael Espindola
a6f149d548 add the FPBinOp class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30980 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 18:32:36 +00:00
Rafael Espindola
90057aaeb7 define the Addr1BinOp class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30979 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 18:18:14 +00:00
Rafael Espindola
15a6c3e976 define the IntBinOp class and use it to implement the multiply instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30978 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 17:57:20 +00:00
Rafael Espindola
bb1e2fbc68 fix assembly syntax 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30977 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 17:38:12 +00:00
Rafael Espindola
82c678b83c implement LDRB, LDRSB, LDRH and LDRSH 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30976 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 17:17:22 +00:00
Rafael Espindola
bec2e38a91 implement smull and umull 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30975 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 16:33:29 +00:00
Rafael Espindola
d2b5668208 expand ISD::BRCOND 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30963 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-14 17:59:54 +00:00
Rafael Espindola
6c5ae3edd3 fix some fp condition codes 
use non trapping comparison instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30962 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-14 13:42:53 +00:00
Evan Cheng
8b2794aeff Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 21:14:26 +00:00
Rafael Espindola
33d06bcfd4 add FNEGS and FNEGD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30932 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 17:37:35 +00:00
Rafael Espindola
5395538307 add SBCS and SUBS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 17:19:20 +00:00
Rafael Espindola
26a76d1024 implement calls to functions that return long 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30929 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 16:47:22 +00:00
Rafael Espindola
42b62f3f81 implement unordered floating point compares 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30928 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 13:14:59 +00:00
Chris Lattner
65d8c1e8d4 mark call adjustments as modifying the SP 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30911 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-12 18:00:26 +00:00
Evan Cheng
af9db75943 Add properties to ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-11 21:03:53 +00:00
Rafael Espindola
493a7fc5c3 uint <-> double conversion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30862 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 20:38:57 +00:00
Rafael Espindola
667c349feb add fp sub 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30859 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 19:35:01 +00:00
Rafael Espindola
b47e1d033c add double <-> int conversion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30858 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 18:55:14 +00:00
Rafael Espindola
0d9fe764df compare doubles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 16:33:47 +00:00
Rafael Espindola
4b20fbc01d initial support for fp compares. Unordered compares not implemented yet 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-10 12:56:00 +00:00
Evan Cheng
466685d41a Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 20:57:25 +00:00
Rafael Espindola
2dc0f2b55c add float -> double and double -> float conversion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 17:50:29 +00:00
Rafael Espindola
ecdb9f93c4 add ADDS and ADCS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30830 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 17:18:28 +00:00
Rafael Espindola
48bc9fbf19 expand ISD::SELECT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30829 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 16:28:33 +00:00
Rafael Espindola
5af3a686a7 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30828 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 14:18:33 +00:00
Rafael Espindola
ad557f9d11 expand ISD::EXTLOAD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30827 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 14:13:40 +00:00
Rafael Espindola
896f10c309 most ARM targets are little endian 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30826 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 14:12:15 +00:00
Rafael Espindola
e5bbd6d753 implement FUITOS and FUITOD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30803 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-07 14:24:52 +00:00
Rafael Espindola
5aca927ae6 implement FLDD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-07 14:03:39 +00:00
Rafael Espindola
d9ae778125 implement fadds, faddd, fmuls and fmuld 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30801 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-07 13:46:42 +00:00
Rafael Espindola
935b1f8fce add optional input flag to FMRRD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30774 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 20:33:26 +00:00
Rafael Espindola
614057b843 add support for calling functions that return double 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30771 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 19:10:05 +00:00
Rafael Espindola
af1dabef35 fix some bugs affecting functions with no arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30767 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 17:26:30 +00:00
Rafael Espindola
1b5076887e fix the stack alignment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30766 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 14:29:47 +00:00
Rafael Espindola
4a408d46d4 add support for calling functions that have double arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30765 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 12:50:22 +00:00
Evan Cheng
786225adf0 Make use of getStore(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 23:01:46 +00:00
Rafael Espindola
39b5a21259 use a const ref for passing the vector to ArgumentLayout 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30756 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 17:46:48 +00:00
Rafael Espindola
a284584352 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30754 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 16:48:49 +00:00
Chris Lattner
1da31ee472 Pass the MachineFunction into EmitJumpTableInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30742 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 03:01:21 +00:00
Chris Lattner
6f6f69950f Use getSectionForFunction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30740 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 02:49:23 +00:00
Rafael Espindola
cd71da5cf0 Implement floating point constants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30704 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-03 17:27:58 +00:00
Rafael Espindola
9e071f0ae3 fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-02 19:30:56 +00:00
Rafael Espindola
27185190e6 add floating point registers 
implement SINT_TO_FP


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-29 21:20:16 +00:00
Rafael Espindola
75645496fa add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30581 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-22 11:36:17 +00:00
Rafael Espindola
ebdabda708 more condition codes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-21 13:06:26 +00:00
Rafael Espindola
7246d33e2a if a constant can't be an immediate, add it to the constant pool 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30566 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-21 11:29:52 +00:00
Rafael Espindola
4d4c021758 fix header 
add comments
untabify


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30486 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-19 16:41:40 +00:00
Rafael Espindola
71f3b94fa8 Implement a MachineFunctionPass to fix the mul instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30485 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-19 15:49:25 +00:00
Rafael Espindola
3ad5e5cf99 add shifts to addressing mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 12:09:43 +00:00
Evan Cheng
c356a572e3 Reflects MachineConstantPoolEntry changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-12 21:04:05 +00:00
Rafael Espindola
817e7fdb8b implement SRL and MUL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30262 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 19:24:19 +00:00
Rafael Espindola
1b3956b516 add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30261 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 19:23:32 +00:00
Rafael Espindola
7cca7c5317 partial implementation of the ARM Addressing Mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 17:25:40 +00:00
Rafael Espindola
ff59d22232 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 12:49:38 +00:00
Anton Korobeynikov
f369dd26fb Removed unnecessary Mangler creation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30239 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-10 21:17:03 +00:00
Rafael Espindola
0a200600e7 implement shl and sra 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 17:36:23 +00:00
Rafael Espindola
4e30764d55 add the eor (xor) instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30189 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 16:59:47 +00:00
Rafael Espindola
5c2aa0a4d8 implement unconditional branches 
fix select.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30186 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 12:47:03 +00:00
Jim Laskey
fde1b3bb2f 1. Remove condition on delete. 
2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30169 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 23:39:26 +00:00
Jim Laskey
a0f3d17daa Make target asm info a property of the target machine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30162 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 22:06:40 +00:00
Jim Laskey
8e8de8f776 Break out target asm info into separate files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30161 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 22:05:02 +00:00
Jim Laskey
563321a258 Separate target specific asm properties from the asm printers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30126 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-06 18:34:40 +00:00
Rafael Espindola
b52b54d4af add the orr instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30125 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-06 18:03:12 +00:00
Chris Lattner
09e460662a Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-05 02:31:13 +00:00
Rafael Espindola
3a02f020eb add support for returning 64bit values 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-04 19:05:01 +00:00
Chris Lattner
1911fd4f85 Completely rearchitect the interface between targets and the pass manager. 
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30081 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-04 04:14:57 +00:00
Chris Lattner
c4fa386471 Simplify target construction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30070 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-03 18:44:02 +00:00
Rafael Espindola
bc4cec9a62 add the SETULT condition code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30067 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-03 13:19:16 +00:00
Rafael Espindola
5f450d2948 add more condition codes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-02 20:24:25 +00:00
Evan Cheng
9ade218533 Select() no longer require Result operand by reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-26 05:34:46 +00:00
Rafael Espindola
755be9b3de use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29876 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-25 17:55:16 +00:00
Rafael Espindola
cdda88cd12 add the "eq" condition code 
implement a movcond instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 17:19:08 +00:00
Rafael Espindola
6f602de3b6 create a generic bcond instruction that has a conditional code argument 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 16:13:15 +00:00
Rafael Espindola
687bc49d1a initial support for branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 13:45:55 +00:00
Rafael Espindola
f4d40050f1 add a README.txt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-22 12:22:46 +00:00
Rafael Espindola
3c000bf817 initial support for select 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-21 22:00:32 +00:00
Rafael Espindola
a5dfc835d4 add the and instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29793 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-21 13:58:59 +00:00
Rafael Espindola
3717ca965b call computeRegisterProperties 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29780 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-20 01:49:49 +00:00
Chris Lattner
5ea64fd9eb Constify some methods. Patch provided by Anton Vayvod, thanks! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-17 22:00:08 +00:00
Rafael Espindola
f3a335cedf add a "load effective address" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-17 17:09:40 +00:00
Rafael Espindola
ec46ea34dc Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-16 14:43:33 +00:00
Rafael Espindola
61369da0e5 select code like 
ldr rx, [ry, #offset]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29664 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-14 19:01:24 +00:00
Chris Lattner
e219945348 Eliminate use of getNode that takes a vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 17:38:39 +00:00
Chris Lattner
8742867f95 elimiante use of getNode that takes vector of operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29612 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 17:22:35 +00:00
Evan Cheng
64a752f7c7 Match tablegen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:08:15 +00:00
Evan Cheng
bb7b844bec CALLSEQ_* produces chain even if that's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:03:33 +00:00
Rafael Espindola
a1ab92d8b7 correctly set LocalAreaOffset of TargetFrameInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29589 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-09 17:37:45 +00:00
Rafael Espindola
7a53bd0890 fix the spill code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29583 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-09 16:41:12 +00:00
Rafael Espindola
2c8cdc6c1a fix the loading of the link register in emitepilogue 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29580 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-09 13:15:47 +00:00
Rafael Espindola
46adf8119d change the addressing mode of the str instruction to reg+imm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-08 20:35:03 +00:00
Rafael Espindola
1a00946817 initial support for variable number of arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29567 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-08 13:02:29 +00:00
Evan Cheng
2ef88a09b7 Match tablegen isel changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-07 22:28:20 +00:00
Rafael Espindola
341b864c8d use a 'register pressure reducing' scheduler 
make sure only one move is used in a hello world


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29520 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-04 12:48:42 +00:00
Rafael Espindola
6312da0fc7 Bug fix: always generate a RET_FLAG in LowerRET 
fixes ret_null.ll and call.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29519 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-03 22:50:11 +00:00
Rafael Espindola
f4fda80403 add and use ARMISD::RET_FLAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29499 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-03 17:02:20 +00:00
Rafael Espindola
1ed3af11b5 start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29451 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-01 18:53:10 +00:00
Rafael Espindola
06c1e7eacb implement LowerConstantPool and LowerGlobalAddress 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29433 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-01 12:58:43 +00:00
Rafael Espindola
6d581e8d15 handle GlobalValue::InternalLinkage in doFinalization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29417 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-31 20:38:13 +00:00
Evan Cheng
2641cad180 Remove InFlightSet hack. No longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29373 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-28 00:47:19 +00:00
Rafael Espindola
b01c4bbb45 emit global constants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29344 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-27 11:38:51 +00:00
Rafael Espindola
fac00a93a9 implement function calling of functions with up to 4 arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29274 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-25 20:17:20 +00:00
Rafael Espindola
44819cb20a implemented sub 
correctly update the stack pointer in the prologue and epilogue


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-21 12:26:16 +00:00
Rafael Espindola
355746359e initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-18 17:00:30 +00:00
Rafael Espindola
84b19be6ab skeleton of a lowerCall implementation for ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-16 01:02:57 +00:00
Rafael Espindola
a4e64359aa add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 11:36:48 +00:00
Rafael Espindola
aefe14299a create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 01:41:35 +00:00
Rafael Espindola
49e4415587 handle the "mov reg1, reg2" case in isMoveInstr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28945 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-27 21:52:45 +00:00
Rafael Espindola
58421d7d08 initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-18 00:08:07 +00:00
Chris Lattner
1790d44d0d Don't pass target name into TargetData anymore, it is never used or needed. 
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28830 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-16 18:22:52 +00:00
Rafael Espindola
337c4ad6e7 lower more then 4 formal arguments. The offset is currently hard coded. 
implement SelectFrameIndex


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28751 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-12 12:28:08 +00:00
Rafael Espindola
4b02367d54 add R0 to liveout 
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28691 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-05 22:26:14 +00:00
Rafael Espindola
85ede37ca9 Expand ret into "CopyToReg;BRIND" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-30 17:33:19 +00:00
Chris Lattner
a5135ba0c9 Ignore generated files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28520 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-27 01:23:30 +00:00
Evan Cheng
6848be1a27 Change RET node to include signness information of the return values. i.e. 
RET chain, value1, sign1, value2, sign2, ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-26 23:10:12 +00:00
Rafael Espindola
a1334cdfb2 On ARM, alignment is in bits 
Add lr as a hard coded operand of bx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28494 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-26 10:56:17 +00:00
Rafael Espindola
2f99b6bd96 implement initial version of ARMAsmPrinter::printOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28470 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-25 12:57:06 +00:00
Rafael Espindola
c3c1a86aa0 port the ARM backend to use ISD::CALL instead of LowerCallTo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28469 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-25 11:00:18 +00:00
Evan Cheng
6a3d5a62f0 Assert if InflightSet is not cleared after instruction selecting a BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-25 00:24:28 +00:00
Evan Cheng
afe358e7d4 Clear HandleMap and ReplaceMap after instruction selection. Or it may cause 
non-deterministic behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-24 20:46:25 +00:00
Chris Lattner
d74ea2bbd8 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-24 17:04:05 +00:00
Rafael Espindola
4b442b528a implement minimal versions of 
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28431 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-23 02:48:20 +00:00
Owen Anderson
d988b32aba Make all of the TargetMachine subclasses use the new string TargetData methods. 
This is part of the on-going work on PR 761.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28414 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-20 00:24:56 +00:00
Rafael Espindola
dc124a234a implement movri 
add a stub LowerFORMAL_ARGUMENTS


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-18 21:45:49 +00:00
Evan Cheng
0f3ac8d8d4 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-18 00:12:58 +00:00
Evan Cheng
c01d497255 Remove PointerType from class Target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-17 21:20:27 +00:00
Rafael Espindola
1c8f0536b3 add an abort after every assert(0) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-15 22:34:39 +00:00
Rafael Espindola
7bc59bc395 added a skeleton of the ARM backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-14 22:18:28 +00:00