llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 05:32:25 +00:00

Author	SHA1	Message	Date
Anton Korobeynikov	875e1eb8ab	Two more hooks for RA and FP registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70738 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:10:40 +00:00
Anton Korobeynikov	40477317f3	Proper handle loading of effective address of stack slot stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70737 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:10:26 +00:00
Anton Korobeynikov	82e46c2595	Match frame indexes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70736 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:10:11 +00:00
Anton Korobeynikov	aa29915b58	First draft of stack slot loads / stores lowering git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70735 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:09:57 +00:00
Anton Korobeynikov	cf14ae5500	Reverse order of memory arguments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70734 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:09:40 +00:00
Anton Korobeynikov	aecfa7897f	Remove bogus pattern git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70733 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:09:24 +00:00
Anton Korobeynikov	1deea5f3a7	Correct asmprinting of memory operands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70732 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:09:10 +00:00
Anton Korobeynikov	0eb6af40e3	Match wrapper node for address git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70731 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:08:51 +00:00
Anton Korobeynikov	3513ca81c6	Add lowering for global address nodes. Not pretty efficient though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70730 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:08:33 +00:00
Anton Korobeynikov	3c2684d136	Some early full call lowering draft for direct calls git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70729 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:08:13 +00:00
Anton Korobeynikov	b561264d2b	Add call frame setup instruction elimination and lowerid for bunch of call-related stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70728 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:07:54 +00:00
Anton Korobeynikov	4428885c5a	Add CALL lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70727 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:07:31 +00:00
Anton Korobeynikov	01e0e8d119	Add bunch of mem-whatever patterns git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70726 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:07:10 +00:00
Anton Korobeynikov	2682bf5979	Add bunch of reg-mem inst patterns git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70725 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:06:46 +00:00
Anton Korobeynikov	54f30d3fc9	Add normal and trunc stores git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70724 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:06:26 +00:00
Anton Korobeynikov	36b6e533c1	Basic support for mem=>reg moves git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70723 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:06:03 +00:00
Anton Korobeynikov	51c31d6888	Add 8-bit insts. zext behaviour is not modelled yet git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70722 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:05:42 +00:00
Anton Korobeynikov	cf9adf2cbb	Add 8-bit regclass and pattern for sext_inreg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70721 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:05:22 +00:00
Anton Korobeynikov	0fc32dae8f	Add pattern for OR git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70720 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:05:00 +00:00
Anton Korobeynikov	6ee626a1c1	Add reg-imm variants git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70719 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:04:41 +00:00
Anton Korobeynikov	c8166ac760	Add hint to nop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70718 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:04:23 +00:00
Anton Korobeynikov	0ba0a89c6b	Add more instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70717 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:04:06 +00:00
Anton Korobeynikov	b8639f5214	Cleanup git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70716 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:03:50 +00:00
Anton Korobeynikov	d2c94ae49e	Add dummy lowering for shifts git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70715 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:03:33 +00:00
Anton Korobeynikov	1476d97037	We don't have any div at all - thus mark it as expensive git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70714 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:03:14 +00:00
Anton Korobeynikov	8d7bb3998b	We're not going to spend 100% of time in interrupts, do we? :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70713 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:02:57 +00:00
Anton Korobeynikov	431beb5fa7	Add simple reg-reg add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70712 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:02:39 +00:00
Anton Korobeynikov	fff5f76c46	gas uses lower letter for register names git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70711 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:02:22 +00:00
Anton Korobeynikov	1df221f2bb	Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70710 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:02:04 +00:00
Anton Korobeynikov	09c42f509a	Add function body printing routine git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70709 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:01:41 +00:00
Anton Korobeynikov	f3085ac973	Add 'msp430' target triple recognizer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70708 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:01:23 +00:00
Anton Korobeynikov	e37db97928	Make emit{Prologue,Epilogue}() noop for now git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70707 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:01:04 +00:00
Anton Korobeynikov	fbf165a74b	Add callee-saved regs & reg classes getter hooks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70706 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:00:46 +00:00
Anton Korobeynikov	3a4fbcfd33	Add simple FP indicator for given function hook git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70705 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:00:28 +00:00
Anton Korobeynikov	dcb802cf7b	Provide set of reserved registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70704 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 13:00:11 +00:00
Anton Korobeynikov	fd1b7c778c	Add proper ISD::RET lowering git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70703 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:59:50 +00:00
Anton Korobeynikov	c8fbb6ae20	Add first draft of MSP430 calling convention stuff and draft of ISD::FORMAL_ARGUMENTS node lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70702 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:59:33 +00:00
Anton Korobeynikov	2dd6cdc920	Fix register names, fix register allocation order, handle frame pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70701 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:59:16 +00:00
Anton Korobeynikov	43ed64a182	Clearify the usage and add some debug stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70700 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:58:58 +00:00
Anton Korobeynikov	9e12339cb2	Cleanup git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70699 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:58:40 +00:00
Anton Korobeynikov	b78e17b33a	Add cmake script. No idea whether it works or not :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70698 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:58:22 +00:00
Anton Korobeynikov	fe3fc5ace7	Add a note git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70697 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:58:05 +00:00
Anton Korobeynikov	f99601fab4	Typo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70695 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:57:47 +00:00
Anton Korobeynikov	f2c3e179ec	Dummy MSP430 backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70694 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-03 12:57:15 +00:00
Chris Lattner	c650f1f141	'The attached patch fixes an issue where llc -march=cpp fails with "Invalid primitive type" on input containing the x86_fp80 type.' Patch by Collin Winter! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70610 91177308-0d34-0410-b5e6-96231b3b80d8	2009-05-01 23:54:26 +00:00
Argyrios Kyrtzidis	9eddfd3687	Fix compilation for some targets other than x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70522 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-30 23:50:26 +00:00
Argyrios Kyrtzidis	a26eae64dd	Make DebugLoc independent of DwarfWriter. -Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable* -Remove DwarfWriter::getOrCreateSourceID -Make necessary changes for the above (fix callsites, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70520 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-30 23:22:31 +00:00
Jakob Stoklund Olesen	ba67d87fe4	getCommonSubClass() - Calculate the largest common sub-class of two register classes. This is implemented as a function rather than a method on TargetRegisterClass because it is symmetric in its arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70512 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-30 21:23:32 +00:00
Dan Gohman	78e04d4aa0	Set mayLoad on MOVZX32_NOREXrm8 too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70466 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-30 03:11:48 +00:00
Evan Cheng	8c1474050d	Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70461 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-30 00:58:57 +00:00
Chris Lattner	cf189964d7	remove progname which is never set. PR4085 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70453 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-30 00:24:33 +00:00
Bill Wendling	98a366d547	Instead of passing in an unsigned value for the optimization level, use an enum, which better identifies what the optimization is doing. And is more flexible for future uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-29 23:29:43 +00:00
Nate Begeman	ec8eee2d3a	Fix infinite recursion in the C++ code which handles movddup by making it unnecessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70425 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-29 22:47:44 +00:00
Nate Begeman	5a5ca1519e	Implement review feedback for vector shuffle work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-29 05:20:52 +00:00
Sanjiv Gupta	a3518a1d6a	Add a public method called getAddressSpace() to the GlobalAddressSDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70366 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-29 04:43:24 +00:00
Bill Wendling	be8cc2a3de	Second attempt: Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-29 00:15:41 +00:00
Anton Korobeynikov	573c92d8ba	Properly print 'P' modifier on inline asm memory operands. This should fix PR3379 and PR4064. Patch inspired by Edwin Török! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70328 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-28 21:49:33 +00:00
Sanjiv Gupta	23b0543e3f	GlobalValue is always pointer type, so an assert isn't required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70300 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-28 16:39:45 +00:00
Bill Wendling	c69d56f115	r70270 isn't ready yet. Back this out. Sorry for the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-28 01:04:53 +00:00
Bill Wendling	2e9d5f912a	Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-28 00:21:31 +00:00
Nate Begeman	9008ca6b6b	2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-27 18:41:29 +00:00
Dan Gohman	4af325d1b4	Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-27 16:41:36 +00:00
Dan Gohman	6241762c5a	Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD, GR32_ABCD, and GR64_ABCD, respectively, to help describe them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-27 16:33:14 +00:00
Dan Gohman	4d47b9bcb9	Break up long multi-mnemonic strings into separate lines for readability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70209 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-27 15:13:28 +00:00
Mon P Wang	a7e01d7efd	Revised 68749 to allow matching of load/stores for address spaces < 256. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70197 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-27 07:22:10 +00:00
Chris Lattner	bc58322d6a	add support for detecting process features on win64, patch by Nicolas Capens! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70057 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-25 18:27:23 +00:00
Bob Wilson	8091524d98	Change LowerCallResult method so that CCValAssign::BCvt can be used with f64 types. This is not used for anything yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70006 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-25 00:33:20 +00:00
Bob Wilson	d55bd51f31	Adjust a comment to reflect what the code does. Splitting a 64-bit argument between registers and the stack may be required with the APCS ABI, but it isn't tied to using a particular version of the ARM architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69978 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-24 17:05:01 +00:00
Bob Wilson	4d59e1d666	Fix up some problems with getCopyToReg and getCopyFromReg nodes being chained and "flagged" together. I also made a few changes to handle the chain and flag values more consistently. I found these problems by inspection so I'm not aware of anything that breaks because of them (thus no testcase). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69977 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-24 17:00:36 +00:00
Bob Wilson	1c2c462d0f	Remove unnecessary references to f32 types. After specifying that f32 should be bit-converted to i32, it is sufficient to list only i32 in subsequent definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69973 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-24 16:55:25 +00:00
Rafael Espindola	15f1b66d64	Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not very elegant, but neither is the tls specification :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69968 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-24 12:59:40 +00:00
Rafael Espindola	15684b2955	Revert 69952. Causes testsuite failures on linux x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-24 12:40:33 +00:00
Nate Begeman	b706d29f9c	PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-24 03:42:54 +00:00
Dan Gohman	f1d012c595	Fix spurious indentation in a comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69934 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-23 22:41:05 +00:00
Sanjiv Gupta	b1f321b553	Banksel immediate constant will always immediately follow the GA/ES, so scan an insn from beginnin to find out the banksel operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69883 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-23 10:34:58 +00:00
Dan Gohman	146a310e66	Add support for printing MO_ExternalSymbol operands in memory operand tuples. This doesn't ever come up in normal code however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69848 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-23 00:57:37 +00:00
Sanjiv Gupta	dd92dba644	Make the function begin label start after ther data pointer. The address of data frame for function can be obtained by subtracting 2 from the function begin label. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69801 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-22 12:02:36 +00:00
Duncan Sands	005e7984cc	Get rid of what looks like a copy-and-pasted typo. Spotted by gcc-4.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69673 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-21 09:44:39 +00:00
Rafael Espindola	7daa13c2a4	TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them. This fixes PR4002. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69672 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-21 08:22:09 +00:00
Sanjiv Gupta	e16178b75f	Handle direct aggregate type arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69665 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-21 05:54:51 +00:00
Dan Gohman	70bc17dbf5	Make X86's copyRegToReg able to handle copies to and from subclasses. This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69635 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-20 22:54:34 +00:00
Daniel Dunbar	75397f4092	Remove unused variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69624 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-20 20:34:38 +00:00
Bob Wilson	998e125a87	Move duplicated AddLiveIn function from X86 and ARM backends to be a method in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-20 18:36:57 +00:00
Devang Patel	91b477d2fa	Match C backend only if it explicitly requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69613 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-20 18:07:22 +00:00
Sanjiv Gupta	2bdf490d71	Emit the auto variables of a function into a different section than parameters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69605 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-20 16:59:35 +00:00
Mon P Wang	0bd07fc5dd	Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69417 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-18 05:16:01 +00:00
Bill Wendling	1824773689	Recommit r69335 and r69336. These were not causing problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69394 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 22:40:38 +00:00
Bob Wilson	e3fa9ef936	Move the AddLiveIn function definition closer to its uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69382 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 20:42:34 +00:00
Bob Wilson	e65586b37b	Rearrange code to reduce indentation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69381 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 20:40:45 +00:00
Bob Wilson	dee46d7f6d	Clean up formatting, remove trailing whitespace, fix comment typos and punctuation. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69378 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 20:35:10 +00:00
Bob Wilson	1f595bb429	Use CallConvLower.h and TableGen descriptions of the calling conventions for ARM. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 19:07:39 +00:00
Rafael Espindola	2ee3db3003	For general dynamic TLS access we must use leaq foo@TLSGD(%rip), %rdi as part of the instruction sequence. Using a register other than %rdi and then copying it to %rdi is not valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69350 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 14:35:58 +00:00
Bill Wendling	c3a76ef955	Revert r69335 and r69336. They were causing build failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69347 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 04:19:22 +00:00
Dan Gohman	d10a4ce582	MOV8rr_NOREX is a "Move" instruction. This doesn't currently matter, because this instruction isn't generated until after things that care. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69336 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 00:45:17 +00:00
Dan Gohman	d51def353c	Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at present, but it's inconsistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69335 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 00:43:09 +00:00
Chris Lattner	9062d9a55b	Fix some failures in targets on available_externally functions, this fixes a crash on CodeGen/Generic/externally_available.ll on ppc hosts. Thanks to Nicholas L for pointing this out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69333 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-17 00:26:12 +00:00
Rafael Espindola	7c36683fa3	fix PR3995. A scale must be 1, 2, 4 or 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69284 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-16 12:34:53 +00:00
Dan Gohman	df7dfc7715	Fix 80-column violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69204 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-15 19:48:57 +00:00
Dan Gohman	25174963f6	Add a folding table entry for MOV8rr_NOREX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69203 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-15 19:48:28 +00:00
Dan Gohman	6288b93f00	Fix X86MachineFunctionInfo's doxygen comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69127 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-15 01:20:18 +00:00
Dan Gohman	aaa1fdb271	Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with the local register allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69115 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-15 00:10:16 +00:00
Dan Gohman	6d9305c7fd	Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69111 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-15 00:04:23 +00:00
Dan Gohman	a2f3703efd	GR8_NOREX can contain the H registers, since they don't require REX prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69108 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-15 00:00:48 +00:00
Dan Gohman	62ad138d70	For the h-register addressing-mode trick, use the correct value for any non-address uses of the address value. This fixes 186.crafty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69094 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-14 22:45:05 +00:00
Evan Cheng	b3f5bfe37f	Some of GR8_NOREX registers are only available in 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-14 16:57:43 +00:00
Sanjiv Gupta	85be408a32	Handle aggregate type arguments to direct and indirect calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69022 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-14 02:49:52 +00:00
Dan Gohman	88c7af096b	Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 21:06:25 +00:00
Devang Patel	0f7fef3872	Reapply 68847. Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68964 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 17:02:03 +00:00
Dan Gohman	21e3dfbc86	Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 16:09:41 +00:00
Dan Gohman	8433df36fb	Remove x86's special-case handling for ISD::TRUNCATE and ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle these cases, and the scheduling issues observed earlier appear to be resolved now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68959 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 15:29:31 +00:00
Dan Gohman	3cf9b3e455	Fix copy+pastos in comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68958 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 15:28:29 +00:00
Dan Gohman	ee30047386	List the l registers before h registers, for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68954 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 15:18:42 +00:00
Dan Gohman	3cd0aa3260	Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68951 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 15:14:03 +00:00
Dan Gohman	04d19f0241	Add a comment about MOVSX64rr8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68950 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 15:13:28 +00:00
Dan Gohman	8cc632f705	Fix another hard-coded constant to use X86AddrNumOperands. This unbreaks the JIT on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68948 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 15:04:25 +00:00
Rafael Espindola	7ff5bff45e	X86-64 TLS support for local exec and initial exec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68947 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 13:02:49 +00:00
Sanjiv Gupta	12f23a86e2	While passing arg of types larger than char only one byte at lower end was getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68946 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 09:38:38 +00:00
Chris Lattner	266c7bbbbc	Add a new "available_externally" linkage type. This is intended to support C99 inline, GNU extern inline, etc. Related bugzilla's include PR3517, PR3100, & PR2933. Nothing uses this yet, but it appears to work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68940 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-13 05:44:34 +00:00
Rafael Espindola	b215776fa1	In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching only if symbolic addresses are RIP relatives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-12 23:00:38 +00:00
Rafael Espindola	49a168daae	refactor some code into X86DAGToDAGISel::MatchWrapper git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68915 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-12 21:55:03 +00:00
Chris Lattner	8d57b778b5	fix a cross-block fastisel crash handling overflow intrinsics. See comment for details. This fixes rdar://6772169 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68890 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-12 07:51:14 +00:00
Chris Lattner	a9a42259ed	simplify code by using IntrinsicInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68887 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-12 07:36:01 +00:00
Chris Lattner	0461c0a8f5	Add new TargetInstrDesc::hasImplicitUseOfPhysReg and hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-12 07:26:51 +00:00
Dan Gohman	c6fa3ff0bd	Revert r68847. It breaks the build on non-Darwin targets, with this message from the assembler: Error: unknown pseudo-op: `.debug_inlined' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68863 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-11 15:57:04 +00:00
Devang Patel	2057532679	Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.) Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68847 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-11 00:16:47 +00:00
Sanjiv Gupta	a3613be963	Added code to handle spilling and reloading of FSRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68783 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-10 15:10:14 +00:00
Rafael Espindola	dbcfb3080a	Don't fold a load if the other operand is a TLS address. With this we generate movl %gs:0, %eax leal i@NTPOFF(%eax), %eax instead of movl $i@NTPOFF, %eax addl %gs:0, %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68778 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-10 10:09:34 +00:00
Chris Lattner	c2406f2341	a few fixes to "addrspace(256) is reference offset of GS segment register". It turns out that there are still several problems with this, will file a bugzilla. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68749 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-10 00:16:23 +00:00
Bill Wendling	7d16e85bfc	Pass in the std::string parameter instead of returning it by value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68747 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-10 00:12:49 +00:00
Dan Gohman	fc1665793e	Remove the obsolete SelectionDAG::getNodeValueTypes and simplify code that uses it by using SelectionDAG::getVTList instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68744 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 23:54:40 +00:00
Owen Anderson	3ca15c989c	Give register alias checking the hash table treatment too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 22:19:30 +00:00
Bob Wilson	d9df501704	Fix pr3954. The register scavenger asserts for inline assembly with register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 17:16:43 +00:00
Sanjiv Gupta	37831d0a12	The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68713 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 17:06:24 +00:00
Sanjiv Gupta	e206b1d142	Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68705 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 10:29:32 +00:00
Chris Lattner	a1cd83a258	Fix code size computation on x86-64, patch by Zoltan Varga! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68690 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 06:10:51 +00:00
Sanjiv Gupta	6e2a46a0b4	r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68671 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 04:03:43 +00:00
Owen Anderson	7d770be047	Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 03:50:16 +00:00
Dan Gohman	349ba4951f	Fix grammaros in comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68666 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-09 02:06:09 +00:00
Rafael Espindola	094fad37b9	Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-08 21:14:34 +00:00
Bob Wilson	2c7dab1864	Fix PR3795: Apply Dan's suggested fix for ARMTargetLowering::isLegalAddressingMode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68619 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-08 17:55:28 +00:00
Rafael Espindola	8ef2b89131	Avoid a hard coded constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68603 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-08 08:09:33 +00:00
Sanjiv Gupta	c1fa70c35a	Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68602 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-08 06:24:04 +00:00
Sanjiv Gupta	7836fc129a	Handle indirect function calls. Every function has the address of its frame in the beginning of code section. The frame address is retrieved and used to pass arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68597 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-08 05:38:48 +00:00
Dan Gohman	97121ba2af	Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-08 00:15:30 +00:00
Bill Wendling	044b5344c4	Temporarily revert r68552. This was causing a failure in the self-hosting LLVM builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-07 22:35:25 +00:00
Rafael Espindola	2a6411bbbd	Reduce code duplication on the TLS implementation. This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-07 21:37:46 +00:00
Jim Grosbach	30eae3c022	PR2985 / <rdar://problem/6584986> When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-07 20:34:09 +00:00
Bob Wilson	8f3434647d	Handle 'a' modifier in ARM inline assembly. Patch by Richard Pennington. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-06 21:46:51 +00:00
Sanjiv Gupta	cae1b628a7	Map stack based frameindices for spills to zero based indices that can be accessed based on an external symbol defining the location of temporary data for a function. For example: we have spill slots addressed as foo.tmp + 0, foo.tmp + 1 etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68442 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-06 10:54:50 +00:00
Bob Wilson	eec4b2d730	Wrap some lines to fix indentation problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68405 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 21:08:42 +00:00
Bob Wilson	1b46a68015	Fix some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68404 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 20:53:25 +00:00
Oscar Fuentes	fcf054bbd4	CMake: removed IA64AsmPrinter.cpp from lib/Target/IA64/CMakeLists.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68384 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 12:11:43 +00:00
Anton Korobeynikov	6c5cfec73e	Separate MIPS asmprinter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68383 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 10:41:41 +00:00
Anton Korobeynikov	60a19a4edd	Fix target library name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68382 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 10:41:17 +00:00
Anton Korobeynikov	c67d1127d0	Fix comment git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68381 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 10:41:00 +00:00
Anton Korobeynikov	ea38970596	Move IA64 asmprinter to separate library git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68380 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 10:38:51 +00:00
Mon P Wang	1e95580925	Added a x86 dag combine to increase the chances to use a movq for v2i64 on x86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68368 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-03 02:43:30 +00:00
Sanjiv Gupta	c2eb87afc1	Fixed build warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68333 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-02 18:33:12 +00:00
Sanjiv Gupta	5274a4afb7	To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68329 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-02 18:03:10 +00:00
Sanjiv Gupta	b84d5a476a	Params are not being generated as static globals now. The caller passes them onto the callee's stack directly and the callee loads the argvals from its own stack. Clang generated frameindexes validatd by recalculating the stack as if all frameindexes represent 1-byte slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68327 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-02 17:42:00 +00:00
Chris Lattner	5867de1243	silence warning in release-asserts build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68253 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-01 22:14:45 +00:00
Dan Gohman	de551f91d8	Use CHAR_BIT instead of hard-coding 8 in several places where it is appropriate. This helps visually differentiate host-oriented calculations from target-oriented calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68227 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-01 18:45:54 +00:00
Dan Gohman	77c5b0d7dc	Use LLVM type names instead of C type names in comments, to be less ambiguous and less C-specific. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68219 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-01 18:10:16 +00:00
Bob Wilson	bf6396bed0	Fix PR3862: Recognize some ARM-specific constraints for immediates in inline assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8	2009-04-01 17:58:54 +00:00
Evan Cheng	d54f2d571d	i128 shift libcalls are not available on x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68133 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 19:38:51 +00:00
Dan Gohman	968dc7a207	Reapply 68073, with fixes. EH Landing-pad basic blocks are not entered via fall-through. Don't miss fallthroughs from blocks terminated by conditional branches. Also, move isOnlyReachableByFallthrough out of line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68129 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 18:39:13 +00:00
Rafael Espindola	523249f856	remove unused arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68109 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 16:16:57 +00:00
Bill Wendling	df4881c68a	Really temporarily revert r68073. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68100 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 08:42:40 +00:00
Bill Wendling	e67f5e4273	Oy! When reverting r68073, I added in experimental code. Sorry... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68099 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 08:41:31 +00:00
Bill Wendling	8fe00540fc	Revert r68073. It's causing a failure in the Apple-style builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68092 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 08:26:26 +00:00
Evan Cheng	4d95232469	X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68082 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-31 01:13:53 +00:00
Dan Gohman	80c93e7442	Except in asm-verbose mode, avoid printing labels for blocks that are only reachable via fall-through edges. This dramatically reduces the number of labels printed, and thus also the number of labels the assembler must parse and remember. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68073 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-30 22:55:17 +00:00
Evan Cheng	73f24c9f0d	When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-30 21:36:47 +00:00
Bob Wilson	d83712ad67	Fix comment to match function name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68050 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-30 18:49:37 +00:00
Anton Korobeynikov	29519b1de0	Fix thinko: put stuff with both global and local relocations into data.rel{.ro}, not .local git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68036 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-30 17:37:43 +00:00
Anton Korobeynikov	fca82deecb	Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68032 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-30 15:27:43 +00:00
Anton Korobeynikov	71a7c6cde0	Add data.rel stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68031 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-30 15:27:03 +00:00
Anton Korobeynikov	721c2c647e	IA64 is as weird as Alpha wrt r/o relocs :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68007 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-29 17:14:35 +00:00
Anton Korobeynikov	01209bc12a	Alpha always requires global relocations to be r/w regardless of PIC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68006 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-29 17:14:14 +00:00
Anton Korobeynikov	db2323148b	Honour relocation behaviour stuff for ro objects git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68005 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-29 17:13:49 +00:00
Chris Lattner	352f3e5d37	add a note git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67953 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-28 19:26:55 +00:00
Rafael Espindola	a0a4f07fb6	Use array_lengthof git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67950 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-28 19:02:18 +00:00
Rafael Espindola	da945e3bb2	Have only one definition of X86AddrNumOperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-28 18:55:31 +00:00
Rafael Espindola	b449a68146	Make code a bit less brittle by no hardcoding the number of operands in an address in so many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67945 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-28 17:03:24 +00:00
Evan Cheng	0b0cd9113a	Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g. x * 40 => shlq $3, %rdi leaq (%rdi,%rdi,4), %rax This has the added benefit of allowing more multiply to be folded into addressing mode. e.g. a * 24 + b => leaq (%rdi,%rdi,2), %rax leaq (%rsi,%rax,8), %rax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-28 05:57:29 +00:00
Jim Grosbach	0ede14f5c0	remove trailing whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-27 23:06:27 +00:00
Rafael Espindola	705d800879	Avoid hardcoding that X86 addresses have 4 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67848 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-27 15:57:50 +00:00
Rafael Espindola	e4d5d34cfc	Use less hard coded constants to make the code less brittle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67846 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-27 15:45:05 +00:00
Rafael Espindola	a82dfca8c6	I am trying to add a segment to the X86 addresses matching to improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html), but that code is VERY brittle. This patch just makes it a bit more resistant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67843 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-27 15:26:30 +00:00
Evan Cheng	9272253381	-no-implicit-float means explicit fp operations are legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67784 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 23:06:32 +00:00
Evan Cheng	9d7b5309c2	tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67765 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 19:09:01 +00:00
Bill Wendling	a02a3dda56	Pull transform from target-dependent code into target-independent code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67742 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 06:14:09 +00:00
Chris Lattner	e7fa1f2a49	fix warning in -asserts mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67739 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 05:29:34 +00:00
Chris Lattner	e3a85838da	fix some warnings in release-asserts mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67738 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 05:28:26 +00:00
Chris Lattner	d4015074e4	fix an apparently real bug exposed by a warning in -asserts mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67737 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 05:28:14 +00:00
Chris Lattner	022a27e363	fix warning in -asserts build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67736 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 05:25:59 +00:00
Bill Wendling	8b4b874cc6	Match this pattern so that we can generate simpler code: %a = ... %b = and i32 %a, 2 %c = srl i32 %b, 1 %d = br i32 %c, into %a = ... %b = and %a, 2 %c = X86ISD::CMP %b, 0 %d = X86ISD::BRCOND %c ... This applies only when the AND constant value has one bit set and the SRL constant is equal to the log2 of the AND constant. The back-end is smart enough to convert the result into a TEST/JMP sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67728 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 01:47:50 +00:00
Bill Wendling	bddc442a00	Doxygen-ify comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67727 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-26 01:46:56 +00:00
Gabor Greif	0c8f7dc67c	do not rely on callee being operand 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67681 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-25 06:32:59 +00:00
Evan Cheng	42bf74be14	CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-25 01:47:28 +00:00
Evan Cheng	7db860d4de	Don't print global names twice with -asm-verbose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67667 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-25 01:08:42 +00:00
Dan Gohman	a96dc14968	I was convinced that it's ok to allow a second i8 return value to be returned in DL. LLVM's multiple-return-value support is not ABI-conforming; front-ends that wish to have code emitted that conforms to an ABI are currently expected to make arrangements for this on their own rather than assuming that multiple-return-values will automatically do the right thing. This commit doesn't fundamentally change this situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67588 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-24 01:04:34 +00:00
Evan Cheng	f1c0ae9de5	Do not emit comments unless -asm-verbose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-24 00:17:40 +00:00
Dale Johannesen	1b25cb2416	Fix internal representation of fp80 to be the same as a normal i80 {low64, high16} rather than its own {high64, low16}. A depressing number of places know about this; I think I got them all. Bitcode readers and writers convert back to the old form to avoid breaking compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67562 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-23 21:16:53 +00:00
Dan Gohman	f871ccb853	Now that errs() is properly non-buffered, there's no need to explicitly flush it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67526 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-23 15:57:19 +00:00
Dan Gohman	2004eb6272	Correct some comments. Operand numbers start at 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-23 15:40:10 +00:00
Evan Cheng	fb11288109	Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-23 08:01:15 +00:00
Dan Gohman	3aff0a63f9	Fix a grammaro in a comment that Bill noticed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67507 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-23 05:02:44 +00:00
Dan Gohman	82f84159e0	Add comments explaining why there's only one register for i8 return values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67502 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-23 04:28:24 +00:00
Bruno Cardoso Lopes	bdfbb74d34	Removed AFGR32 register class Handle odd registers allocation in FGR32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-21 00:05:07 +00:00
Bob Wilson	2a14c521ca	Fix a few more indentation problems and an 80-column violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-20 23:16:43 +00:00
Bob Wilson	2dc4f54324	No functional changes. Fix indentation and whitespace only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-20 22:42:55 +00:00
Sanjiv Gupta	e9d81f0ad8	Fixed comment for libcalls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67373 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-20 14:10:20 +00:00
Sanjiv Gupta	6b830e6d0d	Reformatting. Inserted code comments. Cleaned interfaces. Removed unncessary code. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67371 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-20 13:42:20 +00:00
Mon P Wang	bc65ca8de5	Added option to enable generating less precise mad (multiply addition) for those architectures that support the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67363 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-20 05:06:58 +00:00
Nick Lewycky	9c0f146d50	Remove strange extra semicolons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67287 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-19 05:51:39 +00:00
Nate Begeman	7cee81703d	Add support to tablegen for naming the nodes themselves, not just the operands, in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite, and as it turns out, cleans up a hack in the Alpha instruction info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-19 05:21:56 +00:00
Bruno Cardoso Lopes	b53db4fb32	Added support for Mips O32 Calling Convention git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67280 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-19 02:12:28 +00:00
Chris Lattner	ff81ebf758	Disable the "call to immediate" optimization on x86-64. It is not safe in general because the immediate could be an arbitrary value that does not fit in a 32-bit pcrel displacement. Conservatively fall back to loading the value into a register and calling through it. We still do the optzn on X86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67142 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-18 00:43:52 +00:00
Scott Michel	a82d3f7c57	CellSPU: Revert inadvertent mis-fix of fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67084 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-17 16:45:16 +00:00
Dan Gohman	9626447e70	Recognize bswapl as bswap too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67072 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-17 02:45:40 +00:00
Dan Gohman	d73566609e	Recognize "bswapq" as an alternate spelling for the bswap instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67071 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-17 02:17:27 +00:00
Scott Michel	7ea02ffe91	CellSPU: - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-17 01:15:45 +00:00
Scott Michel	6e1d1470c2	CellSPU: Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-16 18:47:25 +00:00
Bruno Cardoso Lopes	98ea4635ae	This causes incorrect stack frame allocation when the last object is an array allocated on the stack which would lead the compiled program to run over its stack. Thanks to Gil Dogon git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67034 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-15 23:28:07 +00:00
Dan Gohman	72bb0a64af	Use %rip-relative addressing on x86-64 whenever practical, as it has a smaller encoding than absolute addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67002 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-14 02:33:41 +00:00
Dan Gohman	9a49d31b6f	Don't forego folding of loads into 64-bit adds when the other operand is a signed 32-bit immediate. Unlike with the 8-bit signed immediate case, it isn't actually smaller to fold a 32-bit signed immediate instead of a load. In fact, it's larger in the case of 32-bit unsigned immediates, because they can be materialized with movl instead of movq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67001 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-14 02:07:16 +00:00
Dan Gohman	474d3b3f40	Improve FastISel's handling of truncates to i1, and implement ptrtoint and inttoptr in X86FastISel. These casts aren't always handled in the generic FastISel code because X86 sometimes needs custom code to do truncation and zero-extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66988 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 23:53:06 +00:00
Dan Gohman	14ea1ec232	Fix FastISel's assumption that i1 values are always zero-extended by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 20:42:20 +00:00
Rafael Espindola	520ebe6c2f	add 8 and 16 bit TLS moves. add a fixme note on how to remove code duplication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66932 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 19:39:55 +00:00
Rafael Espindola	9b922aa3b8	Improve sext and zext of TLS variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66922 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 18:37:06 +00:00
Chris Lattner	44ceb8a341	generalize this code so that fast isel handles integer truncates to i1, which codegen to the same thing as integer truncates to i8 (the top bits are just undefined). This implements rdar://6667338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66902 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 16:36:42 +00:00
Bill Wendling	105be5ac99	These instructions have special lowering that may lower them to SSE instructions. Prevent that if we don't want implicit uses of SSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66877 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 08:41:47 +00:00
Evan Cheng	1606e8e4cd	Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 07:51:59 +00:00
Chris Lattner	cee56e7d33	generalize the previous code to use the full generality of LEA for i32/i64 expressions (we could also do i16 on cpus where i16 lea is fast, but I didn't add this). On the example, we now generate: _test: movl 4(%esp), %eax cmpl $42, (%eax) setl %al movzbl %al, %eax leal 4(%eax,%eax,8), %eax ret instead of: _test: movl 4(%esp), %eax cmpl $41, (%eax) movl $4, %ecx movl $13, %eax cmovg %ecx, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66869 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 05:53:31 +00:00
Chris Lattner	97a29a5fee	optimize the case of cond ? 42 : 41 and friends. This compiles the example to: _test: movl 4(%esp), %eax cmpl $41, (%eax) setg %al movzbl %al, %eax orl $4294967294, %eax ret instead of: movl 4(%esp), %eax cmpl $41, (%eax) movl $4294967294, %ecx movl $4294967295, %eax cmova %ecx, %eax ret which is smaller in code size and faster. rdar://6668608 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66868 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 05:22:11 +00:00
Dan Gohman	77502c9344	Enhance address-mode folding of ISD::ADD to handle cases where the operands can't both be fully folded at the same time. For example, in the included testcase, a global variable is being added with an add of two values. The global variable wants RIP-relative addressing, so it can't share the address with another base register, but it's still possible to fold the initial add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66865 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-13 02:25:09 +00:00
Evan Cheng	a065200eaf	Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66803 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 18:15:39 +00:00
Chris Lattner	d1980a5acd	Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))" related transformations out of target-specific dag combine into the ARM backend. These were added by Evan in r37685 with no testcases and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll). Add some simple X86-specific (for now) DAG combines that turn things like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently with the recently added cp constant select optimization, but is a very general xform. For example, we now compile the second example in const-select.ll to: _test: movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 seta %al movzbl %al, %eax movl 4(%esp), %ecx movsbl (%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal 4(%eax), %ecx movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 cmovbe %eax, %ecx movsbl (%ecx), %eax ret This passes multisource and dejagnu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 06:52:53 +00:00
Chris Lattner	2b9f434908	improve comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66778 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 06:46:02 +00:00
Evan Cheng	536e66764b	On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66776 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 05:59:15 +00:00
Sanjiv Gupta	054401b9f2	Forgot to check-in this as part of 7761. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66763 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 03:20:07 +00:00
Sanjiv Gupta	d076570a66	Banksel optimization is now based on the section names of symbols, since the symbols in one section will always be put into one bank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66761 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-12 02:10:45 +00:00
Dan Gohman	30143763b9	Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the assembly text output uses an indirect call ("call *") instead of a direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66735 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 23:01:47 +00:00
Rafael Espindola	b316f90e57	optimize i8 and i16 tls values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66725 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 22:40:04 +00:00
Bill Wendling	f9abd7e33e	Add a -no-implicit-float flag. This acts like -soft-float, but may generate floating point instructions that are explicitly specified by the user. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 22:30:01 +00:00
Duncan Sands	4dc2b39bf8	It makes no sense to have a ODR version of common linkage, so remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 20:14:15 +00:00
Mon P Wang	6b3ef693d7	For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66684 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 18:47:57 +00:00
Chris Lattner	eda2ec35a1	fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66660 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 16:14:25 +00:00
Duncan Sands	5f4ee1fc5d	Remove the one-definition-rule version of extern_weak linkage: this linkage type only applies to declarations, but ODR is only relevant to globals with definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66650 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 08:08:06 +00:00
Mon P Wang	37b9a19653	Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66645 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 06:35:11 +00:00
Chris Lattner	47b4ce8529	formatting change, reduce indentation. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66642 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-11 05:48:52 +00:00
Sanjiv Gupta	c29f0c7dde	Mark the Defs and Uses of STATUS register correctly, plus some reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66540 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-10 10:35:34 +00:00
Dan Gohman	3328adda6b	Add more information to the EFLAGS note. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66515 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-10 00:26:23 +00:00
Dan Gohman	ad93e1e5fc	Add a note about EFLAGS optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66508 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-09 23:47:02 +00:00
Evan Cheng	8c6b991635	ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66435 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-09 20:25:39 +00:00
Evan Cheng	6501153fc0	ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-09 19:15:00 +00:00
Chris Lattner	087fcf3e89	do not export all the X86FastISel symbols, ever. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66382 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-08 18:44:31 +00:00
Evan Cheng	4b1747430a	Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-08 04:02:49 +00:00
Chris Lattner	ff9dcee534	add a note. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66360 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-08 03:04:26 +00:00
Chris Lattner	b34487dcba	add a note. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66359 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-08 01:54:43 +00:00
Duncan Sands	667d4b8de6	Introduce new linkage types linkonce_odr, weak_odr, common_odr and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an equivalent global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-07 15:45:40 +00:00
Dan Gohman	3112581441	Arithmetic instructions don't set EFLAGS bits OF and CF bits the same say the "test" instruction does in overflow cases, so eliminating the test is only safe when those bits aren't needed, as is the case for COND_E and COND_NE, or if it can be proven that no overflow will occur. For now, just restrict the optimization to COND_E and COND_NE and don't do any overflow analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66318 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-07 01:58:32 +00:00
Dan Gohman	1f4af262d5	Don't use plain INC32 and DEC32 on x86-64; it needs INC64_32r and INC64_16r, because these instructions are encoded differently on x86-64. This fixes JIT regressions on x86-64 in kimwitu++ and others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66207 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-05 21:32:23 +00:00
Dan Gohman	51bb47480e	When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand. The extra operand didn't appear to cause any trouble, but it was erroneous regardless. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66206 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-05 21:29:28 +00:00
Dan Gohman	4bfcf2a2a6	Fix the "test" optimization to recognize "dec" as an add of negative one, as subtracts of immediates are canonicalized to adds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66180 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-05 19:32:48 +00:00
Dan Gohman	076aee32e8	Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 19:44:21 +00:00
Dan Gohman	fc53fc657e	Correct this comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66057 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 19:24:25 +00:00
Dan Gohman	b37a8206b6	When using MachineInstr operand indices on SDNodes, the number of MachineInstr def operands must be subtracted out. This bug was uncovered by the recent x86 EFLAGS optimization. Before that, the only instructions that ever needed unfolding were things like CMP32rm, where NumDefs is zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66056 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 19:23:38 +00:00
Evan Cheng	ae3f2b6c77	Fix PR3666: isel calls to constant addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66024 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 06:48:53 +00:00
Dan Gohman	29582d1223	Revert r66004 for now; it's causing a variety of test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 03:54:19 +00:00
Dan Gohman	12bbc52aa7	Teach the x86 backend to eliminate "test" instructions by using the EFLAGS result from add, sub, inc, and dec instructions in simple cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 02:33:24 +00:00
Evan Cheng	599a6a88ce	Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-04 01:41:49 +00:00
Dan Gohman	09a2609e20	Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC instructions. These aren't used yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65965 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-03 19:53:46 +00:00
Bob Wilson	f2950b0051	Use early exit to reduce indentation. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65962 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-03 19:26:27 +00:00
Dan Gohman	0f8b53f19d	Fix a bunch of Doxygen syntax issues. Escape special characters, and put @file directives on their own comment line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-03 02:55:14 +00:00
Bob Wilson	24e338e8a3	Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle arbitrary vector sizes. Add an optional MinSplatBits parameter to specify a minimum for the splat element size. Update the PPC target to use the revised interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65899 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-02 23:24:16 +00:00
Bob Wilson	a27ea9e89f	Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new method in a BuildVectorSDNode "pseudo-class". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65747 91177308-0d34-0410-b5e6-96231b3b80d8	2009-03-01 01:13:55 +00:00
Mon P Wang	9feb5dd568	Added another darwin subtarget git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65662 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-28 00:25:30 +00:00
Rafael Espindola	9a58023c6c	Refactor TLS code and add some tests. The tests and expected results are: pic \| declaration \| linkage \| visibility \| !pic \| declaration \| external \| default \| tls1.ll tls2.ll \| local exec pic \| declaration \| external \| default \| tls1-pic.ll tls2-pic.ll \| general dynamic !pic \| !declaration \| external \| default \| tls3.ll tls4.ll \| initial exec pic \| !declaration \| external \| default \| tls3-pic.ll tls4-pic.ll \| general dynamic !pic \| declaration \| external \| hidden \| tls7.ll tls8.ll \| local exec pic \| declaration \| external \| hidden \| X \| local dynamic !pic \| !declaration \| external \| hidden \| tls9.ll tls10.ll \| local exec pic \| !declaration \| external \| hidden \| X \| local dynamic !pic \| declaration \| internal \| default \| tls5.ll tls6.ll \| local exec pic \| declaration \| internal \| default \| X \| local dynamic The ones marked with an X have not been implemented since local dynamic is not implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-27 13:37:18 +00:00
Dale Johannesen	ded2b20e7e	Alignment values for i64 and f64 on ppc64 were wrong, possibly for the reason suggested by the comment. No wonder it didn't work very well. This unblocks bootstrap with assertions on ppc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65601 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-27 00:56:35 +00:00
Evan Cheng	236aa8a503	ADDS{D\|S}rr_Int and MULS{D\|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-26 03:12:02 +00:00
Evan Cheng	a87008d90b	Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-25 22:49:59 +00:00
Nick Lewycky	20babb112c	Add a totally synthetic situation I came up with while looking at a bug in related code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65437 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-25 06:52:48 +00:00
Scott Michel	df38043a46	Remove all "cached" data from BuildVectorSDNode, preferring to retrieve results via reference parameters. This patch also appears to fix Evan's reported problem supplied as a reduced bugpoint test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65426 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-25 03:12:50 +00:00
Bill Wendling	57f0db833d	Overhaul my earlier submission due to feedback. It's a large patch, but most of them are generic changes. - Use the "fast" flag that's already being passed into the asm printers instead of shoving it into the DwarfWriter. - Instead of calling "MI->getParent()->getParent()" for every MI, set the machine function when calling "runOnMachineFunction" in the asm printers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-24 08:30:20 +00:00
Dan Gohman	e9865945ad	Fast-isel can't do TLS yet, so it should fall back to SDISel if it sees TLS addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65341 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-23 22:03:08 +00:00
Evan Cheng	242b38bae5	Only v1i16 (i.e. _m64) is returned via RAX / RDX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65313 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-23 09:03:22 +00:00
Nate Begeman	b9a47b824f	Generate better code for v8i16 shuffles on SSE2 Generate better code for v16i8 shuffles on SSE2 (avoids stack) Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops. Document the shuffle matching logic and add some FIXMEs for later further cleanups. New tests that test the above. Examples: New: _shuf2: pextrw $7, %xmm0, %eax punpcklqdq %xmm1, %xmm0 pshuflw $128, %xmm0, %xmm0 pinsrw $2, %eax, %xmm0 Old: _shuf2: pextrw $2, %xmm0, %eax pextrw $7, %xmm0, %ecx pinsrw $2, %ecx, %xmm0 pinsrw $3, %eax, %xmm0 movd %xmm1, %eax pinsrw $4, %eax, %xmm0 ret ========= New: _shuf4: punpcklqdq %xmm1, %xmm0 pshufb LCPI1_0, %xmm0 Old: _shuf4: pextrw $3, %xmm0, %eax movsd %xmm1, %xmm0 pextrw $3, %xmm1, %ecx pinsrw $4, %ecx, %xmm0 pinsrw $5, %eax, %xmm0 ======== New: _shuf1: pushl %ebx pushl %edi pushl %esi pextrw $1, %xmm0, %eax rolw $8, %ax movd %xmm0, %ecx rolw $8, %cx pextrw $5, %xmm0, %edx pextrw $4, %xmm0, %esi pextrw $3, %xmm0, %edi pextrw $2, %xmm0, %ebx movaps %xmm0, %xmm1 pinsrw $0, %ecx, %xmm1 pinsrw $1, %eax, %xmm1 rolw $8, %bx pinsrw $2, %ebx, %xmm1 rolw $8, %di pinsrw $3, %edi, %xmm1 rolw $8, %si pinsrw $4, %esi, %xmm1 rolw $8, %dx pinsrw $5, %edx, %xmm1 pextrw $7, %xmm0, %eax rolw $8, %ax movaps %xmm1, %xmm0 pinsrw $7, %eax, %xmm0 popl %esi popl %edi popl %ebx ret Old: _shuf1: subl $252, %esp movaps %xmm0, (%esp) movaps %xmm0, 16(%esp) movaps %xmm0, 32(%esp) movaps %xmm0, 48(%esp) movaps %xmm0, 64(%esp) movaps %xmm0, 80(%esp) movaps %xmm0, 96(%esp) movaps %xmm0, 224(%esp) movaps %xmm0, 208(%esp) movaps %xmm0, 192(%esp) movaps %xmm0, 176(%esp) movaps %xmm0, 160(%esp) movaps %xmm0, 144(%esp) movaps %xmm0, 128(%esp) movaps %xmm0, 112(%esp) movzbl 14(%esp), %eax movd %eax, %xmm1 movzbl 22(%esp), %eax movd %eax, %xmm2 punpcklbw %xmm1, %xmm2 movzbl 42(%esp), %eax movd %eax, %xmm1 movzbl 50(%esp), %eax movd %eax, %xmm3 punpcklbw %xmm1, %xmm3 punpcklbw %xmm2, %xmm3 movzbl 77(%esp), %eax movd %eax, %xmm1 movzbl 84(%esp), %eax movd %eax, %xmm2 punpcklbw %xmm1, %xmm2 movzbl 104(%esp), %eax movd %eax, %xmm1 punpcklbw %xmm1, %xmm0 punpcklbw %xmm2, %xmm0 movaps %xmm0, %xmm1 punpcklbw %xmm3, %xmm1 movzbl 127(%esp), %eax movd %eax, %xmm0 movzbl 135(%esp), %eax movd %eax, %xmm2 punpcklbw %xmm0, %xmm2 movzbl 155(%esp), %eax movd %eax, %xmm0 movzbl 163(%esp), %eax movd %eax, %xmm3 punpcklbw %xmm0, %xmm3 punpcklbw %xmm2, %xmm3 movzbl 188(%esp), %eax movd %eax, %xmm0 movzbl 197(%esp), %eax movd %eax, %xmm2 punpcklbw %xmm0, %xmm2 movzbl 217(%esp), %eax movd %eax, %xmm4 movzbl 225(%esp), %eax movd %eax, %xmm0 punpcklbw %xmm4, %xmm0 punpcklbw %xmm2, %xmm0 punpcklbw %xmm3, %xmm0 punpcklbw %xmm1, %xmm0 addl $252, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65311 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-23 08:49:38 +00:00
Bill Wendling	ef4cfc749a	Propagate debug loc info through prologue/epilogue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65298 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-23 00:42:30 +00:00
Scott Michel	4214a5531c	Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR instruction. The class also consolidates the code for detecting constant splats that's shared across PowerPC and the CellSPU backends (and might be useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for generating new BUILD_VECTOR nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-22 23:36:09 +00:00
Evan Cheng	779aee1fea	Add a note. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65275 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-22 08:13:45 +00:00
Evan Cheng	6140a8b057	Be bug compatible with gcc by returning MMX values in RAX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65274 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-22 08:05:12 +00:00
Evan Cheng	c94ebef1b1	Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65273 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-22 08:04:23 +00:00
Anton Korobeynikov	b5bd026a75	Drop bunch of half-working stuff in the ext_weak linkage support. Now we're using one gross, but quite robust hack :) (previous ones did not work, for example, when ext_weak symbol was used deep inside constant expression in the initializer). The proper fix of this problem will require some quite huge asmprinter changes and that's why was postponed. This fixes PR3629 by the way :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65230 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-21 11:53:32 +00:00
Bill Wendling	5a45d76c25	Make sure this doesn't access .end() too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65213 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-21 01:11:36 +00:00
Bill Wendling	8aa374b629	Make sure we don't dereference the .end() of the container. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65211 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-21 01:07:26 +00:00
Bill Wendling	3d2445f5d9	Propagate more debug loc infos. This also includes some code cleaning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65207 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-21 00:43:56 +00:00
Bill Wendling	2625f9b2e4	We need to propagate the debug location information even when dealing with the prologue/epilogue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65206 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-21 00:32:08 +00:00
Evan Cheng	79fb3b434f	Support return of MMX values in 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65152 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-20 20:43:02 +00:00
Torok Edwin	474479fce7	add note about sin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65137 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-20 18:42:06 +00:00
Bill Wendling	cb819f13d7	Put code that generates debug labels into TableGen so that it can be used by everyone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64978 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-18 23:12:06 +00:00
Dan Gohman	38deef9ce5	Add explicit keywords. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64915 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-18 16:37:45 +00:00
Nate Begeman	d6b7a242d3	Add support to the JIT for true non-lazy operation. When a call to a function that has not been JIT'd yet, the callee is put on a list of pending functions to JIT. The call is directed through a stub, which is updated with the address of the function after it has been JIT'd. A new interface for allocating and updating empty stubs is provided. Add support for removing the ModuleProvider the JIT was created with, which would otherwise invalidate the JIT's PassManager, which is initialized with the ModuleProvider's Module. Add support under a new ExecutionEngine flag for emitting the infomration necessary to update Function and GlobalVariable stubs after JITing them, by recording the address of the stub and the name of the GlobalValue. This allows code to be copied from one address space to another, where libraries may live at different virtual addresses, and have the stubs updated with their new correct target addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64906 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-18 08:31:02 +00:00
Dan Gohman	97357614b5	Factor out the code to add a MachineOperand to a MachineInstrBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-18 05:45:50 +00:00
Evan Cheng	caa0c2cadd	GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-18 02:19:52 +00:00
Scott Michel	fdc40a0a69	Remove trailing whitespace to reduce later commit patch noise. (Note: Eventually, commits like this will be handled via a pre-commit hook that does this automagically, as well as expand tabs to spaces and look for 80-col violations.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-17 22:15:04 +00:00
Chris Lattner	a66878b881	add a horrible note git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64719 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-17 01:16:14 +00:00
Bill Wendling	86e6cb924b	--- Merging (from foreign repository) r64714 into '.': U include/llvm/CodeGen/DebugLoc.h U lib/CodeGen/SelectionDAG/LegalizeDAG.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Enable debug location generation at -Os. This goes with the reapplication of the r63639 patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64715 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-17 01:04:54 +00:00
Dan Gohman	9fbb52db98	Delete trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64694 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-16 23:14:14 +00:00
Dan Gohman	35188eb54d	MachineLICM now handles these cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64620 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-15 23:24:52 +00:00
Dan Gohman	b5aa3ad1e7	The x86-64 red zone is now being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64535 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-14 03:30:05 +00:00
Evan Cheng	c7ce29b04f	Teach x86 target -soft-float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64496 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 22:36:38 +00:00
Dale Johannesen	948175785d	Remove non-DebugLoc versions of BuildMI from IA64, Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64438 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:34:39 +00:00
Dale Johannesen	8d13f8f104	Remove non-DebugLoc versions of BuildMI from X86. There were some that might even matter in X86FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:33:27 +00:00
Dale Johannesen	0b4581f16c	missed file git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64436 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:32:04 +00:00
Dale Johannesen	d552eee4a0	Remove non-DebugLoc versions of buildMI from Sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64435 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:31:35 +00:00
Dale Johannesen	01b36e6436	Remove non-DebugLoc versions of BuildMI from Alpha and Cell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:30:42 +00:00
Dale Johannesen	bd9ef18f74	Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64432 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:29:03 +00:00
Dale Johannesen	536a2f1f84	Remove refs to non-DebugLoc version of BuildMI from PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:27:39 +00:00
Dale Johannesen	8a43d98644	and one more file git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64430 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:26:21 +00:00
Dale Johannesen	b67284057e	Remove refs to non-DebugLoc versions of BuildMI from ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:25:56 +00:00
Bill Wendling	92c1e12647	Revert this. It was breaking stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64428 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:16:35 +00:00
Bill Wendling	54fc7d6714	Turn off the old way of handling debug information in the code generator. Use the new way, where all of the information is passed on SDNodes and machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64427 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-13 02:01:04 +00:00
Dale Johannesen	c5b5051357	Check in missing file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64410 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 23:24:44 +00:00
Dale Johannesen	21b5541814	Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 23:08:38 +00:00
Dale Johannesen	78e3e521cd	Arrange to print constants that match "n" and "i" constraints in inline asm as signed (what gcc does). Add partial support for x86-specific "e" and "Z" constraints, with appropriate signedness for printing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64400 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 20:58:09 +00:00
Chris Lattner	8c4d1b2bcf	fix PR3538 for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64384 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 17:38:23 +00:00
Chris Lattner	f902d246b6	fix PR3538 for PPC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64383 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 17:37:15 +00:00
Chris Lattner	1823c92aa7	fix the X86 backend to just drop llvm.declare nodes for VLAs instead of leaving them in the DAG and then getting selection errors. This is a fix for PR3538. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64382 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 17:33:11 +00:00
Bill Wendling	d1c321a89a	Move debug loc info along when the spiller creates new instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-12 00:02:55 +00:00
Bill Wendling	fbef3101a5	Propagate DebugLoc info for spiller call-backs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64329 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-11 21:51:19 +00:00
Dan Gohman	d293e0d2dc	Don't try to set an EFLAGS operand to dead if no instruction was created. This fixes a bug introduced by r61215. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64316 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-11 19:50:24 +00:00
Evan Cheng	1d76864df3	Handle llvm.x86.sse2.maskmov.dqu in 64-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64240 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-10 22:06:28 +00:00
Evan Cheng	7403eeaa88	80 col violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64237 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-10 21:39:44 +00:00
Sanjiv Gupta	2cc753170b	Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64199 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-10 04:20:26 +00:00
Evan Cheng	a0eedac226	Implement FpSET_ST1_*. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64186 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-09 23:32:07 +00:00
Dan Gohman	333014e256	Use doxygen comment syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64150 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-09 18:12:09 +00:00
Evan Cheng	dc54d317e7	Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-09 07:14:22 +00:00
Chris Lattner	be685cc72a	add a note. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64093 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-08 20:44:19 +00:00
Dale Johannesen	6f38cb61a9	Use getDebugLoc forwarder instead of getNode()->getDebugLoc. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-07 19:59:05 +00:00
Dan Gohman	1fdbc1dd4e	Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing ScheduleDAG's TLI member to use const. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-07 16:15:20 +00:00
Dale Johannesen	0469280776	Needs this file too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63993 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-07 00:56:46 +00:00
Dale Johannesen	b300d2aa3e	Get rid of the last non-DebugLoc versions of getNode! Many targets build placeholder nodes for special operands, e.g. GlobalBaseReg on X86 and PPC for the PIC base. There's no sensible way to associate debug info with these. I've left them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. I'm not too happy about this but don't see a good improvement; I considered adding a getPseudoOperand or something, but it seems to me that'll just make it harder to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-07 00:55:49 +00:00
Dan Gohman	2d0a1cc416	Refactor some repeated logic into a separate function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63989 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-07 00:43:41 +00:00
Dan Gohman	288b824cef	Make a comment a doxygen comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63988 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-07 00:42:54 +00:00
Dale Johannesen	e8d7230f48	Remove more non-DebugLoc getNode variants. Use getCALLSEQ_{END,START} to permit passing no DebugLoc there. UNDEF doesn't logically have DebugLoc; add getUNDEF to encapsulate this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 23:05:02 +00:00
Dale Johannesen	de06470330	Remove more non-DebugLoc versions of getNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 21:50:26 +00:00
Bill Wendling	ac06d004a0	Record debug location information in the Dwarf writer. A simple test program shows that debugging works. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63968 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 21:45:08 +00:00
Dan Gohman	9036d80d7b	Use .size and .type on ELF systems; this helps tools that map addresses to symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63962 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 21:15:52 +00:00
Dale Johannesen	f5f5dce897	Eliminate remaining non-DebugLoc version of getTargetNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 19:16:40 +00:00
Sanjiv Gupta	a2d8b06272	Print globl directive for variables with external linkage (global variables). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63943 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 18:24:59 +00:00
Evan Cheng	770bcc7b15	Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 17:43:24 +00:00
Evan Cheng	4350eb86a7	Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 17:17:30 +00:00
Dale Johannesen	f90b2a7742	get rid of some non-DebugLoc getTargetNode variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63909 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 02:08:06 +00:00
Dale Johannesen	ed2eee63a6	Get rid of one more non-DebugLoc getNode and its corresponding getTargetNode. Lots of caller changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-06 01:31:28 +00:00
Dale Johannesen	3484c09e0d	Remove a non-DebugLoc version of getNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63889 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-05 22:07:54 +00:00
Evan Cheng	b3379fbc60	A few more isAsCheapAsAMove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63852 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-05 08:42:55 +00:00
Dale Johannesen	49de98214b	Reapply 63765. Patches for clang and llvm-gcc to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-05 01:49:45 +00:00
Dale Johannesen	2fabcb2776	Get rid of 3 non-DebugLoc getNode variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63808 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-05 01:01:16 +00:00
Dale Johannesen	4be0bdf7c1	Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63800 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-05 00:20:09 +00:00
Dale Johannesen	a05dca4f9e	Remove non-DebugLoc forms of CopyToReg and CopyFromReg. Adjust callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 23:02:30 +00:00
Dale Johannesen	4d452de150	Reverting 63765. This broke the build of both clang and llvm-gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 22:47:25 +00:00
Dale Johannesen	33c960f523	Remove non-DebugLoc versions of getLoad and getStore. Adjust the many callers of those versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 20:06:27 +00:00
Nate Begeman	d24479730a	New feature: add support for target intrinsics being defined in the target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 19:47:21 +00:00
Chris Lattner	e6c1473e56	Bill implemented this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63752 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 19:09:07 +00:00
Chris Lattner	8dfdf5d62d	add a note, this is why we're faster at SciMark-MonteCarlo with SSE disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63751 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 19:08:01 +00:00
Dan Gohman	37eed798a9	Minor code cleanups; no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63740 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 17:28:58 +00:00
Dale Johannesen	39355f9fea	Remove non-DebugLoc forms of the exotic forms of Lod and Sto; patch uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63716 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 02:34:38 +00:00
Dale Johannesen	f5d9789a7f	Remove some more non-DebugLoc versions of construction functions, with callers adjusted to fit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63705 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 01:48:28 +00:00
Dale Johannesen	8ad9b43e69	Remove a few non-DebugLoc versions of node creation functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63703 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 01:17:06 +00:00
Mon P Wang	7bcaefaf59	Fixes a case where we generate an incorrect mask for pshfhw in the presence of undefs and incorrectly determining if we have punpckldq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63702 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 01:16:59 +00:00
Dale Johannesen	dd64c417c0	Patch up omissions in DebugLoc propagation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63693 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-04 00:33:20 +00:00
Dale Johannesen	eacf2dc4bb	Need this file too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63674 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 22:26:34 +00:00
Dale Johannesen	0f502f6f44	Add some DL propagation to places that didn't have it yet. More coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 22:26:09 +00:00
Dale Johannesen	d839254888	DebugLoc propgation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63664 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 21:48:12 +00:00
Dale Johannesen	e4d209dcb8	DebugLoc propagation. done with file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63656 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 20:21:25 +00:00
Dale Johannesen	ace1610df5	DebugLoc propagation. 2/3 through file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63650 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 19:33:06 +00:00
Dan Gohman	605679f0cd	Tevert part of the x86 subtarget logic changes: when -march=x86-64 is given, override the subtarget settings and enable 64-bit support. This restores the earlier behavior, and fixes regressions on Non-64-bit-capable x86-32 hosts. This isn't necessarily the best approach, but the most obvious alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used with -march=x86-64 when the host doesn't have 64-bit support. This makes things little more consistent, but it's less convenient, and it has the practical drawback of requiring lots of test changes, so I opted for the above approach for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63642 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 18:53:21 +00:00
Bill Wendling	9bc96a5720	Create DebugLoc information in FastISel. Several temporary methods were created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63584 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 00:55:04 +00:00
Dan Gohman	f75e5b4d8c	Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has SSE2, however it's possible to disable SSE2, and the subtarget support code thinks that if 64-bit implies SSE2 and SSE2 is disabled then 64-bit should also be disabled. Instead, just mark all the 64-bit subtargets as explicitly supporting SSE2. Also, move the code that makes -march=x86-64 enable 64-bit support by default to only apply when there is no explicit subtarget. If you need to specify a subtarget and you want 64-bit code, you'll need to select a subtarget that supports 64-bit code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63575 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 00:04:43 +00:00
Torok Edwin	b68a88bd48	Only force SSE level if it is not correct. Add an assert to check HasX86_64 status. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63552 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-02 21:57:34 +00:00
Torok Edwin	38870ed13c	remove #if 0 code on Bill's request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63542 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-02 20:23:02 +00:00
Sanjiv Gupta	3b020feb57	Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63521 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-02 16:53:06 +00:00
Evan Cheng	97d0e0e314	ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63509 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-02 09:15:04 +00:00
Evan Cheng	961d6d4ac0	Add comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63506 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-02 08:19:07 +00:00
Evan Cheng	67ad9db15b	Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63505 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-02 08:07:36 +00:00
Torok Edwin	3f142c36ad	Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for var-args, and don't allow FP return values git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63495 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-01 18:15:56 +00:00
Duncan Sands	b0d5cdd52e	Fix PR3453 and probably a bunch of other potential crashes or wrong code with codegen of large integers: eliminate the legacy getIntegerVTBitMask and getIntegerVTSignBit methods, which returned their value as a uint64_t, so couldn't handle huge types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63494 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-01 18:06:53 +00:00
Dale Johannesen	7d2ad624fa	Make LowerCallTo and LowerArguments take a DebugLoc argument. Adjust all callers and overloaded versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-30 23:10:59 +00:00
Bill Wendling	7581bfa275	Get rid of the non-DebugLoc-ified getNOT() method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63442 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-30 23:03:19 +00:00
Sanjiv Gupta	5af3ee2818	Fixed the comment. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63387 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-30 09:01:44 +00:00
Sanjiv Gupta	e0ffc92508	Use sublw for comparison with literals instead of subwf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63382 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-30 07:55:25 +00:00
Mon P Wang	7ad9b51278	When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of an illegal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63380 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-30 07:07:40 +00:00
Sanjiv Gupta	c8d7bc850d	Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63377 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-30 04:25:10 +00:00
Dan Gohman	e5af2d3a22	Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-29 01:59:02 +00:00
Mon P Wang	e91a000889	Fixed lowering of v816 shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63252 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-28 23:11:14 +00:00
Duncan Sands	1465d61bdd	Rename getAnalysisToUpdate to getAnalysisIfAvailable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63198 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-28 13:14:17 +00:00
Evan Cheng	1632782fe9	The memory alignment requirement on some of the mov{h\|l}p{d\|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63195 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-28 08:35:02 +00:00
Mon P Wang	3becd093cc	Add shuffle splat pattern for x86 sse shifts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63193 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-28 08:12:05 +00:00

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10886 Commits