Commit Graph

16756 Commits

Author SHA1 Message Date
Owen Anderson
cfd0e1f3ae Add correct NEON encodings for vtbl and vtbx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 00:18:46 +00:00
Owen Anderson
3eff4af42d Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:56:39 +00:00
Bob Wilson
1fa9d301a8 Fix compiler warnings about signed/unsigned comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:49:00 +00:00
Evan Cheng
f40deed62f Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:41:30 +00:00
Jim Grosbach
7e3383c007 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703 Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 22:49:00 +00:00
Jim Grosbach
6b15639e26 Trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:39:08 +00:00
Owen Anderson
d2fbdb7f5c Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:28:09 +00:00
Kevin Enderby
529b1a4398 Added the x86 instruction ud2b (2nd official undefined instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:46:49 +00:00
Jim Grosbach
ccf72caa92 JIT imm12 encoding for constant pool entry references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:39:40 +00:00
Bob Wilson
f20700ca77 SelectionDAG shuffle nodes do not allow operands with different numbers of
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:38:28 +00:00
Jim Grosbach
f31430f6ec ARM JIT fix for LDRi12 and company.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:55:59 +00:00
Owen Anderson
f587a9352a Provide correct NEON encodings for vdup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:25:54 +00:00
Michael J. Spencer
6dad10ed66 x86-Win32: Switch ftol2 calling convention from stdcall to C.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 18:52:38 +00:00
Jim Grosbach
093177d5cd The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:52:51 +00:00
Owen Anderson
0745c389d9 Add correct NEON encodings for vsli and vsri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:40:08 +00:00
Owen Anderson
dd31ed67e6 Add correct NEON encodings for vsra and vrsra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:29:29 +00:00
Jim Grosbach
063efbf569 The immediate operands of an LDRi12 instruction doesn't need the addrmode2
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 16:50:31 +00:00
Kevin Enderby
e460890351 Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 03:01:02 +00:00
Kevin Enderby
5a378076a4 Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 02:53:04 +00:00
Kevin Enderby
f4630ecc3f Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 02:32:19 +00:00
Jim Grosbach
77aee8e22c LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 01:19:41 +00:00
Kevin Enderby
41e8cc73cf Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
Jim Grosbach
f85dd04bfa One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:38:16 +00:00
Wesley Peck
a06038369b Adding disassembler to the MicroBlaze backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:23:01 +00:00
Jim Grosbach
c1d30212e9 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:19:44 +00:00
Jim Grosbach
28e3fe961f Since I parameterized this bit, I should probably actually use said parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 23:58:04 +00:00
Dale Johannesen
1de4aa904e Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 23:11:10 +00:00
Owen Anderson
86ed2324a6 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:50:46 +00:00
Jim Grosbach
3e55612472 First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:37:02 +00:00
Owen Anderson
632c235a31 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 21:58:41 +00:00
Owen Anderson
ac92262b61 Simplify classes for shift instructions, which are never commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 21:13:59 +00:00
Owen Anderson
3557d00a38 Provide correct NEON encodings for vshl, register and immediate forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 20:56:57 +00:00
Jim Grosbach
0eb7d06ab1 Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 19:34:41 +00:00
Jim Grosbach
c3baf62800 Nuke extraneous comment. It's applicable elsewhere, but not in this func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 19:22:23 +00:00
Owen Anderson
bc4118bd36 Add correct NEON encoding for vpadal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:18:03 +00:00
Rafael Espindola
de42e5c09b handle X86::EH_RETURN64 and X86::EH_RETURN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:09:55 +00:00
Owen Anderson
a88ea03bf2 Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 17:40:54 +00:00
Rafael Espindola
e4f506ff4b Implement some relaxations for arithmetic instructions. The limitation
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 14:09:12 +00:00
Kalle Raiskila
505faa6b12 Change v64 datalayout in SPU.
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 10:45:47 +00:00
Evan Cheng
c8141dfc7f Use instruction itinerary to determine what instructions are 'cheap'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:08:50 +00:00
Evan Cheng
0e9996ca94 NEON vmov's are in Neon domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:03:05 +00:00
Bob Wilson
b3a6817d06 Tidy up redundant check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 00:02:19 +00:00
Rafael Espindola
3336384239 Produce the headers directly in the Finish method. This allows us to use
the existing streamer methods that are endian safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 22:26:55 +00:00
Dale Johannesen
d155d7e428 An stdcall function calling a non-stdcall function
cannot use tailcall.  PR 8461.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 22:17:05 +00:00
Owen Anderson
5258b61966 Add correct encodings for NEON vabal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 21:29:04 +00:00
Owen Anderson
410aebc670 Add correct NEON encodings for vaba.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:52:57 +00:00
Owen Anderson
31e6ed890a Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:17:22 +00:00
Owen Anderson
4110b4325d Provide correct NEON encodings for vbsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:13:13 +00:00
Jim Grosbach
458f2dc5d1 imm12 operands aren't Thumb2 only, so rename the printer helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:00:01 +00:00
Owen Anderson
162875a9f3 Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:43:52 +00:00
Rafael Espindola
4921e2356e Add a virtual destructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:38:32 +00:00
Owen Anderson
8c71eff594 Provide correct NEON encodings for vand, veor, and vorr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:28:30 +00:00
Owen Anderson
d0c5b6170f Add NEON encoding tests for vcgt and vacgt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:03:59 +00:00
Rafael Espindola
cecbc3d282 Add support for emitting ARM file attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:50:35 +00:00
Owen Anderson
10c15e5d58 Add tests for NEON encodings of vcge and vacge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:49:32 +00:00
Owen Anderson
4fe20bbd66 Add a warning about our inability to test the encoding of vceq with immediate zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:33:02 +00:00
Rafael Espindola
24ba4f7f5f Add X86::reloc_global_offset_table and use it to have a single place where
we check for _GLOBAL_OFFSET_TABLE_.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-24 17:35:42 +00:00
Eric Christopher
a4633f5d74 Move rejection of NEON parameters earlier in fast isel call processing,
note that we can actually handle some f64 arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:37:17 +00:00
Benjamin Kramer
4d1dca92bd Make the disassembler tables const so they end up in read-only memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:10:44 +00:00
Michael J. Spencer
c527407010 X86: Emit _fltused instead of __fltused on Windows x64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:06:59 +00:00
Chandler Carruth
19e57025d4 Move the remaining attribute macros to systematic names based on the attribute
name and prefixed with 'LLVM_'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:40:19 +00:00
Chandler Carruth
5117709a1d Remove a define which is never referenced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117202 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:25:16 +00:00
Chandler Carruth
100c267249 Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
until other LLVM projects using these are cleaned up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:10:43 +00:00
Evan Cheng
5c2d428f43 Enable ARM fastcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:19:37 +00:00
Evan Cheng
dd9dd6f857 Latency between CPSR def and branch is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:04:38 +00:00
Jim Grosbach
a9a968d1ef Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:48:29 +00:00
Gabor Greif
41f31ef28e fix memory-layout assumption which only holds on little-endian systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:16:11 +00:00
Jim Grosbach
f8da5f5dfa ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 22:12:16 +00:00
Evan Cheng
b179b46cc5 Transfer implicit ops when forming load multiple and return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 21:29:58 +00:00
Owen Anderson
9b26497273 Add correct NEON encodings for vqdmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:35:48 +00:00
Jim Grosbach
385e136dce Add the encoding information for the rest of the ARM mode multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:15:30 +00:00
Owen Anderson
92205842ca Provide correct encodings for NEON vmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:05:25 +00:00
Evan Cheng
1f8b40d51c Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:57:05 +00:00
Owen Anderson
18341e9e31 Provide correct NEON encodings for vmla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:54:37 +00:00
Jim Grosbach
3870b750e6 More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:35:16 +00:00
Evan Cheng
76f920d316 Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:23:05 +00:00
Jim Grosbach
929a7056d8 Parameterize a bit of ARM encoding information, simplifying some instruction
definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:42:06 +00:00
Benjamin Kramer
a3ac427507 Make some symbols static, move classes into anonymous namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:35:07 +00:00
Jim Grosbach
9463d0e400 More ARM multiply instruction encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:16:17 +00:00
Wesley Peck
eecb858ca8 Making the e_machine configurable by the target backend in ELFObjectWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 15:52:49 +00:00
Andrew Trick
0966ec0861 Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 03:58:29 +00:00
Eric Christopher
4f512efee9 Add some basic ret instruction support to arm fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:28:00 +00:00
Sean Callanan
751752e7ca Fixed handling of immediate operand sizes, which
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:24:11 +00:00
Jim Grosbach
f50af8b5b8 ARM binary encoding for some of the multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:52:30 +00:00
Jim Grosbach
3686046a2c ARM binary encodings for MVN variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:19:32 +00:00
Jim Grosbach
3fea19105d ARM Binary encoding information for BFC/BFI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:03:21 +00:00
Eric Christopher
1778772d1b These don't need to be virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 21:47:51 +00:00
Owen Anderson
90d4cf9314 Move the encoding logic for Q registers into getMachineOpValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:49:13 +00:00
Owen Anderson
d451f888b8 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:21:49 +00:00
Eric Christopher
5b924809e4 Handle storing args to the stack for calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:09:54 +00:00
Wesley Peck
4da992aeba Adding initial AsmParser implementation for the MBlaze backend. It is
mostly based on the ARM AsmParser at this time and is not particularly
functional.

Changed the MBlaze data layout from:
    "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
    "E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.

Cleaned up the MBlaze source code:
    1. The floating point register class has been removed. The
       MicroBlaze does not have floating point registers. Floating
       point values are simply stored in integer registers.
    2. Renaming the CPURegs register class to GPR to reflect the
       standard naming.
    3. Removing a lot of stale code from AsmPrinter after
       the conversion to InstPrinter.
    4. Simplified sign extended loads by marking them as
       expanded in ISelLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:48:38 +00:00
Eric Christopher
212ae937bb More load/store refactoring, call reg+offset simplification from within
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:40:30 +00:00
Jim Grosbach
3ab5658a12 trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:38:40 +00:00
Owen Anderson
1e93466c3a Add correct NEON encodings for vhadd and vrhadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:55:04 +00:00
Owen Anderson
9d50559bae Add correct encodings for NEON vaddw.s* and vaddw.u*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:20:25 +00:00
Owen Anderson
e0e6dc3f4e Provide correct NEON encodings for vaddl.u* and vaddl.s*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:09:17 +00:00
Kevin Enderby
0b9325c97d More tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 17:16:46 +00:00
Duncan Sands
dbbd99faf1 The return value of this call is not used, so no point
in assigning it to a variable (gcc-4.6 warning).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:06:28 +00:00
Duncan Sands
6abfa46987 Remove some variables that are never really used
(gcc-4.6 warns about these).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:03:28 +00:00
Duncan Sands
1e1ca0b56d Add parentheses to pacify gcc, which warns otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:02:12 +00:00
Wesley Peck
42bd9b30d9 Removing stale AsmPrinter directory from MicroBlaze backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 05:05:06 +00:00
Oscar Fuentes
b692360955 Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the
CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 05:01:26 +00:00
Wesley Peck
4e9141fd4c Recommit 116986 with capitalization typo fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:57:26 +00:00
Andrew Trick
5b7a825ec5 putback r116983 and fix simple-fp-encoding.ll tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:40:16 +00:00
Wesley Peck
60e7127e86 Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:34:22 +00:00
Owen Anderson
d9707e3d85 Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:11:16 +00:00
Wesley Peck
13a949071c Major update of the MicroBlaze backend. The new features are:
1. A delay slot filler that searches for valid instructions
       to fill the delay slot with. Previously NOPs would always
       be inserted into delay slots.
    2. Support for MC based instruction printer added.
    3. Support for MC based machine code generation and ELF
       file generation. ELF file generation does not yet
       completely work as much of the ELF support infrastructure
       is still x86/x86-64 specific.
    4. General clean up of the MBlaze backend code. Much of the
       tablegen code has been cleanup and simplified.

Bug Fixes:
    1. Removed duplicate periods from subtarget feature descriptions.
    2. Many of the instructions had bad machine code information
       in the tablegen files. Much of this has been fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:09:55 +00:00
Michael J. Spencer
e9c253e0bc X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 01:41:01 +00:00
Evan Cheng
d6865de2d2 Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 01:12:00 +00:00
Owen Anderson
d7795540d0 Implement correct encodings for NEON vadd, both integer and floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:48:00 +00:00
Michael J. Spencer
dd0a00a6e3 CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args.
This should be the minimum set of functions that could possibly need it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:08:21 +00:00
Eric Christopher
2d8f6fe610 Custom lower f64 args passed in integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:01:47 +00:00
Michael J. Spencer
6e56b18e57 Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 23:40:27 +00:00
Bill Wendling
01aabdac44 Add encoding for moving a value between two ARM core registers and a doublework
extension register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 23:37:40 +00:00
Bill Wendling
7d31a169af Add encodings for movement between ARM core registers and single-precision
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:44:54 +00:00
Dale Johannesen
e4d31593c5 Fix crash introduced in 116852. 8573915.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:03:37 +00:00
Dale Johannesen
e93d99cf07 Remove Synthesizable from the Type system; as MMX vector
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 21:32:10 +00:00
Rafael Espindola
64e6719ee8 Handle _GLOBAL_OFFSET_TABLE_ correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 16:46:08 +00:00
Chandler Carruth
1cd9708f5c Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
#includes in the process.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:27:02 +00:00
Eric Christopher
3659ac22c0 Fix a TODO by removing some unnecesary copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:02:24 +00:00
Jim Grosbach
b8e67fc92b Fix backwards conditional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 01:10:01 +00:00
Jim Grosbach
8b95c3ebfb Add dynamic realignment when rematerializing the base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 00:02:50 +00:00
Jim Grosbach
f6d7df6f21 Nuke a commented out bit that got missed a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:48:47 +00:00
Jim Grosbach
e4ad387a5a Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:27:08 +00:00
Jim Grosbach
8155ea4c3a Update comments to remove obsolete references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 21:34:47 +00:00
Dale Johannesen
575cd148ce Enable using vdup for vector constants which are splat of
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's.  8003375.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 20:00:17 +00:00
Evan Cheng
2312842de0 Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 18:58:51 +00:00
Owen Anderson
081c34b725 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:21:58 +00:00
Daniel Dunbar
9869413802 Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:14:24 +00:00
Che-Liang Chiou
b48f2c2e1d Add lower argument and return of device function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 13:14:40 +00:00
Michael J. Spencer
94f7eeb84d X86: Add MS-CRT libcalls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 07:32:52 +00:00
Michael J. Spencer
87b8665878 Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 07:32:42 +00:00
Evan Cheng
11e8b74a7a - Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:55:07 +00:00
Bob Wilson
3454ed9545 Support alignment for NEON vld-lane and vst-lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:16:32 +00:00
Kevin Enderby
87f4a1a433 Added a few tweaks to the Intel Descriptor-table support instructions to allow
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
Jim Grosbach
70987fbc60 ARM encoding information for [SU]SAT* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 23:35:38 +00:00
Eric Christopher
6e5367d6a3 Revert r116220 - thus turning arm fast isel back on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 22:53:53 +00:00
Bill Wendling
b41ee96d76 Don't recompute MachineRegisterInfo in the Optimize* method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 21:22:31 +00:00
Jim Grosbach
5c57639c28 For Thumb2, try to use frame pointer references for stack slots even when a
base register is available. rdar://8525298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:39:46 +00:00
Rafael Espindola
aa85c21633 Produce ELF::R_386_GOTPC relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:36:12 +00:00
Kevin Enderby
7aef62ff8c Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
Jim Grosbach
0f0127f4a6 ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:48:59 +00:00
Jim Grosbach
e038a206df Grammar tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:38:50 +00:00
Kalle Raiskila
940e7965f1 Improve lowering of sext to i128 on SPU.
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 09:34:19 +00:00
Eric Christopher
4cf34c6c04 Remove the check for invalid calling conventions. Testing shows that they're
working just fine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 06:49:12 +00:00
Eric Christopher
fa87d66752 Lift arg promotion from the X86 backend. This should be unified at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 02:17:53 +00:00
Eric Christopher
404be0c04f Now that we handle all allocas via a non-SP reg offset remove all of the
special case handling for ARM::SP.


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2010-10-17 11:08:44 +00:00
Eric Christopher
ec8bf972f5 Allow more load types to be materialized through the allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 06:07:26 +00:00
Eric Christopher
d56d61af01 Optimize GEP off of intermediate allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:51:42 +00:00
Eric Christopher
7208dbf2d5 Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:42:53 +00:00
Eric Christopher
dc0b0ef6cd Turn on AddOperator folding in GEP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:41:46 +00:00
Eric Christopher
45c607134b Use the i12 immediate versions of the load instructions - they're handled
more in the post-passes.


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2010-10-17 01:40:27 +00:00
Rafael Espindola
f230df9af4 Add a MCObjectFormat class so that code common to all targets that use a
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

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2010-10-16 18:23:53 +00:00
Michael J. Spencer
84ac4d5a2a X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
if any floating point arguments are passed to an external function.

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2010-10-16 08:25:41 +00:00
Eric Christopher
47650ece37 Fix some funky formatting that got through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 01:10:35 +00:00
Bill Wendling
07fda9f9b6 ARMCodeEmitter::emitMiscInstruction is dead. Long live
ARMCodeEmitter::emitMiscInstruction!


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2010-10-15 23:35:12 +00:00
Eric Christopher
c9a91fdaf9 Make sure offset is 0 for load/store register to the stack call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:07:10 +00:00
Eric Christopher
00ed59a968 Formatting.
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2010-10-15 22:49:28 +00:00
Eric Christopher
315030ca74 Fix else if -> if in store machinery.
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2010-10-15 22:32:37 +00:00
Bill Wendling
2695d8edd1 Reformatting. No functionalogicality changes.
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2010-10-15 21:50:45 +00:00
Eric Christopher
a322425642 Refactor ARM fast-isel reg + offset to be a base + offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:32:12 +00:00
Jim Grosbach
5ad01c7728 Encoding information for the various ARM saturating add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 19:49:46 +00:00
Jim Grosbach
84760885e1 ARM binary encoding information for RSB and RSC instructions.
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2010-10-15 18:42:41 +00:00
Jim Grosbach
fd52906478 Don't mark argument value stores as immutable, as otherwise the post-RA
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer

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2010-10-15 18:34:47 +00:00
Bob Wilson
01b35c25de Use simple RegState::Define flag instead of getDefRegState(true).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:25:59 +00:00
Eric Christopher
2896df897c Expand GEP handling for constant offsets.
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2010-10-15 18:02:07 +00:00
Jim Grosbach
6bdc8ae291 When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
an explicit def. Make sure to capture that properly. rdar://8556556

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2010-10-15 17:35:17 +00:00
Jim Grosbach
8abe32af38 ARM mode encoding information for UBFX and SBFX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 17:15:16 +00:00
Bob Wilson
1dd5a2f4e1 Remove unused ARMISD::AND selection DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 04:34:40 +00:00
Bob Wilson
cfbece50f6 ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!


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2010-10-15 03:23:44 +00:00
Jim Grosbach
197a8df640 Encoding info for extension instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 02:29:58 +00:00
Jim Grosbach
58456c0b04 Add missing Rd encoding for MOVs instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 23:28:31 +00:00
Jim Grosbach
7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

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2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.

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2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69 MOVi16 and MOVT ARM mode encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 18:54:27 +00:00
Jim Grosbach
2d294f564b Simplify encoding information and add 'dst' operand info for TAILJMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 17:24:28 +00:00
Oscar Fuentes
7bd698153d Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 15:54:46 +00:00
Eric Christopher
eae8439771 Handle more complex GEP based loads and add a few TODOs to deal with
GEP + alloca.


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2010-10-14 09:29:41 +00:00
Bill Wendling
bbbdcd453d Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.


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2010-10-14 02:33:26 +00:00
Bill Wendling
946a2740a5 Add encoding for 'fmstat'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436 - Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.


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2010-10-14 01:02:08 +00:00
Jim Grosbach
bd38acfa6f Regenerate. No functional change, just cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 00:15:18 +00:00
Jim Grosbach
55561d1882 Detabify and clean up 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:47:11 +00:00
Jim Grosbach
95369599c6 A few 80 column fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:34:31 +00:00
Jim Grosbach
3a37866e53 trailing whitespace
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2010-10-13 23:12:26 +00:00
Jim Grosbach
b4b07b93ea Add a FIXME.
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2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c Add operand encoding bits for SMC and SVC in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062 More encoding cleanup. Also add register Rd operands for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7 Simplify some ARM encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f Update comment.
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2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5 Add a FIXME. The ADR instruction is a bit odd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03 Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133 Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680 Make a few more bits of some simple instructions explicit. nop, yield, wfe,
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

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2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509 Fix encoding for compares. No Rd register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:00:52 +00:00
Rafael Espindola
6d8628061b Fix another case where we were preferring instructions with large
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 13:31:20 +00:00
Eric Christopher
ede42b0a22 Start handling more global variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 09:11:46 +00:00
Evan Cheng
14ce175216 Limit load / store issues (at least until we have a true multi-issue aware scheduler).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 01:54:21 +00:00
Bill Wendling
6932643a37 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.


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2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b Add encodings for VCVT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f Add VCMPZ and VABS.
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2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254 Refactor VCMP instructions.
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2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register)
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

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2010-10-12 23:53:58 +00:00
Bill Wendling
5a1fd8cf68 Add encodings for VNMUL[SD].
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2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab Add encodings for VDIV and VMUL.
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2010-10-12 23:22:27 +00:00
Evan Cheng
3f490f3469 Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:19:28 +00:00
Jim Grosbach
2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the
explicit handling of the instructions referencing it from the MC code
emitter.

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2010-10-12 23:18:08 +00:00
Bill Wendling
52061f83e7 Refactor some of the encoding logic into a base class. This keeps us from having
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.


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2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)


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2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6 Split out the "size" field from the encoding. The newer documentation has it as
a separate bit in the coding.


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2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5 Fix thinko in arm fast isel alloca rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6 Encoding for ARM-mode VADD.F32 instruction.
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2010-10-12 21:22:40 +00:00
Eric Christopher
52b45056b2 Combine these together - should probably have some text associated
that says what why what we just asserted is wrong.


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2010-10-12 19:44:17 +00:00
Nick Lewycky
65b65d6ca4 Mark variable 'NoImplicitFloatOps' used only in an assert as used.
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2010-10-12 18:18:03 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding.
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2010-10-12 18:09:12 +00:00
Dan Gohman
320afb8c81 Initial va_arg support for x86-64. Patch by David Meyer!
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2010-10-12 18:00:49 +00:00
Jim Grosbach
8e157302f4 Nuke unused wrapper function.
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2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
d0eeeeb558 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

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2010-10-12 17:15:00 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic
ARM instructions.

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2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


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2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


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2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads.
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2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes.
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2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted
register operand.

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2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43 Second set of ARM/MC/ELF changes.
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)



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2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f Proper VST scheduling itineraries.
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2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b Use a sane mechanism for that assert.
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2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9 We're not going to handle dynamic allocas anywhere else.
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2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e Make sure that the call stack adjustments have default operands. Also
leave custom lowerings for later.

Fixes some nightly tests.


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2010-10-11 21:20:02 +00:00
Jakob Stoklund Olesen
4f9af2ef65 PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

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2010-10-11 20:43:09 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now.
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2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd Fix help text.
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2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6 Change flag from Enable to Disable since we're enabled by default.
Also don't use fast-isel on non-darwin since it's untested.


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2010-10-11 20:05:22 +00:00
Andrew Trick
1a2cf3b4d9 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
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2010-10-11 19:02:04 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand
matching in tblgen to do the predicate operand.



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2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e Turn on arm fast isel by default.
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2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
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2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9 Copy and pasteo.
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2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43 Whitespace cleanup in ARM fast isel.
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2010-10-11 08:38:55 +00:00
Eric Christopher
6a880d6ba8 Add srem libcall support to ARM fast isel.
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2010-10-11 08:37:26 +00:00
Eric Christopher
7bdc4de4e7 Add i8 sdiv support for ARM fast isel.
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2010-10-11 08:31:54 +00:00
Eric Christopher
3bbd396853 Implement select handling for ARM fast-isel.
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2010-10-11 08:27:59 +00:00