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725 Commits

Author SHA1 Message Date
Evan Cheng
4558b807a2 Only adjust esp around calls in presence of alloca. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 00:42:58 +00:00
Chris Lattner
c3dbe70ce7 no email addrs in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 05:56:43 +00:00
Anton Korobeynikov
2365f51ed0 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-14 14:06:15 +00:00
Dale Johannesen
66a2a8f878 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-12 16:45:35 +00:00
Dale Johannesen
5d9c4b6020 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 18:32:38 +00:00
Evan Cheng
8202010364 Didn't mean the last commit. Revert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 22:00:16 +00:00
Evan Cheng
c608ff22e7 Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 21:49:47 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Chris Lattner
87bdba6d6a The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 17:25:29 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
4b9cb7d135 Incorrect check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:23:19 +00:00
Evan Cheng
06aae67b83 Do away with ImmutablePredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:22:46 +00:00
Evan Cheng
dfb2ebac29 Print the s bit if the instruction is toggled to its CPSR setting form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37932 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:01:34 +00:00
Evan Cheng
04c813d00c PredicateDefOperand -> OptionalDefOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:00:49 +00:00
Evan Cheng
148b6a419f Initial ARM JIT support by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 21:15:40 +00:00
Evan Cheng
d54874a06d Unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:13:19 +00:00
Gabor Greif
a99be51bf5 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:07:56 +00:00
Evan Cheng
0e1d37904a Reflects the chanegs made to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:18:20 +00:00
Evan Cheng
16b6598325 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:17:13 +00:00
Evan Cheng
ee568cf794 Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:15:27 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Evan Cheng
3b5b8368f3 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:11:03 +00:00
John Criswell
e644ef7b09 Convert .cvsignore files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 16:35:07 +00:00
Evan Cheng
e2446c6076 Silence a warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37737 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 18:31:22 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Owen Anderson
0819a9d386 Fix the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37705 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 16:59:54 +00:00
Dan Gohman
ea859be53c Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 14:59:07 +00:00
Dale Johannesen
5411835165 Quote complex names for Darwin X86 and ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37700 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 00:54:56 +00:00
Evan Cheng
97e604e7d8 Be more conservative of duplicating blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37669 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 23:55:02 +00:00
Evan Cheng
277f0741c5 Allow predicated immediate ARM to ARM calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 21:05:09 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:26:51 +00:00
Evan Cheng
d42e56e166 Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37606 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-15 21:15:00 +00:00
Dale Johannesen
13e8b51e3e Handle blocks with 2 unconditional branches in AnalyzeBranch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-13 17:59:52 +00:00
Evan Cheng
bfd2ec4a8e Add a utility routine to check for unpredicated terminator instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio
61718a6285 Define AsmTransCBE for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37527 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 21:06:23 +00:00
Evan Cheng
1fc7cb695c Fix ARM condition code subsumission check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37517 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 09:14:47 +00:00
Evan Cheng
f81dea45b5 tBcc is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 09:13:23 +00:00
Evan Cheng
9328c1ac66 Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37484 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-07 01:37:54 +00:00
Evan Cheng
2c614c5c69 Mark these instructions clobbersPred. They modify the condition code register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:17:05 +00:00
Evan Cheng
5e148a37d3 Print predicate of the second instruction of the two-piece constant MI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37437 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-05 18:55:18 +00:00
Evan Cheng
341dcccb4e PIC label asm printing cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37434 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-05 07:36:38 +00:00
Chris Lattner
c621ae7bba update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-02 18:45:14 +00:00
Evan Cheng
c354334ac4 Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 20:51:29 +00:00
Evan Cheng
144fd1ff0f Set ARM ifcvt duplication limit to 3 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 08:28:59 +00:00
Evan Cheng
df4da14948 Make jumptable non-predicable for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 00:56:15 +00:00
Chris Lattner
3a4205367d Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37373 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-31 18:57:45 +00:00
Evan Cheng
c6f2f6fbb9 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:34:19 +00:00
Evan Cheng
fd488edb1d For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:32:06 +00:00
Evan Cheng
62ccdbf0b3 Add missing const qualifiers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 18:42:18 +00:00
Evan Cheng
69d555611a Hooks for predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-23 07:22:05 +00:00
Evan Cheng
94679e66bb Fix some -march=thumb regressions. tBR_JTr is not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37272 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 23:17:32 +00:00
Dale Johannesen
f23b8cf239 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37271 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:42:04 +00:00
Dale Johannesen
86d4069666 Add some patterns for PIC PC-relative loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:14:33 +00:00
Evan Cheng
5a18ebc70c BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 18:56:31 +00:00
Evan Cheng
dcc50a4aee Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:53:54 +00:00
Evan Cheng
e5e7ce458a Silence some compilation warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:19:57 +00:00
Evan Cheng
9f8cbd147c Set ARM if-conversion block size threshold to 10 instructions for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:19:34 +00:00
Evan Cheng
6ae3626a4f RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:18:17 +00:00
Dale Johannesen
8dd86c14d4 More effective breakdown of memcpy into repeated load/store. These are now 
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 21:31:21 +00:00
Evan Cheng
3f8602cf20 ARM::tB is also predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:43 +00:00
Evan Cheng
02c602b333 PredicateInstruction returns true if the operation was successful. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:07 +00:00
Evan Cheng
75604f81b7 Move if-conversion after all passes that may use register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:52:46 +00:00
Evan Cheng
b5f8eff566 Removed isPredicable(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:23 +00:00
Evan Cheng
5ada199246 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:01 +00:00
Evan Cheng
aeafca0a25 Conditional branch is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 07:45:54 +00:00
Evan Cheng
2706f9771d Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37098 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 05:14:06 +00:00
Evan Cheng
9307292ae2 Hooks for predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 02:01:49 +00:00
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Lauro Ramos Venancio
5d3d44a848 Fix previous patch. GOTOFF can be used only when the symbol has internal 
linkage or hidden visibility.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37055 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 23:20:21 +00:00
Lauro Ramos Venancio
930d161ba2 Optimize PIC implementation. GOTOFF can be used when the symbol is defined 
and used in the same module.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37044 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 18:46:23 +00:00
Lauro Ramos Venancio
69642f11ed Enable aliases on arm-linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 18:32:56 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Lauro Ramos Venancio
356e72c4f1 Fix PR1390 in a better way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36916 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 23:15:16 +00:00
Evan Cheng
c4e600362e This is no longer needed after enabling the DAG combiner xform. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36909 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:29:41 +00:00
Lauro Ramos Venancio
8f57667a5d Fix PR1390. 
Don't spill extra register to align the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 23:44:41 +00:00
Lauro Ramos Venancio
a8e9562906 Add a processor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-04 22:16:30 +00:00
Evan Cheng
97c9bb5cc6 On Mac OS X, GV requires an extra load only when relocation-model is non-static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36718 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-04 00:26:58 +00:00
Evan Cheng
bdc9869dbf Should never see an indexed load / store with zero offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36714 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 23:30:36 +00:00
Dale Johannesen
4ac075c859 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 20:54:42 +00:00
Lauro Ramos Venancio
e8e5495474 Debug support for arm-linux. 
Patch by Raul Herbster.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36690 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 20:28:35 +00:00
Chris Lattner
388488d604 add support for printing offset from global 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36669 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 16:42:23 +00:00
Evan Cheng
0b0a9a90a4 Typo. It's checking if V is multiple of 4, not multiple of 3. :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36663 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 02:00:18 +00:00
Devang Patel
1997473cf7 Drop 'const' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 01:11:54 +00:00
Chris Lattner
72939126d4 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 00:32:00 +00:00
Devang Patel
3e15bf33e0 Use 'static const char' instead of 'static const int'. 
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 21:39:20 +00:00
Dale Johannesen
67cf561b7f Add some support for (Darwin) code-generating directives in getInlineAsmLength. 
Support is incomplete, but more accurate than gcc's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36634 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 01:02:40 +00:00
Devang Patel
794fd75c67 Do not use typeinfo to identify pass in pass manager. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 21:15:47 +00:00
Evan Cheng
1b20168433 Doh. PC displacement is between the constantpool and the add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 20:27:19 +00:00
Evan Cheng
97de913821 eliminateFrameIndex() change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 09:13:03 +00:00
Evan Cheng
5c3885ce8e Under normal circumstances, when a frame pointer is not required, we reserve 
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36607 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 00:52:08 +00:00
Dale Johannesen
9118dbc7bd Remove item: thumb padding in constant islands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36586 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 00:32:06 +00:00
Dale Johannesen
23c968478e remove unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36585 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 00:30:48 +00:00
Lauro Ramos Venancio
0a1817392d Enable protected visibility on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36583 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 00:23:51 +00:00
Dale Johannesen
8593e41855 Rewrite of Thumb constant islands handling (exact allowance for padding 
around islands and jump tables).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-29 19:19:30 +00:00
Dale Johannesen
8650199fbb Make ARM-specific version of getInlineAsmLength 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36572 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-29 19:17:45 +00:00
Dale Johannesen
caa8055cf5 change per review 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36519 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-28 00:36:37 +00:00
Dale Johannesen
25c1f9e125 Prevent Thumb code from generating ARM instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36518 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
4c6d20a096 add parenthesis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36514 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 20:10:08 +00:00
Evan Cheng
185ea1e2aa Doh. ARM::LEApcrel is a single instruction MI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36513 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 18:27:13 +00:00
Lauro Ramos Venancio
fdc9692f97 In Thumb mode, the frame register must be R7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36512 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 17:58:03 +00:00
Lauro Ramos Venancio
64f4fa5e0e ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 13:54:47 +00:00
Evan Cheng
b1df8f2750 Darwin runtime library does not have these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36505 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 08:15:43 +00:00
Evan Cheng
768c9f725b Special handling of LEApcrel and tLEApcrel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36504 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 08:14:15 +00:00
Evan Cheng
eec041a037 Back out previous check-in. Incorrect. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36503 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 07:50:02 +00:00
Evan Cheng
33fdc983fd tLEApcrel is a AddrModeTs, i.e. pc relative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36502 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 07:37:22 +00:00
Evan Cheng
faa510726f Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36483 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 19:00:32 +00:00
Evan Cheng
6c087e5585 Match MachineFunction::UsedPhysRegs changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 22:13:27 +00:00
Lauro Ramos Venancio
305b8a5f62 remember to emit weak reference in one more case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36438 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 14:50:40 +00:00
Evan Cheng
1e341729dd Relex assertions to account for additional implicit def / use operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 07:12:14 +00:00
Dale Johannesen
56c42ef3e4 Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining 
BBOffsets and BBSizes when adjusting conditional branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36372 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 20:09:04 +00:00
Dale Johannesen
bd24f3f398 add Align field, and use when generating function alignment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36371 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 20:07:25 +00:00
Dale Johannesen
24fb52da3c add isThumb (unused as yet) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36370 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 20:04:35 +00:00
Lauro Ramos Venancio
0ae4a3357a Implement PIC for arm-linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36324 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-22 00:04:12 +00:00
Evan Cheng
ba647becb9 Specify S registers as D registers' sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:20:10 +00:00
Chris Lattner
93305bc462 add a crazy idea 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36273 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 20:18:43 +00:00
Lauro Ramos Venancio
267bfb553e Fix a bug in getFrameRegister. 
Reported by Raul Herbster.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36262 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-19 14:09:38 +00:00
Chris Lattner
120fba91a3 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36222 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 22:39:58 +00:00
Chris Lattner
3c30d10b04 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36203 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 18:03:00 +00:00
Anton Korobeynikov
bed2946a96 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 18:10:23 +00:00
Chris Lattner
5a3d40d88f arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-13 06:50:55 +00:00
Chris Lattner
e11529438c Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35909 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 16:17:12 +00:00
Chris Lattner
eb13d1b710 restore support for negative strides 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35859 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-10 03:48:29 +00:00
Chris Lattner
37caf8c68e remove dead target hooks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35846 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 23:33:39 +00:00
Chris Lattner
b445d0cbb9 remove some dead target hooks, subsumed by isLegalAddressingMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 22:27:04 +00:00
Evan Cheng
e21e39666e Implement inline asm modifier P. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35640 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-04 00:13:29 +00:00
Evan Cheng
0a7baa24d1 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35639 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-04 00:06:07 +00:00
Evan Cheng
ed884f3a2f Remove unused constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35635 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:39:48 +00:00
Evan Cheng
b03eacdbf3 Fixed a bug that causes codegen of noop like add r0, r0, #0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35627 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 21:31:21 +00:00
Evan Cheng
3c5ad82ba2 Inverted logic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35619 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:44:25 +00:00
Chris Lattner
b2c594f350 Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35609 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 00:13:57 +00:00
Dale Johannesen
d959aa421a fix off by 1 error in displacement computation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35602 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 20:31:06 +00:00
Chris Lattner
6e0784da77 fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35601 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 18:51:18 +00:00
Chris Lattner
c4e3f8e736 add support for the 'w' inline asm register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35598 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 17:24:08 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:30:03 +00:00
Evan Cheng
3074d9df96 Add i16 address mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35551 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 08:06:46 +00:00
Chris Lattner
c9addb7488 implement the new addressing mode description hook. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 23:15:24 +00:00
Evan Cheng
87c6c9abb3 New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35480 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 21:40:13 +00:00
Evan Cheng
5e3c203cfd Can't re-materialize mov r, imm in thumb since mov would clobber the condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35479 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 21:38:31 +00:00
Evan Cheng
616cc663da Add support for hidden visibility to darwin/arm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35448 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 07:49:34 +00:00
Evan Cheng
caaf69107e Remove isLegalAddressImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:53:55 +00:00
Lauro Ramos Venancio
b8a93a45f8 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 16:19:21 +00:00
Evan Cheng
f6fa5ee5c2 findRegisterUseOperand() changed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35366 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 22:41:48 +00:00
Chris Lattner
4234f57fa0 switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:14:49 +00:00
Dale Johannesen
fa4bce2b76 repair x86 performance, dejagnu problems from previous change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 21:51:52 +00:00
Evan Cheng
a125cbe839 Updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35229 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 22:32:39 +00:00
Dale Johannesen
8e59e163db do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio
64c88d741e bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 17:57:23 +00:00
Evan Cheng
c70d1849b7 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35207 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:11:30 +00:00
Evan Cheng
5603dcf21e New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35206 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:10:17 +00:00
Evan Cheng
bf2c8b3c96 Added MRegisterInfo hook to re-materialize an instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:09:38 +00:00
Chris Lattner
1719e13da0 fix indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35202 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 02:25:53 +00:00
Dale Johannesen
80dae195c7 fix obvious comment bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35196 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 00:30:56 +00:00
Evan Cheng
9f6636ff0c Fix naming inconsistencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:48:02 +00:00
Evan Cheng
fa775d09c6 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:20:03 +00:00
Evan Cheng
a251570417 Constant generation instructions are re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:09:02 +00:00
Lauro Ramos Venancio
368f20fda4 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35128 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 22:54:16 +00:00
Evan Cheng
2770747216 Added isLegalAddressExpression(). Only allows X +/- C for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:43:56 +00:00
Evan Cheng
a13fd108f2 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 21:05:54 +00:00
Evan Cheng
961f879ed8 Zero is always a legal AM immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35087 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 20:37:59 +00:00
Evan Cheng
e8308df0b9 Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35077 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 01:20:42 +00:00
Evan Cheng
b01fad6d19 Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:30:29 +00:00
Evan Cheng
1a9da0d66c Minor stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35049 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:46:06 +00:00
Evan Cheng
44f4fca3c0 Add comments about LSR / ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35048 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:35:33 +00:00
Evan Cheng
2265b49193 Unfinished work and ideas related to register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35047 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:34:51 +00:00
Dale Johannesen
818c085232 apply comments from review of last patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35045 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 19:18:59 +00:00
Dale Johannesen
a6bc6fc170 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35044 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 17:58:17 +00:00
Evan Cheng
23a9570494 Implement inline asm modifier c. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35035 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 22:42:46 +00:00
Evan Cheng
b582b1b1fc Fix a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35030 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 21:59:30 +00:00
Evan Cheng
032953d747 Putting more constants which do not contain relocations into .literal{4|8|16} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35026 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 08:31:54 +00:00
Evan Cheng
bf822eb6a3 Change register allocation order to Dale's suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35021 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 02:56:40 +00:00
Evan Cheng
11788fde93 Bug fix. Not advancing the register scavenger iterator correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35020 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 02:55:08 +00:00
Evan Cheng
98ded765c2 For Darwin, put constant data into .const, .const_data, .literal{4|8|16} 
sections.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35017 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 01:25:25 +00:00
Evan Cheng
603b83ebcd Only safe to use a call-clobbered or spilled callee-saved register as scratch register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35010 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 20:30:36 +00:00
Anton Korobeynikov
d0b82b301d Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35008 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 16:25:09 +00:00
Evan Cheng
cb20998b3f ARM always use register scavenger. No longer reserves R12. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34999 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 02:46:23 +00:00
Evan Cheng
0ea12ec848 Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34998 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 02:38:05 +00:00
Evan Cheng
3d06cf4584 Fix one more Thumb eliminateFrameIndex bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34990 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 00:12:18 +00:00
Evan Cheng
e6257632fc Register scavenging is now on by default for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34987 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 22:02:53 +00:00
Evan Cheng
a90f3408b3 Make load / store optimizer use register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34986 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 21:59:20 +00:00
Evan Cheng
cc1c427266 Code clean up. Prepare to use register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34976 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 18:02:41 +00:00
Evan Cheng
140e33cfd1 Scavenge a register using the register scavenger when needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34966 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 10:03:56 +00:00
Anton Korobeynikov
1d9baccc9b Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34963 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 08:12:33 +00:00
Lauro Ramos Venancio
6d7dd8ef46 Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. 
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34931 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-05 17:59:58 +00:00
Dale Johannesen
9f8e50d4ed eliminate unnecessary reset of SP in epilog on darwin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34824 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-02 01:17:17 +00:00
Evan Cheng
c1c2de0ae7 Use a spilled free callee-saved register as scratch register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34785 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 08:57:52 +00:00
Evan Cheng
f49407b790 - Track which callee-saved registers are spilled. 
- Some code clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34783 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 08:26:31 +00:00
Evan Cheng
cda067bad9 Switch from std::vector<bool> to BitVector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34781 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 07:52:44 +00:00
Bill Wendling
f1d6006ad6 Get rid of verboten <iostream> include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34777 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 06:05:39 +00:00
Dale Johannesen
b71aa2b6ca Changes requested in review of last pass. Also pulled isThumb into a 
member, instead of resetting in every function that uses it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34764 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 23:20:38 +00:00
Evan Cheng
ad78ef2154 Doh. ARM::PC is obvious a reserved register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34763 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 23:12:34 +00:00
Dale Johannesen
f1b214d3ca Add intelligence about where to break large blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34755 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 18:41:23 +00:00
Evan Cheng
36230cdda4 Make requiresRegisterScavenging determination on a per MachineFunction basis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:59:19 +00:00
Evan Cheng
41a4d562f7 Temporary: make R12 available in ARM mode if RegScavenger is being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34709 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:22:44 +00:00
Evan Cheng
1b051fc6a4 Start making use of RegScavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34708 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:21:58 +00:00
Evan Cheng
5e6df4647e PEI now passes a RegScavenger ptr to eliminateFrameIndex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:21:17 +00:00
Evan Cheng
15991bf775 Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-27 23:03:55 +00:00
Evan Cheng
5ef9226f30 Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34692 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-27 21:12:35 +00:00
Dale Johannesen
ce74de46dd cosmetic changes from review of last patch. obvious 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34598 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-25 18:31:31 +00:00
Dale Johannesen
598270a68d remove crediting of Evan Cheng and me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34568 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-25 01:42:36 +00:00
Dale Johannesen
99c49a4b94 Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this 
from README.
When no water available, use end of block if in range.  (More to do here.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34563 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-25 00:47:03 +00:00
Lauro Ramos Venancio
acdfa445ac bugfix: SP wasn't updated for varargs when frame pointer was eliminated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34537 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-23 21:53:48 +00:00
Lauro Ramos Venancio
600c383e5c Fix stack alignment in functions with varargs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34532 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-23 20:32:57 +00:00
Dale Johannesen
88e37ae366 rewrite of constant islands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34523 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-23 05:02:36 +00:00
Evan Cheng
04321f70f5 Added -march=thumb; removed -enable-thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34521 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-23 03:14:31 +00:00
Evan Cheng
ead7590581 Add option to turn on register scavenger; By default, spills kills the register being stored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34514 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-23 01:09:11 +00:00
Jim Laskey
2ad9f17fee Simplify lowering and selection of exception ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-22 14:56:36 +00:00
Jim Laskey
62819f3144 Support to provide exception and selector registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-21 22:54:50 +00:00
Evan Cheng
b371f457b0 Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-19 21:49:54 +00:00
Reid Spencer
a284cbf667 For PR1207: 
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-19 03:20:00 +00:00
Evan Cheng
eceada6728 Added getReservedRegs(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-17 11:06:00 +00:00
Chris Lattner
d2b7cec527 Generalize TargetData strings, to support more interesting forms of data. 
Patch by Scott Michel.


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 2007-02-14 05:52:17 +00:00
Lauro Ramos Venancio
7501605988 Add space between // and the comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34246 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-13 20:06:15 +00:00
Lauro Ramos Venancio
3630e78db9 Add ABI information to ARM subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-13 19:52:28 +00:00
Lauro Ramos Venancio
876eaf1135 According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34241 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-13 14:07:13 +00:00
Evan Cheng
e03cff6812 These vectors are frequently large. Use std::vector instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34109 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-09 23:59:14 +00:00
Evan Cheng
c99ef085b9 Add reference counting to constantpool entries. Delete the unused ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34105 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-09 20:54:44 +00:00
Evan Cheng
bd8251a9a6 isLowRegister() expects input is a physical register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34013 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 21:44:33 +00:00
Evan Cheng
403e4a4725 Rename. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34011 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 21:24:09 +00:00
Evan Cheng
5ebd10e5ac If sp offset will be materialized in a register. Clear the offset field of str / ldr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34010 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 21:19:58 +00:00
Evan Cheng
8fdbe560a0 Get rid of references to iostream. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34009 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 21:18:32 +00:00
Evan Cheng
2ef02a220e New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34000 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 09:22:15 +00:00
Evan Cheng
8bed6c968f In thumb mode, R3 is reserved, but it can be live in to the function. If 
that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33999 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 09:17:36 +00:00
Evan Cheng
1f253d6e97 Update 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33998 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 08:37:57 +00:00
Evan Cheng
7142f8755a - If fp (r7) is used to reference stack objects, use [r, r] address mode. 
- If there is a dynamic alloca, in the epilogue, restore the value of sp
  using r7 - offset.
- Other bug fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33997 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 08:37:31 +00:00
Evan Cheng
a01faf4a7a eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33975 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 02:44:23 +00:00
Evan Cheng
8e59ea998f Spill / restore should avoid modifying the condition register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 00:06:56 +00:00
Evan Cheng
8c1a73ad3f Select add FI, c correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-06 09:11:20 +00:00
Evan Cheng
40984d7449 foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33958 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-06 06:13:29 +00:00
Evan Cheng
88b633165a eliminateFrameIndex() bug when frame pointer is used as base register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33945 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-06 00:23:31 +00:00
Evan Cheng
ad0e465889 - Store val, [sp, c] must be selected to tSTRsp. 
- If c does not fit in the offset field, materialize sp + c into a register
  using tADDhirr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33944 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-06 00:22:06 +00:00
Evan Cheng
b38cba928e ARM callseq_end should have a input flag operand so it would be scheduled right after the call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33832 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-03 09:11:58 +00:00
Evan Cheng
fc4034259f Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33831 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-03 08:53:01 +00:00
Evan Cheng
bd5d3dbdbe - Branch max. displacement calculation bug. 
- Add debugging info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33811 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-03 02:08:34 +00:00
Lauro Ramos Venancio
4642ca6589 bugfix: SP isn't resetted when function has FP and there is no spills. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33800 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 23:08:40 +00:00
Evan Cheng
a21335dd76 Another thumb large stack offset codegen bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33795 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 21:08:39 +00:00
Evan Cheng
05cc424082 Use MBB.empty() instead of MBB.size() for speed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33789 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 19:09:19 +00:00
Evan Cheng
1dd6a606ad Watch out for empty BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33788 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 18:49:02 +00:00
Evan Cheng
f48ae3353e Ugh. Only meant to do this in thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33780 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 08:58:48 +00:00
Chris Lattner
2d1222c060 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33778 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 04:36:46 +00:00
Evan Cheng
9a2ef9509e Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33775 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-02 01:53:26 +00:00
Evan Cheng
b0636156ef Thumb does not have clz. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33773 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 23:34:03 +00:00
Lauro Ramos Venancio
c33f674ca3 Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33763 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 21:43:53 +00:00
Evan Cheng
556f33c6e2 Pasto. Lots of it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33762 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 20:44:52 +00:00
Lauro Ramos Venancio
6f46e59d2a Fix .thumb_func directive on linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33759 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 18:25:34 +00:00
Evan Cheng
b43216ee4a - Off by one bugs in maximum displacement calculation / testing. 
- In thumb mode, a new constpool island BB size should be 4 + 2 to
  compensate for the potential padding due to alignment requirement.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33753 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 10:16:15 +00:00
Evan Cheng
e0c2b6b9a8 .set pc relative displacement bug: label should be moved down one instruction 
to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33744 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 03:04:49 +00:00
Evan Cheng
736cefff85 Add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33743 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 02:46:20 +00:00
Evan Cheng
9312313a56 Also set alignment of stack-based structs to 4 in thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33741 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 02:18:36 +00:00
Evan Cheng
9d945f78e5 Special epilogue for vararg functions. We cannot do a pop to pc because 
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33739 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 01:49:46 +00:00