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2941 Commits

Author SHA1 Message Date
Evan Cheng
5f15992b77 Changed my mind. We now allow remat of instructions whose defs have subreg indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76100 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:15:00 +00:00
Evan Cheng
2b48ab947c With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76094 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 18:44:05 +00:00
Anton Korobeynikov
ebfe2b2722 Make xfail proper 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:53:47 +00:00
Anton Korobeynikov
c975180624 Temporary disable 16 bit bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov
6ff3f2c710 Add bswap patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov
54681eca69 Fix logic inversion for RI-mode address selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:31:14 +00:00
Anton Korobeynikov
9419a0d13d Unbreak the test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76051 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:49 +00:00
Anton Korobeynikov
bb8a04806d Expand 32-bit bitconverts via memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:29 +00:00
Anton Korobeynikov
f2fd8ea1c9 Fix incomin arg stack frame offset in case we need to generate stack frame 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:29:57 +00:00
Anton Korobeynikov
5dd38de2c2 Revert the commit, it just hides the real bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov
75eef89ddb Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov
8bd0db7615 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:18:17 +00:00
Anton Korobeynikov
6fe326c713 Implement 'large' PIC model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov
48e8b3cc58 Implement shifts properly (hopefilly - finally!) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov
0a42d2b437 Properly handle divides. As a bonus - implement memory versions of them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov
014d4639d8 32 bit shifts have only 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov
1ed1e3ecd4 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov
720e3b00b8 Add support for 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:09:35 +00:00
Anton Korobeynikov
980d5503c3 Emit proper lowering of load from arg stack slot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:42 +00:00
Anton Korobeynikov
c772c4408e Implement dynamic allocas 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:15 +00:00
Anton Korobeynikov
c16cdc5de7 Add jump tables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:07:50 +00:00
Anton Korobeynikov
759205d1ac Add rotates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:49 +00:00
Anton Korobeynikov
cfca8b1f62 Add patterns for integer negate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:27 +00:00
Anton Korobeynikov
8c993e1632 Provide proper patterns for and with imm instructions. Tune the tests accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:00 +00:00
Anton Korobeynikov
25af73303f Add 32 bit and reg-imm and disable invalid patterns for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:32 +00:00
Anton Korobeynikov
747052c1a5 Add z9 and z10 target processors. Mark z10-only instructions as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:00 +00:00
Anton Korobeynikov
22836d1b31 Proper lower 'small' results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:58:24 +00:00
Anton Korobeynikov
eb68f1c661 Completel forgot about unconditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:52 +00:00
Anton Korobeynikov
bad769f11a Lower addresses of globals 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75960 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:27 +00:00
Anton Korobeynikov
ed1a6d4cad Test (incomplete) for easy muls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75959 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:03 +00:00
Anton Korobeynikov
8d1837d9be Provide "wide" muls and divs/rems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75958 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:56:42 +00:00
Anton Korobeynikov
ecf22d5bdc Tests for cmp / br_cc / select_cc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:53:15 +00:00
Anton Korobeynikov
ef5decab53 Emit callee-saved regs spills / restores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov
ba249e41f3 Some preliminary call lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov
3c98c616c5 Prologue / epilogue emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov
51f613fb2b Add simple frame index elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:25 +00:00
Anton Korobeynikov
81c0325cdf Provide proper test :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75938 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:48:59 +00:00
Anton Korobeynikov
711d5b68e0 Add address computation stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov
c8301d17a8 Add mem-imm stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:14 +00:00
Anton Korobeynikov
961bb6f430 Add stores and truncstores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:45:00 +00:00
Anton Korobeynikov
dc28955b3f Add patterns for various extloads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:44:30 +00:00
Anton Korobeynikov
9e4816e09f Add shifts and reg-imm address matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:43:18 +00:00
Anton Korobeynikov
a51752cbea Add bunch of 32-bit patterns... Uffff :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:42:31 +00:00
Anton Korobeynikov
da308c9a67 Add bunch of reg-imm movs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:34:50 +00:00
Anton Korobeynikov
89edcd0927 Provide masked reg-imm 'or' and 'and' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:57 +00:00
Anton Korobeynikov
c79629536a Fix test running lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:21 +00:00
Anton Korobeynikov
e6220fb230 Add reg-reg and pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:49 +00:00
Anton Korobeynikov
bdc9081693 Add sub reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:16 +00:00
Anton Korobeynikov
b573f99ab7 Add xor reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:31:28 +00:00
Anton Korobeynikov
26ba0b1ec5 Add or reg-reg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:53 +00:00
Anton Korobeynikov
0676d2887a Add add reg-reg and reg-imm patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:15 +00:00
Anton Korobeynikov
1cc9dc7267 Add simple reg-reg and reg-imm moves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:29:38 +00:00
Anton Korobeynikov
87a24e3ee4 Minimal lowering for formal_arguments / ret 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:59 +00:00
Anton Korobeynikov
b24f97dd74 Add testsuite dir for systemz stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:22 +00:00
Richard Osborne
db9e697725 Combine an unaligned store of unaligned load into a memmove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 12:50:48 +00:00
Richard Osborne
ccb7e96ef0 Expand unaligned 32 bit loads from an address which is a constant 
offset from a 32 bit aligned base as follows:

  ldw low, base[offset >> 2]
  ldw high, base[(offset >> 2) + 1]
  shr low_shifted, low, (offset & 0x3) * 8
  shl high_shifted, high, 32 - (offset & 0x3) * 8
  or result, low_shifted, high_shifted

Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662 Custom lower unaligned 32 bit stores and loads into libcalls. This is 
a big code size win since before they were expanding to upto 16
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:21:18 +00:00
Evan Cheng
378445303b Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 09:20:10 +00:00
Evan Cheng
a499effd3b ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill situations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75838 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 21:39:50 +00:00
Richard Osborne
1d05b237a5 Fix pattern for LD16S_3r, add basic tests to check load / store instructions 
are being properly selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 17:06:59 +00:00
Richard Osborne
3af282f16a Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 15:46:56 +00:00
Chris Lattner
4fb63d088b fix an arm codegen bug (the same as PR4482 on ppc) where available_externally 
symbols were not getting stubs.  While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 04:12:33 +00:00
Chris Lattner
392db3e11d get the PPC stub temporary label from the mangler instead of 
using horrible string hacking.  This gives us a different label,
but it's just an assembler temporary, so the name doesn't matter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 02:56:53 +00:00
Chris Lattner
a9aa3523bf convert this to filecheck style and make it a test of darwin/PPC's 
extremely elaborate pic/nopic stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75726 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 01:43:31 +00:00
Chris Lattner
0bc26723c5 simplify this test to test the esentials. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75725 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 01:32:33 +00:00
Chris Lattner
9e3152b381 convert to filecheck style, simplify RUN line, and add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75667 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 19:49:11 +00:00
Chris Lattner
8be6cb5b0f convert this test to filecheck style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75663 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 18:57:40 +00:00
Chris Lattner
b8158acc23 Reapply my previous asmprinter changes now with more testing and two 
additional bug fixes:

1. The bug that everyone hit was a problem in the asmprinter where it
   would remove $stub but keep the L prefix on a name when emitting the
   indirect symbol.  This is easy to fix by keeping the name of the stub
   and the name of the symbol in a StringMap instead of just keeping a
   StringSet and trying to reconstruct it late.

2. There was a problem printing the personality function.  The current
   logic to print out the personality function from the DWARF information
   is a bit of a cesspool right now that duplicates a bunch of other 
   logic in the asm printer.  The short version of it is that it depends
   on emitting both the L and _ prefix for symbols (at least on darwin)
   and until I can untangle it, it is best to switch the mangler back to
   emitting both prefixes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75646 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 18:17:16 +00:00
Daniel Dunbar
41ffe6c7af Revert r75610 (and r75620, which was blocking the revert), in the hopes of 
unbreaking llvm-gcc (on Darwin).

--- Reverse-merging r75620 into '.':
U    include/llvm/Support/Mangler.h
--- Reverse-merging r75610 into '.':
U    test/CodeGen/X86/loop-hoist.ll
G    include/llvm/Support/Mangler.h
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/VMCore/Mangler.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75636 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 15:57:55 +00:00
Chris Lattner
03e9dd9ffa Change the X86 asmprinter to use the mangler to apply suffixes like "$non_lazy_ptr" 
to symbols instead of doing it with "printSuffixedName".  This gets us to the point
where there is a real separation between computing a symbol name and printing it,
something I need for MC printer stuff.

This patch also fixes a corner case bug where unnamed private globals wouldn't get
the private label prefix.

Next up, rename all uses of getValueName -> getMangledName for better greppability,
and then tackle the ppc/arm backends to eliminate "printSuffixedName".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 06:04:35 +00:00
Chris Lattner
1cda87c3a0 Change the internal interface to makeNameProper to take a bool that 
indicates whether the label is private or not, instead of taking
prefix stuff.  One effect of this is that symbols will be generated
with *just* the private prefix, instead of both the private prefix
*and* the user-label-prefix, but this doesn't matter as long as it
is consistent.  For example we'll now get "Lfoo" instead of "L_foo".
These are just assembler temporary labels anyway, so they never even
make it into the .o file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75607 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 04:50:12 +00:00
David Goodwin
c2ffd286af Fix detection of valid BFC immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75576 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:57:56 +00:00
Bill Wendling
91267547f7 Check for the correct unnamed name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75573 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:53:58 +00:00
Dan Gohman
45f91b70c4 Check in a reduced version of this testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75544 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-13 23:04:44 +00:00
Chris Lattner
d4f53b373e Two changes: 
1) unique globals with the existing "Count" local in Mangler, not with
atomic nonsense.  Using atomics will give us nondeterminstic output
from the compiler when using multiple threads, which is bad.

2) Do not mangle an unknown global name with a type suffix.  We don't
   need this anymore now that llvm ir doesn't have type planes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75541 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-13 22:48:46 +00:00
Dan Gohman
08d4ec0b20 Add testcases for PR4538, PR4537, and PR4534. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-13 22:30:31 +00:00
Chris Lattner
4cef7db13f remove tests for removed intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75433 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-12 21:30:06 +00:00
Chris Lattner
0df3b369a5 add nounwind 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-12 00:46:16 +00:00
Nick Lewycky
f5c21ecfa6 Darwin prepends an _ to internal globals, Linux doesn't. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75405 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 23:48:59 +00:00
Chris Lattner
65a7a6f7a3 fix x86-64 static codegen to materialize the address of a global with movl instead 
of lea.  It is better for code size (and presumably efficiency) to use:

  movl $foo, %eax

rather than:

  leal foo, eax

Both give a nice zero extending "move immediate" instruction, the former is just
smaller.  Note that global addresses should be handled different by the x86
backend, but I chose to follow the style already in place and add more fixme's.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75403 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 23:17:29 +00:00
Chris Lattner
8ddb9989e6 this test was incorrect for x86-64 static. It passed on darwin, because darwin 
doesn't have static x86-64 mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75392 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 22:30:05 +00:00
Chris Lattner
4f06649497 Fix PR4533, which is about buggy codegen in x86-64 -static mode. 
Basically, using:
  lea symbol(%rip), %rax

is not valid in -static mode, because the current RIP may not be
within 32-bits of "symbol" when an app is built partially pic and
partially static.  The fix for this is to compile it to:

  lea symbol, %rax

It would be better to codegen this as:

  movq $symbol, %rax

but that will come next.


The hard part of fixing this bug was fixing abi-isel, which was actively
testing for the wrong behavior.  Also, the RUN lines are completely impossible
to understand what they are testing.  To help with this, convert the -static 
x86-64 codegen tests to use filecheck.  This is much more stable and makes it
more clear what the codegen is expected to be.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75382 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 20:29:19 +00:00
Chris Lattner
238f5100c6 We get the P modifier wrong in a lot of cases, just add some more rigorous testing. 
In addition to fixing this, I still need to do some more testing on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 08:30:22 +00:00
Evan Cheng
ed338e80f9 Don't put IT instruction before conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:26:20 +00:00
Evan Cheng
2f297df02e Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:08:13 +00:00
Evan Cheng
446c428bf3 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:43:01 +00:00
Chris Lattner
84232681cc convert test to use FileCheck, which is much more precise and faster than 
the previous RUN lines.  Hopefully this will be an inspiration for future
tests :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75261 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 18:34:47 +00:00
Evan Cheng
06e16587eb Add a thumb2 pass to insert IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 01:54:42 +00:00
Evan Cheng
9c06178e35 Remove a bogus assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 00:23:48 +00:00
Bob Wilson
9b4b00ad43 Handle 'a' modifier on inline assembly operands. 
This is part of the fix for pr4521.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75201 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 23:54:51 +00:00
Eli Friedman
c680ac9003 Make EXTRACT_VECTOR_ELT a bit more flexible in terms of the returned 
value.  Adjust other code to deal with that correctly.  Make 
DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT take advantage of 
this new flexibility to simplify the code and make it deal with unusual 
vectors (like <4 x i1>) correctly.  Fixes PR3037.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75176 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 22:01:03 +00:00
Evan Cheng
910139f9ca Targets sometimes assign fixed stack object to spill certain callee-saved 
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 06:53:48 +00:00
Lang Hames
ffd1326ff8 Improved tracking of value number kills. VN kills are now represented 
as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75097 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 03:57:02 +00:00
Chris Lattner
39f56b6d16 remove eh, convert to FileCheck style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75087 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 01:07:22 +00:00
Chris Lattner
f4a9774e2b we have no tests for dllimport/export. Add one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 00:53:44 +00:00
Chris Lattner
9f44b3a411 * add some assertions for sanity checking. 
* remove some old code that was needed when we'd put ESP in the scale instead of 
  the base of some instructions.
* Fix a bug with the P modifier in inline asm that caused us to drop it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75077 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 00:27:29 +00:00
Chris Lattner
600f175834 add a test for dale's recent change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75074 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 00:00:16 +00:00
Chris Lattner
ab711cc593 switch test to FileCheck-style and test the P and non-P cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75071 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:44:06 +00:00
Chris Lattner
e5646ccf66 rename a test to make it a feature test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75070 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:40:57 +00:00
David Goodwin
f1daf7d8ab Use common code for both ARM and Thumb-2 instruction and register info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:10:31 +00:00
Bob Wilson
2ed334694f Implement NEON vst1 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 20:32:02 +00:00
Chris Lattner
515cdbe49d add some more check for vector compares. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 18:51:25 +00:00
Chris Lattner
57e56cd72a convert a test to "FileCheck" style. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75023 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 18:48:24 +00:00
Bob Wilson
205a5ca6cf Implement NEON vld1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 18:11:30 +00:00
David Goodwin
a928f27d23 Add rev16 test... xfail for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75012 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 16:15:06 +00:00
David Goodwin
334c26473b Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 16:09:28 +00:00
Chris Lattner
a47d9669b7 eliminate the v[if]cmp versions of these tests, now that [if]cmp+sext works. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 00:49:35 +00:00
Chris Lattner
b2773e1ada Change these tests to use [fi]cmp+sext instead of v[fi]cmp. No 
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 00:46:57 +00:00
Chris Lattner
2b7a271c71 dag combine sext(setcc) -> vsetcc before legalize. To make this safe, 
VSETCC must define all bits, which is different than it was documented
to before.  Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the 
documentation.  We now get nice code for vec_compare.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74978 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 00:31:33 +00:00
Chris Lattner
c2c27b3627 add support for legalizing an icmp where the result is illegal (4xi1) but 
the input is legal (4 x i32)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74964 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 23:03:54 +00:00
Chris Lattner
cb178c61e4 add a trivial test that vector compares work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74963 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 22:51:09 +00:00
Chris Lattner
5962ed0a36 implement support for spliting and scalarizing vector setcc's. This 
finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 22:47:46 +00:00
Chris Lattner
33d6a3451b verify that the fcmp version of this works just as well as the 
vfcmp version.  We actually get better code for this silly testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 22:07:47 +00:00
Evan Cheng
e253c951b3 Add Thumb2 movcc instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 20:39:03 +00:00
Evan Cheng
35bd43da76 Add missing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74945 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 20:38:08 +00:00
Evan Cheng
40289b041a Add Thumb2 pkhbt / pkhtb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74895 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 05:35:52 +00:00
Evan Cheng
5b9fcd1c8e Add some more Thumb2 multiplication instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 01:17:28 +00:00
Evan Cheng
36a0aebac2 Add bfc to armv6t2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 22:23:46 +00:00
Evan Cheng
edcbada3d0 Added ARM::mls for armv6t2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 22:05:45 +00:00
Evan Cheng
2c4d96dfe9 Avoid adding a duplicate def. This fixes PR4478. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74857 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 21:34:05 +00:00
Evan Cheng
d27c9fc403 Add thumb2 sign / zero extend with rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-03 01:43:10 +00:00
Evan Cheng
6d94f11196 Added indexed stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-03 00:06:39 +00:00
Evan Cheng
4fbb9960ad Sign extending pre/post indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 23:16:11 +00:00
Evan Cheng
e88d5cee9d Thumb2 pre/post indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 07:28:31 +00:00
Chris Lattner
cd714b12fc @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing. 
This fixes an llvm-gcc bootstrap problem I introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74691 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 04:22:01 +00:00
Chris Lattner
27598ec1e2 Fix yet-another bug I introduced into fastisel, this time handling 
constant pool references that weren't getting properly rip-relative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74689 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 03:14:25 +00:00
Chris Lattner
4fb75e5425 Fix codegen for references to available_externally symbols. This fixes 
PR4482.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74613 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 16:53:44 +00:00
Evan Cheng
498c2903e2 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 08:29:08 +00:00
Evan Cheng
459a7c6b6a Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. 
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 08:19:36 +00:00
Chris Lattner
35c28eca62 Fix some fast-isel problems selecting global variable addressing in 
pic mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 03:27:19 +00:00
Evan Cheng
2578ba26e7 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 01:59:31 +00:00
David Goodwin
d1fa120aee Add PIC load and store patterns for Thumb-2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 00:01:13 +00:00
David Goodwin
73b8f16b36 Add thumb-2 store word, halfword, and byte. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 22:11:34 +00:00
David Goodwin
c9a59b5960 Improve Thumb-2 jump table support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 19:50:22 +00:00
Rafael Espindola
af5f6ba32d Fix PR4485. 
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74534 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 16:40:03 +00:00
Rafael Espindola
f55715c5c7 Fix PR4484. 
This was caused by me confounding FP0 and ST(0).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74523 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 12:18:16 +00:00
Evan Cheng
50564ebc9e Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 09:19:42 +00:00
Evan Cheng
4784f1fc73 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. 
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 08:49:04 +00:00
Evan Cheng
f3c21b857b A few more load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 02:15:48 +00:00
David Goodwin
4ff863c257 Enhance tests to include shifted-register operand testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74490 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 01:02:20 +00:00
David Goodwin
baeb911d60 Add Thumb-2 support for TEQ amd TST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 22:49:42 +00:00
David Goodwin
8ba221d5c5 Thumb-2 tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74464 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 22:25:22 +00:00
Rafael Espindola
63de5c3b7e FIX PR 4459. 
Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74446 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 20:29:59 +00:00
David Goodwin
c0309b48b5 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 15:33:01 +00:00
Evan Cheng
055b0310f8 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 07:51:04 +00:00
Chris Lattner
74d3f50a80 factor some logic out into a helper function, allow remat of loads from constant 
globals.  This implements remat-constant.ll even without aggressive-remat.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74373 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-27 04:38:55 +00:00
Chris Lattner
18c5987fa3 Reimplement rip-relative addressing in the X86-64 backend. The new 
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-27 04:16:01 +00:00
Chris Lattner
600d006cc7 remove some unneeded eh info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74371 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-27 04:07:31 +00:00
Chris Lattner
18eed20051 testcase for PR4466 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74367 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-27 01:33:35 +00:00
David Goodwin
dcdaebc592 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 23:13:13 +00:00
Dan Gohman
16bdfdb178 Add some testcases for some of the recent ScalarEvolution bug fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74353 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:54:11 +00:00
David Goodwin
7f98cac93a Thumb-2 tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74345 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:37:07 +00:00
Chris Lattner
93677c99a4 remove unwind info, add test for asmprinting of jump table labels with (%rip) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74337 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:16:49 +00:00
Evan Cheng
2c2fb823b9 Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:00:19 +00:00
David Goodwin
24062ac5be Thumb-2 has CLZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74322 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 20:47:43 +00:00
David Goodwin
7ce720b448 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 20:45:56 +00:00
Daniel Dunbar
d2deed0091 More spelling Count as count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74306 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:35:07 +00:00
Daniel Dunbar
039c43dccc Spell Count as count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74298 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:21:54 +00:00
David Goodwin
2634e98a93 Add Thumb-2 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74295 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:10:30 +00:00
David Goodwin
93d95bd2c3 ADC used to implement adde should use "adcs" opcode instead of "adc". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74293 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:07:25 +00:00
David Goodwin
caffbd7b01 ORN and BIC tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74289 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 16:20:06 +00:00
David Goodwin
83b3593478 Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. 
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74288 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 16:10:07 +00:00
Evan Cheng
6677f51127 Fix tests: Count -> count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74282 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 07:05:57 +00:00
Evan Cheng
c0ad80fd9e Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74276 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 05:59:16 +00:00
Daniel Dunbar
12cccf10a7 Fix spelling of 'count' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 01:33:02 +00:00
Evan Cheng
6267422318 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 23:34:10 +00:00
David Goodwin
0919a916bf Use MVN for ~t2_so_imm immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74223 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 23:11:21 +00:00
Bill Wendling
06b76b834f Don't grep the -debug output. This isn't the way to test changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74211 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 21:59:32 +00:00
Chris Lattner
5f04d1e522 down with unwind info :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 21:48:17 +00:00
Evan Cheng
1e249e3705 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 20:59:23 +00:00
Evan Cheng
a09b9ca10f Add Thumb2 pc relative add. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 23:47:58 +00:00
Evan Cheng
2e1af3529b We should run these tests as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74121 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 21:36:26 +00:00
Chris Lattner
7556bfd6af unwind info not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74112 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 19:48:04 +00:00
Evan Cheng
9f76ed5127 Move thumb and thumb2 tests into separate directories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 06:36:07 +00:00
Evan Cheng
ef5d070bbe Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74053 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 02:05:51 +00:00
Dan Gohman
40a5a1b39e Extend ScalarEvolution's multiple-exit support to compute exact 
trip counts in more cases.

Generalize ScalarEvolution's isLoopGuardedByCond code to recognize
And and Or conditions, splitting the code out into an
isNecessaryCond helper function so that it can evaluate Ands and Ors
recursively, and make SCEVExpander be much more aggressive about
hoisting instructions out of loops.

test/CodeGen/X86/pr3495.ll has an additional instruction now, but
it appears to be due to an arbitrary register allocation difference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 01:18:18 +00:00
Evan Cheng
a67efd1226 Proper patterns for thumb2 shift and rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 19:39:13 +00:00
Bob Wilson
5bafff36c7 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 23:27:02 +00:00
Evan Cheng
524961e57f It's coalescer, not coaleser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:09:17 +00:00
Bob Wilson
54fc124d72 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:01:46 +00:00
Evan Cheng
81909b7423 Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 20:49:32 +00:00
Evan Cheng
8dcbbdd00e hasFP should return true if frame address is taken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 18:38:48 +00:00
Rafael Espindola
1c3329f707 Fix PR4185. 
Handle FpSET_ST0_80 being used when ST0 is still alive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-21 12:02:51 +00:00
Chris Lattner
5c0b16d0c4 change TLS_ADDR lowering to lower to a real mem operand, instead of matching as 
a global with that gets printed with the :mem modifier.  All operands to lea's 
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this.  There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).

This also makes the use of EBX explicit in the operand list in the 32-bit, 
instead of implicit in the instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73834 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 20:38:48 +00:00
Chris Lattner
6bfb669f82 no need for unwind info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73832 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 19:48:26 +00:00
Chris Lattner
811ac0b088 no need for unwind info here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 19:43:09 +00:00
Evan Cheng
694f6c81e8 Fix PR4419: handle defs of partial uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73816 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 04:34:51 +00:00
Dan Gohman
2781f30eac Re-apply r73718, now that the fix in r73787 is in, and add a 
hand-crafted testcase which demonstrates the bug that was exposed
in 254.gap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73793 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 23:23:27 +00:00
Evan Cheng
ae69a2a12b Enable arm pre-allocation load / store multiple optimization pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 23:17:27 +00:00
Evan Cheng
73a76736fb Revert 73718. It's breaking 254.gap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73783 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 21:15:06 +00:00
Eli Friedman
7e2242be71 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to 
handle with an SSE2 instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73760 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 07:00:55 +00:00
Eli Friedman
6b7bb42c36 Mark a few Thumb instructions commutable; just happened to spot this 
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 01:43:08 +00:00
Evan Cheng
b13bafe5c1 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 20:37:15 +00:00
Dan Gohman
4658c9b4ea Generalize LSR's OptimizeSMax to handle unsigned max tests as well 
as signed max tests. Along with r73717, this helps CodeGen avoid
emitting code for a maximum operation for this class of loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73718 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 20:23:18 +00:00
Dan Gohman
4e8a98519e Remove the code from IVUsers that attempted to handle 
casted induction variables in cases where the cast
isn't foldable. It ended up being a pessimization in
many cases. This could be fixed, but it would require
a bunch of complicated code in IVUsers' clients. The
advantages of this approach aren't visible enough to
justify it at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73706 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 16:54:06 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
a4e968cb0e Make the test target-neutral 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73547 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 20:25:25 +00:00
Anton Korobeynikov
2932795309 GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 18:49:08 +00:00
Evan Cheng
67fcf56ac4 If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. 
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 07:12:58 +00:00
Eli Friedman
db3c169f3a Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 
support for x86, and UMULO/SMULO for many architectures, including PPC 
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73477 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 06:58:29 +00:00