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Author SHA1 Message Date
Bill Wendling
bc4224bc6b Reapply r121808 now that the missing patterns have been supplied. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:03:19 +00:00
Bill Wendling
415af3452e Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:58:57 +00:00
Bill Wendling
7d1d8db54a Revert r121808 until I can fix the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:04:00 +00:00
Jim Grosbach
9d04dc52a5 thumb adr fixup needs alignment just like the t2 version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:47:35 +00:00
Bill Wendling
345cdb6475 Comments and cleaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:42:48 +00:00
Bill Wendling
2af0fd3fee Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In 
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:40:49 +00:00
Jim Grosbach
d40963c406 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:28:03 +00:00
Bill Wendling
ee2b350d83 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:26:49 +00:00
Bill Wendling
b6faf65215 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:10:49 +00:00
Jim Grosbach
8d6d7d6e30 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:28:29 +00:00
Jim Grosbach
40edf73a62 Refactor a bit for legibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:10:47 +00:00
Jim Grosbach
00f25fa43e trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 20:46:39 +00:00
Jim Grosbach
eb61272150 Make sure to propagate the predicate operands for LEApcrel to ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 20:45:47 +00:00
Owen Anderson
86abd48fd0 Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 19:42:53 +00:00
Jakob Stoklund Olesen
414e5023f8 Add TargetRegisterInfo::printReg() to pretty-print registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 18:53:39 +00:00
Daniel Dunbar
abfbac52df MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 17:37:16 +00:00
Jim Grosbach
e8eb1ea6ac Trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 16:25:15 +00:00
Bill Wendling
971321bb70 Use the integer scheduling intrinsic for integer loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 12:33:05 +00:00
Bill Wendling
f4caf69720 The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 03:36:38 +00:00
Evan Cheng
0c1aec1891 bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 03:22:07 +00:00
Owen Anderson
a838a25d59 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 00:36:49 +00:00
Bob Wilson
4711d5cda3 Remove the rest of the *_sfp Neon instruction patterns. 
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 23:02:37 +00:00
Bob Wilson
0e6d540d17 Simplify N2VSPat, removing some unnecessary type arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 23:02:31 +00:00
Owen Anderson
6b8719fd7d Revert r121721, which broke buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 22:51:08 +00:00
Owen Anderson
e8d02539d7 Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR, 
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 22:29:52 +00:00
Bob Wilson
4dedddce93 Delete a line that I forgot to revert previously. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121719 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 22:05:55 +00:00
Bob Wilson
1e6f59608b Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns. 
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 21:58:05 +00:00
Bob Wilson
3a6756cb1c Use pseudo instructions for 2-register Neon instructions for scalar FP. 
Partial fix for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 21:05:52 +00:00
Bob Wilson
6dbcea1f8e Remove unused instruction class arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 21:05:44 +00:00
Evan Cheng
30fb13f97a Generalize BFI isel lowering a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 20:32:54 +00:00
Owen Anderson
c266600bec In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or 
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 19:31:11 +00:00
Jim Grosbach
56a2535474 Use 32-bit types for 32-bit values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 19:25:46 +00:00
Jim Grosbach
7e294cfcf9 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121708 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 19:18:13 +00:00
Evan Cheng
de7f920835 Disable auto-detection of AVX support since AVX codegen support is not ready. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 04:23:53 +00:00
Chris Lattner
a97c91f014 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 00:15:25 +00:00
Wesley Peck
638f7a9a5e Missed some ADDI <-> ADDIK conversions in 121649. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-12 22:53:14 +00:00
Wesley Peck
8f40b24ca1 MBlaze delay slot filler was not capable of using ADDK and variants to fill delay slots. This broke several test cases when 121649 was committed. This fixes the regression. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-12 22:22:49 +00:00
Wesley Peck
a7c7b9dccb The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121649 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-12 22:02:31 +00:00
Wesley Peck
eb13382333 1. Change MBlaze indirect branches to use absolute branch BRALD instead of pc relative branch BRLD. 
2. Make sure that the MBlaze stack is aligned to 4-byte boundaries.
3. Determine frame indexes that should be placed in the callers stack frame, as per the MBlaze ABI, and place them in the correct locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121639 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-12 20:52:31 +00:00
Benjamin Kramer
2f7228b80c Generalize the and-icmp-select instcombine further by allowing selects of the form 
(x & 2^n) ? 2^m+C : C

we can offset both arms by C to get the "(x & 2^n) ? 2^m : 0" form, optimize the
select to a shift and apply the offset afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-11 10:49:22 +00:00
Benjamin Kramer
20e3b4b380 Factor the (x & 2^n) ? 2^m : 0 instcombine into its own method and generalize it 
to catch cases where n != m with a shift.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-11 09:42:59 +00:00
Evan Cheng
a9688c4b57 (or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-11 04:11:38 +00:00
Jim Grosbach
092e2cd569 Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 23:41:10 +00:00
Owen Anderson
63ee22065d Attempt to get Thumb2 branch fixups working properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 23:02:28 +00:00
Owen Anderson
5fd873d8e8 Fix merge error in my last fix to Thumb2 vldr fixups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:53:48 +00:00
Owen Anderson
e2e0f58809 Fixups for Thumb2 vldr's need to have the effective PC aligned as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:46:47 +00:00
Bill Wendling
1591b293d6 The MCFixupKindInfo table needs to be in the order that the enums were 
declared. Add a note specifying this and spruce up the list a bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:37:19 +00:00
Owen Anderson
ac00e96273 Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:32:08 +00:00
Bob Wilson
746fa17d59 Add float patterns for Neon vld1-lane/dup and vst1-lane operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:13:32 +00:00
Bob Wilson
20d5515aa5 Remove unused arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:13:24 +00:00
Owen Anderson
0f4b60d43a Fix encoding of Thumb1 LDRB and STRB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 22:11:13 +00:00
Jim Grosbach
7bf4c02789 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 21:57:34 +00:00
Owen Anderson
808c7d1482 Fix Thumb2 encodings of STREX and LDREX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121579 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 21:52:38 +00:00
Jim Grosbach
0be099da79 Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121525 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 21:24:18 +00:00
Jim Grosbach
90cc533fda Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 21:05:07 +00:00
Jim Grosbach
683fc3e9af More trivial cleanup. No need to define the EncoderMethod property type. Can 
just assign to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121523 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 20:53:44 +00:00
Jim Grosbach
04da9bf9f1 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121522 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 20:51:35 +00:00
Jim Grosbach
a79bd0e1e0 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121521 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 20:47:29 +00:00
Bob Wilson
a92bac64cb Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. 
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed.  Add tests for this, too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 19:37:42 +00:00
Jim Grosbach
568f528c99 Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR 
instructions to restore a single register rather than an LDM instruction.
rdar://8754999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121498 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 18:41:15 +00:00
Jim Grosbach
e246717c3a Thumb unconditional branch binary encoding. rdar://8754994 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 18:21:33 +00:00
Jim Grosbach
0108645139 Thumb conditional branch binary encodings. rdar://8745367 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 17:13:40 +00:00
Rafael Espindola
89b9372605 Fixed version of 121434 with no new memory leaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 07:39:47 +00:00
Rafael Espindola
eda4a530c9 Fix cmake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 04:28:37 +00:00
Rafael Espindola
f7fd4aa261 Revert my previous patch to make the valgrind bots happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 04:01:09 +00:00
NAKAMURA Takumi
8070812f4c lib/Target/CMakeLists.txt: Add missing lib/Target/TargetAsmInfo.cpp, following up to r121434. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 02:15:24 +00:00
Kevin Enderby
44a9e8f869 Fix the leak from r121401 of the Operands erased in the list but not deleted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 01:41:56 +00:00
Nate Begeman
d191751f0e Add some missing predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121445 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 00:54:26 +00:00
Nate Begeman
2ea8ee7c76 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 00:26:57 +00:00
Rafael Espindola
1c952b9cc9 Initial support for the cfi directives. This is just enough to get 
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 23:48:29 +00:00
Bill Wendling
272df516d7 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 21:49:07 +00:00
Nate Begeman
3c49706a61 Add support for AVX to materialize +0.0 when doing scalar FP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 21:43:51 +00:00
Owen Anderson
fe7fac74b4 Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect, 
but it gets many more of them correct than it did previously.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 21:34:47 +00:00
Owen Anderson
05018c2f28 Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating 
the offset.  Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this.  It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 20:27:52 +00:00
Jim Grosbach
b492a7c213 Rename CB/CBZ specific fixup accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 19:50:12 +00:00
Kevin Enderby
193c3acbe5 Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 19:19:43 +00:00
Jim Grosbach
027d6e8d1c Rename the encoder method for t_cbtarget to match. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 19:04:53 +00:00
Jim Grosbach
cf6220a9de Thumb needs a few different encoding schemes for branch targets. Rename 
t_brtarget to be more specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121398 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 19:01:46 +00:00
Jim Grosbach
c6f9261711 ARM stm/ldm instructions require more than one register in the register list. 
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 18:31:13 +00:00
Bruno Cardoso Lopes
908b6ddad6 Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 17:32:30 +00:00
Bruno Cardoso Lopes
90c595425b Fix delay slot filler for non mips1 targets. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 17:31:11 +00:00
Kalle Raiskila
7d17097e4a Dont' feed ILA two inputs - it takes just one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 16:17:31 +00:00
Jim Grosbach
bfd0daa6a6 tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 16:15:41 +00:00
Jim Grosbach
2a4f0986ac 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 16:14:46 +00:00
Eric Christopher
d8c0536651 Rewrite the darwin tlv support to use a chain and return to copying 
the output to the correct register. Fixes a hidden problem uncovered
by the last patch where we'd try to DAG combine our MVT::Other node
oddly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 06:25:53 +00:00
Wesley Peck
8397be0427 Reworking the stack layout generated by the MBlaze backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 03:42:04 +00:00
Owen Anderson
6b0fa635d5 Fix encoding of the immediate operands on post-indexed LDR and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 02:56:12 +00:00
Eric Christopher
1a48c032bd Fix up some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121351 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:57:45 +00:00
Owen Anderson
d7b3f5870d Fix Thumb2 fixups for ldr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:51:07 +00:00
Jim Grosbach
766a63d20e Add a textual message to the assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:23:51 +00:00
Jim Grosbach
9702e6075c Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are 
referencing the stack pointer as they say they are.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:22:19 +00:00
Jim Grosbach
cde31293d4 When using multiple instructions to reference a frame index, make sure to 
update the opcode when necessary as well as the source register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121346 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:22:13 +00:00
Jim Grosbach
a0e23c5e95 The add/sub SP instructions are really pseudos. The assembler should ignore 
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121345 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:21:27 +00:00
Matt Beaumont-Gay
0a29c270b5 Remove unused variables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:04:43 +00:00
Owen Anderson
8f07943317 Fix typo in Thumb2 branch fixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 01:02:09 +00:00
Eric Christopher
2040961f89 Stop confusing people, it's not really a chain, or a tumor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:57:19 +00:00
Bill Wendling
2fe813af23 Remove extraneous semicolon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:51:54 +00:00
Bill Wendling
797b7aab35 Attempt to make the bit-twiddling readable resulted in the binary value being 
overwritten.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121337 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:44:33 +00:00
Bill Wendling
09aa3f0ef3 The BLX instruction is encoded differently than the BL, because why not? In 
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:39:08 +00:00
Eric Christopher
8bce7cc3bf Remove extraneous copy from DAG conversion for darwin tls. This was 
popping up at O0 when it wasn't folded and the fast allocator would
complain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121330 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:27:58 +00:00
Owen Anderson
fb20d89075 Fix Thumb2 BCC encoding and fixups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121329 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:27:41 +00:00
Eric Christopher
2871768f40 Add rsp to the uses for the same reason as 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121328 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:26:41 +00:00
Kevin Enderby
76331754d4 Allow a slash, '/', as a prefix separator for X86. rdar://8741045 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:57:59 +00:00
Jason W Kim
045869c12a Style nit and whitespace cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:35:25 +00:00
Jim Grosbach
60fc2ed2bb Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME 
for more thorough cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121315 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:30:19 +00:00
Jim Grosbach
20e0fa698d Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:24:29 +00:00
Jason W Kim
0062db8b4f Removed dead comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:19:44 +00:00
Jason W Kim
a0871e7927 ARM/MC/ELF TPsoft is now a proper pseudo inst. 
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:14:44 +00:00
Jim Grosbach
7685ff84ad T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:13:01 +00:00
Jim Grosbach
37474e6d68 Add operand encoding for Thumb2 subw SP + imm. rdar://8745434 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:12:09 +00:00
Jim Grosbach
07e9b26371 Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:04:16 +00:00
Bill Wendling
dff2f7151f Support the "target" encodings for the CB[N]Z instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:01:43 +00:00
Evan Cheng
5d9e016025 Fix an obvious cut-n-paste error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:01:18 +00:00
Jim Grosbach
b76dfe06d9 Add operand encoding for Thumb2 addw SP + imm. rdar://8745434 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121305 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 22:50:19 +00:00
Jim Grosbach
7c6d85a981 Parameterize opcode encoding bits for Thumb2 extended precision integer 
multiply instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121301 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 22:38:41 +00:00
Jim Grosbach
5208204899 Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121297 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 22:29:28 +00:00
Jim Grosbach
8638692362 Simplify T2 operand assignment notation a bit. No need to specify a bit range 
for the source field when it's the whole thing that's being referenced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 22:10:43 +00:00
Jim Grosbach
0c2c217244 Tweak ARM fixup value adjustments for Thumb to better handle the half-word 
ordering of thumb mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 20:32:07 +00:00
Andrew Trick
6b1207267f Generalize PostRAHazardRecognizer so it can be used in any pass for 
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 20:04:29 +00:00
Owen Anderson
cc78f5c09c Improve comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 19:31:11 +00:00
Jim Grosbach
022ab3779c Add initializer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 15:36:45 +00:00
Evan Cheng
275bf63115 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 06:29:02 +00:00
Bill Wendling
b8958b031e Add support for loading from a constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 01:57:09 +00:00
Jim Grosbach
5be6d2af38 Let target asm backends see assembler flags as they go by. Use that to handle 
thumb vs. arm mode differences in WriteNopData().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 01:16:55 +00:00
Owen Anderson
255eafbd49 Simplify the byte reordering logic slightly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 00:21:33 +00:00
Owen Anderson
d8e351b96f VLDR fixups need special handling under Thumb. While the encoding is the same, 
the order of the bytes in the data stream is flipped around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay
2bf315f087 Fix a warning about a variable which is only used in an assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:26:21 +00:00
Bill Wendling
d832fa053b Cleanup in the Darwin end. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:11:00 +00:00
Evan Cheng
06d65f5156 Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal 
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}

vpush and vpop do not allow gaps in the register list.
rdar://8728956


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:08:38 +00:00
Bill Wendling
52e635ea35 A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No 
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:05:20 +00:00
Jim Grosbach
d967cd096a Binary encoding for ARM tLDRspi and tSTRspi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 21:50:47 +00:00
Owen Anderson
bdf714450b Fix Thumb2 encoding of the S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:50:15 +00:00
Jim Grosbach
97a884d602 Refactor the ARM CMPz* patterns to just use the normal CMP instructions when 
possible. They were duplicates for everything exception the source pattern
before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:41:06 +00:00
Evan Cheng
52f21e35e8 Code clean up; no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:11:46 +00:00
Evan Cheng
9801b5c822 Code clean up; no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:59:34 +00:00
Bruno Cardoso Lopes
bd3af09cef Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:04:14 +00:00
Bruno Cardoso Lopes
ab8d53a56a Match a pattern generated by a dag combiner opt where: 
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:00:20 +00:00
Jim Grosbach
5169220624 Encode the literal field for tCMPzi instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121153 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 17:48:24 +00:00
Benjamin Kramer
6aa4943599 Add parens to pacify gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 15:50:35 +00:00
Jay Foad
40f8f6264d PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and 
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 08:25:19 +00:00
NAKAMURA Takumi
63fbb52163 lib/Target/X86/X86MCAsmInfo.cpp: [PR8741] On Win64, specify explicit PrivateGlobalPrefix as ".L". 
Or, global symbols @Lxxxx might be treated as temporal symbol by MCSymbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121103 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 02:43:45 +00:00
Owen Anderson
eb6779c5b9 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 00:45:21 +00:00
Jim Grosbach
662a816e89 Add fixup for Thumb1 BL/BLX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 23:57:07 +00:00
Wesley Peck
a3b2200472 Adding bug fix that was suppose to be part of 121044. 
patch contributed by Jack Whitham!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 22:19:28 +00:00
Wesley Peck
dc80380de8 Fixed reversed operands for IDIV and CMP instructions in MBlaze backend. 
Use BRAD instead of BRD for indirect branches in MBlaze backend.

patch contributed by Jack Whitham!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121044 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 22:06:49 +00:00
Wesley Peck
1e8cdd599c Fix a 16-bit immediate value detection bug in the MBlaze delay slot filler. 
Address more hazards in the MBlaze delay slot filler.

patch contributed by Jack Whitham!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121037 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 21:11:01 +00:00
Rafael Espindola
179821ac1f Remove the instruction fragment to data fragment lowering since it was causing 
freed data to be read. I will open a bug to track it being reenabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 19:08:48 +00:00
Owen Anderson
c76c59840b Revert r121021, which broke the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:57:40 +00:00
Jim Grosbach
ba3368ceae Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:47:44 +00:00
Owen Anderson
4c386fc754 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:35:51 +00:00
Jim Grosbach
04f74942f2 Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if 
the instruction is predicated, reg0 otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:30:57 +00:00
Jim Grosbach
d67641b6f8 The ARM AsmMatcher needs to know that the CCOut operand is a register value, 
not an immediate. It stores either ARM::CPSR or reg0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:21:12 +00:00
Rafael Espindola
0bbe0b440e Second try at making direct object emission produce the same results 
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 17:27:56 +00:00
Che-Liang Chiou
f964486771 ptx: add shift instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 04:00:03 +00:00
Evan Cheng
04e2b639c1 Eliminate unneeded #include's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120971 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
714e07f75d ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120966 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:08:57 +00:00
Evan Cheng
167be80ee7 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:03:45 +00:00
Evan Cheng
f79ed109ec Remove an unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:03:35 +00:00
Evan Cheng
48575f6ea7 Making use of VFP / NEON floating point multiply-accumulate / subtraction is 
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 22:04:16 +00:00
Chris Lattner
9637d5b22e Teach X86ISelLowering that the second result of X86ISD::UMUL is a flags 
result.  This allows us to compile:

void *test12(long count) {
      return new int[count];
}

into:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	movq	$-1, %rdi
	cmovnoq	%rax, %rdi
	jmp	__Znam                  ## TAILCALL

instead of:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	seto	%cl
	testb	%cl, %cl
	movq	$-1, %rdi
	cmoveq	%rax, %rdi
	jmp	__Znam

Of course it would be even better if the regalloc inverted the cmov to 'cmovoq',
which would eliminate the need for the 'movq %rdi, %rax'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 07:49:54 +00:00
Chris Lattner
b20e0b1fdd it turns out that when ".with.overflow" intrinsics were added to the X86 
backend that they were all implemented except umul.  This one fell back
to the default implementation that did a hi/lo multiply and compared the
top.  Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test.  Now we compile:

void *func(long count) {
      return new int[count];
}

into:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	seto	%cl                     ## encoding: [0x0f,0x90,0xc1]
	testb	%cl, %cl                ## encoding: [0x84,0xc9]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

instead of:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 07:30:36 +00:00
Chris Lattner
96908b17ae generalize the previous check to handle -1 on either side of the 
select, inserting a not to compensate.  Add a missing isZero check
that I lost somehow.

This improves codegen of:

void *func(long count) {
      return new int[count];
}

from:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]

to:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	cmpq	$1, %rdx                ## encoding: [0x48,0x83,0xfa,0x01]
	sbbq	%rdi, %rdi              ## encoding: [0x48,0x19,0xff]
	notq	%rdi                    ## encoding: [0x48,0xf7,0xd7]
	orq	%rax, %rdi              ## encoding: [0x48,0x09,0xc7]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 02:00:51 +00:00
Chris Lattner
a2b5600e61 Improve an integer select optimization in two ways: 
1. generalize 
    (select (x == 0), -1, 0) -> (sign_bit (x - 1))
to:
    (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y

2. Handle the identical pattern that happens with !=:
   (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y

cmov is often high latency and can't fold immediates or
memory operands.  For example for (x == 0) ? -1 : 1, before 
we got:

< 	testb	%sil, %sil
< 	movl	$-1, %ecx
< 	movl	$1, %eax
< 	cmovel	%ecx, %eax

now we get:

> 	cmpb	$1, %sil
> 	sbbl	%eax, %eax
> 	orl	$1, %eax




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 01:23:24 +00:00
Bill Wendling
d643486058 Initialize HasPOPCNT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 23:57:24 +00:00
Benjamin Kramer
1292c22645 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 20:32:23 +00:00
Benjamin Kramer
983839609f Simplify code. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 14:22:24 +00:00
Bob Wilson
c24130bade The Thumb tADDrSPi instruction is not valid when the destination is SP. 
Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 04:40:19 +00:00
Rafael Espindola
5d4918dbd1 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 03:21:47 +00:00
Jim Grosbach
ceab50198e Encode condition code for Thumb1 conditional branch instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 00:20:40 +00:00
Jim Grosbach
ed09087dd3 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:54:18 +00:00
Bill Wendling
fb62d550de Use correct variable names to match the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:44:24 +00:00
Jim Grosbach
1b555d9f96 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:21:25 +00:00
Jim Grosbach
4fa102b84e Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:33:42 +00:00
Jim Grosbach
d91f4e40e6 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:31:40 +00:00
Nate Begeman
5812b10adb Revert this change since it breaks a couple of the AVX tests. 
I'm unclear if the tests are actually correct or not, but reverting for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120847 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:29:15 +00:00
Nate Begeman
07c21d85b4 Scalar f32/f64 are also subregs of ymm regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 21:54:39 +00:00
Nate Begeman
163e83d69a Remove SSE1-4 disable when AVX is enabled. While this may be useful for development, 
it completely breaks scalar fp in xmm regs when AVX is enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 21:54:14 +00:00
Jim Grosbach
41ad0c4c73 When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 20:33:01 +00:00
Benjamin Kramer
b3a04d46e8 Remove unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:55:37 +00:00
Jim Grosbach
6e57298127 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:47:11 +00:00
Jason W Kim
2ccf148fba fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120832 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:40:23 +00:00
Jim Grosbach
0b951ceb02 No need to declare EncoderMethod property anymore; just assign to it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:31:00 +00:00
Jim Grosbach
d253545c17 Add FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 18:37:17 +00:00
Jim Grosbach
2c971ab9d9 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 18:31:03 +00:00
Bill Wendling
278b6e81c8 Don't overwrite the opcode passed into the T1Special pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 02:02:58 +00:00
Bill Wendling
534a5e4305 Add Thumb encoding for some more instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 01:55:47 +00:00
Rafael Espindola
32a006e606 Try to resolve symbol differences early, and if successful create a plain 
data fragment. This reduces the time to assemble the test in 8711 from 60s to
54s.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 00:55:40 +00:00
Bill Wendling
0bdf0c05b9 The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 00:53:22 +00:00
Jim Grosbach
7721e7f279 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 23:05:38 +00:00
Devang Patel
ee4854faf3 Use set directive for StartMinusEndExpr. 
This is a fix for llvm-gcc-i386-darwin9 buildbot failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 21:32:30 +00:00
Jim Grosbach
1ab4b211ea When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 16:42:25 +00:00
Jim Grosbach
ce4fadf884 Fix copy/pasto in vmin.f32 encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 16:30:58 +00:00
Wesley Peck
2e06398405 Teaching MBlaze backend how to reverse branch conditions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 16:17:11 +00:00
Jim Grosbach
dff84b0325 Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 00:28:45 +00:00
Devang Patel
0be938e389 Revert r120580. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-02 00:22:29 +00:00
Evan Cheng
1bf891ae6e Fix and re-enable tail call optimization of expanded libcalls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120622 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 22:59:46 +00:00
Jason W Kim
0c628c2617 fixing style nit: move class static to global static 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120619 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 22:46:50 +00:00
Bill Wendling
cf590263cd Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 21:54:50 +00:00
Jim Grosbach
5177f79c37 Use the correct fixup type for ARM VLDR* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 21:09:40 +00:00
Jim Grosbach
5d14f9be7b Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:47:31 +00:00
Owen Anderson
9d63d90de5 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:18:46 +00:00
Jason W Kim
1920d82f75 kill trailing space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:07:22 +00:00
Jim Grosbach
3990d8f89f 10 bits, not 12. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 18:51:32 +00:00
Devang Patel
056745cab6 Disable debug info for x86-darwin9 and earlier until PR 8715 and radar 8709290 are fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 16:59:34 +00:00
Duncan Sands
38169788fa I don't think it makes any sense to assert that the target supports SSE3 here. 
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 12:58:13 +00:00
Che-Liang Chiou
3608d2ac67 ptx: bug fix: use after free 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 11:45:53 +00:00
Jim Grosbach
887c0e4cbf Elaborate on FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 04:01:17 +00:00
Jim Grosbach
baf120fbe8 Move the ARMAsmPrinter class defintiion into a header file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 03:45:07 +00:00
Evan Cheng
28cd48fffb Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 03:27:20 +00:00
Bill Wendling
ff25116a09 Remove "comparison of integers of different signs" warning by making the 
variable unsigned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120541 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:49:04 +00:00
Bill Wendling
43f7b2d370 General cleanups of comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120536 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:42:55 +00:00
Jason W Kim
85fed5e0c5 ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:40:06 +00:00
Bill Wendling
0480e28fb2 Formatting. It's all the rage! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120533 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:36:55 +00:00
Bill Wendling
1d045ee884 More refactoring. This time the T1pI pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120532 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 02:28:08 +00:00
Eric Christopher
564857f776 Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:40:24 +00:00
Jan Wen Voung
a63bf704b4 Initialize an ARMConstantPoolValue field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120525 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:38:58 +00:00
Bill Wendling
40062fb747 s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:38:08 +00:00
Bill Wendling
0b424dc6b7 Renaming variables to coincide with documentation. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120522 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:32:02 +00:00
Bill Wendling
76f4e10388 Refactor T1sI and T1sIt encodings into helper classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 01:20:15 +00:00
Bill Wendling
a5a42d9b3c Refactor the T1sIt encodings into a parent class to get rid of all of the "let" 
statements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 00:48:44 +00:00
Owen Anderson
ca6945e5e2 Use by-name rather than by-order matching for NEON operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120507 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 00:28:25 +00:00
Evan Cheng
3d2125c9db Enable sibling call optimization of libcalls which are expanded during 
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 23:55:39 +00:00
Bill Wendling
3f8c110dc6 Rename operands to match ARM documentation. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120500 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 23:54:45 +00:00
Jim Grosbach
b0708d292b Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120499 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 23:51:41 +00:00
Jim Grosbach
d309b413a5 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120497 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 23:29:24 +00:00
Jason W Kim
61db62990b Thanks to JimG for catching this! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 23:27:18 +00:00
Bill Wendling
2cbc9fe837 Inline classes that were used in only one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 23:16:25 +00:00
Bill Wendling
1fd374e9c1 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 22:57:21 +00:00
Owen Anderson
80dd3e0612 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 22:45:47 +00:00
Jim Grosbach
97dd28fb89 Fix handling of ARM negative pc-relative fixups for loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 22:40:36 +00:00
Eric Christopher
c563ded794 Move X86InstrFPStack.td over to PseudoI as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120470 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 21:57:32 +00:00
Eric Christopher
6bac79deb3 Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violations 
while I'm in there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 21:37:36 +00:00
Owen Anderson
c7373f8158 Provide Thumb2 encodings for a few miscellaneous instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 20:00:01 +00:00
Jim Grosbach
c02ba66d41 Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 19:25:56 +00:00
Owen Anderson
0e1bcdf4f7 Add encoding support for Thumb2 PLD and PLI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 19:19:31 +00:00
Eric Christopher
06a86da323 Noticed this on inspection, fix and update some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 19:14:07 +00:00
Jim Grosbach
2e812e1635 Pseudo-ize ARM MOVPCRX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120442 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 18:56:36 +00:00
Owen Anderson
eb05a8d250 Provide encodings for a few more load/store variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120439 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 18:38:28 +00:00
Jim Grosbach
a0d2c8a40f Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 18:30:19 +00:00
Che-Liang Chiou
21d8b9bcad ptx: add command-line options for gpu target and ptx version 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120423 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 10:14:14 +00:00
Eric Christopher
fc967c9927 Fix some grammar in comments I noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120416 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 09:11:54 +00:00
Eric Christopher
7f216bac5d This defaults to GenericDomain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 09:11:07 +00:00
Eric Christopher
d872f144e2 Implement a PseudoI class and transfer the sse instructions over to use 
it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 08:57:23 +00:00
Eric Christopher
41c902fdbe Fix insertion point in pcmp expander. 
While I'm there, clean up too many \n even for me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 08:20:21 +00:00
Eric Christopher
82be220092 Fix some cleanups from my last patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 08:10:28 +00:00
Bill Wendling
ef4a68badb Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 07:44:32 +00:00
Che-Liang Chiou
3f8e617891 ptx: add ld instruction 
support register and register-immediate addressing mode

todo: immediate and register-register addressing mode



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120407 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 07:34:44 +00:00
Eric Christopher
228232b282 Rewrite mwait and monitor support and custom lower arguments. 
Fixes PR8573.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 07:20:12 +00:00
Bill Wendling
0e45a5a901 Minor cleanups. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:50:22 +00:00
Bill Wendling
6e46d84eea s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:48:15 +00:00
Bill Wendling
647fea57fd Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't 
able to match this yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120369 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:34:08 +00:00
Jim Grosbach
532c2f1d50 Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction 
and which are pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:24:05 +00:00
Bill Wendling
67077419c6 Add some encoding for the adr instruction. Labels still need to be finished. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:18:30 +00:00
Owen Anderson
6af50f7dd1 Correct Thumb2 encodings for a much wider range of loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:14:31 +00:00
Jim Grosbach
5c86a0a2b5 Make a few more ARM pseudo instructions actually use the PseudoInst base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:09:06 +00:00
Bill Wendling
8ca2fd6665 Predicate encoding should be withing {}s. And general cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120361 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:08:20 +00:00
Bill Wendling
194271a76e Predicate encoding should be withing {}s. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:05:25 +00:00
Bob Wilson
8e0c7b5287 Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:00:42 +00:00
Bob Wilson
173fb1421a Rename VLDnDUP instructions with double-spaced registers 
in an attempt to make things a little more consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:00:38 +00:00
Bob Wilson
6c4c982f83 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:00:35 +00:00
Jim Grosbach
e76473d9ba Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 23:51:31 +00:00
Jim Grosbach
6e4221153b Parameterize ARMPseudoInst size property. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 23:48:41 +00:00
Jim Grosbach
00a257af5b Add a few missing initializers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 23:41:10 +00:00
Jim Grosbach
03f44a04e6 Nuke trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 23:18:01 +00:00
Jim Grosbach
cd3c7cb915 Nuke a FIXME. No need to be fancier here, as ARM handles constant pools 
locations and formatting specially. rdar://7353441

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 23:09:20 +00:00
Owen Anderson
75579f739f Provide Thumb2 encodings for basic loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:44:32 +00:00
Evan Cheng
1e0eab122b Mark Darwin call instructions as using "r7" to prevent the frame-register 
assignment instructions from being moved below / above calls.
rdar://8690640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:43:27 +00:00
Jim Grosbach
a0bb253119 Nuke dead isCodeGenOnly annotation and extraneous comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:40:58 +00:00
Jim Grosbach
fbf0cb18cb tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120335 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:38:48 +00:00
Bill Wendling
9b0e92ca5b Thumb encodings for conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120334 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:37:46 +00:00
Jim Grosbach
5ca66696e7 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:37:40 +00:00
Bill Wendling
a46a493c02 Refactor some of the "disassembly-only" instructions into a base class. This 
reduces some code duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:15:03 +00:00
Eric Christopher
7bb5996e47 Update fastisel for the changes in r120272. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 21:56:23 +00:00
Jim Grosbach
d092a87ba3 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 21:28:32 +00:00
Owen Anderson
5404c2b36e Improving the factoring of several instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 20:38:48 +00:00
Bob Wilson
86c6d80a7a Add support for NEON VLD3-dup instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:35:29 +00:00
Bob Wilson
2fcda63763 Fix copy-and-paste errors in VLD2-dup scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:35:23 +00:00
Jim Grosbach
f1aa47dc1a ARM Pseudo-ize tBR_JTr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:32:47 +00:00
Owen Anderson
00a035f74f Thumb2 encodings for MSR and MRS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:29:15 +00:00
Owen Anderson
d18a9c9b9d Thumb2 encodings for system instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:22:08 +00:00
Owen Anderson
05bf595122 Thumb2 encodings for branches and IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:54:38 +00:00
Jim Grosbach
11fbff8085 The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to 
get the pretty-printer. That's handled explicityly by the MC lowering now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120305 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:53:24 +00:00
Michael J. Spencer
3cc52ea33c I swear I did a make clean and make before committing all this... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120304 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:47:54 +00:00
Jim Grosbach
2dc7768d73 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:37:44 +00:00
Michael J. Spencer
1f6efa3996 Merge System into Support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:16:10 +00:00
Kalle Raiskila
9363f739cd Handle lshr for i128 correctly on SPU also when 
shiftamount > 7.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120288 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 14:44:28 +00:00
Kalle Raiskila
c2ebfd454c Enable PostRA scheduling for SPU. 
This speeds up selected test cases with up to
5% - no slowdowns observed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 10:30:25 +00:00
Kalle Raiskila
b00f24b13c Allow machine LICM to do its job on SPU. 
-return a sensible value for register pressure
-add pattern to 'ila' instrucion


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120285 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 10:08:09 +00:00
Kalle Raiskila
11edd0cedc Add missing i128 case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120284 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 09:36:26 +00:00
Bill Wendling
2f17bf2a44 Add more Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 01:07:48 +00:00
Bill Wendling
5cbbf68e35 More Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 01:00:43 +00:00
Bill Wendling
d19ac0c75a Add Thumb encodings for REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 00:42:50 +00:00
Bill Wendling
849f2e381e Add more Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 00:18:15 +00:00
Rafael Espindola
ec0b428398 Make EmitIntValue non virtual. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120271 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 23:22:44 +00:00
Rafael Espindola
d652dbe720 Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 21:16:39 +00:00
Chris Lattner
d8f717911d fix PR8686, accepting a 'b' suffix at the end of all the setcc 
instructions.  I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne".  The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120260 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 20:23:50 +00:00
Nicolas Geoffray
7509ccda93 When emitting a single function with cppgen=function, you don't want to emit 
initializers of global variables used in the function.
Also make sure to emit the operands of a constant.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120253 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 18:00:53 +00:00
Rafael Espindola
a484f2c405 Move the PTXMCAsmStreamer class to the .cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 14:48:34 +00:00
Rafael Espindola
e04ed7e45f Define generic 1, 2 and 4 byte pc relative relocations. They are common 
and at least the 4 byte one will be needed to implement the .cfi_* directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 14:17:56 +00:00
Bob Wilson
b1dfa7a8e0 Add support for NEON VLD2-dup instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:26 +00:00
Bob Wilson
f3d2f9d4be Another minor refactoring for VLD1DUP instructions. 
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:15 +00:00
Bob Wilson
364a72a8e5 Add entry in getTargetNodeName() for ARMISD::VBICIMM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:11 +00:00
Anton Korobeynikov
94c5ae0875 Move more PEI-related hooks to TFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
cd775ceff0 Move callee-saved regs spills / reloads to TFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 23:05:03 +00:00
Rafael Espindola
5bf7c534cf Lower TLS_addr32 and TLS_addr64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 20:43:02 +00:00
Rafael Espindola
bfd2d26159 Implement the data16 prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 20:29:45 +00:00
Bob Wilson
bce55776af Refactor. Set alignment bit in VLD1-dup instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 07:12:02 +00:00
Bob Wilson
2a0e97431e Add NEON VLD1-dup instructions (load 1 element to all lanes). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 06:35:16 +00:00
Bob Wilson
8d41294664 Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. 
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from.  As far as I can tell now,
these instruction stages are clearly intended to overlap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 06:35:09 +00:00
Daniel Dunbar
36d76a8dbc MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 04:38:36 +00:00
Rafael Espindola
fd46797d0d Remove the unused TheTarget member. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-26 04:24:21 +00:00
Rafael Espindola
2ace1b68ac Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120147 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-25 17:14:16 +00:00
Benjamin Kramer
c62feda741 Namespacify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120146 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-25 16:42:51 +00:00
Wesley Peck
42e75a3cf1 Updating MBlaze .mask and .frame directives to match GCC's output and fixing regression introduced in 120095 by checking MCStreamer::hasRawTextSupport. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 16:32:35 +00:00
Wesley Peck
82dc040d06 1. Fixing error where basic block labels were not being printed out when they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots. 
2. Re-adding .mask and .frame directives in printed assembly.
3. Adding .ent and .end directives in printed assembly.
4. Minor cleanups to MBlaze backend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 15:39:32 +00:00
Kalle Raiskila
7de8101668 Use i8 as SETCC result type for i1 in SPU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120092 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 12:59:16 +00:00
Kalle Raiskila
702a4046a9 Allow for 'fcmp ogt' in SPU. 
Fix by Visa Putkinen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-24 11:42:17 +00:00
Benjamin Kramer
c21a821e9f The srem -> urem transform is not safe for any divisor that's not a power of two. 
E.g. -5 % 5 is 0 with srem and 1 with urem.

Also addresses Frits van Bommel's comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 20:33:57 +00:00
Jason W Kim
13534672de Move the ARM reloc constants to Support/ELF.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 19:40:36 +00:00
Bob Wilson
626613d5e8 Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations. 
We need to check if the individual vector elements are sign/zero-extended
values.  For now this only handles constants values.  Radar 8687140.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 19:38:38 +00:00
Benjamin Kramer
b70ebd2aa3 InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is positive. 
This allows to transform the rem in "1 << ((int)x % 8);" to an and.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 18:52:42 +00:00
Kalle Raiskila
0cc5b1f60e Division by pow-of-2 is not cheap on SPU, do it with 
shifts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 13:27:59 +00:00
Rafael Espindola
beb6898df8 Implement the rex64 prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 11:23:24 +00:00
Rafael Espindola
d93ceeb125 Produce a relocation for pcrel absolute values. Based on a patch by David Meyer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 07:20:12 +00:00
Wesley Peck
bf17cfa3f9 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 03:31:01 +00:00
Rafael Espindola
d80f8d08ce Remove duplicated constants. Thanks to Jason for noticing it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 21:49:05 +00:00
Benjamin Kramer
93f8455d73 InstCombine: Implement X - A*-B -> X + A*B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 20:31:27 +00:00
Evan Cheng
ab5c703fdb Fix epilogue codegen to avoid leaving the stack pointer in an invalid 
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 18:12:04 +00:00
Kalle Raiskila
d87e571e62 Fix a bug with extractelement on SPU. 
In the attached testcase, the element was
never extracted (missing rotate).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119973 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 16:28:26 +00:00
Benjamin Kramer
ce750f0332 Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization. 
This currently only catches the most basic case, a two-case switch, but can be
extended later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 09:45:38 +00:00
Duncan Sands
3d93893895 Fix a compiler warning about Kind being used uninitialized 
when assertions are disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 09:38:00 +00:00
Eric Christopher
9d89311df8 Pseudos default to 4byte size, let the instruction size field notice 
that branch tables are special.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 23:38:19 +00:00
Wesley Peck
4b04713423 Implement ELF object file writing support for the MBlaze backend. Its not perfect yet, but it works for many tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 22:06:28 +00:00
Wesley Peck
46a928b864 Implement branch analysis in the MBlaze backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 21:53:36 +00:00
Wesley Peck
6e749f31c6 Make it a little bit more explicit that the MBlaze backend only supports upto 
32-bit immediate values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 21:39:46 +00:00
Wesley Peck
5437ba48ce Fix an error in the MBlaze delay slot filler where instructions that already 
fill a delay slot are moved to fill a different delay slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 21:36:12 +00:00
Chris Lattner
8bc1e45295 apparently tailcalls are better on darwin/x86-64 than on linux? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 18:59:20 +00:00
Bill Wendling
dcf0a47b76 More Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:49:36 +00:00
Bill Wendling
af2b573614 Add encoding for ARM "trap" instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:05:29 +00:00
Bill Wendling
9717fa9f29 The "trap" instruction is one of this which doesn't have a condition code. Hack 
the code to not add a "condition code" if it's trap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 10:56:05 +00:00
Bill Wendling
7d0affdf02 - Give "trap" the correct encoding, at least according to Darwin's assembler. 
- Add comments saying where the encodings for other instructions came from.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 10:55:23 +00:00
Chris Lattner
cbf5d74e6a implement PR8524, apparently mainline gas accepts movq as an alias for movd 
when transfering between i64 gprs and mmx regs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 08:18:57 +00:00
Chris Lattner
3e41106de4 add some random notes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 07:05:31 +00:00
Owen Anderson
aa54524a44 Use by-name rather than by-order operand matching for some NEON encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:47:06 +00:00
Chris Lattner
75d8f599e7 optimize: 
void a(int x) { if (((1<<x)&8)==0) b(); }

into "x != 3", which occurs over 100 times in 403.gcc but in no
other program in llvm-test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119922 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:44:42 +00:00
Chris Lattner
79a980ad85 tail calls on x86 are implemented. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:10:27 +00:00
Jim Grosbach
0eb49c57f0 BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119918 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 01:26:01 +00:00
Bill Wendling
5cc88a205d A few more thumb instruction MC encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119913 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:52:33 +00:00
Eric Christopher
827656dab4 Rewrite address handling to use a structure with all the possible address 
mode variables. Handle frame indexes in load/store and allocas again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:38:27 +00:00
Eric Christopher
13df1a0bac STRH only needs the additional operand, not t2STRH. Also invert conditional 
to match the one from the load emitter above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:01:38 +00:00