more fixes to settings import/export

* fix compatibility with Windows
* add RAW export option

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "ip/pulpino_qsys"]
+	path = ip/pulpino_qsys
+	url = https://github.com/marqs85/pulpino_qsys.git

CREDITS

@@ -0,0 +1,28 @@
+Original design and code
+* marqs
+
+Audio add-on board, scanline improvements
+* borti4938
+
+Reverse LPF, scanline improvements
+* paulb_nl
+
+Technical advisory, testing
+* Fudoh
+
+Sales & support, testing
+* BuckoA51
+
+Profile improvements
+* megari
+
+Japanese translation
+* 511141 / lui
+
+Early testing
+* juji82
+* Konsolkongen
+* Edenal
+* NYYRIKKI
+* stt
+* oasiz

README.md

@@ -12,6 +12,7 @@ Requirements for building and debugging firmware
 
 * Software
   * [Altera Quartus II + Cyclone IV support](http://dl.altera.com/?edition=lite) (v 16.1 or higher - free Lite Edition suffices)
+  * [RISC-V GNU Compiler Toolchain](https://github.com/riscv/riscv-gnu-toolchain)
   * GCC (or another C compiler) for host architecture (for building a SD card image)
   * Make
   * [iconv](https://en.wikipedia.org/wiki/Iconv) (for building with JP lang menu)
@@ -19,51 +20,70 @@ Requirements for building and debugging firmware
 
 Architecture
 ------------------------------
-* [Reference board schematics](https://www.niksula.hut.fi/~mhiienka/ossc/diy-v1.5/ossc_v1.5-diy_schematic.pdf)
+* [Reference board schematics](https://github.com/marqs85/ossc_pcb/raw/v1.6/ossc_board.pdf)
 * [Reference PCB project](https://github.com/marqs85/ossc_pcb)
 
 
+SW toolchain build procedure
+--------------------------
+1. Download, configure, build and install RISC-V toolchain with Newlib + RV32EMC support:
+~~~~
+git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
+cd riscv-gnu-toolchain
+./configure --prefix=/opt/riscv --with-arch=rv32emc --with-abi=ilp32e
+sudo make    # sudo needed if installing under default /opt/riscv location
+~~~~
+2. Compile custom binary to IHEX converter:
+~~~~
+gcc tools/bin2hex.c -o tools/bin2hex
+~~~~
+
+
+Building RTL (bitstream)
+--------------------------
+1. Initialize pulpino submodules (once after cloning ossc project or when submoduled have been updated)
+~~~~
+git submodule update --init --recursive ip/pulpino_qsys
+~~~~
+2. Load the project (ossc.qpf) in Quartus
+3. Generate QSYS output files (only needed before first compilation or when QSYS structure has been modified)
+    * Open Platform Designer (Tools -> Platform Designer)
+    * Load platform configuration (sys.qsys)
+    * Generate output (Generate -> Generate HDL, Generate)
+    * Close Platform Designer
+    * Run "touch software/sys_controller_bsp/bsp_timestamp" to acknowledge QSYS update
+3. Generate the FPGA bitstream (Processing -> Start Compilation)
+4. Ensure that there are no severe timing violations by looking into Timing Analyzer report
+
+NOTE: If the software image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) was not up to date at the time of compilation, bitstream can be quickly rebuilt with updated hex by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
+
+
 Building software image
 --------------------------
-1. Enter BSP directory:
-~~~~
-cd software/sys_controller_bsp
-~~~~
-2. (Optionally) edit BSP settings:
-~~~~
-nios2-bsp-editor
-~~~~
-3. Generate BSP:
-~~~~
-nios2-bsp-generate-files --bsp-dir . --settings settings.bsp
-~~~~
-NOTE: the previous step must be done every time after RTL/bitstream is built
-4. Enter software root directory:
+1. Enter software root directory:
 ~~~~
 cd software/sys_controller
 ~~~~
-5. Build SW image for target configuration:
+2. Build SW for target configuration:
 ~~~~
-make <OPTIONS> mem_init_generate
+make [OPTIONS] [TARGET]
 ~~~~
-where OPTIONS may include following definitions:
-* OSDLANG=JP (Japanese language menu. Run "iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c ossc/menu_sjis.c" before make)
-* DIY_AUDIO=y (Includes code for DIY audio board)
-6. Optionally test updated SW by programming Nios2 CPU via JTAG (RTL-SW interface in active FW must be compatible new SW BSP configuration)
+OPTIONS may include following definitions:
+* OSDLANG=JP (Japanese language menu)
+* ENABLE_AUDIO=y (Includes audio setup code for v1.6 PCB / DIY audio add-on board)
+
+TARGET is typically one of the following:
+* all (Default target. Compiles an ELF file)
+* generate_hex (Generates a memory initialization file required for bitstream and direct download)
+* clean (cleans ELF and intermediate files. Should be invoked every time OPTIONS are changed between compilations, expect with generate_hex where it is done automatically)
+
+3. Optionally test updated SW by directly downloading memory image to block RAM via JTAG
 ~~~~
-nios2-download -g --accept-bad-sysid sys_controller.elf
+make rv-reprogram
 ~~~~
 
 
-Building RTL / bitstream
---------------------------
-1. Load the project (ossc.qpf) in Quartus
-2. Generate the FPGA bitstream (Processing -> Start Compilation). NOTE: make sure software image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) is up to date before generating bitstream.
-3. Ensure that there are no severe timing violations by looking into Timing Analyzer report
-
-If only software image is updated, bitstream can be quickly rebuilt by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
-
-Installing the firmware via JTAG
+Installing firmware via JTAG
 --------------------------
 The bitstream can be either directly programmed into FPGA (volatile method, suitable for quick testing), or into serial flash chip where it is automatically loaded every time FPGA is subsequently powered on (nonvolatile method, suitable for long-term use).
 
@@ -72,15 +92,34 @@ To program FPGA, open Programmer in Quartus, select your USB Blaster device, add
 To program flash, FPGA configuration file must be first converted into JTAG indirect Configuration file (.jic). Open conversion tool ("File->Convert Programming Files") in Quartus, click "Open Conversion Setup Data", select "ossc.cof" and press Generate. Then open Programmer, add generated file (output_files/ossc.jic) and press Start after which flash is programmed. Installed/updated firmware is activated after power-cycling the board.
 
 
+Generating SD card image
+--------------------------
+Bitstream file (Altera propiertary format) must be wrapped with custom header structure (including checksums) so that it can be processed reliably on the CPU. This can be done with included helper application which generates a disk image which can written to a SD card and subsequently loaded on OSSC:
+
+1. Compile tools/create_fw_img.c
+~~~~
+cd tools && gcc create_fw_img.c -o create_fw_img
+~~~~
+2. Generate the firmware image:
+~~~~
+./create_fw_img <rbf> <version> [version_suffix]
+~~~~
+where
+* \<rbf\> is RBF format bitstream file (typically ../output_files/ossc.rbf)
+* \<version\> is version string (e.g. 0.78)
+* \[version_suffix\] is optional max. 8 character suffix name (e.g. "mytest")
+
+
 Debugging
 --------------------------
 1. Rebuild the software in debug mode:
 ~~~~
-make clean && make APP_CFLAGS_DEFINED_SYMBOLS="-DDEBUG"
+make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex
 ~~~~
-NOTE: Fw update functionality via SD card is disabled in debug build due to code space limitations
-2. Program Nios2 CPU via JTAG and open terminal for UART
+NOTE: Fw update functionality via SD card is disabled in debug builds due to code space limitations. If audio support is enabled on debug build, other functionality needs to be disabled as well.
+
+2. Download memory image via JTAG and open terminal for UART
 ~~~~
-nios2-download -g --accept-bad-sysid sys_controller.elf && nios2-terminal
+make rv-reprogram && nios2-terminal
 ~~~~
 Remember to close nios2-terminal after debug session, otherwise any JTAG transactions will hang/fail.

ip/altera_epcq_controller_mod/altera_epcq_controller.sv

@@ -1,611 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-`timescale 1ps / 1ps
-
-module altera_epcq_controller #(
-	parameter CS_WIDTH		= 1,
-	parameter ENABLE_4BYTE_ADDR = 1,
-	parameter ADDR_WIDTH	= 22,
-	parameter ASI_WIDTH		= 1,
-	parameter DEVICE_FAMILY = "CYCLONE V",
-	parameter ASMI_ADDR_WIDTH = 22,
-	parameter CHIP_SELS = 1
-)(
-	input 	wire		  								clk,
-	input 	wire		  								reset_n,
-	                                        			
-	// ports to access csr                        			
-	input 	wire										avl_csr_write,
-	input 	wire		  								avl_csr_read,
-	input 	wire 	[2:0] 								avl_csr_addr,
-	input 	wire 	[31:0] 								avl_csr_wrdata,
-	output 	reg 	[31:0] 								avl_csr_rddata,
-	output 	reg 		 								avl_csr_rddata_valid,
-	output 	reg 			 							avl_csr_waitrequest,
-	                                        			
-	// ports to access memory        			
-	input	wire		  								avl_mem_write,
-	input	wire										avl_mem_read,
-	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
-	input	wire	[31:0]								avl_mem_wrdata,
-	input	wire 	[3:0]								avl_mem_byteenable,
-	input	wire	[6:0]								avl_mem_burstcount,
-	output	wire	[31:0]								avl_mem_rddata,
-	output	reg											avl_mem_rddata_valid,
-	output 	reg 			 							avl_mem_waitrequest,
-	
-	// interrupt signal
-	output	reg 										irq,
-	
-	// Disable dedicated active serial interface
-	input  	wire	[ASI_WIDTH-1:0]						epcq_dataout,
-	output  reg											epcq_dclk,
-	output  reg		[CS_WIDTH-1:0] 						epcq_scein,
-	output  reg		[ASI_WIDTH-1:0]						epcq_sdoin,
-	output  reg		[ASI_WIDTH-1:0]						epcq_dataoe,
-	
-	// ASMI PARALLEL interface
-	input   wire	[ASI_WIDTH-1:0]						ddasi_dataoe,
-	output  reg 	[ASI_WIDTH-1:0]						ddasi_dataout,
-	input   wire 										ddasi_dclk,
-	input   wire 	[CS_WIDTH-1:0] 						ddasi_scein,
-	input   reg		[ASI_WIDTH-1:0]  					ddasi_sdoin,
-	
-	input   wire										asmi_busy,
-	input   wire										asmi_data_valid,
-	input   wire	[7:0]  								asmi_dataout,
-	output  reg											asmi_clkin,
-	output  reg											asmi_reset,
-	output  reg		[CS_WIDTH-1:0] 						asmi_sce,
-	output	reg	    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr,
-	output  reg		[7:0]  								asmi_datain,
-	output  reg											asmi_fast_read,
-	output  wire										asmi_rden,
-	output  reg											asmi_shift_bytes,
-	output  reg 										asmi_en4b_addr,
-	output  wire										asmi_wren,
-	output  reg											asmi_write,
-	
-	input   wire										asmi_illegal_erase,
-	input   wire										asmi_illegal_write,
-	input   wire	[7:0]  								asmi_rdid_out,
-	input   wire	[7:0]  								asmi_status_out,
-	input   wire	[7:0]  								asmi_epcs_id,
-	output  reg											asmi_read_rdid,
-	output  reg											asmi_read_status,
-	output	reg											asmi_read_sid,
-	output  reg 										asmi_bulk_erase,
-	output  reg											asmi_sector_erase,
-	output  reg											asmi_sector_protect
-);
-	localparam LOCAL_ADDR_WIDTH = ADDR_WIDTH+2;
-	localparam CSR_DATA_WIDTH   = 32;
-	localparam LAST_ADDR_BIT    = (ASMI_ADDR_WIDTH == 24) ? 15 :
-									(ASMI_ADDR_WIDTH == 32) ? 23 : 15;
-	
-	reg  [8:0] wr_burstcount_cnt, rd_burstcount_cnt;
-	reg	 [8:0] rd_mem_burstcount, wr_mem_burstcount;
-	
-	wire last_wr_byte;
-	wire access_csr_status, access_csr_sid, access_csr_rdid, access_csr_mem_op, access_isr, access_imr, access_sce;
-	wire read_status_combi, read_sid_combi, read_rdid_combi, read_isr_combi, read_imr_combi, write_isr_combi, write_imr_combi, write_sce_combi;
-	wire bulk_erase_combi, sector_erase_combi, sector_protect_combi;
-	wire wren_combi, illegal_write_combi, illegal_erase_combi;
-	wire m_illegal_write_combi, m_illegal_erase_combi;
-	wire read_mem_combi, write_mem_combi;
-	wire data_valid_combi, pending_wr_data;
-	wire detect_addroffset;
-	wire [8:0] wfifo_data_in_0, wfifo_data_in_1, wfifo_data_in_2, wfifo_data_in_3;
-	wire [ADDR_WIDTH-1:0] temp_mem_addr;
-	
-	reg reset_n_reg;
-	reg wr_mem_waitrequest, local_waitrequest;
-	reg illegal_write_reg, illegal_erase_reg, m_illegal_write_reg, m_illegal_erase_reg;
-	reg read_status_valid, read_sid_valid, read_rdid_valid, read_isr_valid, read_imr_valid;
-	reg read_status_en, read_sid_en, read_rdid_en;
-	reg wren_internal;
-	reg [LOCAL_ADDR_WIDTH-1:0] wr_mem_addr;
-	reg [7:0] rd_data_reg [4];
-	reg [3:0][8:0] wr_data_reg;
-	reg [1:0] rd_cnt;
-	reg [1:0] wr_cnt;
-	reg [3:0] wr_data_reg_full;
-	reg detect_addroffset_reg, asmi_busy_reg;
-	reg [2:0] temp_sce;
-	
-	// Direct connection
-	assign asmi_clkin 		= clk;
-	assign asmi_reset 		= ~reset_n;
-	assign ddasi_dataout 	= epcq_dataout;
-	assign epcq_dclk 		= ddasi_dclk;
-	assign epcq_scein		= ddasi_scein;
-	assign epcq_sdoin		= ddasi_sdoin;
-	assign epcq_dataoe		= ddasi_dataoe;
-	
-	// chip select
-	generate if (DEVICE_FAMILY == "Arria 10") begin
-		always @(posedge clk or negedge reset_n) begin
-			if (~reset_n) begin
-				asmi_sce			<= {CS_WIDTH{1'b0}};
-			end 
-// to pack the address space this is needed
-			else if (write_mem_combi || read_mem_combi) begin
-				if (CHIP_SELS == 1 ) 					
-					asmi_sce			<= 3'b001;
-				else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 0) 
-					asmi_sce			<= 3'b001;
-				else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 1) 
-					asmi_sce			<= 3'b010;
-				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1] == 1)	
-					asmi_sce			<= 3'b100;
-				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 0) 	
-					asmi_sce			<= 3'b001;
-				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 1) 	
-					asmi_sce			<= 3'b010;
-				else
-					asmi_sce			<= {CS_WIDTH{1'b0}};
-			end
-			else if (write_sce_combi) begin
-				asmi_sce			<= avl_csr_wrdata[2:0];
-			end
-			else if (asmi_en4b_addr) begin
-				asmi_sce			<= temp_sce;
-			end
-		end
-// decoder ring  if the CHIP_SEL is only 1 then avalon address is the temp address
-//		if the chipsele is 2 then need to remove top address bit
-//		if the chipelect is 3 then remove the top 2 address bits.  
-		assign temp_mem_addr	= CHIP_SELS == 1 ? avl_mem_addr:( CHIP_SELS == 2 ? {1'b0,avl_mem_addr[ADDR_WIDTH-2:0]}:{2'b00,avl_mem_addr[ADDR_WIDTH-3:0]});
-	end
-	else begin
-		always @(posedge clk) begin
-			asmi_sce				<= {CS_WIDTH{1'b0}};
-		end
-		assign temp_mem_addr	= avl_mem_addr;
-	end
-	endgenerate
-	
-	// wait_request generation logic
-	assign avl_mem_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
-	assign avl_csr_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
-	
-	// access CSR decoding logic
-	assign access_csr_status	= (avl_csr_addr == 3'b000);
-	assign access_csr_sid		= (avl_csr_addr == 3'b001);
-	assign access_csr_rdid		= (avl_csr_addr == 3'b010);
-	assign access_csr_mem_op	= (avl_csr_addr == 3'b011);
-	assign access_isr			= (avl_csr_addr == 3'b100);
-	assign access_imr			= (avl_csr_addr == 3'b101);
-	assign access_sce			= (avl_csr_addr == 3'b110);
-	
-	// read/write memory combi logic
-	assign read_mem_combi		= (avl_mem_read && ~avl_mem_waitrequest);
-	assign write_mem_combi		= (avl_mem_write && ~avl_mem_waitrequest);
-
-	// read csr logic
-	assign read_status_combi	= (avl_csr_read && access_csr_status && ~avl_csr_waitrequest);
-	assign read_sid_combi		= (avl_csr_read && access_csr_sid && ~avl_csr_waitrequest);
-	assign read_rdid_combi		= (avl_csr_read && access_csr_rdid && ~avl_csr_waitrequest);
-	assign read_isr_combi		= (avl_csr_read && access_isr && ~avl_csr_waitrequest);
-	assign read_imr_combi		= (avl_csr_read && access_imr && ~avl_csr_waitrequest);
-	assign write_isr_combi		= (avl_csr_write && access_isr && ~avl_csr_waitrequest);
-	assign write_imr_combi		= (avl_csr_write && access_imr && ~avl_csr_waitrequest);
-	assign write_sce_combi		= (avl_csr_write && access_sce && ~avl_csr_waitrequest);
-	
-	// write csr logic
-	assign bulk_erase_combi		= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b01);
-	assign sector_erase_combi	= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b10);
-	assign sector_protect_combi	= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b11);
-	assign illegal_write_combi	= (asmi_illegal_write) ? 1'b1 :
-									(write_isr_combi && avl_csr_wrdata[1]) ? 1'b0 : 
-										illegal_write_reg;
-	assign illegal_erase_combi	= (asmi_illegal_erase) ? 1'b1 :
-									(write_isr_combi && avl_csr_wrdata[0]) ? 1'b0 : 
-										illegal_erase_reg;
-	assign m_illegal_write_combi= (write_imr_combi) ? avl_csr_wrdata[1] : m_illegal_write_reg;
-	assign m_illegal_erase_combi= (write_imr_combi) ? avl_csr_wrdata[0] : m_illegal_erase_reg;
-	assign wren_combi			= (sector_protect_combi || sector_erase_combi || bulk_erase_combi);
-										
-	assign asmi_rden			= (rd_burstcount_cnt > 9'd0);		// deasserted at the last 2 byte - refer to ASMI_PARALLEL UG
-
-	// interrupt signal
-	assign irq = (illegal_write_reg && m_illegal_write_reg) || (illegal_erase_reg && m_illegal_erase_reg);
-	
-	assign last_wr_byte = (wr_burstcount_cnt == wr_mem_burstcount - 9'd1) ? 1'b1 : 1'b0;
-	
-	assign asmi_wren = wren_internal || asmi_en4b_addr || asmi_shift_bytes || asmi_write;
-	
-	assign data_valid_combi = (rd_burstcount_cnt[1:0] == 2'b00) ? asmi_data_valid : 1'b0;
-	
-	assign wfifo_data_in_0 = {avl_mem_byteenable[0], avl_mem_wrdata[7:0]   };
-	assign wfifo_data_in_1 = {avl_mem_byteenable[1], avl_mem_wrdata[15:8]  };
-	assign wfifo_data_in_2 = {avl_mem_byteenable[2], avl_mem_wrdata[23:16] };
-	assign wfifo_data_in_3 = {avl_mem_byteenable[3], avl_mem_wrdata[31:24] };
-	
-	assign avl_mem_rddata  = {rd_data_reg[3], rd_data_reg[2], rd_data_reg[1], rd_data_reg[0]};
-	assign pending_wr_data = (|wr_data_reg_full) ? 1'b1 : 1'b0;
-	assign detect_addroffset = (pending_wr_data && wr_data_reg[wr_cnt][8]) ? 1'b1 : 
-								(wr_burstcount_cnt == {9{1'b0}}) ? 1'b0 : detect_addroffset_reg;
-
-	//-------------------------------- array to store write data -------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			wr_data_reg			<= '{{9{1'b0}}, {9{1'b0}}, {9{1'b0}}, {9{1'b0}}};
-			wr_data_reg_full	<= {4{1'b0}};
-		end 
-		else if (write_mem_combi) begin
-			wr_data_reg			<= {wfifo_data_in_3, wfifo_data_in_2, wfifo_data_in_1, wfifo_data_in_0};
-			wr_data_reg_full	<= {4{1'b1}};
-		end
-		else if (wr_data_reg_full > 4'b0000) begin
-			wr_data_reg_full	<= wr_data_reg_full << 1;
-		end
-	end
-	
-	//-------------------------------- array to store read data -------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			rd_data_reg			<= '{{8{1'b0}}, {8{1'b0}}, {8{1'b0}}, {8{1'b0}}};
-			rd_cnt				<= {2{1'b0}};
-		end 
-		else if (asmi_data_valid) begin
-			rd_data_reg[rd_cnt]	<= asmi_dataout;
-			rd_cnt				<= rd_cnt + 2'b01;
-		end
-	end
-	
-	//------------------------------- Enable 4-byte addressing out of reset ----------------------
-	generate 
-	if (ENABLE_4BYTE_ADDR) begin
-		typedef enum logic[1:0] {EN4B_CHIP1, EN4B_CHIP2, EN4B_CHIP3, IDLE} state_t;
-		state_t state;
-	
-		always @(posedge clk or negedge reset_n_reg) begin	// use reset_n_reg because user is allow to send cmd to ASMI_PARALLEL 2 clock cycles after reset
-			if (~reset_n_reg) begin	
-				state					<= EN4B_CHIP1;
-				asmi_en4b_addr			<= 1'b1;
-				temp_sce				<= 3'b001;
-			end
-			else begin
-				case (state)
-					EN4B_CHIP1 : begin
-									asmi_en4b_addr			<= 1'b1;
-									if (~asmi_busy) begin
-										if (CHIP_SELS > 1) begin
-											state					<= EN4B_CHIP2;
-											temp_sce				<= 3'b010;
-										end
-										else begin
-											state					<= IDLE;
-											temp_sce				<= 3'b000;
-										end
-									end
-								 end
-					EN4B_CHIP2 : begin
-									asmi_en4b_addr			<= 1'b1;
-									if (~asmi_busy) begin
-										if (CHIP_SELS > 2) begin
-											state					<= EN4B_CHIP3;
-											temp_sce				<= 3'b100;
-										end
-										else begin
-											state					<= IDLE;
-											temp_sce				<= 3'b000;
-										end
-									end
-								 end
-					EN4B_CHIP3 : begin
-									asmi_en4b_addr			<= 1'b1;
-									if (~asmi_busy) begin
-										state					<= IDLE;
-										temp_sce				<= 3'b000;
-									end
-								 end
-					IDLE	   : begin
-									asmi_en4b_addr			<= 1'b0;
-									state					<= IDLE;
-									temp_sce				<= 3'b000;
-								 end
-					default : 	 begin
-									asmi_en4b_addr			<= 1'b0;
-									state					<= IDLE;
-									temp_sce				<= 3'b000;
-								 end
-				endcase
-			end
-		end
-	end
-	else begin
-		always @(posedge clk) begin
-			asmi_en4b_addr				<= 1'b0;
-			temp_sce					<= 3'b000;
-		end
-	end
-	endgenerate
-	
-	//--------------------------------------- Waitrequest logic ----------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			wr_mem_waitrequest			<= 1'b0;
-			local_waitrequest			<= 1'b0;
-		end
-		else begin
-			if (read_mem_combi || read_status_combi || read_sid_combi || read_rdid_combi || bulk_erase_combi || sector_erase_combi || sector_protect_combi || asmi_en4b_addr) begin		// no back pressure during imr & isr access
-				local_waitrequest		<= 1'b1;
-			end
-			else if (asmi_busy_reg && ~asmi_busy) begin
-				local_waitrequest		<= 1'b0;
-			end
-			
-			if (write_mem_combi) begin
-				wr_mem_waitrequest	<= 1'b1;
-			end
-			else if ((~pending_wr_data && ~asmi_write) || asmi_busy_reg && ~asmi_busy) begin
-				wr_mem_waitrequest	<= 1'b0;
-			end
-		end
-	end
-	
-	// -------------------------------------- MEM ACCESS -----------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			rd_mem_burstcount			<= {9{1'b0}};
-			wr_mem_burstcount			<= {9{1'b0}};
-			wr_mem_addr					<= {LOCAL_ADDR_WIDTH{1'b0}};
-		end
-		else begin
-			if (read_mem_combi) begin
-				rd_mem_burstcount		<= {avl_mem_burstcount, 2'b00}; 
-			end
-			if (write_mem_combi && (wr_burstcount_cnt == {9{1'b0}})) begin
-				wr_mem_addr				<= {temp_mem_addr, 2'b00};
-				wr_mem_burstcount		<= {avl_mem_burstcount, 2'b00}; 
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			wr_burstcount_cnt				<= {9{1'b0}};
-		end
-		else begin
-			if (pending_wr_data) begin
-				wr_burstcount_cnt			<= wr_burstcount_cnt + 9'd1;
-			end
-			else if (wr_burstcount_cnt == wr_mem_burstcount) begin
-				wr_burstcount_cnt			<= {9{1'b0}};
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			rd_burstcount_cnt				<= {9{1'b0}};
-		end
-		else begin
-			if (read_mem_combi) begin
-				rd_burstcount_cnt			<= 9'd1;
-			end
-			else if (rd_burstcount_cnt == rd_mem_burstcount) begin		// each rd 4 burst
-				rd_burstcount_cnt			<= {9{1'b0}};
-			end
-			else if (asmi_data_valid && rd_burstcount_cnt > 0) begin
-				rd_burstcount_cnt			<= rd_burstcount_cnt + 9'd1;
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			asmi_addr					<= {ASMI_ADDR_WIDTH{1'b0}};
-		end
-		else begin
-			if (sector_erase_combi) begin // set lower 16 bits to zero so that erase at starting address of each sector
-				asmi_addr				<= {avl_csr_wrdata[LAST_ADDR_BIT : 8], {16{1'b0}}};	
-			end
-			if (read_mem_combi) begin
-				asmi_addr				<= {temp_mem_addr, 2'b00};
-			end
-			
-			if (detect_addroffset && ~detect_addroffset_reg) begin
-				asmi_addr			<= wr_mem_addr + {{LOCAL_ADDR_WIDTH-9{1'b0}}, wr_burstcount_cnt};
-			end
-
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			asmi_datain					<= {8{1'b0}};
-			wr_cnt						<= {2{1'b0}};
-			asmi_shift_bytes			<= 1'b0;
-		end
-		else begin
-			if (sector_protect_combi) begin
-				asmi_datain				<= {{1{1'b0}}, avl_csr_wrdata[11], avl_csr_wrdata[12], avl_csr_wrdata[10:8], {2{1'b0}}};	// BP3, TB, BP2, BP1, BP0
-			end
-			if (pending_wr_data) begin
-				asmi_datain				<= wr_data_reg[wr_cnt][7:0];
-				wr_cnt					<= wr_cnt + 2'd1;
-			end
-			if (pending_wr_data && wr_data_reg[wr_cnt][8]) begin
-				asmi_shift_bytes		<= 1'b1;
-			end
-			else begin
-				asmi_shift_bytes		<= 1'b0;
-			end
-		end
-	end
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			asmi_read_status			<= 1'b0;
-			asmi_read_sid				<= 1'b0;
-			asmi_read_rdid				<= 1'b0;
-			asmi_bulk_erase				<= 1'b0;
-			asmi_sector_erase			<= 1'b0;
-			asmi_sector_protect			<= 1'b0;
-			wren_internal				<= 1'b0;
-			asmi_write					<= 1'b0;
-			asmi_fast_read				<= 1'b0;
-			asmi_busy_reg				<= 1'b0;
-			avl_mem_rddata_valid		<= 1'b0;
-			detect_addroffset_reg		<= 1'b0;
-			reset_n_reg					<= 1'b0;
-		end
-		else begin
-			asmi_read_status			<= read_status_combi;
-			asmi_read_sid				<= read_sid_combi;
-			asmi_read_rdid				<= read_rdid_combi;
-			asmi_bulk_erase				<= bulk_erase_combi;
-			asmi_sector_erase			<= sector_erase_combi;				
-			asmi_sector_protect			<= sector_protect_combi;
-			wren_internal				<= wren_combi;
-			asmi_write					<= last_wr_byte;
-			asmi_fast_read				<= read_mem_combi;
-			asmi_busy_reg				<= asmi_busy;
-			avl_mem_rddata_valid		<= data_valid_combi;
-			detect_addroffset_reg		<= detect_addroffset;
-			reset_n_reg					<= 1'b1;
-		end
-	end
-	
-	// --------------------------------------------- CSR ACCESS -------------------------------------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			illegal_write_reg			<= 1'b0;
-			illegal_erase_reg			<= 1'b0;
-			m_illegal_write_reg			<= 1'b0;
-			m_illegal_erase_reg			<= 1'b0;
-		end
-		else begin
-			illegal_write_reg			<= illegal_write_combi;
-			illegal_erase_reg			<= illegal_erase_combi;
-			m_illegal_write_reg			<= m_illegal_write_combi;
-			m_illegal_erase_reg			<= m_illegal_erase_combi;
-		end
-	end
-	
-	// csr read only registers enable logic
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			read_status_en				<= 1'b0;
-			read_sid_en 				<= 1'b0;
-			read_rdid_en				<= 1'b0;
-		end
-		else if (asmi_read_status) begin
-			read_status_en				<= 1'b1;
-		end
-		else if (asmi_read_sid) begin
-			read_sid_en					<= 1'b1;
-		end
-		else if (asmi_read_rdid) begin
-			read_rdid_en				<= 1'b1;
-		end
-		else if (asmi_busy == 0) begin
-			read_status_en				<= 1'b0;
-			read_sid_en 				<= 1'b0;
-			read_rdid_en				<= 1'b0;
-		end
-	end
-	
-	// generation logic for avl csr read data valid
-	assign avl_csr_rddata_valid	= read_status_valid || read_sid_valid || read_rdid_valid || read_isr_valid || read_imr_valid;
-	
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			read_status_valid			<= 1'b0;
-			read_sid_valid				<= 1'b0;
-			read_rdid_valid				<= 1'b0;
-			read_isr_valid				<= 1'b0;
-			read_imr_valid				<= 1'b0;
-		end
-		else begin
-			if (read_status_en && asmi_busy == 0) begin
-				read_status_valid			<= 1'b1;
-			end
-			else begin
-				read_status_valid			<= 1'b0;
-			end
-			
-			if (read_sid_en && asmi_busy == 0) begin
-				read_sid_valid				<= 1'b1;
-			end
-			else begin
-				read_sid_valid				<= 1'b0;
-			end
-			
-			if (read_rdid_en && asmi_busy == 0) begin
-				read_rdid_valid				<= 1'b1;
-			end
-			else begin
-				read_rdid_valid				<= 1'b0;
-			end
-			
-			if (read_isr_combi) begin
-				read_isr_valid				<= 1'b1;
-			end
-			else begin
-				read_isr_valid				<= 1'b0;
-			end
-			
-			if (read_imr_combi) begin
-				read_imr_valid				<= 1'b1;
-			end
-			else begin
-				read_imr_valid				<= 1'b0;
-			end
-		end
-	end
-	
-	// generation logic for avl csr read data
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			avl_csr_rddata				<= {CSR_DATA_WIDTH{1'b0}};
-		end
-		else begin
-			if (read_status_en && asmi_busy == 0) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_status_out};
-			end
-			if (read_sid_en && asmi_busy == 0) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_epcs_id};
-			end
-			if (read_rdid_en && asmi_busy == 0) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_rdid_out};
-			end
-			if (read_isr_combi) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-2{1'b0}}, illegal_write_reg, illegal_erase_reg};
-			end
-			if (read_imr_combi) begin
-				avl_csr_rddata				<= {{CSR_DATA_WIDTH-2{1'b0}}, m_illegal_write_reg, m_illegal_erase_reg};
-			end
-		end
-	end
-	
-
-endmodule

ip/altera_epcq_controller_mod/altera_epcq_controller_arb.sv

@@ -1,230 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// (C) 2001-2014 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-`timescale 1ps / 1ps
-
-module altera_epcq_controller_arb #(
-	parameter CS_WIDTH		= 1,
-	parameter ENABLE_4BYTE_ADDR = 1,
-	parameter ADDR_WIDTH	= 22,
-	parameter ASI_WIDTH		= 1,
-	parameter DEVICE_FAMILY = "CYCLONE V",
-	parameter ASMI_ADDR_WIDTH = 22,
-	parameter CHIP_SELS = 1
-)(
-	input 	wire		  								clk,
-	input 	wire		  								reset_n,
-	                                        			
-	// ports to access csr                        			
-	input 	wire										avl_csr_write,
-	input 	wire		  								avl_csr_read,
-	input 	wire 	[2:0] 								avl_csr_addr,
-	input 	wire 	[31:0] 								avl_csr_wrdata,
-	output 	reg 	[31:0] 								avl_csr_rddata,
-	output 	reg 		 								avl_csr_rddata_valid,
-	output 	reg 			 							avl_csr_waitrequest,
-	                                        			
-	// ports to access memory        			
-	input	wire		  								avl_mem_write,
-	input	wire										avl_mem_read,
-	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
-	input	wire	[31:0]								avl_mem_wrdata,
-	input	wire 	[3:0]								avl_mem_byteenable,
-	input	wire	[6:0]								avl_mem_burstcount,
-	output	wire	[31:0]								avl_mem_rddata,
-	output	reg											avl_mem_rddata_valid,
-	output 	reg 			 							avl_mem_waitrequest,
-	
-	// interrupt signal
-	output	reg 										irq,
-	
-	// Disable dedicated active serial interface
-	input  	wire	[ASI_WIDTH-1:0]						epcq_dataout,
-	output  reg											epcq_dclk,
-	output  reg		[CS_WIDTH-1:0] 						epcq_scein,
-	output  reg		[ASI_WIDTH-1:0]						epcq_sdoin,
-	output  reg		[ASI_WIDTH-1:0]						epcq_dataoe,
-	
-	// ASMI PARALLEL interface
-	input   wire	[ASI_WIDTH-1:0]						ddasi_dataoe,
-	output  reg 	[ASI_WIDTH-1:0]						ddasi_dataout,
-	input   wire 										ddasi_dclk,
-	input   wire 	[CS_WIDTH-1:0] 						ddasi_scein,
-	input   reg		[ASI_WIDTH-1:0]  					ddasi_sdoin,
-	
-	input   wire										asmi_busy,
-	input   wire										asmi_data_valid,
-	input   wire	[7:0]  								asmi_dataout,
-	output  reg											asmi_clkin,
-	output  reg											asmi_reset,
-	output  reg		[CS_WIDTH-1:0] 						asmi_sce,
-	output	reg	    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr,
-	output  reg		[7:0]  								asmi_datain,
-	output  reg											asmi_fast_read,
-	output  wire										asmi_rden,
-	output  reg											asmi_shift_bytes,
-	output  reg 										asmi_en4b_addr,
-	output  wire										asmi_wren,
-	output  reg											asmi_write,
-	
-	input   wire										asmi_illegal_erase,
-	input   wire										asmi_illegal_write,
-	input   wire	[7:0]  								asmi_rdid_out,
-	input   wire	[7:0]  								asmi_status_out,
-	input   wire	[7:0]  								asmi_epcs_id,
-	output  reg											asmi_read_rdid,
-	output  reg											asmi_read_status,
-	output	reg											asmi_read_sid,
-	output  reg 										asmi_bulk_erase,
-	output  reg											asmi_sector_erase,
-	output  reg											asmi_sector_protect
-);
-
-	reg temp_mem_write, temp_mem_read, mem_write, mem_read, back_pressured_ctrl;
-	reg [ADDR_WIDTH-1:0] temp_mem_addr, mem_addr;		
-	reg [31:0] temp_mem_wrdata, mem_wrdata;
-	reg [3:0] temp_mem_byteenable, mem_byteenable;
-	reg [6:0] temp_mem_burstcount, mem_burstcount;
-	
-	wire back_pressured, temp_csr_waitrequest, temp_mem_waitrequest;
-
-	//-------------------- Arbitration logic between avalon csr and mem interface -----------
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			back_pressured_ctrl		<= 1'b0;
-		end 
-		else if (back_pressured) begin
-			back_pressured_ctrl		<= 1'b1;
-		end
-		else if (~temp_csr_waitrequest) begin
-			back_pressured_ctrl		<= 1'b0;
-		end
-	end
-
-	always @(posedge clk or negedge reset_n) begin
-		if (~reset_n) begin
-			mem_write 			<= 1'b0;
-			mem_read 			<= 1'b0;
-			mem_addr			<= {ADDR_WIDTH{1'b0}};
-			mem_wrdata			<= {32{1'b0}};
-			mem_byteenable		<= {4{1'b0}};
-			mem_burstcount		<= {7{1'b0}};
-		end 
-		else if ((avl_csr_write || avl_csr_read) && ~avl_csr_waitrequest && (avl_mem_write || avl_mem_read) && ~avl_mem_waitrequest) begin
-			// to back pressure master
-			mem_write 			<= avl_mem_write;
-			mem_read 			<= avl_mem_read;
-			mem_addr			<= avl_mem_addr;
-			mem_wrdata			<= avl_mem_wrdata;
-			mem_byteenable		<= avl_mem_byteenable;
-			mem_burstcount		<= avl_mem_burstcount;
-		end
-	end
-	
-	assign back_pressured	   = ((avl_csr_write || avl_csr_read) && ~temp_csr_waitrequest && (avl_mem_write || avl_mem_read)) ? 1'b1 : 1'b0; // to back pressure controller
-	assign avl_csr_waitrequest = (~avl_csr_write && ~avl_csr_read && back_pressured_ctrl) ? 1'b1 : temp_csr_waitrequest;
-	assign avl_mem_waitrequest = (back_pressured_ctrl) ? 1'b1 : temp_mem_waitrequest;
-	assign temp_mem_write	   = (back_pressured) ? 1'b0 :
-									(back_pressured_ctrl) ? mem_write : avl_mem_write;
-	assign temp_mem_read	   = (back_pressured) ? 1'b0 :
-									(back_pressured_ctrl) ? mem_read : avl_mem_read;
-	assign temp_mem_addr	   = (back_pressured) ? {ADDR_WIDTH{1'b0}} :
-									(back_pressured_ctrl) ? mem_addr : avl_mem_addr;
-	assign temp_mem_wrdata	   = (back_pressured) ? {32{1'b0}} :
-									(back_pressured_ctrl) ? mem_wrdata : avl_mem_wrdata;
-	assign temp_mem_byteenable = (back_pressured) ? {4{1'b0}} :
-									(back_pressured_ctrl) ? mem_byteenable : avl_mem_byteenable;
-	assign temp_mem_burstcount = (back_pressured) ? {7{1'b0}} :
-									(back_pressured_ctrl) ? mem_burstcount : avl_mem_burstcount;
-	
-	
-	//---------------------------------------------------------------------------------------//
-	
-	altera_epcq_controller #(
-		.CS_WIDTH		   (CS_WIDTH),
-		.DEVICE_FAMILY     (DEVICE_FAMILY),
-		.ADDR_WIDTH        (ADDR_WIDTH),
-		.ASMI_ADDR_WIDTH   (ASMI_ADDR_WIDTH),
-		.ASI_WIDTH         (ASI_WIDTH),
-		.CHIP_SELS	 (CHIP_SELS),
-		.ENABLE_4BYTE_ADDR (ENABLE_4BYTE_ADDR)
-	) controller (
-		.clk                  (clk),                  
-		.reset_n              (reset_n),              
-		.avl_csr_read         (avl_csr_read),         
-		.avl_csr_waitrequest  (temp_csr_waitrequest),  
-		.avl_csr_write        (avl_csr_write),        
-		.avl_csr_addr         (avl_csr_addr),         
-		.avl_csr_wrdata       (avl_csr_wrdata),       
-		.avl_csr_rddata       (avl_csr_rddata),       
-		.avl_csr_rddata_valid (avl_csr_rddata_valid), 
-		.avl_mem_write        (temp_mem_write),        
-		.avl_mem_burstcount   (temp_mem_burstcount),   
-		.avl_mem_waitrequest  (temp_mem_waitrequest),  
-		.avl_mem_read         (temp_mem_read),         
-		.avl_mem_addr         (temp_mem_addr),         
-		.avl_mem_wrdata       (temp_mem_wrdata),
-		.avl_mem_byteenable   (temp_mem_byteenable),
-		.avl_mem_rddata       (avl_mem_rddata),       
-		.avl_mem_rddata_valid (avl_mem_rddata_valid), 
-		.asmi_status_out      (asmi_status_out),      
-		.asmi_epcs_id         (asmi_epcs_id),         
-		.asmi_illegal_erase   (asmi_illegal_erase),   
-		.asmi_illegal_write   (asmi_illegal_write),   
-		.ddasi_dataoe         (ddasi_dataoe),         
-		.ddasi_dclk           (ddasi_dclk),           
-		.ddasi_scein          (ddasi_scein),          
-		.ddasi_sdoin          (ddasi_sdoin),          
-		.asmi_busy            (asmi_busy),            
-		.asmi_data_valid      (asmi_data_valid),      
-		.asmi_dataout         (asmi_dataout),         
-		.epcq_dataout         (epcq_dataout),         
-		.ddasi_dataout        (ddasi_dataout),        
-		.asmi_read_rdid       (asmi_read_rdid),       
-		.asmi_read_status     (asmi_read_status),     
-		.asmi_read_sid        (asmi_read_sid),        
-		.asmi_bulk_erase      (asmi_bulk_erase),      
-		.asmi_sector_erase    (asmi_sector_erase),    
-		.asmi_sector_protect  (asmi_sector_protect),  
-		.epcq_dclk            (epcq_dclk),            
-		.epcq_scein           (epcq_scein),           
-		.epcq_sdoin           (epcq_sdoin),           
-		.epcq_dataoe          (epcq_dataoe),          
-		.asmi_clkin           (asmi_clkin),           
-		.asmi_reset           (asmi_reset),           
-		.asmi_sce			  (asmi_sce),
-		.asmi_addr            (asmi_addr),            
-		.asmi_datain          (asmi_datain),          
-		.asmi_fast_read       (asmi_fast_read),       
-		.asmi_rden            (asmi_rden),            
-		.asmi_shift_bytes     (asmi_shift_bytes),     
-		.asmi_wren            (asmi_wren),            
-		.asmi_write           (asmi_write),           
-		.asmi_rdid_out        (asmi_rdid_out),        
-		.asmi_en4b_addr       (asmi_en4b_addr),       
-		.irq                  (irq)                   
-	);                                                
-
-endmodule

ip/altera_epcq_controller_mod/altera_epcq_controller_fifo.v

@@ -1,176 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo 
-
-// ============================================================
-// File Name: altera_epcq_controller_fifo.v
-// Megafunction Name(s):
-// 			scfifo
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 14.1.0 Internal Build 64 05/14/2014 PN Full Version
-// ************************************************************
-
-
-//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, the Altera Quartus II License Agreement,
-//the Altera MegaCore Function License Agreement, or other 
-//applicable license agreement, including, without limitation, 
-//that your use is for the sole purpose of programming logic 
-//devices manufactured by Altera and sold by Altera or its 
-//authorized distributors.  Please refer to the applicable 
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module altera_epcq_controller_fifo #(
-	parameter DEVICE_FAMILY = "CYCLONE V",
-	parameter MEMORY_TYPE	= "RAM_BLOCK_TYPE=MLAB"
-)(
-	clock,
-	data,
-	rdreq,
-	wrreq,
-	empty,
-	full,
-	q);
-
-	input	  clock;
-	input	[35:0]  data;
-	input	  rdreq;
-	input	  wrreq;
-	output	  empty;
-	output	  full;
-	output	[35:0]  q;
-
-	wire  sub_wire0;
-	wire  sub_wire1;
-	wire [35:0] sub_wire2;
-	wire  empty = sub_wire0;
-	wire  full = sub_wire1;
-	wire [35:0] q = sub_wire2[35:0];
-
-	scfifo	scfifo_component (
-				.clock (clock),
-				.data (data),
-				.rdreq (rdreq),
-				.wrreq (wrreq),
-				.empty (sub_wire0),
-				.full (sub_wire1),
-				.q (sub_wire2),
-				.aclr (),
-				.almost_empty (),
-				.almost_full (),
-				.sclr (),
-				.usedw ());
-	defparam
-		scfifo_component.add_ram_output_register = "OFF",
-		scfifo_component.intended_device_family = DEVICE_FAMILY,
-		scfifo_component.lpm_hint = MEMORY_TYPE,
-		scfifo_component.lpm_numwords = 1024,
-		scfifo_component.lpm_showahead = "ON",
-		scfifo_component.lpm_type = "scfifo",
-		scfifo_component.lpm_width = 36,
-		scfifo_component.lpm_widthu = 10,
-		scfifo_component.overflow_checking = "ON",
-		scfifo_component.underflow_checking = "ON",
-		scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "1024"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf

ip/altera_epcq_controller_mod/altera_epcq_controller_hw.tcl

@@ -1,453 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-# TCL File Generated by Component Editor 14.1
-# Fri May 09 18:08:10 MYT 2014
-# DO NOT MODIFY
-
-
-# 
-# altera_epcq_controller_core "Altera EPCQ Serial Flash controller core" v14.1
-# Altera Coorperation 2014.05.23.15:01:29
-# This component is a serial flash controller which allows user to access Altera EPCQ devices
-# 
-
-# 
-# request TCL package from ACDS 14.1
-# 
-package require -exact qsys 14.1
-
-
-
-# 
-# module altera_epcq_controller
-# 
-set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
-set_module_property NAME altera_epcq_controller_core
-set_module_property VERSION 16.1
-set_module_property INTERNAL true
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR "Altera Corporation"
-set_module_property DISPLAY_NAME "Altera EPCQ Serial Flash controller core"
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property HIDE_FROM_QUARTUS true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-set_module_property VALIDATION_CALLBACK "validate"
-# 
-# file sets
-# 
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_arb
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
-add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv 
-
-add_fileset SIM_VERILOG SIM_VERILOG "" ""
-set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_arb
-set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
-add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
-add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv
-
-#
-# add system info parameter
-add_parameter           deviceFeaturesSystemInfo   STRING 			"None"
-set_parameter_property  deviceFeaturesSystemInfo   system_info		"DEVICE_FEATURES"
-set_parameter_property  deviceFeaturesSystemInfo   VISIBLE false
-
-# 
-# parameters
-# 
-add_parameter           DEVICE_FAMILY		STRING          ""
-set_parameter_property  DEVICE_FAMILY		SYSTEM_INFO     "DEVICE_FAMILY"
-set_parameter_property  DEVICE_FAMILY		HDL_PARAMETER   true
-set_parameter_property  DEVICE_FAMILY		VISIBLE	      	false
-
-add_parameter ADDR_WIDTH INTEGER 19
-set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
-set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
-set_parameter_property ADDR_WIDTH DERIVED true
-set_parameter_property ADDR_WIDTH TYPE INTEGER
-set_parameter_property ADDR_WIDTH VISIBLE false
-set_parameter_property ADDR_WIDTH UNITS None
-set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}		
-set_parameter_property ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ASMI_ADDR_WIDTH INTEGER 24
-set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
-set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
-set_parameter_property ASMI_ADDR_WIDTH DERIVED true
-set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
-set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
-set_parameter_property ASMI_ADDR_WIDTH UNITS None
-set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}		
-set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ASI_WIDTH INTEGER 1
-set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
-set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
-set_parameter_property ASI_WIDTH DERIVED true
-set_parameter_property ASI_WIDTH TYPE INTEGER
-set_parameter_property ASI_WIDTH VISIBLE false
-set_parameter_property ASI_WIDTH UNITS None
-set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
-set_parameter_property ASI_WIDTH HDL_PARAMETER true
-
-add_parameter CS_WIDTH INTEGER 1
-set_parameter_property CS_WIDTH DEFAULT_VALUE 1
-set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
-set_parameter_property CS_WIDTH DERIVED true
-set_parameter_property CS_WIDTH TYPE INTEGER
-set_parameter_property CS_WIDTH VISIBLE false
-set_parameter_property CS_WIDTH UNITS None
-set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
-set_parameter_property CS_WIDTH HDL_PARAMETER true
-
-add_parameter CHIP_SELS INTEGER "1"
-set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
-set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
-set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
-set_parameter_property CHIP_SELS HDL_PARAMETER true
-set_parameter_property CHIP_SELS AFFECTS_GENERATION true
-
-add_parameter DDASI	INTEGER "0"
-set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
-set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
-set_parameter_property DDASI AFFECTS_GENERATION true
-set_parameter_property DDASI VISIBLE false
-set_parameter_property DDASI DERIVED false
-
-add_parameter ENABLE_4BYTE_ADDR	INTEGER "0"
-set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
-set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
-set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
-set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
-set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
-set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
-
-# SPI device selection
-add_parameter FLASH_TYPE STRING "EPCQ16"
-set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
-set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
-set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
-set_parameter_property FLASH_TYPE VISIBLE true
-set_parameter_property FLASH_TYPE DERIVED false
-
-add_parameter IO_MODE STRING "STANDARD"
-set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
-set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
-set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
-
-# 
-# display items
-# 
-
-
-# 
-# connection point clock_sink
-# 
-add_interface clock_sink clock end
-set_interface_property clock_sink clockRate 0
-set_interface_property clock_sink ENABLED true
-set_interface_property clock_sink EXPORT_OF ""
-set_interface_property clock_sink PORT_NAME_MAP ""
-set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
-set_interface_property clock_sink SVD_ADDRESS_GROUP ""
-
-add_interface_port clock_sink clk clk Input 1
-
-
-# 
-# connection point reset
-# 
-add_interface reset reset end
-set_interface_property reset associatedClock clock_sink
-set_interface_property reset synchronousEdges DEASSERT
-set_interface_property reset ENABLED true
-set_interface_property reset EXPORT_OF ""
-set_interface_property reset PORT_NAME_MAP ""
-set_interface_property reset CMSIS_SVD_VARIABLES ""
-set_interface_property reset SVD_ADDRESS_GROUP ""
-
-add_interface_port reset reset_n reset_n Input 1
-
-
-# 
-# connection point avl_csr
-# 
-add_interface avl_csr avalon end
-set_interface_property avl_csr addressUnits WORDS
-set_interface_property avl_csr associatedClock clock_sink
-set_interface_property avl_csr associatedReset reset
-set_interface_property avl_csr bitsPerSymbol 8
-set_interface_property avl_csr burstOnBurstBoundariesOnly false
-set_interface_property avl_csr burstcountUnits WORDS
-set_interface_property avl_csr explicitAddressSpan 0
-set_interface_property avl_csr holdTime 0
-set_interface_property avl_csr linewrapBursts false
-set_interface_property avl_csr maximumPendingReadTransactions 1
-set_interface_property avl_csr maximumPendingWriteTransactions 0
-set_interface_property avl_csr readLatency 0
-set_interface_property avl_csr readWaitTime 0
-set_interface_property avl_csr setupTime 0
-set_interface_property avl_csr timingUnits Cycles
-set_interface_property avl_csr writeWaitTime 0
-set_interface_property avl_csr ENABLED true
-set_interface_property avl_csr EXPORT_OF ""
-set_interface_property avl_csr PORT_NAME_MAP ""
-set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
-set_interface_property avl_csr SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_csr avl_csr_read read Input 1
-add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
-add_interface_port avl_csr avl_csr_write write Input 1
-add_interface_port avl_csr avl_csr_addr address Input 3
-add_interface_port avl_csr avl_csr_wrdata writedata Input 32
-add_interface_port avl_csr avl_csr_rddata readdata Output 32
-add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
-
-
-# 
-# connection point avl_mem
-# 
-add_interface avl_mem avalon end
-set_interface_property avl_mem addressUnits WORDS
-set_interface_property avl_mem associatedClock clock_sink
-set_interface_property avl_mem associatedReset reset
-set_interface_property avl_mem bitsPerSymbol 8
-set_interface_property avl_mem burstOnBurstBoundariesOnly false
-set_interface_property avl_mem burstcountUnits WORDS
-set_interface_property avl_mem explicitAddressSpan 0
-set_interface_property avl_mem holdTime 0
-set_interface_property avl_mem linewrapBursts true
-set_interface_property avl_mem maximumPendingReadTransactions 1
-set_interface_property avl_mem maximumPendingWriteTransactions 0
-set_interface_property avl_mem constantBurstBehavior true
-set_interface_property avl_mem readLatency 0
-set_interface_property avl_mem readWaitTime 0
-set_interface_property avl_mem setupTime 0
-set_interface_property avl_mem timingUnits Cycles
-set_interface_property avl_mem writeWaitTime 0
-set_interface_property avl_mem ENABLED true
-set_interface_property avl_mem EXPORT_OF ""
-set_interface_property avl_mem PORT_NAME_MAP ""
-set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
-set_interface_property avl_mem SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_mem avl_mem_write write Input 1
-add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
-add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
-add_interface_port avl_mem avl_mem_read read Input 1
-add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
-add_interface_port avl_mem avl_mem_wrdata writedata Input 32
-add_interface_port avl_mem avl_mem_rddata readdata Output 32
-add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
-add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
-
-
-# 
-# connection point conduit_out
-# 
-add_interface asmi_status_out conduit end
-add_interface_port asmi_status_out asmi_status_out conduit_status_out Input 8
-
-add_interface asmi_epcs_id conduit end
-add_interface_port asmi_epcs_id asmi_epcs_id conduit_epcs_id Input 8
-
-add_interface asmi_illegal_erase conduit end
-add_interface_port asmi_illegal_erase asmi_illegal_erase conduit_illegal_erase Input 1
-
-add_interface asmi_illegal_write conduit end
-add_interface_port asmi_illegal_write asmi_illegal_write conduit_illegal_write Input 1
-
-add_interface ddasi_dataoe conduit end
-add_interface_port ddasi_dataoe ddasi_dataoe conduit_ddasi_dataoe Input ASI_WIDTH
-
-add_interface ddasi_dclk conduit end
-add_interface_port ddasi_dclk ddasi_dclk conduit_ddasi_dclk Input 1
-
-add_interface ddasi_scein conduit end
-add_interface_port ddasi_scein ddasi_scein conduit_ddasi_scein Input CS_WIDTH
-
-add_interface ddasi_sdoin conduit end
-add_interface_port ddasi_sdoin ddasi_sdoin conduit_ddasi_sdoin Input ASI_WIDTH
-
-add_interface asmi_busy conduit end
-add_interface_port asmi_busy asmi_busy conduit_busy Input 1
-
-add_interface asmi_data_valid conduit end
-add_interface_port asmi_data_valid asmi_data_valid conduit_data_valid Input 1
-
-add_interface asmi_dataout conduit end
-add_interface_port asmi_dataout asmi_dataout conduit_dataout Input 8
-
-add_interface epcq_dataout conduit end
-add_interface_port epcq_dataout epcq_dataout conduit_epcq_dataout Input ASI_WIDTH
-
-add_interface ddasi_dataout conduit end
-add_interface_port ddasi_dataout ddasi_dataout conduit_ddasi_dataout Output ASI_WIDTH
-
-add_interface asmi_read_rdid conduit end
-add_interface_port asmi_read_rdid asmi_read_rdid conduit_read_rdid Output 1
-
-add_interface asmi_read_status conduit end
-add_interface_port asmi_read_status asmi_read_status conduit_read_status Output 1
-
-add_interface asmi_read_sid conduit end
-add_interface_port asmi_read_sid asmi_read_sid conduit_read_sid Output 1
-
-add_interface asmi_bulk_erase conduit end
-add_interface_port asmi_bulk_erase asmi_bulk_erase conduit_bulk_erase Output 1
-
-add_interface asmi_sector_erase conduit end
-add_interface_port asmi_sector_erase asmi_sector_erase conduit_sector_erase Output 1
-
-add_interface asmi_sector_protect conduit end
-add_interface_port asmi_sector_protect asmi_sector_protect conduit_sector_protect Output 1
-
-add_interface epcq_dclk conduit end
-add_interface_port epcq_dclk epcq_dclk conduit_epcq_dclk Output 1
-
-add_interface epcq_scein conduit end
-add_interface_port epcq_scein epcq_scein conduit_epcq_scein Output CS_WIDTH
-
-add_interface epcq_sdoin conduit end
-add_interface_port epcq_sdoin epcq_sdoin conduit_epcq_sdoin Output ASI_WIDTH
-
-add_interface epcq_dataoe conduit end
-add_interface_port epcq_dataoe epcq_dataoe conduit_epcq_dataoe Output ASI_WIDTH
-
-add_interface asmi_clkin conduit end
-add_interface_port asmi_clkin asmi_clkin conduit_clkin Output 1
-
-add_interface asmi_reset conduit end
-add_interface_port asmi_reset asmi_reset conduit_reset Output 1
-
-add_interface asmi_sce conduit end
-add_interface_port asmi_sce asmi_sce conduit_asmi_sce Output CS_WIDTH
-
-add_interface asmi_addr conduit end
-add_interface_port asmi_addr asmi_addr conduit_addr Output ASMI_ADDR_WIDTH
-
-add_interface asmi_datain conduit end
-add_interface_port asmi_datain asmi_datain conduit_datain Output 8
-
-add_interface asmi_fast_read conduit end
-add_interface_port asmi_fast_read asmi_fast_read conduit_fast_read Output 1
-
-add_interface asmi_rden conduit end
-add_interface_port asmi_rden asmi_rden conduit_rden Output 1
-
-add_interface asmi_shift_bytes conduit end
-add_interface_port asmi_shift_bytes asmi_shift_bytes conduit_shift_bytes Output 1
-
-add_interface asmi_wren conduit end
-add_interface_port asmi_wren asmi_wren conduit_wren Output 1
-
-add_interface asmi_write conduit end
-add_interface_port asmi_write asmi_write conduit_write Output 1
-
-add_interface asmi_rdid_out conduit end
-add_interface_port asmi_rdid_out asmi_rdid_out conduit_rdid_out Input 8
-
-add_interface asmi_en4b_addr conduit end
-add_interface_port asmi_en4b_addr asmi_en4b_addr conduit_en4b_addr Output 1
-
-# 
-# connection point interrupt_sender
-# 
-add_interface interrupt_sender interrupt end
-set_interface_property interrupt_sender associatedAddressablePoint avl_csr
-set_interface_property interrupt_sender associatedClock clock_sink
-set_interface_property interrupt_sender associatedReset reset
-set_interface_property interrupt_sender bridgedReceiverOffset ""
-set_interface_property interrupt_sender bridgesToReceiver ""
-set_interface_property interrupt_sender ENABLED true
-set_interface_property interrupt_sender EXPORT_OF ""
-set_interface_property interrupt_sender PORT_NAME_MAP ""
-set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
-set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
-
-add_interface_port interrupt_sender irq irq Output 1
-
-proc validate {} {
-	set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
-							"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
-							
-	set_parameter_property  FLASH_TYPE  	"ALLOWED_RANGES"  $all_supported_SPI_list
-	set DEVICE_FAMILY 		[ get_parameter_value DEVICE_FAMILY ]
-	set CHIP_SELS			    [ get_parameter_value CHIP_SELS]
-	set temp_addr_width 	[ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
-	set_parameter_value		ENABLE_4BYTE_ADDR	[ proc_get_derive_enable_2byte_addr  [ get_parameter_value FLASH_TYPE ] ]
-	
-	if { [ get_parameter_value ENABLE_4BYTE_ADDR ] } {
-		set_parameter_value ASMI_ADDR_WIDTH 32
-	} else {
-		set_parameter_value ASMI_ADDR_WIDTH 24
-	}
-	
-	# check whether devices supporting multiple flash - only for Arria 10
-	if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
-		set is_multi_flash_support	"true"
-		if {$CHIP_SELS eq 3 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 2]}
-		if {$CHIP_SELS eq 2 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 1]}
-		if {$CHIP_SELS eq 1 } {set_parameter_value 	ADDR_WIDTH 		$temp_addr_width }
-	} else {
-		set is_multi_flash_support	"false"
-		set_parameter_value 	ADDR_WIDTH 		$temp_addr_width
-	}
-	
-}
-
-proc proc_get_derive_enable_2byte_addr {flash_type} {
-    if { [ string match "*256*" "$flash_type" ] || [ string match "*512*" "$flash_type" ] || [ string match "*1024*" "$flash_type" ]} {
-		return true
-	} else {
-		return false
-	}
-}
-
-proc proc_get_derive_addr_width {flash_type} {
-    switch $flash_type {
-        "EPCS16" - "EPCQ16" {
-            return 19 
-        }
-        "EPCS64" - "EPCQ64" {
-            return 21
-        }
-        "EPCS128" - "EPCQ128" {
-            return 22
-        }
-		"EPCQ32" {
-            return 20
-		}
-        "EPCQ256" - "EPCQL256" {
-            return 23
-        }
-        "EPCQ512" - "EPCQL512" {
-            return 24
-        }
-        "EPCQL1024" {
-            return 25
-        }
-        default {
-            # Should never enter this function
-            send_message error "$flash_type is not a valid flash type"
-        }
-    
-    }
-}

ip/altera_epcq_controller_mod/altera_epcq_controller_sw.tcl

@@ -1,58 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-#
-# altera_epcq_controller_sw.tcl
-#
-
-# Create a new driver
-create_driver altera_epcq_controller_mod_driver
-
-# Associate it with some hardware known as "altera_epcq_controller"
-set_sw_property hw_class_name altera_epcq_controller_mod
-
-# The version of this driver
-set_sw_property version 14.1
-
-# This driver may be incompatible with versions of hardware less
-# than specified below. Updates to hardware and device drivers
-# rendering the driver incompatible with older versions of
-# hardware are noted with this property assignment.
-set_sw_property min_compatible_hw_version 14.1
-
-# Initialize the driver in alt_sys_init()
-set_sw_property auto_initialize true
-
-# This driver only works when the following combinations of interfaces 
-# are enabled and connected as a group of CSR interfaces.
-set_sw_property csr_interfaces "avl_mem,avl_csr"
-
-# The EPCQ interrupt has an interrupt but it is not used in the driver. 
-# These assignments are still required by the Nios II SBT
-set_sw_property isr_preemption_supported true
-set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
-
-# Location in generated BSP that above sources will be copied into
-set_sw_property bsp_subdirectory drivers
-
-# Header files
-add_sw_property include_source HAL/inc/altera_epcq_controller_mod.h
-add_sw_property include_source inc/altera_epcq_controller_mod_regs.h
-
-# C/C++ source files
-add_sw_property c_source HAL/src/altera_epcq_controller_mod.c
-
-
-# This driver supports HAL & UCOSII BSP (OS) types
-add_sw_property supported_bsp_type HAL 
-add_sw_property supported_bsp_type UCOSII

ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper.sv.terp

@@ -1,248 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-`timescale 1ps / 1ps
-
-${MULTICHIP}
-${DDASI_ON}		
-${SID_EN}
-${BULK_ERASE_EN}
-${4BYTE_ADDR_EN}
-
-module altera_epcq_controller_wrapper #(
-	parameter CS_WIDTH		= 1,
-	parameter DEVICE_FAMILY = "Arria V",
-	parameter ADDR_WIDTH	= 24,
-	parameter ASI_WIDTH		= 1,
-	parameter ENABLE_4BYTE_ADDR = 1,
-	parameter ASMI_ADDR_WIDTH = 22,
-	parameter CHIP_SELS       = 1
-)(
-	input 	wire		  								clk,
-	input 	wire		  								reset_n,
-	                                        			
-	// ports to access csr                        			
-	input 	wire										avl_csr_write,
-	input 	wire		  								avl_csr_read,
-	input 	wire 	[2:0] 								avl_csr_addr,
-	input 	wire 	[31:0] 								avl_csr_wrdata,
-	output 	wire	[31:0] 								avl_csr_rddata,
-	output 	wire		 								avl_csr_rddata_valid,
-	output 	wire			 							avl_csr_waitrequest,
-	                                        			
-	// ports to access memory        			
-	input	wire		  								avl_mem_write,
-	input	wire										avl_mem_read,
-	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
-	input	wire	[31:0]								avl_mem_wrdata,
-	input	wire	[6:0]								avl_mem_burstcount,
-	input	wire 	[3:0]								avl_mem_byteenable,
-	output	wire	[31:0]								avl_mem_rddata,
-	output	wire										avl_mem_rddata_valid,
-	output 	wire			 							avl_mem_waitrequest,
-
-`ifdef DDASI_ON
-	output 	wire	[ASI_WIDTH-1:0]						epcq_dataout, 
-    output 	wire			 							epcq_dclk,    
-    output 	wire	[CS_WIDTH-1:0]  					epcq_scein,   
-    output 	wire	[ASI_WIDTH-1:0]						epcq_sdoin,   
-    output 	wire	[ASI_WIDTH-1:0]						epcq_dataoe,  
-`endif
-
-	// interrupt signal
-	output	reg 										irq
-);
-
-`ifdef DDASI_ON
-	wire	[ASI_WIDTH-1:0]						ddasi_dataoe;
-	wire 	[ASI_WIDTH-1:0]						ddasi_dataout;
-	wire 										ddasi_dclk;
-	wire 	[CS_WIDTH-1:0]						ddasi_scein;
-	wire	[ASI_WIDTH-1:0]  					ddasi_sdoin;
-`endif
-	wire										asmi_busy;
-	wire										asmi_data_valid;
-	wire	[7:0]  								asmi_dataout;
-	wire										asmi_clkin;
-	wire										asmi_reset;
-`ifdef MULTICHIP
-	wire	[CS_WIDTH-1:0]  					asmi_sce;
-`endif
-	wire    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr;
-	wire	[7:0]  								asmi_datain;
-	wire										asmi_fast_read;
-	wire										asmi_rden;
-	wire										asmi_shift_bytes;
-	wire										asmi_wren;
-	wire										asmi_write;
-	
-	wire										asmi_illegal_erase;
-	wire										asmi_illegal_write;
-	wire	[7:0]  								asmi_rdid_out;
-	wire	[7:0]  								asmi_status_out;
-`ifdef ENABLE_SID
-	wire	[7:0]  								asmi_epcs_id;
-`endif
-	wire										asmi_read_rdid;
-	wire										asmi_read_status;
-	wire										asmi_read_sid;
-`ifdef ENABLE_4BYTE_ADDR_CODE
-	wire										asmi_en4b_addr;
-`endif
-`ifdef ENABLE_BULK_ERASE
-	wire										asmi_bulk_erase;
-`endif
-	wire										asmi_sector_erase;
-	wire										asmi_sector_protect;
-
-	altera_epcq_controller_core	#(
-		.DEVICE_FAMILY 		(DEVICE_FAMILY),
-		.ADDR_WIDTH			(ADDR_WIDTH),
-		.ASI_WIDTH			(ASI_WIDTH),
-		.ASMI_ADDR_WIDTH   	(ASMI_ADDR_WIDTH),
-		.CS_WIDTH			(CS_WIDTH),
-		.ENABLE_4BYTE_ADDR	(ENABLE_4BYTE_ADDR),
-		.CHIP_SELS          (CHIP_SELS)
-	) epcq_controller_inst (
-		.clk						 (clk					 ),
-		.reset_n                     (reset_n                ),
-		.avl_csr_write               (avl_csr_write          ),
-		.avl_csr_read                (avl_csr_read           ),
-		.avl_csr_addr                (avl_csr_addr           ),
-		.avl_csr_wrdata              (avl_csr_wrdata         ),
-		.avl_csr_rddata              (avl_csr_rddata         ),
-		.avl_csr_rddata_valid        (avl_csr_rddata_valid   ),
-		.avl_csr_waitrequest         (avl_csr_waitrequest    ),
-		.avl_mem_write               (avl_mem_write          ),
-		.avl_mem_read                (avl_mem_read           ),
-		.avl_mem_addr			     (avl_mem_addr			 ),					
-		.avl_mem_wrdata              (avl_mem_wrdata         ),
-		.avl_mem_burstcount          (avl_mem_burstcount     ),
-		.avl_mem_byteenable          (avl_mem_byteenable     ),
-		.avl_mem_rddata              (avl_mem_rddata         ),
-		.avl_mem_rddata_valid        (avl_mem_rddata_valid   ),
-		.avl_mem_waitrequest         (avl_mem_waitrequest    ),
-		.irq                         (irq                    ),
-`ifdef DDASI_ON
-		.epcq_dataout                (epcq_dataout           ),
-		.epcq_dclk                   (epcq_dclk              ),
-		.epcq_scein                  (epcq_scein             ),
-		.epcq_sdoin                  (epcq_sdoin             ),
-		.epcq_dataoe                 (epcq_dataoe            ),
-		.ddasi_dataoe                (ddasi_dataoe           ),
-		.ddasi_dataout               (ddasi_dataout          ),
-		.ddasi_dclk                  (ddasi_dclk             ),
-		.ddasi_scein                 (ddasi_scein            ),
-		.ddasi_sdoin                 (ddasi_sdoin            ),
-`else
-		.epcq_dataout                ({ASI_WIDTH{1'b0}}	     ),
-		.epcq_dclk                   (	         	         ),
-		.epcq_scein                  (	         	         ),
-		.epcq_sdoin                  (	         	         ),
-		.epcq_dataoe                 (	         	         ),
-		.ddasi_dataoe                ({ASI_WIDTH{1'b0}}      ),
-		.ddasi_dataout               (				         ),
-		.ddasi_dclk                  (1'b0	         	     ),
-		.ddasi_scein                 ({CS_WIDTH{1'b0}}       ),
-		.ddasi_sdoin                 ({ASI_WIDTH{1'b0}}      ),
-`endif
-		.asmi_busy                   (asmi_busy              ),
-		.asmi_data_valid             (asmi_data_valid        ),
-		.asmi_dataout                (asmi_dataout           ),
-		.asmi_clkin                  (asmi_clkin             ),
-		.asmi_reset                  (asmi_reset             ),
-`ifdef MULTICHIP
-		.asmi_sce					 (asmi_sce				),
-`else
-		.asmi_sce					 (						),
-`endif
-		.asmi_addr                   (asmi_addr              ),
-		.asmi_datain                 (asmi_datain            ),
-		.asmi_fast_read              (asmi_fast_read         ),
-		.asmi_rden                   (asmi_rden              ),
-		.asmi_shift_bytes            (asmi_shift_bytes       ),
-		.asmi_wren                   (asmi_wren              ),
-		.asmi_write                  (asmi_write             ),
-		.asmi_illegal_erase          (asmi_illegal_erase     ),
-		.asmi_illegal_write          (asmi_illegal_write     ),
-		.asmi_rdid_out               (asmi_rdid_out          ),
-		.asmi_status_out             (asmi_status_out        ),
-`ifdef ENABLE_SID
-		.asmi_epcs_id                (asmi_epcs_id			 ),
-		.asmi_read_sid               (asmi_read_sid			 ),
-`else
-		.asmi_epcs_id                ({8{1'b0}}			 	 ),
-		.asmi_read_sid               (						 ),
-`endif
-		.asmi_read_rdid              (asmi_read_rdid         ),
-		.asmi_read_status            (asmi_read_status       ),
-`ifdef ENABLE_4BYTE_ADDR_CODE
-		.asmi_en4b_addr              (asmi_en4b_addr         ),
-`else
-		.asmi_en4b_addr              (				         ),
-`endif
-`ifdef ENABLE_BULK_ERASE
-		.asmi_bulk_erase             (asmi_bulk_erase        ),
-`else
-		.asmi_bulk_erase             (				        ),
-`endif
-		.asmi_sector_erase           (asmi_sector_erase      ),
-		.asmi_sector_protect         (asmi_sector_protect    )
-	);
-	
-	altera_asmi_parallel asmi_parallel_inst (
-		.busy                   (asmi_busy              ),
-		.data_valid             (asmi_data_valid        ),
-		.dataout                (asmi_dataout           ),
-		.clkin                  (asmi_clkin             ),
-		.reset                  (asmi_reset             ),
-`ifdef MULTICHIP
-		.sce					(asmi_sce				),
-`endif
-		.addr                   (asmi_addr				),
-		.datain                 (asmi_datain            ),
-		.fast_read              (asmi_fast_read         ),
-		.rden                   (asmi_rden              ),
-		.shift_bytes            (asmi_shift_bytes       ),
-		.wren                   (asmi_wren              ),
-		.write                  (asmi_write             ),
-		.illegal_erase          (asmi_illegal_erase     ),
-		.illegal_write          (asmi_illegal_write     ),
-		.rdid_out               (asmi_rdid_out          ),
-		.status_out             (asmi_status_out        ),
-		.read_dummyclk			(1'b0),
-`ifdef ENABLE_SID
-		.epcs_id                (asmi_epcs_id           ),
-		.read_sid               (asmi_read_sid          ),
-`endif
-		.read_rdid              (asmi_read_rdid         ),
-		.read_status            (asmi_read_status       ),
-`ifdef ENABLE_4BYTE_ADDR_CODE
-		.en4b_addr              (asmi_en4b_addr         ),
-`endif
-`ifdef ENABLE_BULK_ERASE
-		.bulk_erase             (asmi_bulk_erase        ),
-`endif
-`ifdef DDASI_ON
-		.asmi_dataoe            (ddasi_dataoe           ),   
-		.asmi_dataout           (ddasi_dataout          ),   
-		.asmi_dclk              (ddasi_dclk             ),   
-		.asmi_scein             (ddasi_scein            ),   
-		.asmi_sdoin             (ddasi_sdoin            )    
-`endif           
-		.sector_erase           (asmi_sector_erase      ),
-		.sector_protect         (asmi_sector_protect    )
-	);
-	
-endmodule

ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper_hw.tcl

@@ -1,648 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-package require -exact qsys 14.1
-package require -exact altera_terp 1.0
-
-
-# 
-# module altera_trace_wrapper
-# 
-set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
-set_module_property NAME altera_epcq_controller_mod
-set_module_property VERSION 17.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property GROUP "Basic Functions/Configuration and Programming"
-set_module_property AUTHOR "Altera Corporation"
-set_module_property DISPLAY_NAME "Altera Serial Flash Controller"
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property HIDE_FROM_QUARTUS true
-set_module_property EDITABLE true
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-set_module_property ELABORATION_CALLBACK	elaboration
-
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH add_topwrapper_fileset_proc
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-
-add_fileset SIM_VERILOG SIM_VERILOG add_topwrapper_fileset_proc
-set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_wrapper
-set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
-# 
-# parameters
-#
-# +-----------------------------------
-# | device family info
-# +-----------------------------------
-set all_supported_device_families_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "Stratix IV" \
-											"Cyclone IV GX" "Cyclone IV E" "Cyclone III GL" "Arria II GZ" "Arria II GX"}
-									
-proc check_device_ini {device_families_list}     {
-
-    set enable_max10    [get_quartus_ini enable_max10_active_serial ENABLED]
-    
-    if {$enable_max10 == 1} {
-        lappend device_families_list    "MAX 10 FPGA"
-     } 
-    return $device_families_list
-}
-
-set device_list    [check_device_ini $all_supported_device_families_list]
-set_module_property SUPPORTED_DEVICE_FAMILIES    $device_list
-
-add_parameter 			DEVICE_FAMILY 	STRING
-set_parameter_property 	DEVICE_FAMILY 	SYSTEM_INFO 	{DEVICE_FAMILY}
-set_parameter_property 	DEVICE_FAMILY 	VISIBLE 		false
-set_parameter_property  DEVICE_FAMILY 	HDL_PARAMETER true
-
-add_parameter ASI_WIDTH INTEGER 1
-set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
-set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
-set_parameter_property ASI_WIDTH DERIVED true
-set_parameter_property ASI_WIDTH TYPE INTEGER
-set_parameter_property ASI_WIDTH VISIBLE false
-set_parameter_property ASI_WIDTH UNITS None
-set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
-set_parameter_property ASI_WIDTH HDL_PARAMETER true
-
-add_parameter CS_WIDTH INTEGER 1
-set_parameter_property CS_WIDTH DEFAULT_VALUE 1
-set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
-set_parameter_property CS_WIDTH DERIVED true
-set_parameter_property CS_WIDTH TYPE INTEGER
-set_parameter_property CS_WIDTH VISIBLE false
-set_parameter_property CS_WIDTH UNITS None
-set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
-set_parameter_property CS_WIDTH HDL_PARAMETER true
-
-add_parameter ADDR_WIDTH INTEGER 19
-set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
-set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
-set_parameter_property ADDR_WIDTH DERIVED true
-set_parameter_property ADDR_WIDTH TYPE INTEGER
-set_parameter_property ADDR_WIDTH VISIBLE false
-set_parameter_property ADDR_WIDTH UNITS None
-# 16M-19bit, 32M-20bit, 64M-21bit, 128M-22bit, 256M-23bit, 512M-24bit, 1024M-25bit, 2048M-26bit...
-set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}	
-set_parameter_property ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ASMI_ADDR_WIDTH INTEGER 24
-set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
-set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
-set_parameter_property ASMI_ADDR_WIDTH DERIVED true
-set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
-set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
-set_parameter_property ASMI_ADDR_WIDTH UNITS None
-set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}		
-set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
-
-add_parameter ENABLE_4BYTE_ADDR	INTEGER "0"
-set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
-set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
-set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
-set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
-set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
-set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
-
-# +-----------------------------------
-
-# add system info parameter
-add_parameter           deviceFeaturesSystemInfo   STRING 			"None"
-set_parameter_property  deviceFeaturesSystemInfo   system_info		"DEVICE_FEATURES"
-set_parameter_property  deviceFeaturesSystemInfo   VISIBLE false
-
-add_parameter DDASI	INTEGER "0"
-set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
-set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
-set_parameter_property DDASI AFFECTS_GENERATION true
-set_parameter_property DDASI VISIBLE false
-set_parameter_property DDASI DERIVED false
-
-add_parameter clkFreq LONG
-set_parameter_property clkFreq DEFAULT_VALUE {0}
-set_parameter_property clkFreq DISPLAY_NAME {clkFreq}
-set_parameter_property clkFreq VISIBLE {0}
-set_parameter_property clkFreq AFFECTS_GENERATION {1}
-set_parameter_property clkFreq HDL_PARAMETER {0}
-set_parameter_property clkFreq SYSTEM_INFO {clock_rate clk}
-set_parameter_property clkFreq SYSTEM_INFO_TYPE {CLOCK_RATE}
-set_parameter_property clkFreq SYSTEM_INFO_ARG {clock_sink}
-
-# 
-# connection point clock_sink
-# 
-add_interface clock_sink clock end
-set_interface_property clock_sink clockRate 0
-set_interface_property clock_sink ENABLED true
-set_interface_property clock_sink EXPORT_OF ""
-set_interface_property clock_sink PORT_NAME_MAP ""
-set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
-set_interface_property clock_sink SVD_ADDRESS_GROUP ""
-
-add_interface_port clock_sink clk clk Input 1
-
-
-# 
-# connection point reset
-# 
-add_interface reset reset end
-set_interface_property reset associatedClock clock_sink
-set_interface_property reset synchronousEdges DEASSERT
-set_interface_property reset ENABLED true
-set_interface_property reset EXPORT_OF ""
-set_interface_property reset PORT_NAME_MAP ""
-set_interface_property reset CMSIS_SVD_VARIABLES ""
-set_interface_property reset SVD_ADDRESS_GROUP ""
-
-add_interface_port reset reset_n reset_n Input 1
-
-
-# 
-# connection point avl_csr
-# 
-add_interface avl_csr avalon end
-set_interface_property avl_csr addressUnits WORDS
-set_interface_property avl_csr associatedClock clock_sink
-set_interface_property avl_csr associatedReset reset
-set_interface_property avl_csr bitsPerSymbol 8
-set_interface_property avl_csr burstOnBurstBoundariesOnly false
-set_interface_property avl_csr burstcountUnits WORDS
-set_interface_property avl_csr explicitAddressSpan 0
-set_interface_property avl_csr holdTime 0
-set_interface_property avl_csr linewrapBursts false
-set_interface_property avl_csr maximumPendingReadTransactions 1
-set_interface_property avl_csr maximumPendingWriteTransactions 0
-set_interface_property avl_csr readLatency 0
-set_interface_property avl_csr readWaitTime 0
-set_interface_property avl_csr setupTime 0
-set_interface_property avl_csr timingUnits Cycles
-set_interface_property avl_csr writeWaitTime 0
-set_interface_property avl_csr ENABLED true
-set_interface_property avl_csr EXPORT_OF ""
-set_interface_property avl_csr PORT_NAME_MAP ""
-set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
-set_interface_property avl_csr SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_csr avl_csr_read read Input 1
-add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
-add_interface_port avl_csr avl_csr_write write Input 1
-add_interface_port avl_csr avl_csr_addr address Input 3
-add_interface_port avl_csr avl_csr_wrdata writedata Input 32
-add_interface_port avl_csr avl_csr_rddata readdata Output 32
-add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
-
-# 
-# connection point avl_mem
-# 
-add_interface avl_mem avalon end
-set_interface_property avl_mem addressUnits WORDS
-set_interface_property avl_mem associatedClock clock_sink
-set_interface_property avl_mem associatedReset reset
-set_interface_property avl_mem bitsPerSymbol 8
-set_interface_property avl_mem burstOnBurstBoundariesOnly false
-set_interface_property avl_mem burstcountUnits WORDS
-set_interface_property avl_mem explicitAddressSpan 0
-set_interface_property avl_mem holdTime 0
-set_interface_property avl_mem linewrapBursts true
-set_interface_property avl_mem maximumPendingReadTransactions 1
-set_interface_property avl_mem maximumPendingWriteTransactions 0
-set_interface_property avl_mem constantBurstBehavior true
-set_interface_property avl_mem readLatency 0
-set_interface_property avl_mem readWaitTime 0
-set_interface_property avl_mem setupTime 0
-set_interface_property avl_mem timingUnits Cycles
-set_interface_property avl_mem writeWaitTime 0
-set_interface_property avl_mem ENABLED true
-set_interface_property avl_mem EXPORT_OF ""
-set_interface_property avl_mem PORT_NAME_MAP ""
-set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
-set_interface_property avl_mem SVD_ADDRESS_GROUP ""
-
-add_interface_port avl_mem avl_mem_write write Input 1
-add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
-add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
-add_interface_port avl_mem avl_mem_read read Input 1
-add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
-add_interface_port avl_mem avl_mem_wrdata writedata Input 32
-add_interface_port avl_mem avl_mem_rddata readdata Output 32
-add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
-add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
-
-# 
-# connection point interrupt_sender
-# 
-add_interface interrupt_sender interrupt end
-set_interface_property interrupt_sender associatedAddressablePoint avl_csr
-set_interface_property interrupt_sender associatedClock clock_sink
-set_interface_property interrupt_sender associatedReset reset
-set_interface_property interrupt_sender bridgedReceiverOffset ""
-set_interface_property interrupt_sender bridgesToReceiver ""
-set_interface_property interrupt_sender ENABLED true
-set_interface_property interrupt_sender EXPORT_OF ""
-set_interface_property interrupt_sender PORT_NAME_MAP ""
-set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
-set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
-
-add_interface_port interrupt_sender irq irq Output 1
-
-proc proc_get_derive_addr_width {flash_type} {
-    switch $flash_type {
-        "EPCS16" - "EPCQ16" {
-            return 19 
-        }
-        "EPCS64" - "EPCQ64" {
-            return 21
-        }
-        "EPCS128" - "EPCQ128" {
-            return 22
-        }
-		"EPCQ32" {
-            return 20
-		}
-        "EPCQ256" - "EPCQL256" {
-            return 23
-        }
-        "EPCQ512" - "EPCQL512" {
-            return 24
-        }
-        "EPCQL1024" {
-            return 25
-        }
-        default {
-            # Should never enter this function
-            send_message error "$flash_type is not a valid flash type"
-        }
-    
-    }
-}
-
-set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
-							"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
-							
-# SPI device selection
-add_parameter FLASH_TYPE STRING "EPCQ16"
-set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
-set_parameter_property FLASH_TYPE ALLOWED_RANGES $all_supported_SPI_list
-set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
-set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
-set_parameter_property FLASH_TYPE VISIBLE true
-set_parameter_property FLASH_TYPE DERIVED false
-
-add_parameter IO_MODE STRING "STANDARD"
-set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
-set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
-set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
-
-add_parameter CHIP_SELS INTEGER "1"
-set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
-set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
-set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
-set_parameter_property CHIP_SELS HDL_PARAMETER true
-set_parameter_property CHIP_SELS AFFECTS_GENERATION true
-#
-# Add instance 
-#
-proc add_topwrapper_fileset_proc {altera_epcq_controller} {
-	# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
-	set supported_4byte_addr 	{"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
-	set DDASI 					[ get_parameter_value DDASI ]
-	set DEVICE_FAMILY 			[ get_parameter_value DEVICE_FAMILY ]
-	set FLASH_TYPE 				[ get_parameter_value FLASH_TYPE ]
-	set ADDR_WIDTH				[ get_parameter_value ADDR_WIDTH ]
-	set is_4byte_addr_support	"false"
-	
-	# check whether devices supporting multiple flash - only for Arria 10
-	if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
-		set MULTICHIP 1
-	} else {
-		set MULTICHIP 0
-	}
-	
-	if { $DDASI eq "1" } {
-		set DDASI_ON 1
-	} else {
-		set DDASI_ON 0
-	}
-	
-	if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
-		set ENABLE_SID 1
-	} else {
-		set ENABLE_SID 0
-	}
-	
-	if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
-		set ENABLE_BULK_ERASE 0
-	} else {
-		set ENABLE_BULK_ERASE 1
-	}
-	
-	 # check whether SPI device support 4-byte addressing
-	foreach re_spi_1   $supported_4byte_addr {
-		if {$re_spi_1 eq $FLASH_TYPE} {
-			set is_4byte_addr_support	"true"
-			break;
-		 }
-	 }
-	 
-	if {$is_4byte_addr_support eq "true"} {
-		set ENABLE_4BYTE_ADDR_CODE 1
-	} else {
-		set ENABLE_4BYTE_ADDR_CODE 0
-	}
-	
-	# ---------------------------------
-	#   Terp for top level wrapper
-	# ---------------------------------
-	#Do Terp
-	set template_file [ file join "./" "altera_epcq_controller_wrapper.sv.terp" ]  
-	set template   [ read [ open $template_file r ] ]
-	
-	if {$DDASI_ON} {
-		set params(DDASI_ON) 		"`define DDASI_ON" 	
-	} else {
-		set params(DDASI_ON) 		"" 	
-	}
-	
-	if {$MULTICHIP} {
-		set params(MULTICHIP) 		"`define MULTICHIP" 	
-	} else {
-		set params(MULTICHIP) 		"" 	
-	}
-	
-	if {$ENABLE_SID} {
-		set params(SID_EN) 			"`define ENABLE_SID"
-	} else {
-		set params(SID_EN) 			""
-	}
-	
-	if {$ENABLE_BULK_ERASE} {
-		set params(BULK_ERASE_EN) 	"`define ENABLE_BULK_ERASE"
-	} else {
-		set params(BULK_ERASE_EN) 	""
-	}
-	
-	if {$ENABLE_4BYTE_ADDR_CODE} {
-		set params(4BYTE_ADDR_EN) 		"`define ENABLE_4BYTE_ADDR_CODE"
-	} else {
-		set params(4BYTE_ADDR_EN) 		""
-	}
-	
-	set result   					[ altera_terp $template params ]
-	
-	#Add top wrapper file
-	add_fileset_file ./altera_epcq_controller_wrapper.sv SYSTEM_VERILOG TEXT $result 
-}
-
-# This proc is called by elaboration proc to set embeddedsw C Macros assignments 
-# used by downstream tools
-proc set_cmacros {is_qspi flash_type} {
-    if {$is_qspi eq "true"} {
-        set_module_assignment embeddedsw.CMacro.IS_EPCS 0
-    } else {
-        set_module_assignment embeddedsw.CMacro.IS_EPCS 1
-    }
-
-    #string name of flash
-    set_module_assignment embeddedsw.CMacro.FLASH_TYPE $flash_type
-
-    #page size in bytes
-    set_module_assignment embeddedsw.CMacro.PAGE_SIZE 256
-    
-    #sector and subsector size in bytes
-    set_module_assignment embeddedsw.CMacro.SUBSECTOR_SIZE 4096
-    set_module_assignment embeddedsw.CMacro.SECTOR_SIZE 65536
-
-    #set number of sectors
-    switch $flash_type {
-        "EPCS16" - "EPCQ16" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 32
-        }
-        "EPCQ32" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 64
-		}
-        "EPCS64" - "EPCQ64" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 128
-        }
-        "EPCS128" - "EPCQ128" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 256
-        }
-        "EPCQ256" - "EPCQL256" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 512
-        }
-        "EPCQ512" - "EPCQL512" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 1024
-        }
-        "EPCQL1024" {
-            set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 2048
-        }
-        default {
-            # Should never enter this function
-            send_message error "$flash_type is not a valid flash type"
-        }
-    }
-}
-
-proc elaboration {} {
-	# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
-	set supported_4byte_addr 	{"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
-	set DDASI_ON 				[ get_parameter_value DDASI ]
-	set FLASH_TYPE 				[ get_parameter_value FLASH_TYPE ]
-	set IO_MODE 				[ get_parameter_value IO_MODE ]
-	set DEVICE_FAMILY 			[ get_parameter_value DEVICE_FAMILY ]
-	set ASI_WIDTH 				[ get_parameter_value ASI_WIDTH ]
-	set CS_WIDTH 				[ get_parameter_value CS_WIDTH ]
-	set ASMI_ADDR_WIDTH 		[ get_parameter_value ASMI_ADDR_WIDTH ]
-	set CHIP_SELS			    [ get_parameter_value CHIP_SELS]
-	set temp_addr_width 		[ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
-	set clkFreq 				[ get_parameter_value clkFreq ]
-	set is_4byte_addr_support	"false"
-	set is_qspi					"false"
-
-    # we're not using slow and expensive EPCS flash, thus higher frequency allowed
-	if { $clkFreq > 50000000 } {
-		send_message error "The maximum input clock frequency for Altera Serial Flash controller is 25Mhz."
-	}
-	
-	# check whether SPI device support 4-byte addressing
-	foreach re_spi_1   $supported_4byte_addr {
-		if {$re_spi_1 eq $FLASH_TYPE} {
-			set is_4byte_addr_support	"true"
-			break;
-		 }
-	 }
-	 
-	if {$is_4byte_addr_support eq "true"} {
-		set_parameter_value 	ENABLE_4BYTE_ADDR "1"
-		set_parameter_value		ASMI_ADDR_WIDTH 32
-	} else {
-		set_parameter_value 	ENABLE_4BYTE_ADDR "0"
-		set_parameter_value		ASMI_ADDR_WIDTH 24
-	}
-	
-	# check whether devices supporting multiple flash - only for Arria 10
-	if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
-		set is_multi_flash_support	"true"
-		if {$CHIP_SELS eq 3 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 2]}
-		if {$CHIP_SELS eq 2 } {set_parameter_value 	ADDR_WIDTH 		[ expr $temp_addr_width + 1]}
-		if {$CHIP_SELS eq 1 } {set_parameter_value 	ADDR_WIDTH 		$temp_addr_width }
-	} else {
-		set is_multi_flash_support	"false"
-		set_parameter_value 	ADDR_WIDTH 		$temp_addr_width
-	}
-	
-	
-	set_instance_parameter_value	altera_epcq_controller_core DDASI $DDASI_ON
-	set_instance_parameter_value	altera_epcq_controller_core FLASH_TYPE $FLASH_TYPE
-	set_instance_parameter_value	altera_epcq_controller_core IO_MODE $IO_MODE
-	set_instance_parameter_value	altera_epcq_controller_core ASI_WIDTH $ASI_WIDTH
-	set_instance_parameter_value	altera_epcq_controller_core CS_WIDTH $CS_WIDTH
-	set_instance_parameter_value	altera_epcq_controller_core CHIP_SELS $CHIP_SELS
-	set_instance_parameter_value	altera_epcq_controller_core ASMI_ADDR_WIDTH [ get_parameter_value ASMI_ADDR_WIDTH ]
-	set_instance_parameter_value	altera_epcq_controller_core ADDR_WIDTH [ get_parameter_value ADDR_WIDTH ]
-	set_instance_parameter_value	altera_epcq_controller_core ENABLE_4BYTE_ADDR [ get_parameter_value ENABLE_4BYTE_ADDR ]
-
-	set QSPI_list {"EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" \
-					"N25Q512" "S25FL127S"}
-	
-	# devices that supported QSPI - Quad/Dual data width, asmi_dataout, asmi_sdoin, asmi_dataoe
-	set supported_QSPI_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V"}
-	
-	# devices that supported simulation
-	set supported_sim_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "MAX 10 FPGA"}
-	
-	# check whether is QSPI devices
-	foreach re_spi_0   $QSPI_list {
-		if {$re_spi_0 eq $FLASH_TYPE} { 
-			set is_qspi		"true"
-			break;
-		 }
-	 }
-	 
-	if {[check_device_family_equivalence $DEVICE_FAMILY $supported_QSPI_devices_list]} {
-		set is_qspi_devices_list	"true"
-	} else {
-		set is_qspi_devices_list	"false"
-	}
-	
-	if {[check_device_family_equivalence $DEVICE_FAMILY $supported_sim_devices_list]} {
-		set is_sim_devices_list	"true"
-	} else {
-		set is_sim_devices_list	"false"
-	}
-	
-	if {$is_qspi_devices_list eq "true" && $is_qspi eq "true"} {
-		set_parameter_property	IO_MODE	ENABLED		true
-		set_instance_parameter_value 	altera_asmi_parallel DATA_WIDTH 		$IO_MODE
-		set_parameter_value ASI_WIDTH 4
-    } else {
-		set_parameter_property	IO_MODE	ENABLED		false
-		set_parameter_value ASI_WIDTH 1
-	}
-	
-	if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
-		set_instance_parameter_value 	altera_asmi_parallel gui_bulk_erase 		false
-		set ENABLE_BULK_ERASE 0
-	} else {
-		set_instance_parameter_value 	altera_asmi_parallel gui_bulk_erase 		true
-		set ENABLE_BULK_ERASE 1
-	}
-	
-	if { $is_multi_flash_support eq "true"} {
-		set_parameter_value CS_WIDTH 3
-		set_parameter_property	CHIP_SELS	ENABLED		true
-	} else {
-		set_parameter_value CS_WIDTH 1
-		set_parameter_property	CHIP_SELS	ENABLED		false
-	}
-	
-	set_instance_parameter_value 	altera_asmi_parallel EPCS_TYPE 				$FLASH_TYPE
-	set_instance_parameter_value 	altera_asmi_parallel gui_fast_read 			true
-	set_instance_parameter_value 	altera_asmi_parallel gui_page_write 		true
-	
-	if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
-		set_instance_parameter_value 	altera_asmi_parallel gui_read_sid 		true
-	} else {
-		set_instance_parameter_value 	altera_asmi_parallel gui_read_sid 		false
-	}
-	
-	set_instance_parameter_value 	altera_asmi_parallel gui_read_rdid 			true
-	set_instance_parameter_value 	altera_asmi_parallel gui_read_status 		true
-	set_instance_parameter_value 	altera_asmi_parallel gui_sector_erase 		true
-	set_instance_parameter_value 	altera_asmi_parallel gui_sector_protect 	true
-	set_instance_parameter_value 	altera_asmi_parallel gui_wren 				true
-	set_instance_parameter_value 	altera_asmi_parallel gui_write 				true
-	set_instance_parameter_value 	altera_asmi_parallel gui_read_dummyclk		true
-	set_instance_parameter_value 	altera_asmi_parallel PAGE_SIZE 				256
-	set_instance_parameter_value 	altera_asmi_parallel gui_use_asmiblock		$DDASI_ON
-	
-	if {$is_sim_devices_list eq "true"} {
-		set_instance_parameter_value 	altera_asmi_parallel ENABLE_SIM			true
-	} else {
-		set_instance_parameter_value 	altera_asmi_parallel ENABLE_SIM			false
-	}
-
-    set_cmacros $is_qspi $FLASH_TYPE
-}
-
-# add ASMI PARALLEL
-add_hdl_instance 		altera_asmi_parallel altera_asmi_parallel
-
-# add EPCQ CONTROLLER
-add_hdl_instance 		altera_epcq_controller_core altera_epcq_controller_core
-
-# +-------------------------------------
-# | Add settings needed by Nios tools
-# +-------------------------------------
-# Tells us component is a flash 
-set_module_assignment embeddedsw.memoryInfo.IS_FLASH 1
-
-# interface assignments for embedded software
-set_interface_assignment avl_mem embeddedsw.configuration.isFlash 1
-set_interface_assignment avl_mem embeddedsw.configuration.isMemoryDevice 1
-set_interface_assignment avl_mem embeddedsw.configuration.isNonVolatileStorage 1
-set_interface_assignment avl_mem embeddedsw.configuration.isPrintableDevice 0
-
-# These assignments tells tools to create byte-addressed .hex files only
-set_module_assignment embeddedsw.memoryInfo.GENERATE_HEX 1
-set_module_assignment embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX 1
-set_module_assignment embeddedsw.memoryInfo.GENERATE_DAT_SYM 0
-set_module_assignment embeddedsw.memoryInfo.GENERATE_FLASH 0
-
-# Width of memory
-set_module_assignment embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 32
-
-# Output directories for programming files
-#set_module_assignment embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR {SIM_DIR}
-#set_module_assignment embeddedsw.memoryInfo.FLASH_INSTALL_DIR {APP_DIR}
-set_module_assignment embeddedsw.memoryInfo.HEX_INSTALL_DIR {QPF_DIR}
-
-# Module assignments related to names of simulation files
-#set_module_assignment postgeneration.simulation.init_file.param_name {INIT_FILENAME}
-#set_module_assignment postgeneration.simulation.init_file.type {MEM_INIT}
-
-# +-------------------------------------
-# | Add settings needed by DTG tools
-# +-------------------------------------
-# add device tree properties
-set_module_assignment embeddedsw.dts.vendor "altr"
-set_module_assignment embeddedsw.dts.name "epcq"
-set_module_assignment embeddedsw.dts.group "epcq"
-set_module_assignment embeddedsw.dts.compatible "altr,epcq-1.0"
-
-## Add documentation links for user guide and/or release notes
-add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1431459459085 
-add_documentation_link "Release Notes" https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300

ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h

@@ -1,260 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-*                                                                             *
-******************************************************************************/
-
-#ifndef __ALTERA_EPCQ_CONTROLLER_REGS_H__
-#define __ALTERA_EPCQ_CONTROLLER_REGS_H__
-
-#include <io.h>
-
-/*
- * EPCQ_RD_STATUS register offset
- *
- * The EPCQ_RD_STATUS register contains information from the read status 
- * register operation. A full description of the register can be found in the 
- * data sheet,
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_STATUS_REG                       (0x0)
-
-/*
- * EPCQ_RD_STATUS register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG, data)
-
-/*
- * EPCQ_RD_STATUS register description macros
- */
-
-/** Write in progress bit */
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK                  (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_AVAILABLE             (0x00000000)
-#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY                  (0x00000001)
-/** When to time out a poll of the write in progress bit */
-/* 0.7 sec time out */
-#define ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE    		    700000 
-
-/*
- * EPCQ_RD_SID register offset
- *
- * The EPCQ_RD_SID register contains the information from the read silicon ID 
- * operation and can be used to determine what type of EPCS device we have.
- * Only support in EPCS16 and EPCS64.
- *
- * This register is valid only if the device is an EPCS.
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_SID_REG                          (0x4)
-
-/*
- * EPCQ_RD_SID register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_SID(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_SID(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG, data)
-
-/*
- * EPCQ_RD_SID register description macros
- * 
- * Specific device values obtained from Table 14 of: 
- * "Serial Configuration (EPCS) Devices Datasheet"
- */
-#define ALTERA_EPCQ_CONTROLLER_SID_MASK                         (0x000000FF)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS16                       (0x00000014)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS64                       (0x00000016)
-#define ALTERA_EPCQ_CONTROLLER_SID_EPCS128                      (0x00000018)
-
-/*
- * EPCQ_RD_RDID register offset
- *
- * The EPCQ_RD_RDID register contains the information from the read memory 
- * capacity operation and can be used to determine what type of EPCQ device 
- * we have.
- *
- * This register is only valid if the device is an EPCQ.
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_RDID_REG                         (0x8)
-
-/*
- * EPCQ_RD_RDID register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_RDID(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_RDID(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG, data)
-
-/*
- * EPCQ_RD_RDID register description macros
- * 
- * Specific device values obtained from Table 28 of: 
- *  "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
- *  Devices Datasheet"
- */
-#define ALTERA_EPCQ_CONTROLLER_RDID_MASK                         (0x000000FF)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16                       (0x00000015)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32                       (0x00000016)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64                       (0x00000017)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128                      (0x00000018)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256                      (0x00000019)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512                      (0x00000020)
-#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024                     (0x00000021)
-
-/*
- * EPCQ_MEM_OP register offset
- *
- * The EPCQ_MEM_OP register is used to do memory protect and erase operations
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_REG                       (0xC)
-
-/*
- * EPCQ_MEM_OP register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG, data)
-
-/*
- * EPCQ_MEM_OP register description macros
- */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_CMD_MASK                  (0x00000003)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_BULK_ERASE_CMD            (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
-
-/** see datasheet for sector values */
-#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
-
-/*
- * EPCQ_ISR register offset
- *
- * The EPCQ_ISR register is used to determine whether an invalid write or erase 
- * operation triggered an interrupt
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_ISR_REG                          (0x10)
-
-/*
- * EPCQ_ISR register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_ISR(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_ISR(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG, data)
-
-/*
- * EPCQ_ISR register description macros
- */
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
-
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
-
-
-/*
- * EPCQ_IMR register offset
- *
- * The EPCQ_IMR register is used to mask the invalid erase or the invalid write 
- * interrupts.
- *
- */
-#define ALTERA_EPCQ_CONTROLLER_IMR_REG                          (0x14)
-
-/*
- * EPCQ_IMR register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CONTROLLER_IMR(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
-
-#define IORD_ALTERA_EPCQ_CONTROLLER_IMR(base) \
-    IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
-
-#define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG, data)
-
-/*
- * EPCQ_IMR register description macros
- */
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
-
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
-#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
-
-/*
- * EPCQ_CHIP_SELECT register offset
- *
- * The EPCQ_CHIP_SELECT register is used to issue chip select 
- */
-#define ALTERA_EPCQ_CHIP_SELECT_REG                          (0x18)
-
-/*
- * EPCQ_CHIP_SELECT register access macros
- */
-#define IOADDR_ALTERA_EPCQ_CHIP_SELECT(base) \
-    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CHIP_SELECT_REG)
-
-#define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \
-    IOWR_32DIRECT(base, ALTERA_EPCQ_CHIP_SELECT_REG, data)
-
-/*
- * EPCQ_CHIP_SELECT register description macros
- */
-#define ALTERA_EPCQ_CHIP1_SELECT        (0x00000001)
-#define ALTERA_EPCQ_CHIP2_SELECT        (0x00000002)
-#define ALTERA_EPCQ_CHIP3_SELECT        (0x00000003)
-
-#endif /* __ALTERA_EPCQ_CONTROLLER_REGS_H__ */

ip/altera_jtag_avalon_master_mod/altera_jtag_avalon_master_mod_hw.tcl

@@ -0,0 +1,246 @@
+package require -exact sopc 9.1
+
+# +-----------------------------------
+# | module altera_jtag_avalon_master_mod
+# |
+set_module_property NAME altera_jtag_avalon_master_mod
+set_module_property DESCRIPTION "The JTAG to Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using the new JTAG channel."
+set_module_property VERSION "20.1"
+set_module_property GROUP "Basic Functions/Bridges and Adaptors/Memory Mapped"
+set_module_property AUTHOR  "Altera Corporation"
+set_module_property DISPLAY_NAME "JTAG to Avalon Master Bridge (customized)"
+set_module_property DATASHEET_URL "http://www.altera.com/literature/hb/nios2/qts_qii55011.pdf"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE false
+set_module_property ANALYZE_HDL false
+set_module_property VALIDATION_CALLBACK validate
+set_module_property COMPOSE_CALLBACK compose
+
+set_module_assignment debug.hostConnection {type jtag id 110:132}
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# |
+add_parameter USE_PLI INTEGER 0
+set_parameter_property USE_PLI DISPLAY_NAME "Use Simulation Link Mode"
+set_parameter_property USE_PLI DISPLAY_HINT boolean
+set_parameter_property USE_PLI UNITS None
+set_parameter_property USE_PLI HDL_PARAMETER true
+
+add_parameter PLI_PORT INTEGER 50000
+set_parameter_property PLI_PORT DISPLAY_NAME "Simulation Link Server Port"
+set_parameter_property PLI_PORT UNITS None
+set_parameter_property PLI_PORT VISIBLE true
+set_parameter_property PLI_PORT ENABLED false
+set_parameter_property PLI_PORT HDL_PARAMETER true
+
+add_parameter COMPONENT_CLOCK INTEGER 0
+set_parameter_property COMPONENT_CLOCK SYSTEM_INFO { CLOCK_RATE clock }
+set_parameter_property COMPONENT_CLOCK VISIBLE false
+
+add_parameter           FAST_VER              "INTEGER" "0" ""
+set_parameter_property  FAST_VER              "VISIBLE" true
+set_parameter_property  FAST_VER              "DISPLAY_NAME" "Enhanced transaction master"
+set_parameter_property  FAST_VER              "DESCRIPTION"  "Increase transaction master throughput"
+set_parameter_property  FAST_VER              "DISPLAY_HINT" "boolean"
+set_parameter_property  FAST_VER              "STATUS" experimental
+
+add_parameter           FIFO_DEPTHS           "INTEGER" "2" ""
+set_parameter_property  FIFO_DEPTHS           "VISIBLE" true
+set_parameter_property  FIFO_DEPTHS           "HDL_PARAMETER" true
+set_parameter_property  FIFO_DEPTHS           "ALLOWED_RANGES" "2:8192"
+set_parameter_property  FIFO_DEPTHS           "DISPLAY_NAME" "FIFO depth"
+set_parameter_property  FIFO_DEPTHS           "DESCRIPTION"  "User need to tweak this to find the sweet spot"
+set_parameter_property  FIFO_DEPTHS           "STATUS" experimental
+
+add_parameter USE_MEMORY_BLOCKS INTEGER 0
+set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks instead of LEs"
+set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
+set_parameter_property USE_MEMORY_BLOCKS UNITS None
+set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
+# |
+# +-----------------------------------
+# +-----------------------------------
+# | Validate
+# |
+proc validate {} {
+    set use_pli [ get_parameter_value USE_PLI ]
+    set use_fast [ get_parameter_value FAST_VER ]
+    if {$use_pli == ""} {
+        set_parameter_value USE_PLI 0
+        set use_pli 0
+    }
+    if {$use_fast == ""} {
+        set_parameter_value FAST_VER 0
+        set use_fast 0
+    }
+    if {$use_pli == 0} {
+      set_parameter_property PLI_PORT ENABLED false
+    } else {
+      set_parameter_property PLI_PORT ENABLED true
+    }
+    if {$use_fast == 0} {
+        set_parameter_property FIFO_DEPTHS ENABLED false
+    } else {
+        set_parameter_property FIFO_DEPTHS ENABLED true
+    }
+}
+# |
+# +-----------------------------------
+# +-----------------------------------
+# | Compose
+# |
+proc compose {} {
+
+    # +-----------------------------------
+    # | submodule instantiation
+    # |
+    #add_instance clk_src     clock_source
+    add_instance  clk_src    altera_clock_bridge
+    add_instance  clk_rst    altera_reset_bridge
+    add_instance jtag_phy_embedded_in_jtag_master altera_jtag_dc_streaming
+    add_instance timing_adt  timing_adapter
+    add_instance fifo        altera_avalon_sc_fifo
+    add_instance b2p         altera_avalon_st_bytes_to_packets
+    add_instance p2b         altera_avalon_st_packets_to_bytes
+    add_instance transacto   altera_avalon_packets_to_master
+    add_instance b2p_adapter channel_adapter
+    add_instance p2b_adapter channel_adapter
+
+    # altera_reset_bridge parameters
+    set_instance_parameter clk_rst SYNCHRONOUS_EDGES none
+    # altera_jtag_dc_streaming parameters
+    set_instance_parameter jtag_phy_embedded_in_jtag_master PURPOSE 1
+    set_instance_parameter jtag_phy_embedded_in_jtag_master DOWNSTREAM_FIFO_SIZE 64
+    set_instance_parameter jtag_phy_embedded_in_jtag_master USE_PLI  [ get_parameter_value USE_PLI ]
+    set_instance_parameter jtag_phy_embedded_in_jtag_master PLI_PORT [ get_parameter_value PLI_PORT ]
+    # timing adapter parameters
+    set_instance_parameter timing_adt inBitsPerSymbol   8
+    set_instance_parameter timing_adt inChannelWidth    0
+    set_instance_parameter timing_adt inErrorWidth      0
+    set_instance_parameter timing_adt inMaxChannel      0
+    set_instance_parameter timing_adt inReadyLatency    0
+    set_instance_parameter timing_adt inSymbolsPerBeat  1
+    set_instance_parameter timing_adt inUseEmpty        false
+    set_instance_parameter timing_adt inUseEmptyPort    NO
+    set_instance_parameter timing_adt inUsePackets      false
+    set_instance_parameter timing_adt inUseReady        [ get_parameter_value USE_PLI ]
+    set_instance_parameter timing_adt inUseValid        true
+    set_instance_parameter timing_adt outReadyLatency   0
+    set_instance_parameter timing_adt outUseReady       true
+    set_instance_parameter timing_adt outUseValid       true
+    # b2p channel adapter parameters
+    set_instance_parameter b2p_adapter inBitsPerSymbol   8
+    set_instance_parameter b2p_adapter inChannelWidth    8
+    set_instance_parameter b2p_adapter inErrorWidth      0
+    set_instance_parameter b2p_adapter inMaxChannel      255
+    set_instance_parameter b2p_adapter inReadyLatency    0
+    set_instance_parameter b2p_adapter inSymbolsPerBeat  1
+    set_instance_parameter b2p_adapter inUseEmpty        false
+    set_instance_parameter b2p_adapter inUseEmptyPort    AUTO
+    set_instance_parameter b2p_adapter inUsePackets      true
+    set_instance_parameter b2p_adapter inUseReady        true
+    set_instance_parameter b2p_adapter outChannelWidth   0
+    set_instance_parameter b2p_adapter outMaxChannel     0
+    # p2b channel adapter parameters
+    set_instance_parameter p2b_adapter inBitsPerSymbol   8
+    set_instance_parameter p2b_adapter inChannelWidth    0
+    set_instance_parameter p2b_adapter inErrorWidth      0
+    set_instance_parameter p2b_adapter inMaxChannel      0
+    set_instance_parameter p2b_adapter inReadyLatency    0
+    set_instance_parameter p2b_adapter inSymbolsPerBeat  1
+    set_instance_parameter p2b_adapter inUseEmpty        false
+    set_instance_parameter p2b_adapter inUseEmptyPort    AUTO
+    set_instance_parameter p2b_adapter inUsePackets      true
+    set_instance_parameter p2b_adapter inUseReady        true
+    set_instance_parameter p2b_adapter outChannelWidth   8
+    set_instance_parameter p2b_adapter outMaxChannel     255
+    # sc fifo parameters
+    set_instance_parameter fifo SYMBOLS_PER_BEAT    1
+    set_instance_parameter fifo BITS_PER_SYMBOL     8
+    set_instance_parameter fifo FIFO_DEPTH          64
+    set_instance_parameter fifo CHANNEL_WIDTH       0
+    set_instance_parameter fifo ERROR_WIDTH         0
+    set_instance_parameter fifo USE_PACKETS         0
+    set_instance_parameter fifo USE_FILL_LEVEL      0
+    set_instance_parameter fifo USE_STORE_FORWARD   0
+    set_instance_parameter fifo USE_ALMOST_FULL_IF  0
+    set_instance_parameter fifo USE_ALMOST_EMPTY_IF 0
+    set_instance_parameter fifo USE_MEMORY_BLOCKS  [ get_parameter_value USE_MEMORY_BLOCKS ]
+    # transacto parameters
+    set_instance_parameter transacto EXPORT_MASTER_SIGNALS  0
+    set_instance_parameter transacto FAST_VER               [ get_parameter_value FAST_VER ]
+    set_instance_parameter transacto FIFO_DEPTHS            [ get_parameter_value FIFO_DEPTHS ]
+    # |
+    # +-----------------------------------
+
+    # +-----------------------------------
+    # | connection point clk
+    # |
+    add_interface           clk clock end
+    set_interface_property  clk export_of clk_src.in_clk
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | connection point clk_reset
+    # |
+    add_interface           clk_reset reset end
+    set_interface_property  clk_reset export_of clk_rst.in_reset
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | connection point master
+    # |
+    add_interface           master avalon start
+    set_interface_property  master export_of transacto.avalon_master
+    set_interface_assignment master debug.providesServices master
+    set_interface_assignment master debug.visible true
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | connection point master_reset
+    # |
+    add_interface           master_reset reset start
+    set_interface_property  master_reset export_of jtag_phy_embedded_in_jtag_master.resetrequest
+    # |
+    # +-----------------------------------
+    # +-----------------------------------
+    # | submodule interface connections
+    # |
+    add_connection clk_src.out_clk jtag_phy_embedded_in_jtag_master.clock
+    add_connection clk_src.out_clk timing_adt.clk
+    add_connection clk_src.out_clk fifo.clk
+    add_connection clk_src.out_clk b2p.clk
+    add_connection clk_src.out_clk p2b.clk
+    add_connection clk_src.out_clk transacto.clk
+    add_connection clk_src.out_clk b2p_adapter.clk
+    add_connection clk_src.out_clk p2b_adapter.clk
+
+    add_connection clk_rst.out_reset jtag_phy_embedded_in_jtag_master.clock_reset
+    add_connection clk_rst.out_reset timing_adt.reset
+    add_connection clk_rst.out_reset fifo.clk_reset
+    add_connection clk_rst.out_reset b2p.clk_reset
+    add_connection clk_rst.out_reset p2b.clk_reset
+    add_connection clk_rst.out_reset transacto.clk_reset
+    add_connection clk_rst.out_reset b2p_adapter.reset
+    add_connection clk_rst.out_reset p2b_adapter.reset
+
+    add_connection jtag_phy_embedded_in_jtag_master.src                timing_adt.in
+    add_connection timing_adt.out         fifo.in
+    add_connection fifo.out               b2p.in_bytes_stream
+    add_connection b2p.out_packets_stream b2p_adapter.in
+    add_connection b2p_adapter.out        transacto.in_stream
+    add_connection transacto.out_stream   p2b_adapter.in
+    add_connection p2b_adapter.out        p2b.in_packets_stream
+    add_connection p2b.out_bytes_stream   jtag_phy_embedded_in_jtag_master.sink
+    # |
+    # +-----------------------------------
+}
+# |
+# +-----------------------------------
+
+
+## Add documentation links for user guide and/or release notes
+add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1401396548170

ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys.v

@@ -1,56 +0,0 @@
-// (C) 2001-2015 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Altera Program License Subscription 
-// Agreement, Altera MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Altera and sold by 
-// Altera or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-//Legal Notice: (C)2010 Altera Corporation. All rights reserved.  Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors.  Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings 
-// altera message_level Level1 
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 
-
-module endianconverter_qsys (
-                        // inputs:
-                         dataa,
-                         datab,
-
-                        // outputs:
-                         result
-                      )
-;
-
-  output  [ 31: 0] result;
-  input   [ 31: 0] dataa;
-  input   [ 31: 0] datab;
-
-  wire    [ 31: 0] result;
-  //s1, which is an e_custom_instruction_slave
-  assign result[7 : 0] = dataa[31 : 24];
-  assign result[15 : 8] = dataa[23 : 16];
-  assign result[23 : 16] = dataa[15 : 8];
-  assign result[31 : 24] = dataa[7 : 0];
-
-endmodule
-

ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys_hw.tcl

@@ -1,84 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-# TCL File Generated by Component Editor 10.1
-# Tue Aug 17 15:04:48 MYT 2010
-# DO NOT MODIFY
-
-
-# +-----------------------------------
-# | 
-# | 
-# |    ./converter_0.v syn, sim
-# | 
-# +-----------------------------------
-
-# +-----------------------------------
-# | request TCL package from ACDS 10.1
-# | 
-package require -exact sopc 10.1
-# | 
-# +-----------------------------------
-
-# +-----------------------------------
-# | module altera_nios_custom_instr_endian_converter
-# | 
-set_module_property NAME altera_nios_custom_instr_endianconverter
-set_module_property VERSION 17.0
-set_module_property INTERNAL false
-set_module_property GROUP "Custom Instruction Modules"
-set_module_property AUTHOR "Altera Corporation"
-set_module_property DISPLAY_NAME "Endian Converter"
-set_module_property HIDE_FROM_SOPC true
-set_module_property TOP_LEVEL_HDL_FILE endianconverter_qsys.v
-set_module_property TOP_LEVEL_HDL_MODULE endianconverter_qsys
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property SIMULATION_MODEL_IN_VHDL true
-set_module_property EDITABLE false
-set_module_property ANALYZE_HDL FALSE
-# | 
-# +-----------------------------------
-
-# +-----------------------------------
-# | files
-# | 
-add_file endianconverter_qsys.v {SYNTHESIS SIMULATION}
-# | 
-# +-----------------------------------
-
-# +-----------------------------------
-# | parameters
-# | 
-# | 
-# +-----------------------------------
-
-# +-----------------------------------
-# | display items
-# | 
-# | 
-# +-----------------------------------
-
-# +-----------------------------------
-# | connection point s1
-# | 
-add_interface s1 nios_custom_instruction end
-set_interface_property s1 clockCycle 1
-set_interface_property s1 operands 1
-
-set_interface_property s1 ENABLED true
-
-add_interface_port s1 dataa dataa Input 32
-add_interface_port s1 datab datab Input 32
-add_interface_port s1 result result Output 32
-# | 
-# +-----------------------------------

ip/hw_crc32_qsys/hw_crc32_hw.tcl

@@ -0,0 +1,105 @@
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module pulpino
+# 
+set_module_property DESCRIPTION "HW CRC32"
+set_module_property NAME hw_crc32
+#set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "DSP"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME hw_crc32
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+set adv_dbg_if false
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Component
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE
+
+
+add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+set_fileset_property SIM_VERILOG TOP_LEVEL CRC_Component
+add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE
+
+
+
+#
+# connection point clk_sink
+#
+add_interface clk_sink clock end
+set_interface_property clk_sink ENABLED true
+set_interface_property clk_sink EXPORT_OF ""
+set_interface_property clk_sink PORT_NAME_MAP ""
+set_interface_property clk_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clk_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clk_sink clk clk Input 1
+
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clk_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink reset reset Input 1
+
+
+
+# 
+# connection point avalon_slave
+# 
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clk_sink
+set_interface_property avalon_slave associatedReset reset_sink
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave readLatency 1
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+add_interface_port avalon_slave address address Input 3
+add_interface_port avalon_slave readdata readdata Output 32
+add_interface_port avalon_slave read read Input 1
+add_interface_port avalon_slave chipselect chipselect Input 1
+add_interface_port avalon_slave byteenable byteenable Input 4
+add_interface_port avalon_slave write write Input 1
+add_interface_port avalon_slave writedata writedata Input 32

ip/i2c_opencores/HAL/inc/i2c_opencores.h

@@ -17,7 +17,7 @@ int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read);
 alt_u32 I2C_read(alt_u32 base,alt_u32 last);
 alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last);
 void SPI_read(alt_u32 base, alt_u8 *rdata, int len);
-void SPI_write(alt_u32 base, alt_u8 *wdata, int len);
+void SPI_write(alt_u32 base, const alt_u8 *wdata, int len);
 #define I2C_OK (0)
 #define I2C_ACK (0)
 #define I2C_NOACK (1)

ip/i2c_opencores/HAL/src/i2c_opencores.c

@@ -69,7 +69,7 @@ int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read)
   IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_STA_MSK | I2C_OPENCORES_CR_WR_MSK );
 
           /* wait for the trnasaction to be over.*/
-  while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
+  while (IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK) {}
 
          /* now check to see if the address was acknowledged */
    if(IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_RXNACK_MSK)
@@ -119,7 +119,7 @@ alt_u32 I2C_read(alt_u32 base,alt_u32 last)
           IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK );
   }
           /* wait for the trnasaction to be over.*/
-  while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
+  while (IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK) {}
 
          /* now read the data */
         return (IORD_I2C_OPENCORES_RXR(base));
@@ -162,7 +162,7 @@ alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last)
           IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK );
   }
            /* wait for the trnasaction to be over.*/
-  while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
+  while (IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK) {}
 
          /* now check to see if the address was acknowledged */
    if(IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_RXNACK_MSK)
@@ -197,7 +197,7 @@ void SPI_read(alt_u32 base, alt_u8 *rdata, int len)
     }
 }
 
-void SPI_write(alt_u32 base, alt_u8 *wdata, int len)
+void SPI_write(alt_u32 base, const alt_u8 *wdata, int len)
 {
     int i;
 

ip/i2c_opencores/i2c_opencores_hw.tcl

@@ -20,7 +20,7 @@ package require -exact qsys 13.1
 # 
 set_module_property DESCRIPTION "I2C Master Peripheral from opencores.org, plus SPI master (CPOL=1, CPHA=1) functionality using the same bus."
 set_module_property NAME i2c_opencores
-set_module_property VERSION 17.0
+set_module_property VERSION 17.1
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property GROUP "Interface Protocols/Serial"

ip/nios2_hw_crc/HAL/doc/crc_main.c

@@ -1,224 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-* Altera does not recommend, suggest or require that this reference design    *
-* file be used in conjunction or combination with any other product.          *
-******************************************************************************/
-
-
-/******************************************************************************
-* Author - JCJB                                                               *
-*                                                                             *
-* This design uses the following CRC-32 implementations:                      *
-*                                                                             *
-* --> Software - Uses modulo 2 division to perform the remainder calculation. *
-* --> Optimized Software - Uses a lookup table of all possible division       *
-*                          values.  The calculation operates on 8 bit data.   *
-* --> Custom Instruction - Uses a parallel hardware CRC circuit to calculate  *
-*                          the remainder.  The calculation operates on 8,     *
-*                          16, 24, or 32 bit data.                            *
-*                                                                             *
-* The software implementations can be changed to CRC-16 or CRC-CCITT however  *
-* the custom instruction must be modified as well to support the same         *
-* standard.  Simply use the values defined in crc.h to change the standard    *
-* used (using the same values in the hardware parameterization) or define     *
-* your own standard.                                                          * 
-*******************************************************************************/
-
-#include "system.h"
-#include "stdio.h"
-#include "crc.h"
-#include "ci_crc.h"
-#include "sys/alt_timestamp.h"
-#include "stdlib.h"
-
-
-/* Modify these values to adjust the test being performed */
-#define NUMBER_OF_BUFFERS 32
-#define BUFFER_SIZE 256 /* in bytes */
-
-/* Change the name of memory device according to what you are using
- *  e.g.: DDR_SDRAM_0 ##_SPAN
- *        SSRAM_0 ##_SPAN                                        
- */
-#define MEMORY_DEVICE_SIZE 32768
-
-
-/* Make sure there is room left for Nios II text, rodata, rwdata, stack,
- * and heap.  This software and the buffer space must fit within the
- * size of memory device.  A total of 1.5 MBytes is reserved. If BUFFER_SIZE
- * is a multiple of four then exactly 256kB will be left, otherwise is 
- * amount will be less since the column dimension needs some padding to 
- * stay 32 bit aligned
- */
-#if ((BUFFER_SIZE * NUMBER_OF_BUFFERS) >= MEMORY_DEVICE_SIZE - 10000)
-  #error Your buffer space has exceeded the maximum allowable space.  Please\
-         reduce the buffer space so that there is enough room to hold Nios II\
-         code.
-#endif
-
-
-/* This will line up the data onto a 32 bit (or greater) boundary.  A 2d array
- * is being used here for simplicity.  The first dimension represents a byte
- * of data and the second dimension represents an individual buffer 
- */
-#if ((BUFFER_SIZE & 0x3) == 0)
-  unsigned char data_buffer_region[NUMBER_OF_BUFFERS][BUFFER_SIZE] __attribute__ ((aligned(4)));
-#else /* need to allocate extra bytes so that all buffers start on a 32 bit
-         boundaries by rounding up the column dimension to the next power of 4
-       */
-  unsigned char data_buffer_region[NUMBER_OF_BUFFERS][BUFFER_SIZE + 4 - (BUFFER_SIZE&0x3)] __attribute__ ((aligned(4)));  
-#endif
-
-
-
-
-
-int main()
-{
-  unsigned long buffer_counter, data_counter;
-  unsigned long sw_slow_results[NUMBER_OF_BUFFERS];
-  unsigned long sw_fast_results[NUMBER_OF_BUFFERS];
-  unsigned long ci_results[NUMBER_OF_BUFFERS];
-  unsigned char random_data = 0x5A;
-  //unsigned long sw_slow_timeA, sw_slow_timeB;
- // unsigned long sw_fast_timeA, sw_fast_timeB;
- // unsigned long ci_timeA, ci_timeB;
-
-  alt_u32 sw_slow_timeA, sw_slow_timeB;
-  alt_u32 sw_fast_timeA, sw_fast_timeB;
-  alt_u32 ci_timeA, ci_timeB;
-
-
-  printf("+-----------------------------------------------------------+\n");
-  printf("| Comparison between software and custom instruction CRC32  |\n");
-  printf("+-----------------------------------------------------------+\n\n\n");
-  
-  printf("System specification\n");
-  printf("--------------------\n");
-
-  printf("System clock speed = %lu MHz\n", (unsigned long)ALT_CPU_FREQ /(unsigned long)1000000);
-  printf("Number of buffer locations = %d\n", NUMBER_OF_BUFFERS);
-  printf("Size of each buffer = %d bytes\n\n\n", BUFFER_SIZE);
-
-
-  /* Initializing the data buffers */
-  printf("Initializing all of the buffers with pseudo-random data\n");
-  printf("-------------------------------------------------------\n");
-  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
-  {
-    for(data_counter = 0; data_counter < BUFFER_SIZE; data_counter++)
-    {
-      data_buffer_region[buffer_counter][data_counter] = random_data;
-      random_data = (random_data >> 4) + (random_data << 4) + (data_counter & 0xFF);
-    }
-  }
-  printf("Initialization completed\n\n\n");
-
-
-  if(alt_timestamp_start() < 0) // starts the timestamp timer
-  {
-    printf("Please add the high resolution timer to the timestamp timer setting in the syslib properties page.\n");
-    exit(1);
-  }
-
-
-  /* Slow software CRC based on a modulo 2 division implementation */
-  printf("Running the software CRC\n");
-  printf("------------------------\n");
-  sw_slow_timeA = alt_timestamp();
-
-  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
-  {
-    sw_slow_results[buffer_counter] = crcSlow(data_buffer_region[buffer_counter], BUFFER_SIZE);
-  }
- sw_slow_timeB = alt_timestamp();
-
-  printf("Completed\n\n\n");
-
-
-  /* Fast software CRC based on a lookup table implementation */
-  crcInit();
-  printf("Running the optimized software CRC\n");
-  printf("----------------------------------\n");
-  sw_fast_timeA = alt_timestamp();
-  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
-  {
-    sw_fast_results[buffer_counter] = crcFast(data_buffer_region[buffer_counter], BUFFER_SIZE);
-  }
- sw_fast_timeB = alt_timestamp();
-  printf("Completed\n\n\n");
-
-
-  /* Custom instruction CRC */
-  printf("Running the custom instruction CRC\n");
-  printf("----------------------------------\n");
- ci_timeA = alt_timestamp();
-  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
-  {
-    ci_results[buffer_counter] = crcCI(data_buffer_region[buffer_counter], BUFFER_SIZE);
-  }
-  ci_timeB = alt_timestamp();
-  printf("Completed\n\n\n");
-
-  /* Validation of results */  
-  printf("Validating the CRC results from all implementations\n");
-  printf("----------------------------------------------------\n");
-  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
-  {
-    /* Test every combination of results to make sure they are consistant */
-    if((sw_slow_results[buffer_counter] != ci_results[buffer_counter]) | 
-       (sw_fast_results[buffer_counter] != ci_results[buffer_counter]))
-    {
-      printf("FAILURE!  Software CRC = 0x%lx, Optimized Software CRC = 0x%lx, Custom Instruction CRC = 0x%lx,\n",
-      sw_slow_results[buffer_counter], sw_fast_results[buffer_counter], ci_results[buffer_counter]);       
-      exit(1);     
-    }
-  }
-  printf("All CRC implementations produced the same results\n\n\n");
-
-
-  // Report processing times
-  printf("Processing time for each implementation\n");
-  printf("---------------------------------------\n");
-  printf("Software CRC = %.2lu ms\n", 1000*((unsigned long)(sw_slow_timeB-sw_slow_timeA))/((unsigned long)alt_timestamp_freq()));
-  printf("Optimized software CRC = %.2lu ms\n", 1000*((unsigned long)(sw_fast_timeB-sw_fast_timeA))/((unsigned long)alt_timestamp_freq()));
-  printf("Custom instruction CRC = %.2lu ms\n\n\n", 1000*((unsigned long)(ci_timeB-ci_timeA))/((unsigned long)alt_timestamp_freq()));
-
-  printf("Processing throughput for each implementation\n"); // throughput = total bits / (time(s) * 1000000)
-  printf("---------------------------------------------\n");
-  printf("Software CRC = %.2lu Mbps\n", (8 * NUMBER_OF_BUFFERS * BUFFER_SIZE)/(1000000*(unsigned long)(sw_slow_timeB-sw_slow_timeA)/((unsigned long)alt_timestamp_freq())));
-  printf("Optimized software CRC = %.2lu Mbps\n", (8 * NUMBER_OF_BUFFERS * BUFFER_SIZE)/(1000000*(unsigned long)(sw_fast_timeB-sw_fast_timeA)/((unsigned long)alt_timestamp_freq())));
-  printf("Custom instruction CRC = %.2lu Mbps\n\n\n", (8 * NUMBER_OF_BUFFERS * BUFFER_SIZE)/(1000000*(unsigned long)(ci_timeB-ci_timeA)/((unsigned long)alt_timestamp_freq())));
-
-  printf("Speedup ratio\n");
-  printf("-------------\n");
-  printf("Custom instruction CRC vs software CRC = %lu\n", ((unsigned long)(sw_slow_timeB-sw_slow_timeA))/((unsigned long)(ci_timeB-ci_timeA)));
-  printf("Custom instruction CRC vs optimized software CRC = %lu\n", ((unsigned long)(sw_fast_timeB-sw_fast_timeA))/((unsigned long)(ci_timeB-ci_timeA)));
-  printf("Optimized software CRC vs software CRC= %lu\n", ((unsigned long)(sw_slow_timeB-sw_slow_timeA))/((unsigned long)(sw_fast_timeB-sw_fast_timeA)));
-  return 0;
-}

ip/nios2_hw_crc/HAL/inc/crc.h

@@ -1,109 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-* Altera does not recommend, suggest or require that this reference design    *
-* file be used in conjunction or combination with any other product.          *
-******************************************************************************/
-
-
-/**********************************************************************
- *
- * Filename:    crc.h
- * 
- * Description: A header file describing the various CRC standards.
- *
- * Notes:       
- *
- * 
- * Copyright (c) 2000 by Michael Barr.  This software is placed into
- * the public domain and may be used for any purpose.  However, this
- * notice must not be changed or removed and no warranty is either
- * expressed or implied by its publication or distribution.
- **********************************************************************/
-
-#ifndef _crc_h
-#define _crc_h
-
-
-#define FALSE	0
-#define TRUE	!FALSE
-
-/*
- * Select the CRC standard from the list that follows.
- */
-#define CRC32
-
-
-#if defined(CRC_CCITT)
-
-typedef unsigned short  crc;
-
-#define CRC_NAME			"CRC-CCITT"
-#define POLYNOMIAL			0x1021
-#define INITIAL_REMAINDER	0xFFFF
-#define FINAL_XOR_VALUE		0x0000
-#define REFLECT_DATA		FALSE
-#define REFLECT_REMAINDER	FALSE
-#define CHECK_VALUE			0x29B1
-
-#elif defined(CRC16)
-
-typedef unsigned short  crc;
-
-#define CRC_NAME			"CRC-16"
-#define POLYNOMIAL			0x8005
-#define INITIAL_REMAINDER	0x0000
-#define FINAL_XOR_VALUE		0x0000
-#define REFLECT_DATA		TRUE
-#define REFLECT_REMAINDER	TRUE
-#define CHECK_VALUE			0xBB3D
-
-#elif defined(CRC32)
-
-typedef unsigned long  crc;
-
-#define CRC_NAME			"CRC-32"
-#define POLYNOMIAL			0x04C11DB7
-#define INITIAL_REMAINDER	0xFFFFFFFF
-#define FINAL_XOR_VALUE		0xFFFFFFFF
-#define REFLECT_DATA		TRUE
-#define REFLECT_REMAINDER	TRUE
-#define CHECK_VALUE			0xCBF43926
-
-#else
-
-#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd."
-
-#endif
-
-
-void  crcInit(void);
-crc   crcSlow(unsigned char const message[], int nBytes);
-crc   crcFast(unsigned char const message[], int nBytes);
-
-
-#endif /* _crc_h */

ip/nios2_hw_crc/HAL/src/ci_crc.c

@@ -1,97 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-* Altera does not recommend, suggest or require that this reference design    *
-* file be used in conjunction or combination with any other product.          *
-******************************************************************************/
-
-
-/**********************************************************************
- *
- * Filename:    ci_crc.c
- * 
- * Description: Custom instruction implementations of the CRC.
- *
- * Notes:       A macro is defined that is used to access the CRC custom  
- *              instruction.
- *********************************************************************/
- 
-#include "system.h"
-
-/*The n values and their corresponding operation are as follow:
- * n = 0, Initialize the custom instruction to the initial remainder value
- * n = 1, Write  8 bits data to custom instruction
- * n = 2, Write 16 bits data to custom instruction
- * n = 3, Write 32 bits data to custom instruction
- * n = 4, Read  32 bits data from the custom instruction
- * n = 5, Read  64 bits data from the custom instruction
- * n = 6, Read  96 bits data from the custom instruction
- * n = 7, Read 128 bits data from the custom instruction*/
-#define CRC_CI_MACRO(n, A)        __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N + (n & 0x7), (A))
-
-unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize)
-{
-  unsigned long index;
-  /* copy of the data buffer pointer so that it can advance by different widths */
-  void * input_data_copy = (void *)input_data;
-
-  /* The custom instruction CRC will initialize to the inital remainder value */    
-  if (do_initialize)
-    CRC_CI_MACRO(0,0);
-  
-  /* Write 32 bit data to the custom instruction.  If the buffer does not end
-   * on a 32 bit boundary then the remaining data will be sent to the custom
-   * instruction in the 'if' statement below.
-   */
-  for(index = 0; index < (input_data_length & 0xFFFFFFFC); index+=4)
-  {
-    CRC_CI_MACRO(3, *(unsigned long *)input_data_copy);
-    input_data_copy += 4;  /* void pointer, must move by 4 for each word */
-  }
-
-  /* Write the remainder of the buffer if it does not end on a word boundary */  
-  if((input_data_length & 0x3) == 0x3)  /* 3 bytes left */
-  {
-    CRC_CI_MACRO(2, *(unsigned short *)input_data_copy);
-    input_data_copy += 2;
-    CRC_CI_MACRO(1, *(unsigned char *)input_data_copy);
-  }
-  else if((input_data_length & 0x3) == 0x2) /* 2 bytes left */
-  {
-    CRC_CI_MACRO(2, *(unsigned short *)input_data_copy);    
-  }
-  else if((input_data_length & 0x3) == 0x1) /* 1 byte left */
-  {
-    CRC_CI_MACRO(1, *(unsigned char *)input_data_copy);    
-  }
-  
-  /* There are 4 registers in the CRC custom instruction.  Since
-   * this example uses CRC-32 only the first register must be read
-   * in order to receive the full result.
-   */
-  return CRC_CI_MACRO(4, 0);
-}

ip/nios2_hw_crc/HAL/src/crc.c

@@ -1,265 +0,0 @@
-/******************************************************************************
-*                                                                             *
-* License Agreement                                                           *
-*                                                                             *
-* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
-* All rights reserved.                                                        *
-*                                                                             *
-* Permission is hereby granted, free of charge, to any person obtaining a     *
-* copy of this software and associated documentation files (the "Software"),  *
-* to deal in the Software without restriction, including without limitation   *
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
-* and/or sell copies of the Software, and to permit persons to whom the       *
-* Software is furnished to do so, subject to the following conditions:        *
-*                                                                             *
-* The above copyright notice and this permission notice shall be included in  *
-* all copies or substantial portions of the Software.                         *
-*                                                                             *
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
-* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
-* DEALINGS IN THE SOFTWARE.                                                   *
-*                                                                             *
-* This agreement shall be governed in all respects by the laws of the State   *
-* of California and by the laws of the United States of America.              *
-* Altera does not recommend, suggest or require that this reference design    *
-* file be used in conjunction or combination with any other product.          *
-******************************************************************************/
-
-
-/**********************************************************************
- *
- * Filename:    crc.c
- * 
- * Description: Slow and fast implementations of the CRC standards.
- *
- * Notes:       The parameters for each supported CRC standard are
- *        defined in the header file crc.h.  The implementations
- *        here should stand up to further additions to that list.
- *
- * 
- * Copyright (c) 2000 by Michael Barr.  This software is placed into
- * the public domain and may be used for any purpose.  However, this
- * notice must not be changed or removed and no warranty is either
- * expressed or implied by its publication or distribution.
- **********************************************************************/
- 
-#include "crc.h"
-
-
-/*
- * Derive parameters from the standard-specific parameters in crc.h.
- */
-#define WIDTH    (8 * sizeof(crc))
-#define TOPBIT   (1 << (WIDTH - 1))
-
-#if (REFLECT_DATA == TRUE)
-#undef  REFLECT_DATA
-#define REFLECT_DATA(X)     ((unsigned char) reflect((X), 8))
-#else
-#undef  REFLECT_DATA
-#define REFLECT_DATA(X)     (X)
-#endif
-
-#if (REFLECT_REMAINDER == TRUE)
-#undef  REFLECT_REMAINDER
-#define REFLECT_REMAINDER(X)  ((crc) reflect((X), WIDTH))
-#else
-#undef  REFLECT_REMAINDER
-#define REFLECT_REMAINDER(X)  (X)
-#endif
-
-
-/*********************************************************************
- *
- * Function:    reflect()
- * 
- * Description: Reorder the bits of a binary sequence, by reflecting
- *        them about the middle position.
- *
- * Notes:   No checking is done that nBits <= 32.
- *
- * Returns:   The reflection of the original data.
- *
- *********************************************************************/
-static unsigned long
-reflect(unsigned long data, unsigned char nBits)
-{
-  unsigned long  reflection = 0x00000000;
-  unsigned char  bit;
-
-  /*
-   * Reflect the data about the center bit.
-   */
-  for (bit = 0; bit < nBits; ++bit)
-  {
-    /*
-     * If the LSB bit is set, set the reflection of it.
-     */
-    if (data & 0x01)
-    {
-      reflection |= (1 << ((nBits - 1) - bit));
-    }
-
-    data = (data >> 1);
-  }
-
-  return (reflection);
-
-} /* reflect() */
-
-
-/*********************************************************************
- *
- * Function:    crcSlow()
- * 
- * Description: Compute the CRC of a given message.
- *
- * Notes:   
- *
- * Returns:   The CRC of the message.
- *
- *********************************************************************/
-crc
-crcSlow(unsigned char const message[], int nBytes)
-{
-    crc            remainder = INITIAL_REMAINDER;
-  int            byte;
-  unsigned char  bit;
-
-
-    /*
-     * Perform modulo-2 division, a byte at a time.
-     */
-    for (byte = 0; byte < nBytes; ++byte)
-    {
-        /*
-         * Bring the next byte into the remainder.
-         */
-        remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
-
-        /*
-         * Perform modulo-2 division, a bit at a time.
-         */
-        for (bit = 8; bit > 0; --bit)
-        {
-            /*
-             * Try to divide the current data bit.
-             */
-            if (remainder & TOPBIT)
-            {
-                remainder = (remainder << 1) ^ POLYNOMIAL;
-            }
-            else
-            {
-                remainder = (remainder << 1);
-            }
-        }
-    }
-
-    /*
-     * The final remainder is the CRC result.
-     */
-    return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
-
-}   /* crcSlow() */
-
-
-crc  crcTable[256];
-
-
-/*********************************************************************
- *
- * Function:    crcInit()
- * 
- * Description: Populate the partial CRC lookup table.
- *
- * Notes:   This function must be rerun any time the CRC standard
- *        is changed.  If desired, it can be run "offline" and
- *        the table results stored in an embedded system's ROM.
- *
- * Returns:   None defined.
- *
- *********************************************************************/
-void
-crcInit(void)
-{
-    crc        remainder;
-  int        dividend;
-  unsigned char  bit;
-
-
-    /*
-     * Compute the remainder of each possible dividend.
-     */
-    for (dividend = 0; dividend < 256; ++dividend)
-    {
-        /*
-         * Start with the dividend followed by zeros.
-         */
-        remainder = dividend << (WIDTH - 8);
-
-        /*
-         * Perform modulo-2 division, a bit at a time.
-         */
-        for (bit = 8; bit > 0; --bit)
-        {
-            /*
-             * Try to divide the current data bit.
-             */     
-            if (remainder & TOPBIT)
-            {
-                remainder = (remainder << 1) ^ POLYNOMIAL;
-            }
-            else
-            {
-                remainder = (remainder << 1);
-            }
-        }
-
-        /*
-         * Store the result into the table.
-         */
-        crcTable[dividend] = remainder;
-    }
-
-}   /* crcInit() */
-
-
-/*********************************************************************
- *
- * Function:    crcFast()
- * 
- * Description: Compute the CRC of a given message.
- *
- * Notes:   crcInit() must be called first.
- *
- * Returns:   The CRC of the message.
- *
- *********************************************************************/
-crc
-crcFast(unsigned char const message[], int nBytes)
-{
-    crc            remainder = INITIAL_REMAINDER;
-    unsigned char  data;
-  int            byte;
-
-
-    /*
-     * Divide the message by the polynomial, a byte at a time.
-     */
-    for (byte = 0; byte < nBytes; ++byte)
-    {
-        data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
-      remainder = crcTable[data] ^ (remainder << 8);
-    }
-
-    /*
-     * The final remainder is the CRC.
-     */
-    return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
-
-}   /* crcFast() */

ip/nios2_hw_crc/hdl/CRC_Custom_Instruction.v

@@ -1,101 +0,0 @@
-/*
-  Legal Notice: (C)2006 Altera Corporation. All rights reserved.  Your
-  use of Altera Corporation's design tools, logic functions and other
-  software and tools, and its AMPP partner logic functions, and any
-  output files any of the foregoing (including device programming or
-  simulation files), and any associated documentation or information are
-  expressly subject to the terms and conditions of the Altera Program
-  License Subscription Agreement or other applicable license agreement,
-  including, without limitation, that your use is for the sole purpose
-  of programming logic devices manufactured by Altera and sold by Altera
-  or its authorized distributors.  Please refer to the applicable
-  agreement for further details.
-*/
-
-/* 
-  This thin wrapper re-uses the CRC Avalon component as a Nios II
-  custom instruction. The n port of custom instruction is used as
-  control to the CRC Avalon component. Below are the values of n and
-  the corresponding operations perform by the custom instruction:
-  n = 0, Initialize the custom instruction to the initial remainder value
-  n = 1, Write  8 bits data to custom instruction
-  n = 2, Write 16 bits data to custom instruction
-  n = 3, Write 32 bits data to custom instruction
-  n = 4, Read  32 bits data from the custom instruction
-  n = 5, Read  64 bits data from the custom instruction
-  n = 6, Read  96 bits data from the custom instruction
-  n = 7, Read 128 bits data from the custom instruction 
-*/
-
-
-
-module CRC_Custom_Instruction(clk,
-                              reset,
-                              dataa,
-                              n,
-                              clk_en,
-                              start,
-					done,
-                              result);
-  /*
-    See the Avalon CRC component for details on the meaning of each
-    parameter listed below.
-  */
-  parameter crc_width = 32;
-  parameter polynomial_inital = 32'hFFFFFFFF;
-  parameter polynomial = 32'h04C11DB7;
-  parameter reflected_input = 1;
-  parameter reflected_output = 1;
-  parameter xor_output = 32'hFFFFFFFF;
-
-  input clk;
-  input reset;
-  input [31:0] dataa;  
-  input [2:0] n;
-  input clk_en;
-  input start;
-  output done;
-  output [31:0] result;
-
-  wire [2:0] address;
-  wire [3:0] byteenable;
-  wire write;
-  wire read;
-  reg done_delay;
-
-  assign write = (n<4);
-  assign read = (n>3);
-  assign byteenable = (n==1)?4'b0001 : (n==2)?4'b0011 : (n==3)?4'b1111 : 4'b0000;
-  assign address = (n==0)?3'b000 : ((n==1)|(n==2)|(n==3))?3'b001 : (n==4)?3'b100 : (n==5)?3'b101 : (n==6)?3'b110 : 3'b111;
-  assign done = (n>3)? done_delay : start;
-
-  always @ (posedge clk or posedge reset)
-  begin
-  if (reset)
-		done_delay <= 0;
-  else
-		done_delay <= start;
-  end
-
-  /* 
-    Instantiating the Avalon CRC component and wiring it to be
-    custom instruction compilant
-  */
-  CRC_Component wrapper_wiring(.clk(clk),
-                               .reset(reset),
-                               .address(address),
-                               .writedata(dataa),
-                               .byteenable(byteenable),
-                               .write(write & start),
-                               .read(read),
-                               .chipselect(clk_en),
-                               .readdata(result));
-
-  defparam wrapper_wiring.crc_width = crc_width;
-  defparam wrapper_wiring.polynomial_inital = polynomial_inital;
-  defparam wrapper_wiring.polynomial = polynomial;
-  defparam wrapper_wiring.reflected_input = reflected_input;
-  defparam wrapper_wiring.reflected_output = reflected_output;
-  defparam wrapper_wiring.xor_output = xor_output;
-
-endmodule

ip/nios2_hw_crc/nios2_hw_crc32_hw.tcl

@@ -1,116 +0,0 @@
-# TCL File Generated by Component Editor 15.1
-# Tue Dec 22 18:46:40 EET 2015
-# DO NOT MODIFY
-
-
-# 
-# nios2_hw_crc32 "nios2_hw_crc32" v1.0
-#  2015.12.22.18:46:40
-# 
-# 
-
-# 
-# request TCL package from ACDS 15.1
-# 
-package require -exact qsys 15.1
-
-
-# 
-# module nios2_hw_crc32
-# 
-set_module_property DESCRIPTION ""
-set_module_property NAME nios2_hw_crc32
-set_module_property VERSION 17.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property GROUP "Custom Instruction Modules"
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME nios2_hw_crc32
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-# 
-# file sets
-# 
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Custom_Instruction
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file CRC_Component.v VERILOG PATH hdl/CRC_Component.v
-add_fileset_file CRC_Custom_Instruction.v VERILOG PATH hdl/CRC_Custom_Instruction.v TOP_LEVEL_FILE
-
-
-# 
-# parameters
-# 
-add_parameter crc_width INTEGER 32
-set_parameter_property crc_width DEFAULT_VALUE 32
-set_parameter_property crc_width DISPLAY_NAME crc_width
-set_parameter_property crc_width TYPE INTEGER
-set_parameter_property crc_width UNITS None
-set_parameter_property crc_width HDL_PARAMETER true
-add_parameter polynomial_inital STD_LOGIC_VECTOR 4294967295
-set_parameter_property polynomial_inital DEFAULT_VALUE 4294967295
-set_parameter_property polynomial_inital DISPLAY_NAME polynomial_inital
-set_parameter_property polynomial_inital TYPE STD_LOGIC_VECTOR
-set_parameter_property polynomial_inital UNITS None
-set_parameter_property polynomial_inital ALLOWED_RANGES 0:17179869183
-set_parameter_property polynomial_inital HDL_PARAMETER true
-add_parameter polynomial STD_LOGIC_VECTOR 79764919
-set_parameter_property polynomial DEFAULT_VALUE 79764919
-set_parameter_property polynomial DISPLAY_NAME polynomial
-set_parameter_property polynomial TYPE STD_LOGIC_VECTOR
-set_parameter_property polynomial UNITS None
-set_parameter_property polynomial ALLOWED_RANGES 0:17179869183
-set_parameter_property polynomial HDL_PARAMETER true
-add_parameter reflected_input INTEGER 1
-set_parameter_property reflected_input DEFAULT_VALUE 1
-set_parameter_property reflected_input DISPLAY_NAME reflected_input
-set_parameter_property reflected_input TYPE INTEGER
-set_parameter_property reflected_input UNITS None
-set_parameter_property reflected_input HDL_PARAMETER true
-add_parameter reflected_output INTEGER 1
-set_parameter_property reflected_output DEFAULT_VALUE 1
-set_parameter_property reflected_output DISPLAY_NAME reflected_output
-set_parameter_property reflected_output TYPE INTEGER
-set_parameter_property reflected_output UNITS None
-set_parameter_property reflected_output HDL_PARAMETER true
-add_parameter xor_output STD_LOGIC_VECTOR 4294967295
-set_parameter_property xor_output DEFAULT_VALUE 4294967295
-set_parameter_property xor_output DISPLAY_NAME xor_output
-set_parameter_property xor_output TYPE STD_LOGIC_VECTOR
-set_parameter_property xor_output UNITS None
-set_parameter_property xor_output ALLOWED_RANGES 0:17179869183
-set_parameter_property xor_output HDL_PARAMETER true
-
-
-# 
-# display items
-# 
-
-
-# 
-# connection point nios_custom_instruction_slave
-# 
-add_interface nios_custom_instruction_slave nios_custom_instruction end
-set_interface_property nios_custom_instruction_slave clockCycle 0
-set_interface_property nios_custom_instruction_slave operands 1
-set_interface_property nios_custom_instruction_slave ENABLED true
-set_interface_property nios_custom_instruction_slave EXPORT_OF ""
-set_interface_property nios_custom_instruction_slave PORT_NAME_MAP ""
-set_interface_property nios_custom_instruction_slave CMSIS_SVD_VARIABLES ""
-set_interface_property nios_custom_instruction_slave SVD_ADDRESS_GROUP ""
-
-add_interface_port nios_custom_instruction_slave clk clk Input 1
-add_interface_port nios_custom_instruction_slave clk_en clk_en Input 1
-add_interface_port nios_custom_instruction_slave dataa dataa Input 32
-add_interface_port nios_custom_instruction_slave done done Output 1
-add_interface_port nios_custom_instruction_slave n n Input 3
-add_interface_port nios_custom_instruction_slave reset reset Input 1
-add_interface_port nios_custom_instruction_slave result result Output 32
-add_interface_port nios_custom_instruction_slave start start Input 1
-

ip/nios2_hw_crc/nios2_hw_crc32_sw.tcl

@@ -1,58 +0,0 @@
-# (C) 2001-2015 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and other 
-# software and tools, and its AMPP partner logic functions, and any output 
-# files any of the foregoing (including device programming or simulation 
-# files), and any associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License Subscription 
-# Agreement, Altera MegaCore Function License Agreement, or other applicable 
-# license agreement, including, without limitation, that your use is for the 
-# sole purpose of programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-
-
-# TCL File Generated by Altera University Program
-# DO NOT MODIFY
-
-set aup_version 15.1
-
-# Create a new driver - this name must be different than the 
-# hardware component name
-create_driver nios2_hw_crc32_driver
-
-# Associate it with some hardware
-set_sw_property hw_class_name nios2_hw_crc32
-
-# The version of this driver
-set_sw_property version $aup_version
-
-# This driver is proclaimed to be compatible with 'component'
-# as old as version "1.0". The component hardware version is set in the 
-# _hw.tcl file - If the hardware component  version number is not equal 
-# or greater than the min_compatable_hw_version number, the driver 
-# source files will not be copied over to the BSP driver directory
-set_sw_property min_compatible_hw_version 1.0
-
-# Initialize the driver in alt_sys_init()
-set_sw_property auto_initialize false
-
-# Location in generated BSP that sources will be copied into
-set_sw_property bsp_subdirectory drivers
-
-#
-# Source file listings...
-#
-
-# C/C++ source files
-add_sw_property c_source HAL/src/ci_crc.c
-add_sw_property c_source HAL/src/crc.c
-
-# Include files
-add_sw_property include_source HAL/inc/ci_crc.h
-add_sw_property include_source HAL/inc/crc.h
-
-# This driver supports HAL type
-add_sw_property supported_bsp_type HAL
-
-# End of file
-

ip/osd_generator/bin/char_rom.hex

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ip/osd_generator/inc/osd_generator_regs.h

@@ -0,0 +1,61 @@
+//
+// Copyright (C) 2019-2020  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef OSD_GENERATOR_REGS_H_
+#define OSD_GENERATOR_REGS_H_
+
+#define OSD_CHAR_ROWS 30
+#define OSD_CHAR_COLS 16
+#define OSD_CHAR_SECTIONS 2
+
+#include <stdint.h>
+
+typedef union {
+    struct {
+        uint8_t enable:1;
+        uint8_t status_refresh:1;
+        uint8_t menu_active:1;
+        uint8_t status_timeout:2;
+        uint8_t x_offset:3;
+        uint8_t y_offset:3;
+        uint8_t x_size:2;
+        uint8_t y_size:2;
+        uint8_t border_color:2;
+        uint32_t osd_rsv:15;
+    } __attribute__((packed, __may_alias__));
+    uint32_t data;
+} osd_config_reg;
+
+// char regs
+typedef struct {
+    char data[OSD_CHAR_ROWS][OSD_CHAR_SECTIONS][OSD_CHAR_COLS];
+} osd_char_array;
+
+typedef struct {
+    uint32_t mask;
+} osd_enable_color_reg;
+
+typedef struct {
+    osd_char_array osd_array;
+    osd_config_reg osd_config;
+    osd_enable_color_reg osd_sec_enable[OSD_CHAR_SECTIONS];
+    osd_enable_color_reg osd_row_color;
+} __attribute__((packed, __may_alias__)) osd_regs;
+
+#endif //OSD_GENERATOR_REGS_H_

ip/osd_generator/osd_generator_hw.tcl

@@ -0,0 +1,159 @@
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+# 
+# module
+# 
+set_module_property DESCRIPTION "OSD generator"
+set_module_property NAME osd_generator
+#set_module_property VERSION 18.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Processors and Peripherals"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME osd_generator
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+#
+# parameters
+#
+#add_parameter USE_MEMORY_BLOCKS INTEGER 1
+#set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks for character array"
+#set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
+#set_parameter_property USE_MEMORY_BLOCKS UNITS None
+#set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL osd_generator_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+set_fileset_property SIM_VERILOG TOP_LEVEL osd_generator_top
+add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink clk_i clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_i reset Input 1
+
+
+# 
+# connection point avalon_s
+# 
+add_interface avalon_s avalon end
+set_interface_property avalon_s addressUnits WORDS
+set_interface_property avalon_s associatedClock clock_sink
+set_interface_property avalon_s associatedReset reset_sink
+set_interface_property avalon_s bitsPerSymbol 8
+set_interface_property avalon_s burstOnBurstBoundariesOnly false
+set_interface_property avalon_s burstcountUnits WORDS
+set_interface_property avalon_s explicitAddressSpan 0
+set_interface_property avalon_s holdTime 0
+set_interface_property avalon_s linewrapBursts false
+set_interface_property avalon_s maximumPendingReadTransactions 0
+set_interface_property avalon_s maximumPendingWriteTransactions 0
+set_interface_property avalon_s readLatency 0
+set_interface_property avalon_s readWaitTime 1
+set_interface_property avalon_s setupTime 0
+set_interface_property avalon_s timingUnits Cycles
+set_interface_property avalon_s writeWaitTime 0
+set_interface_property avalon_s ENABLED true
+set_interface_property avalon_s EXPORT_OF ""
+set_interface_property avalon_s PORT_NAME_MAP ""
+set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_s SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_s avalon_s_address address Input 8
+add_interface_port avalon_s avalon_s_writedata writedata Input 32
+add_interface_port avalon_s avalon_s_readdata readdata Output 32
+add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
+add_interface_port avalon_s avalon_s_write write Input 1
+add_interface_port avalon_s avalon_s_read read Input 1
+add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
+add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
+set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point bus
+# 
+#add_sv_interface bus osd_if
+
+# Setting the parameter property to add SV interface parameters
+#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
+
+# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
+#set_port_property p2 SV_INTERFACE_PORT bus
+#set_port_property p1 SV_INTERFACE_SIGNAL bus
+#set_port_property p2 SV_INTERFACE_SIGNAL bus
+
+#Adding the SV Interface File
+#add_fileset_file osd_if.sv SYSTEM_VERILOG PATH osd_if.sv SYSTEMVERILOG_INTERFACE
+
+
+# 
+# connection point osd_if
+# 
+add_interface osd_if conduit end
+set_interface_property osd_if associatedClock ""
+set_interface_property osd_if associatedReset ""
+set_interface_property osd_if ENABLED true
+set_interface_property osd_if EXPORT_OF ""
+set_interface_property osd_if PORT_NAME_MAP ""
+set_interface_property osd_if CMSIS_SVD_VARIABLES ""
+set_interface_property osd_if SVD_ADDRESS_GROUP ""
+
+add_interface_port osd_if vclk vclk Input 1
+add_interface_port osd_if xpos xpos Input 11
+add_interface_port osd_if ypos ypos Input 11
+add_interface_port osd_if osd_enable osd_enable Output 1
+add_interface_port osd_if osd_color osd_color Output 2

ip/osd_generator/osd_generator_sw.tcl

@@ -0,0 +1,54 @@
+#
+# osd_generator_sw.tcl
+#
+
+# Create a new driver
+create_driver osd_generator_driver
+
+# Associate it with some hardware known as "opencores_i2c"
+set_sw_property hw_class_name osd_generator
+
+# The version of this driver
+set_sw_property version 1.0
+
+# This driver may be incompatible with versions of hardware less
+# than specified below. Updates to hardware and device drivers
+# rendering the driver incompatible with older versions of
+# hardware are noted with this property assignment.
+#
+# Multiple-Version compatibility was introduced in version 7.1;
+# prior versions are therefore excluded.
+set_sw_property min_compatible_hw_version 1.0
+
+# Initialize the driver in alt_sys_init()
+set_sw_property auto_initialize false
+
+# Location in generated BSP that above sources will be copied into
+set_sw_property bsp_subdirectory drivers
+
+
+# Interrupt properties:
+# This peripheral has an IRQ output but the driver doesn't currently
+# have any interrupt service routine. To ensure that the BSP tools
+# do not otherwise limit the BSP functionality for users of the
+# Nios II enhanced interrupt port, these settings advertise 
+# compliance with both legacy and enhanced interrupt APIs, and to state
+# that any driver ISR supports preemption. If an interrupt handler
+# is added to this driver, these must be re-examined for validity.
+set_sw_property isr_preemption_supported true
+set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
+
+#
+# Source file listings...
+#
+
+# C/C++ source files
+
+# Include files
+add_sw_property include_source inc/osd_generator_regs.h
+
+# This driver supports HAL & UCOSII BSP (OS) types
+add_sw_property supported_bsp_type HAL
+add_sw_property supported_bsp_type UCOSII
+
+# End of file

ip/osd_generator/osd_generator_top.sv

@@ -0,0 +1,238 @@
+//
+// Copyright (C) 2019-2020  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module osd_generator_top (
+    // common
+    input clk_i,
+    input rst_i,
+    // avalon slave
+    input [31:0] avalon_s_writedata,
+    output [31:0] avalon_s_readdata,
+    input [7:0] avalon_s_address,
+    input [3:0] avalon_s_byteenable,
+    input avalon_s_write,
+    input avalon_s_read,
+    input avalon_s_chipselect,
+    output avalon_s_waitrequest_n,
+    // OSD interface
+    input vclk,
+    input [10:0] xpos,
+    input [10:0] ypos,
+    output reg osd_enable,
+    output reg [1:0] osd_color
+);
+
+localparam CHAR_ROWS = 30;
+localparam CHAR_COLS = 16;
+localparam CHAR_SECTIONS = 2;
+localparam CHAR_SEC_SEPARATOR = 2;
+
+localparam BG_BLACK =   2'h0;
+localparam BG_BLUE =    2'h1;
+localparam BG_YELLOW =  2'h2;
+localparam BG_WHITE =   2'h3;
+
+localparam OSD_CONFIG_REGNUM =          8'hf0;
+localparam OSD_ROW_LSEC_ENABLE_REGNUM = 8'hf1;
+localparam OSD_ROW_RSEC_ENABLE_REGNUM = 8'hf2;
+localparam OSD_ROW_COLOR_REGNUM =       8'hf3;
+
+reg [31:0] osd_config;
+reg [31:0] config_reg[OSD_ROW_LSEC_ENABLE_REGNUM:OSD_ROW_COLOR_REGNUM] /* synthesis ramstyle = "logic" */;
+
+reg [10:0] xpos_osd_area_scaled, xpos_text_scaled;
+reg [10:0] ypos_osd_area_scaled, ypos_text_scaled;
+reg [7:0] x_ptr[2:5], y_ptr[2:5] /* synthesis ramstyle = "logic" */;
+reg osd_text_act_pp[2:6], osd_act_pp[3:6];
+reg [14:0] to_ctr, to_ctr_ms;
+reg char_px;
+
+wire render_enable = osd_config[0];
+wire status_refresh = osd_config[1];
+wire menu_active = osd_config[2];
+wire [1:0] status_timeout = osd_config[4:3];
+wire [2:0] x_offset = osd_config[7:5];
+wire [2:0] y_offset = osd_config[10:8];
+wire [1:0] x_size = osd_config[12:11];
+wire [1:0] y_size = osd_config[14:13];
+wire [1:0] border_color = osd_config[16:15];
+
+wire [10:0] xpos_scaled_w = (xpos >> x_size)-({3'h0, x_offset} << 3);
+wire [10:0] ypos_scaled_w = (ypos >> y_size)-({3'h0, y_offset} << 3);
+wire [7:0] rom_rdaddr;
+wire [0:7] char_data[7:0];
+wire [4:0] char_row = (ypos_text_scaled >> 3);
+wire [5:0] char_col = (xpos_text_scaled >> 3) - (((xpos_text_scaled >> 3) >= CHAR_COLS) ? CHAR_SEC_SEPARATOR : 0);
+wire [9:0] char_idx = 32*char_row + char_col;
+
+assign avalon_s_waitrequest_n = 1'b1;
+
+char_array char_array_inst (
+    .byteena_a(avalon_s_byteenable),
+    .data(avalon_s_writedata),
+    .rdaddress(char_idx),
+    .rdclock(vclk),
+    .wraddress(avalon_s_address),
+    .wrclock(clk_i),
+    .wren(avalon_s_chipselect && avalon_s_write && (avalon_s_address < CHAR_ROWS*CHAR_COLS*CHAR_SECTIONS)),
+    .q(rom_rdaddr)
+);
+
+char_rom char_rom_inst (
+    .clock(vclk),
+    .address(rom_rdaddr),
+    .q({char_data[7],char_data[6],char_data[5],char_data[4],char_data[3],char_data[2],char_data[1],char_data[0]})
+);
+
+// Pipeline structure
+// |    0     |    1     |    2    |    3    |    4    |    5    |   6    |
+// |----------|----------|---------|---------|---------|---------|--------|
+// > POS_TEXT | POS_AREA |         |         |         |         |        |
+// >          |   PTR    |   PTR   |   PTR   |   PTR   |         |        |
+// >          |  ENABLE  | ENABLE  | ENABLE  | ENABLE  | ENABLE  | ENABLE |
+// >          |  INDEX   |  INDEX  |         |         |         |        |
+// >          |          |         | CHARROM | CHARROM | CHAR_PX | COLOR  |
+integer idx, pp_idx;
+always @(posedge vclk) begin
+    xpos_text_scaled <= xpos_scaled_w;
+    ypos_text_scaled <= ypos_scaled_w;
+
+    xpos_osd_area_scaled <= xpos_text_scaled + 3'h4;
+    ypos_osd_area_scaled <= ypos_text_scaled + 3'h4;
+
+    x_ptr[2] <= xpos_text_scaled[7:0];
+    y_ptr[2] <= ypos_text_scaled[7:0];
+    for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin
+        x_ptr[pp_idx] <= x_ptr[pp_idx-1];
+        y_ptr[pp_idx] <= y_ptr[pp_idx-1];
+    end
+
+    osd_text_act_pp[2] <= render_enable &
+                          (menu_active || (to_ctr_ms > 0)) &
+                          (((xpos_text_scaled < 8*CHAR_COLS) & config_reg[OSD_ROW_LSEC_ENABLE_REGNUM][ypos_text_scaled/8]) |
+                           ((xpos_text_scaled >= 8*(CHAR_COLS+CHAR_SEC_SEPARATOR)) & (xpos_text_scaled < 8*(2*CHAR_COLS+CHAR_SEC_SEPARATOR)) & config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][ypos_text_scaled/8])) &
+                          (ypos_text_scaled < 8*CHAR_ROWS);
+    for(pp_idx = 3; pp_idx <= 6; pp_idx = pp_idx+1) begin
+        osd_text_act_pp[pp_idx] <= osd_text_act_pp[pp_idx-1];
+    end
+
+    osd_act_pp[3] <= render_enable &
+                     (menu_active || (to_ctr_ms > 0)) &
+                     (((xpos_osd_area_scaled/8 < (CHAR_COLS+1)) & config_reg[OSD_ROW_LSEC_ENABLE_REGNUM][(ypos_osd_area_scaled/8) ? ((ypos_osd_area_scaled/8)-1) : 0]) |
+                      ((xpos_osd_area_scaled/8 >= (CHAR_COLS+1)) & (xpos_osd_area_scaled/8 < (2*CHAR_COLS+CHAR_SEC_SEPARATOR+1)) & (config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][(ypos_osd_area_scaled/8)-1] | config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][ypos_osd_area_scaled/8]))) &
+                     (ypos_osd_area_scaled < 8*(CHAR_ROWS+1));
+    for(pp_idx = 4; pp_idx <= 6; pp_idx = pp_idx+1) begin
+        osd_act_pp[pp_idx] <= osd_act_pp[pp_idx-1];
+    end
+
+    char_px <= char_data[y_ptr[5]][x_ptr[5]];
+
+    osd_enable <= osd_act_pp[6];
+
+    if (osd_text_act_pp[6]) begin
+        if (char_px) begin
+            osd_color <= config_reg[OSD_ROW_COLOR_REGNUM][char_row] ? BG_YELLOW : BG_WHITE;
+        end else begin
+            osd_color <= BG_BLUE;
+        end
+    end else begin // border
+        osd_color <= border_color;
+    end
+end
+
+// OSD status timeout counters
+always @(posedge clk_i)
+begin
+    if (status_refresh) begin
+        to_ctr <= 15'd0;
+        case (status_timeout)
+            default: to_ctr_ms <= 2000; // 2s
+            2'b01:   to_ctr_ms <= 5000; // 5s
+            2'b10:   to_ctr_ms <= 10000; // 10s
+            2'b11:   to_ctr_ms <= 0;    // off
+        endcase
+    end else begin
+        if (to_ctr == 27000-1) begin
+            to_ctr <= 0;
+            if (to_ctr_ms != 15'h0)
+                to_ctr_ms <= to_ctr_ms - 1'b1;
+        end else begin
+            to_ctr <= to_ctr + 1'b1;
+        end
+    end
+end
+
+// Avalon register interface
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        osd_config <= 32'h0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==OSD_CONFIG_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                osd_config[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                osd_config[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                osd_config[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                osd_config[7:0] <= avalon_s_writedata[7:0];
+        end else begin
+            osd_config[1] <= 1'b0; // reset timer refresh bit
+        end
+    end
+end
+
+genvar i;
+generate
+    for (i=OSD_ROW_LSEC_ENABLE_REGNUM; i <= OSD_ROW_COLOR_REGNUM; i++) begin : gen_reg
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                config_reg[i] <= 0;
+            end else begin
+                if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==i)) begin
+                    if (avalon_s_byteenable[3])
+                        config_reg[i][31:24] <= avalon_s_writedata[31:24];
+                    if (avalon_s_byteenable[2])
+                        config_reg[i][23:16] <= avalon_s_writedata[23:16];
+                    if (avalon_s_byteenable[1])
+                        config_reg[i][15:8] <= avalon_s_writedata[15:8];
+                    if (avalon_s_byteenable[0])
+                        config_reg[i][7:0] <= avalon_s_writedata[7:0];
+                end
+            end
+        end
+    end
+endgenerate
+
+
+always @(*) begin
+    if (avalon_s_chipselect && avalon_s_read) begin
+        case (avalon_s_address)
+            OSD_CONFIG_REGNUM:              avalon_s_readdata = osd_config;
+            OSD_ROW_LSEC_ENABLE_REGNUM:     avalon_s_readdata = config_reg[OSD_ROW_LSEC_ENABLE_REGNUM];
+            OSD_ROW_RSEC_ENABLE_REGNUM:     avalon_s_readdata = config_reg[OSD_ROW_RSEC_ENABLE_REGNUM];
+            OSD_ROW_COLOR_REGNUM:           avalon_s_readdata = config_reg[OSD_ROW_COLOR_REGNUM];
+            default:                        avalon_s_readdata = 32'h00000000;
+        endcase
+    end else begin
+        avalon_s_readdata = 32'h00000000;
+    end
+end
+
+endmodule

ip/pll_reconfig/inc/pll_reconfig_regs.h

@@ -0,0 +1,47 @@
+//
+// Copyright (C) 2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef PLL_RECONFIG_REGS_H_
+#define PLL_RECONFIG_REGS_H_
+
+#include <alt_types.h>
+
+typedef union {
+    struct {
+        alt_u8 reset:1;
+        alt_u8 update:1;
+        alt_u8 t_config_id:4;
+        alt_u32 pll_reconfig_rsv:21;
+        alt_u8 c_config_id:4;
+        alt_u8 busy:1;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} pll_config_status_reg;
+
+// char regs
+typedef struct {
+    char data[160];
+} pll_config_data_regs;
+
+typedef struct {
+    pll_config_status_reg pll_config_status;
+    pll_config_data_regs pll_config_data;
+} __attribute__((packed, __may_alias__)) pll_reconfig_regs;
+
+#endif //OSD_GENERATOR_REGS_H_

ip/pll_reconfig/pll_reconfig_hw.tcl

@@ -0,0 +1,151 @@
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+# 
+# module
+# 
+set_module_property DESCRIPTION "PLL reconfig"
+set_module_property NAME pll_reconfig
+#set_module_property VERSION 18.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Processors and Peripherals"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME pll_reconfig
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL pll_reconfig_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file pll_reconfig_top.sv VERILOG PATH pll_reconfig_top.sv
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+set_fileset_property SIM_VERILOG TOP_LEVEL pll_reconfig_top
+add_fileset_file pll_reconfig_top.sv VERILOG PATH pll_reconfig_top.sv
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink clk_i clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_i reset Input 1
+
+
+# 
+# connection point avalon_s
+# 
+add_interface avalon_s avalon end
+set_interface_property avalon_s addressUnits WORDS
+set_interface_property avalon_s associatedClock clock_sink
+set_interface_property avalon_s associatedReset reset_sink
+set_interface_property avalon_s bitsPerSymbol 8
+set_interface_property avalon_s burstOnBurstBoundariesOnly false
+set_interface_property avalon_s burstcountUnits WORDS
+set_interface_property avalon_s explicitAddressSpan 0
+set_interface_property avalon_s holdTime 0
+set_interface_property avalon_s linewrapBursts false
+set_interface_property avalon_s maximumPendingReadTransactions 0
+set_interface_property avalon_s maximumPendingWriteTransactions 0
+set_interface_property avalon_s readLatency 0
+set_interface_property avalon_s readWaitTime 1
+set_interface_property avalon_s setupTime 0
+set_interface_property avalon_s timingUnits Cycles
+set_interface_property avalon_s writeWaitTime 0
+set_interface_property avalon_s ENABLED true
+set_interface_property avalon_s EXPORT_OF ""
+set_interface_property avalon_s PORT_NAME_MAP ""
+set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_s SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_s avalon_s_address address Input 3
+add_interface_port avalon_s avalon_s_writedata writedata Input 32
+add_interface_port avalon_s avalon_s_readdata readdata Output 32
+add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
+add_interface_port avalon_s avalon_s_write write Input 1
+add_interface_port avalon_s avalon_s_read read Input 1
+add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
+add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
+set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point bus
+# 
+#add_sv_interface bus pll_reconfig_if
+
+# Setting the parameter property to add SV interface parameters
+#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
+
+# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
+#set_port_property p2 SV_INTERFACE_PORT bus
+#set_port_property p1 SV_INTERFACE_SIGNAL bus
+#set_port_property p2 SV_INTERFACE_SIGNAL bus
+
+#Adding the SV Interface File
+#add_fileset_file pll_reconfig_if.sv SYSTEM_VERILOG PATH pll_reconfig_if.sv SYSTEMVERILOG_INTERFACE
+
+
+# 
+# connection point pll_reconfig_if
+# 
+add_interface pll_reconfig_if conduit end
+set_interface_property pll_reconfig_if associatedClock ""
+set_interface_property pll_reconfig_if associatedReset ""
+set_interface_property pll_reconfig_if ENABLED true
+set_interface_property pll_reconfig_if EXPORT_OF ""
+set_interface_property pll_reconfig_if PORT_NAME_MAP ""
+set_interface_property pll_reconfig_if CMSIS_SVD_VARIABLES ""
+set_interface_property pll_reconfig_if SVD_ADDRESS_GROUP ""
+
+add_interface_port pll_reconfig_if areset areset Output 1
+add_interface_port pll_reconfig_if scanclk scanclk Output 1
+add_interface_port pll_reconfig_if scanclkena scanclkena Output 1
+add_interface_port pll_reconfig_if configupdate configupdate Output 1
+add_interface_port pll_reconfig_if scandata scandata Output 1
+add_interface_port pll_reconfig_if scandone scandone Input 1

ip/pll_reconfig/pll_reconfig_sw.tcl

@@ -0,0 +1,54 @@
+#
+# pll_reconfig_sw.tcl
+#
+
+# Create a new driver
+create_driver pll_reconfig_driver
+
+# Associate it with some hardware known as "opencores_i2c"
+set_sw_property hw_class_name pll_reconfig
+
+# The version of this driver
+set_sw_property version 1.0
+
+# This driver may be incompatible with versions of hardware less
+# than specified below. Updates to hardware and device drivers
+# rendering the driver incompatible with older versions of
+# hardware are noted with this property assignment.
+#
+# Multiple-Version compatibility was introduced in version 7.1;
+# prior versions are therefore excluded.
+set_sw_property min_compatible_hw_version 7.1
+
+# Initialize the driver in alt_sys_init()
+set_sw_property auto_initialize false
+
+# Location in generated BSP that above sources will be copied into
+set_sw_property bsp_subdirectory drivers
+
+
+# Interrupt properties:
+# This peripheral has an IRQ output but the driver doesn't currently
+# have any interrupt service routine. To ensure that the BSP tools
+# do not otherwise limit the BSP functionality for users of the
+# Nios II enhanced interrupt port, these settings advertise 
+# compliance with both legacy and enhanced interrupt APIs, and to state
+# that any driver ISR supports preemption. If an interrupt handler
+# is added to this driver, these must be re-examined for validity.
+set_sw_property isr_preemption_supported true
+set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
+
+#
+# Source file listings...
+#
+
+# C/C++ source files
+
+# Include files
+add_sw_property include_source inc/pll_reconfig_regs.h
+
+# This driver supports HAL & UCOSII BSP (OS) types
+add_sw_property supported_bsp_type HAL
+add_sw_property supported_bsp_type UCOSII
+
+# End of file

ip/pll_reconfig/pll_reconfig_top.sv

@@ -0,0 +1,195 @@
+//
+// Copyright (C) 2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module pll_reconfig_top (
+    // common
+    input clk_i,
+    input rst_i,
+    // avalon slave
+    input [31:0] avalon_s_writedata,
+    output [31:0] avalon_s_readdata,
+    input [2:0] avalon_s_address,
+    input [3:0] avalon_s_byteenable,
+    input avalon_s_write,
+    input avalon_s_read,
+    input avalon_s_chipselect,
+    output avalon_s_waitrequest_n,
+    // reconfig interface
+    output areset,
+    output scanclk,
+    output reg scanclkena,
+    output reg configupdate,
+    output scandata,
+    input scandone
+);
+
+localparam PLL_CONFIG_DATA_BITS = 8'd144;
+localparam PLL_CONFIG_DATA_REGS = 5;
+
+localparam PLL_CONFIG_STATUS_REGNUM =   3'h0;
+localparam PLL_CONFIG_DATA_STARTREG =   3'h1;
+
+localparam STATE_IDLE       = 2'h0;
+localparam STATE_SHIFT      = 2'h1;
+localparam STATE_WAITRESP   = 2'h2;
+
+reg [31:0] pll_config_status;
+reg [31:0] config_data[0:(PLL_CONFIG_DATA_REGS-1)] /* synthesis ramstyle = "logic" */;
+reg areset_strobe;
+reg [1:0] state;
+reg scan_shift;
+reg scandone_prev;
+reg configupdate_pre;
+reg [7:0] shift_ctr;
+
+wire pll_reset = pll_config_status[0];
+wire start_update = pll_config_status[1];
+wire [3:0] t_config_id = pll_config_status[5:2];
+wire [3:0] c_config_id = pll_config_status[30:27];
+wire config_busy = pll_config_status[31];
+
+assign areset = pll_reset | areset_strobe;
+assign scanclk = clk_i;
+assign scandata = config_data[0][16];
+
+assign avalon_s_waitrequest_n = 1'b1;
+
+
+// Avalon register interface
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        pll_config_status[7:0] <= 8'h0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==PLL_CONFIG_STATUS_REGNUM)) begin
+            /*if (avalon_s_byteenable[3])
+                pll_config_status[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                pll_config_status[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                pll_config_status[15:8] <= avalon_s_writedata[15:8];*/
+            if (avalon_s_byteenable[0])
+                pll_config_status[7:0] <= avalon_s_writedata[7:0];
+        end else begin
+            pll_config_status[1] <= 1'b0; // reset start_update bit
+        end
+    end
+end
+
+
+genvar i;
+generate
+    for (i = 0; i < PLL_CONFIG_DATA_REGS; i = i + 1) begin : genreg
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                config_data[i] <= 32'h0;
+            end else begin
+                if (!scan_shift) begin
+                    if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==(PLL_CONFIG_DATA_STARTREG+PLL_CONFIG_DATA_REGS-1-i))) begin
+                        if (avalon_s_byteenable[3])
+                            config_data[i][31:24] <= avalon_s_writedata[31:24];
+                        if (avalon_s_byteenable[2])
+                            config_data[i][23:16] <= avalon_s_writedata[23:16];
+                        if (avalon_s_byteenable[1])
+                            config_data[i][15:8] <= avalon_s_writedata[15:8];
+                        if (avalon_s_byteenable[0])
+                            config_data[i][7:0] <= avalon_s_writedata[7:0];
+                    end
+                end else begin
+                    if (i==(PLL_CONFIG_DATA_REGS-1)) begin
+                        config_data[i] <= {1'b0, config_data[i][31:1]};
+                    end else begin
+                        config_data[i] <= {config_data[i+1][0], config_data[i][31:1]};
+                    end
+                end
+            end
+        end
+    end
+endgenerate
+
+// Main FSM
+always @(posedge clk_i or posedge rst_i)
+begin
+    if (rst_i) begin
+        state <= STATE_IDLE;
+        scanclkena <= 1'b0;
+        configupdate_pre <= 1'b0;
+        configupdate <= 1'b0;
+        areset_strobe <= 1'b0;
+        scan_shift <= 1'b0;
+        scandone_prev <= 1'b0;
+        pll_config_status[31] <= 1'b0;
+    end else begin
+        case (state)
+            STATE_IDLE:
+                begin
+                    areset_strobe <= 1'b0;
+
+                    if (start_update) begin
+                        pll_config_status[31] <= 1'b1;
+                        scanclkena <= 1'b1;
+                        shift_ctr <= PLL_CONFIG_DATA_BITS;
+                        state <= STATE_SHIFT;
+                    end else begin
+                        pll_config_status[31] <= 1'b0;
+                    end
+                end
+            STATE_SHIFT:
+                begin
+                    scan_shift <= 1'b1;
+                    if (shift_ctr > 0) begin
+                        shift_ctr <= shift_ctr - 1'b1;
+                    end else begin
+                        scan_shift <= 1'b0;
+                        scanclkena <= 1'b0;
+                        configupdate_pre <= 1'b1;
+                        state <= STATE_WAITRESP;
+                    end
+                end    
+            STATE_WAITRESP:
+                begin
+                    configupdate_pre <= 1'b0;
+                    if (pll_reset) begin
+                        state <= STATE_IDLE;
+                    end else if (scandone_prev) begin
+                        areset_strobe <= 1'b1;
+                        pll_config_status[30:27] <= t_config_id;
+                        state <= STATE_IDLE;
+                    end
+                end
+            default:
+                state <= STATE_IDLE;
+        endcase
+
+        scandone_prev <= scandone;
+        configupdate <= configupdate_pre;
+    end
+end
+
+always @(*) begin
+    if (avalon_s_chipselect && avalon_s_read) begin
+        case (avalon_s_address)
+            PLL_CONFIG_STATUS_REGNUM: avalon_s_readdata = pll_config_status;
+            default: avalon_s_readdata = 32'h00000000;
+        endcase
+    end else begin
+        avalon_s_readdata = 32'h00000000;
+    end
+end
+
+endmodule

ip/pulpino_qsys

@@ -0,0 +1 @@
+Subproject commit b11dd7718e6d367cbaef8a362ce206510fd87ed0

ip/sc_config/inc/sc_config_regs.h

@@ -0,0 +1,137 @@
+//
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef SC_CONFIG_REGS_H_
+#define SC_CONFIG_REGS_H_
+
+#include <alt_types.h>
+
+// bit-fields coded as little-endian
+typedef union {
+    struct {
+        alt_u16 vmax:11;
+        alt_u8 interlace_flag:1;
+        alt_u8 sc_rsv2:4;
+        alt_u8 fpga_vsyncgen:2;
+        alt_u16 vmax_tvp:11;
+        alt_u8 sc_rsv:2;
+        alt_u8 vsync_flag:1;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} sc_status_reg;
+
+typedef union {
+    struct {
+        alt_u32 pcnt_frame:20;
+        alt_u16 sc_rsv:12;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} sc_status2_reg;
+
+typedef union {
+    struct {
+        alt_u16 lt_lat_result:16;
+        alt_u16 lt_stb_result:12;
+        alt_u8 lt_rsv:3;
+        alt_u8 lt_finished:1;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} lt_status_reg;
+
+typedef union {
+    struct {
+        alt_u16 h_active:11;
+        alt_u16 h_backporch:9;
+        alt_u8 h_synclen:8;
+        alt_u8 h_l3_240x360:1;
+        alt_u8 h_l5fmt:1;
+        alt_u8 h_multmode:2;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} h_config_reg;
+
+typedef union {
+    struct {
+        alt_u16 h_opt_startoff:10;
+        alt_u8 h_opt_sample_mult:3;
+        alt_u8 h_opt_sample_sel:3;
+        alt_u8 h_opt_scale:3;
+        alt_u16 h_mask:11;
+        alt_u8 h_rsv:2;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} h_config2_reg;
+
+typedef union {
+    struct {
+        alt_u16 v_active:11;
+        alt_u8 v_backporch:8;
+        alt_u8 v_synclen:3;
+        alt_u8 v_mask:6;
+        alt_u8 v_rsv:1;
+        alt_u8 v_multmode:3;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} v_config_reg;
+
+typedef union {
+    struct {
+        alt_u8 mask_br:4;
+        alt_u8 mask_color:3;
+        alt_u8 rev_lpf_str:5;
+        alt_u8 panasonic_hack:1;
+        alt_u32 misc_rsv:19;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} misc_config_reg;
+
+typedef union {
+    struct {
+        alt_u32 sl_l_str_arr:20;
+        alt_u8 sl_l_overlay:5;
+        alt_u8 sl_hybr_str:5;
+        alt_u8 sl_method:1;
+        alt_u8 sl_no_altern:1;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} sl_config_reg;
+
+typedef union {
+    struct {
+        alt_u32 sl_c_str_arr:24;
+        alt_u8 sl_c_overlay:6;
+        alt_u8 sl_rsv:1;
+        alt_u8 sl_altiv:1;
+    } __attribute__((packed, __may_alias__));
+    alt_u32 data;
+} sl_config2_reg;
+
+typedef struct {
+    sc_status_reg sc_status;
+    sc_status2_reg sc_status2;
+    lt_status_reg lt_status;
+    h_config_reg h_config;
+    h_config2_reg h_config2;
+    v_config_reg v_config;
+    misc_config_reg misc_config;
+    sl_config_reg sl_config;
+    sl_config2_reg sl_config2;
+} __attribute__((packed, __may_alias__)) sc_regs;
+
+#endif //SC_CONFIG_REGS_H_

ip/sc_config/sc_config_hw.tcl

@@ -0,0 +1,154 @@
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+# 
+# module
+# 
+set_module_property DESCRIPTION "Scanconverter config"
+set_module_property NAME sc_config
+#set_module_property VERSION 18.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "Interface Protocols"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME sc_config
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL sc_config_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file sc_config_top.sv VERILOG PATH sc_config_top.sv
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
+set_fileset_property SIM_VERILOG TOP_LEVEL sc_config_top
+add_fileset_file sc_config_top.sv VERILOG PATH sc_config_top.sv
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink clk_i clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_i reset Input 1
+
+
+# 
+# connection point avalon_s
+# 
+add_interface avalon_s avalon end
+set_interface_property avalon_s addressUnits WORDS
+set_interface_property avalon_s associatedClock clock_sink
+set_interface_property avalon_s associatedReset reset_sink
+set_interface_property avalon_s bitsPerSymbol 8
+set_interface_property avalon_s burstOnBurstBoundariesOnly false
+set_interface_property avalon_s burstcountUnits WORDS
+set_interface_property avalon_s explicitAddressSpan 0
+set_interface_property avalon_s holdTime 0
+set_interface_property avalon_s linewrapBursts false
+set_interface_property avalon_s maximumPendingReadTransactions 0
+set_interface_property avalon_s maximumPendingWriteTransactions 0
+set_interface_property avalon_s readLatency 0
+set_interface_property avalon_s readWaitTime 1
+set_interface_property avalon_s setupTime 0
+set_interface_property avalon_s timingUnits Cycles
+set_interface_property avalon_s writeWaitTime 0
+set_interface_property avalon_s ENABLED true
+set_interface_property avalon_s EXPORT_OF ""
+set_interface_property avalon_s PORT_NAME_MAP ""
+set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_s SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_s avalon_s_address address Input 4
+add_interface_port avalon_s avalon_s_writedata writedata Input 32
+add_interface_port avalon_s avalon_s_readdata readdata Output 32
+add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
+add_interface_port avalon_s avalon_s_write write Input 1
+add_interface_port avalon_s avalon_s_read read Input 1
+add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
+add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
+set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point bus
+# 
+#add_sv_interface bus sc_if
+
+# Setting the parameter property to add SV interface parameters
+#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
+
+# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
+#set_port_property p2 SV_INTERFACE_PORT bus
+#set_port_property p1 SV_INTERFACE_SIGNAL bus
+#set_port_property p2 SV_INTERFACE_SIGNAL bus
+
+#Adding the SV Interface File
+#add_fileset_file sc_if.sv SYSTEM_VERILOG PATH sc_if.sv SYSTEMVERILOG_INTERFACE
+
+
+# 
+# connection point sc_if
+# 
+add_interface sc_if conduit end
+set_interface_property sc_if associatedClock ""
+set_interface_property sc_if associatedReset ""
+set_interface_property sc_if ENABLED true
+set_interface_property sc_if EXPORT_OF ""
+set_interface_property sc_if PORT_NAME_MAP ""
+set_interface_property sc_if CMSIS_SVD_VARIABLES ""
+set_interface_property sc_if SVD_ADDRESS_GROUP ""
+
+add_interface_port sc_if sc_status_i sc_status_i Input 32
+add_interface_port sc_if sc_status2_i sc_status2_i Input 32
+add_interface_port sc_if lt_status_i lt_status_i Input 32
+add_interface_port sc_if h_config_o h_config_o Output 32
+add_interface_port sc_if h_config2_o h_config2_o Output 32
+add_interface_port sc_if v_config_o v_config_o Output 32
+add_interface_port sc_if misc_config_o misc_config_o Output 32
+add_interface_port sc_if sl_config_o sl_config_o Output 32
+add_interface_port sc_if sl_config2_o sl_config2_o Output 32

ip/sc_config/sc_config_sw.tcl

@@ -0,0 +1,54 @@
+#
+# opencores_i2c_sw.tcl
+#
+
+# Create a new driver
+create_driver sc_config_driver
+
+# Associate it with some hardware known as "opencores_i2c"
+set_sw_property hw_class_name sc_config
+
+# The version of this driver
+set_sw_property version 1.0
+
+# This driver may be incompatible with versions of hardware less
+# than specified below. Updates to hardware and device drivers
+# rendering the driver incompatible with older versions of
+# hardware are noted with this property assignment.
+#
+# Multiple-Version compatibility was introduced in version 7.1;
+# prior versions are therefore excluded.
+set_sw_property min_compatible_hw_version 7.1
+
+# Initialize the driver in alt_sys_init()
+set_sw_property auto_initialize false
+
+# Location in generated BSP that above sources will be copied into
+set_sw_property bsp_subdirectory drivers
+
+
+# Interrupt properties:
+# This peripheral has an IRQ output but the driver doesn't currently
+# have any interrupt service routine. To ensure that the BSP tools
+# do not otherwise limit the BSP functionality for users of the
+# Nios II enhanced interrupt port, these settings advertise 
+# compliance with both legacy and enhanced interrupt APIs, and to state
+# that any driver ISR supports preemption. If an interrupt handler
+# is added to this driver, these must be re-examined for validity.
+set_sw_property isr_preemption_supported true
+set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
+
+#
+# Source file listings...
+#
+
+# C/C++ source files
+
+# Include files
+add_sw_property include_source inc/sc_config_regs.h
+
+# This driver supports HAL & UCOSII BSP (OS) types
+add_sw_property supported_bsp_type HAL
+add_sw_property supported_bsp_type UCOSII
+
+# End of file

ip/sc_config/sc_config_top.sv

@@ -0,0 +1,179 @@
+//
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module sc_config_top(
+    // common
+    input clk_i,
+    input rst_i,
+    // avalon slave
+    input [31:0] avalon_s_writedata,
+    output [31:0] avalon_s_readdata,
+    input [3:0] avalon_s_address,
+    input [3:0] avalon_s_byteenable,
+    input avalon_s_write,
+    input avalon_s_read,
+    input avalon_s_chipselect,
+    output avalon_s_waitrequest_n,
+    // SC interface
+    input [31:0] sc_status_i,
+    input [31:0] sc_status2_i,
+    input [31:0] lt_status_i,
+    output reg [31:0] h_config_o,
+    output reg [31:0] h_config2_o,
+    output reg [31:0] v_config_o,
+    output reg [31:0] misc_config_o,
+    output reg [31:0] sl_config_o,
+    output reg [31:0] sl_config2_o
+);
+
+localparam SC_STATUS_REGNUM =   4'h0;
+localparam SC_STATUS2_REGNUM =  4'h1;
+localparam LT_STATUS_REGNUM =   4'h2;
+localparam H_CONFIG_REGNUM =    4'h3;
+localparam H_CONFIG2_REGNUM =   4'h4;
+localparam V_CONFIG_REGNUM =    4'h5;
+localparam MISC_CONFIG_REGNUM = 4'h6;
+localparam SL_CONFIG_REGNUM =   4'h7;
+localparam SL_CONFIG2_REGNUM =  4'h8;
+
+
+assign avalon_s_waitrequest_n = 1'b1;
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        h_config_o <= 0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==H_CONFIG_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                h_config_o[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                h_config_o[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                h_config_o[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                h_config_o[7:0] <= avalon_s_writedata[7:0];
+        end
+    end
+end
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        h_config2_o <= 0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==H_CONFIG2_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                h_config2_o[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                h_config2_o[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                h_config2_o[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                h_config2_o[7:0] <= avalon_s_writedata[7:0];
+        end
+    end
+end
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        v_config_o <= 0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==V_CONFIG_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                v_config_o[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                v_config_o[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                v_config_o[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                v_config_o[7:0] <= avalon_s_writedata[7:0];
+        end
+    end
+end
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        misc_config_o <= 0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==MISC_CONFIG_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                misc_config_o[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                misc_config_o[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                misc_config_o[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                misc_config_o[7:0] <= avalon_s_writedata[7:0];
+        end
+    end
+end
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sl_config_o <= 0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==SL_CONFIG_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                sl_config_o[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                sl_config_o[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                sl_config_o[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                sl_config_o[7:0] <= avalon_s_writedata[7:0];
+        end
+    end
+end
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sl_config2_o <= 0;
+    end else begin
+        if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==SL_CONFIG2_REGNUM)) begin
+            if (avalon_s_byteenable[3])
+                sl_config2_o[31:24] <= avalon_s_writedata[31:24];
+            if (avalon_s_byteenable[2])
+                sl_config2_o[23:16] <= avalon_s_writedata[23:16];
+            if (avalon_s_byteenable[1])
+                sl_config2_o[15:8] <= avalon_s_writedata[15:8];
+            if (avalon_s_byteenable[0])
+                sl_config2_o[7:0] <= avalon_s_writedata[7:0];
+        end
+    end
+end
+
+always @(*) begin
+    if (avalon_s_chipselect && avalon_s_read) begin
+        case (avalon_s_address)
+            SC_STATUS_REGNUM: avalon_s_readdata = sc_status_i;
+            SC_STATUS2_REGNUM: avalon_s_readdata = sc_status2_i;
+            LT_STATUS_REGNUM: avalon_s_readdata = lt_status_i;
+            H_CONFIG_REGNUM: avalon_s_readdata = h_config_o;
+            H_CONFIG2_REGNUM: avalon_s_readdata = h_config2_o;
+            V_CONFIG_REGNUM: avalon_s_readdata = v_config_o;
+            MISC_CONFIG_REGNUM: avalon_s_readdata = misc_config_o;
+            SL_CONFIG_REGNUM: avalon_s_readdata = sl_config_o;
+            SL_CONFIG2_REGNUM: avalon_s_readdata = sl_config2_o;
+            default: avalon_s_readdata = 32'h00000000;
+        endcase
+    end else begin
+        avalon_s_readdata = 32'h00000000;
+    end
+end
+
+endmodule

ossc.cof

@@ -10,7 +10,7 @@
 		<user_name>Page_0</user_name>
 		<page_flags>1</page_flags>
 		<bit0>
-			<sof_filename>output_files/ossc.sof</sof_filename> 
+			<sof_filename>output_files/ossc.sof<compress_bitstream>1</compress_bitstream></sof_filename> 
 		</bit0>
 	</sof_data>
 	<version>10</version>

ossc.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
 set_global_assignment -name TOP_LEVEL_ENTITY ossc
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03  MAY 17, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -57,7 +57,7 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
 
 
 set_location_assignment PIN_25 -to clk27
-set_location_assignment PIN_99 -to reset_n
+set_location_assignment PIN_99 -to hw_reset_n
 set_location_assignment PIN_23 -to ir_rx
 
 #============================================================
@@ -162,12 +162,6 @@ set_location_assignment PIN_129 -to btn[1]
 set_location_assignment PIN_128 -to btn[0]
 
 
-set_instance_assignment -name PLL_COMPENSATE ON -to G_in
-set_instance_assignment -name PLL_COMPENSATE ON -to FID_in
-set_instance_assignment -name PLL_COMPENSATE ON -to HSYNC_in
-set_instance_assignment -name PLL_COMPENSATE ON -to R_in
-set_instance_assignment -name PLL_COMPENSATE ON -to VSYNC_in
-set_instance_assignment -name PLL_COMPENSATE ON -to B_in
 
 
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
@@ -185,7 +179,7 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name SMART_RECOMPILE ON
 
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
@@ -211,31 +205,46 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 50%
 
 
-
 #set_location_assignment PLL_4 -to "scanconverter:scanconverter_inst|pll_3x:pll_linetriple|altpll:altpll_component|pll_3x_altpll:auto_generated|pll1"
 #set_location_assignment PLL_3 -to "scanconverter:scanconverter_inst|pll_3x_lowfreq:pll_linetriple_lowfreq|altpll:altpll_component|pll_3x_lowfreq_altpll:auto_generated|pll1"
 #set_location_assignment PLL_1 -to "scanconverter:scanconverter_inst|pll_2x:pll_linedouble|altpll:altpll_component|pll_2x_altpll:auto_generated|pll1"
 
 
-
-
-
 set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
 set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
+
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name SEED 2
+
+
+
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
 set_global_assignment -name VERILOG_FILE rtl/videogen.v
-set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
 set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
-set_global_assignment -name SDC_FILE ossc.sdc
-set_global_assignment -name QSYS_FILE sys.qsys
 set_global_assignment -name VERILOG_FILE rtl/ossc.v
 set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
+set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
+set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
+set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
 set_global_assignment -name QIP_FILE rtl/linebuf.qip
+set_global_assignment -name QIP_FILE rtl/char_rom.qip
 set_global_assignment -name QIP_FILE rtl/pll_2x.qip
-set_global_assignment -name QIP_FILE rtl/pll_3x.qip
+set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref_pre.qip
+set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref.qip
+set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
+set_global_assignment -name SDC_FILE ossc.sdc
 set_global_assignment -name CDF_FILE output_files/Chain1.cdf
 set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
+set_global_assignment -name QIP_FILE rtl/char_array.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

ossc.sdc

@@ -9,14 +9,38 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
 
 ### Scanconverter clock constraints ###
 
-create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
-create_clock -period 27MHz -name pclk_sdtv [get_ports PCLK_in] -add
+create_clock -period 108MHz -name pclk_1x [get_ports PCLK_in]
+create_clock -period 54MHz -name pclk_2x_source [get_ports PCLK_in] -add
+create_clock -period 54MHz -name pclk_3x_source [get_ports PCLK_in] -add
+create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
+create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
 
 #derive_pll_clocks
-create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
-create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
-create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
-create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
+create_generated_clock -name pclk_2x -master_clock pclk_2x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 2 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
+create_generated_clock -name pclk_3x -master_clock pclk_3x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 3 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
+create_generated_clock -name pclk_4x -master_clock pclk_4x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 4 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
+create_generated_clock -name pclk_5x -master_clock pclk_5x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 5 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
+create_generated_clock -name pclk_27mhz -master_clock clk27 -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 1 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
+
+# retrieve post-mapping clkmux output pin
+set clkmux_output [get_pins scanconverter_inst|clkctrl1|outclk]
+
+# specify postmux clocks which clock postprocess pipeline
+create_generated_clock -name pclk_1x_postmux -master_clock pclk_1x -source [get_pins scanconverter_inst|clkctrl1|inclk[0]] -multiply_by 1 $clkmux_output
+create_generated_clock -name pclk_2x_postmux -master_clock pclk_2x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_3x_postmux -master_clock pclk_3x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_4x_postmux -master_clock pclk_4x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_5x_postmux -master_clock pclk_5x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
+create_generated_clock -name pclk_27mhz_postmux -master_clock pclk_27mhz -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
+
+# specify output clocks that drive PCLK output pin
+set pclk_out_port [get_ports HDMI_TX_PCLK]
+create_generated_clock -name pclk_1x_out -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port
+create_generated_clock -name pclk_2x_out -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_3x_out -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_4x_out -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_5x_out -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
+create_generated_clock -name pclk_27mhz_out -master_clock pclk_27mhz_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
 
 derive_clock_uncertainty
 
@@ -24,60 +48,46 @@ derive_clock_uncertainty
 set TVP_dmin 0
 set TVP_dmax 1.5
 set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
-set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs
-set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
-set_input_delay -clock pclk_sdtv -min $TVP_dmin $critinputs -add_delay
-set_input_delay -clock pclk_sdtv -max $TVP_dmax $critinputs -add_delay
+foreach_in_collection c [get_clocks "pclk_1x pclk_*_source"] {
+    set_input_delay -clock $c -min $TVP_dmin $critinputs -add_delay
+    set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
+}
 
-# output delay constraints
-set IT_Tsu 1.0
+# output delay constraints as documented in the IT6613 datasheet
+# -- increased IT_Tsu from 1.0 to 1.5 due to #52
+set IT_Tsu 1.5
 set IT_Th -0.5
 set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -min $IT_Th $critoutputs_hdmi
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -max $IT_Tsu $critoutputs_hdmi
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -max $IT_Tsu $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -min $IT_Th $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -max $IT_Tsu $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -min $IT_Th $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -max $IT_Tsu $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -min $IT_Th $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -max $IT_Tsu $critoutputs_hdmi -add_delay
+foreach_in_collection c [get_clocks pclk_*_out] {
+    set_output_delay -clock $c -min $IT_Th $critoutputs_hdmi -add
+    set_output_delay -clock $c -max $IT_Tsu $critoutputs_hdmi -add
+}
 set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
 
 
 ### CPU/scanconverter clock relations ###
 
-# Set hdtv pixel clock group as exclusive
-set_clock_groups -exclusive -group {pclk_hdtv}
-
 # Treat CPU clock asynchronous to pixel clocks 
-set_clock_groups -asynchronous -group {clk27}
-
-# Ignore following clock transfers
-set_false_path -from [get_clocks pclk_2x] -to [get_clocks {pclk_sdtv pclk_3x pclk_4x pclk_5x}]
-set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv pclk_2x pclk_4x pclk_5x}]
-set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_5x}]
-set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_4x}]
-
-# Ignore paths which would result from pclk_act switchover during postprocess chain
-set pclk_act_regs [get_cells {scanconverter:scanconverter_inst|R_out* \
-                            scanconverter:scanconverter_inst|G_out* \
-                            scanconverter:scanconverter_inst|B_out* \
-                            scanconverter:scanconverter_inst|HSYNC_out* \
-                            scanconverter:scanconverter_inst|VSYNC_out* \
-                            scanconverter:scanconverter_inst|DE_out* \
-                            scanconverter:scanconverter_inst|*_pp1* \
-                            scanconverter:scanconverter_inst|*_pp2* \
-                            scanconverter:scanconverter_inst|*_pp3*}]
-set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs
-set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*]
+set_clock_groups -asynchronous -group \
+                            {clk27 pclk_27mhz pclk_27mhz_postmux pclk_27mhz_out} \
+                            {pclk_1x pclk_1x_postmux pclk_1x_out} \
+                            {pclk_2x_source pclk_2x pclk_2x_postmux pclk_2x_out} \
+                            {pclk_3x_source pclk_3x pclk_3x_postmux pclk_3x_out} \
+                            {pclk_4x_source pclk_4x pclk_4x_postmux pclk_4x_out} \
+                            {pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
 
 # Ignore paths from registers which are updated only at leading edge of vsync
-set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
+set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_*}]
 
 # Ignore paths from registers which are updated only at leading edge of hsync
-#set_false_path -from [get_cells {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
+#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
+
+# Ignore paths that cross clock domains from 3x to 2x and 5x to 4x, since they share a clock line, but cannot co-occur.
+set_false_path -from [get_clocks {pclk_3x*}] -to [get_registers {scanconverter:scanconverter_inst|*_2x*}]
+set_false_path -from [get_clocks {pclk_5x*}] -to [get_registers {scanconverter:scanconverter_inst|*_4x*}]
+
+# Ignore paths to latency tester sync regs
+set_false_path -to [get_registers {lat_tester:lt0|mode_synced* lat_tester:lt0|VSYNC_in_* lat_tester:lt0|trigger_*}]
 
 
 ### JTAG Signal Constraints ###

ossc_rtl.project

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_rtl" InternalType="">
+<CodeLite_Project Name="ossc_rtl" InternalType="" Version="11000">
   <VirtualDirectory Name="ip">
     <VirtualDirectory Name="nios2_hw_crc">
       <VirtualDirectory Name="hdl">
@@ -24,6 +24,23 @@
   </VirtualDirectory>
   <Description/>
   <Dependencies/>
+  <VirtualDirectory Name="rtl">
+    <File Name="rtl/ir_rcv.v"/>
+    <File Name="rtl/ossc.v"/>
+    <File Name="rtl/pll_2x.v"/>
+    <File Name="rtl/pll_3x_lowfreq.v"/>
+    <File Name="rtl/pll_3x_lowfreq_bb.v"/>
+    <File Name="rtl/linebuf_inst.v"/>
+    <File Name="rtl/videogen.v"/>
+    <File Name="rtl/timescale.v"/>
+    <File Name="rtl/pll_2x_bb.v"/>
+    <File Name="rtl/linebuf.v"/>
+    <File Name="rtl/pll_3x.v"/>
+    <File Name="rtl/scanconverter.v"/>
+    <File Name="rtl/linebuf_bb.v"/>
+  </VirtualDirectory>
+  <Dependencies Name="Debug"/>
+  <Dependencies Name="Release"/>
   <Settings Type="Dynamic Library">
     <GlobalSettings>
       <Compiler Options="" C_Options="" Assembler="">
@@ -41,6 +58,7 @@
       <Linker Options="" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
       <General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
       </Environment>
@@ -79,6 +97,7 @@
       <Linker Options="-O2" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
       <General OutputFile="" IntermediateDirectory="./Release" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
       </Environment>
@@ -111,21 +130,4 @@
       </Completion>
     </Configuration>
   </Settings>
-  <VirtualDirectory Name="rtl">
-    <File Name="rtl/ir_rcv.v"/>
-    <File Name="rtl/ossc.v"/>
-    <File Name="rtl/pll_2x.v"/>
-    <File Name="rtl/pll_3x_lowfreq.v"/>
-    <File Name="rtl/pll_3x_lowfreq_bb.v"/>
-    <File Name="rtl/linebuf_inst.v"/>
-    <File Name="rtl/videogen.v"/>
-    <File Name="rtl/timescale.v"/>
-    <File Name="rtl/pll_2x_bb.v"/>
-    <File Name="rtl/linebuf.v"/>
-    <File Name="rtl/pll_3x.v"/>
-    <File Name="rtl/scanconverter.v"/>
-    <File Name="rtl/linebuf_bb.v"/>
-  </VirtualDirectory>
-  <Dependencies Name="Debug"/>
-  <Dependencies Name="Release"/>
 </CodeLite_Project>

ossc_sw_bsp.project

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_sw_bsp" InternalType="">
+<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="11000">
   <Plugins>
     <Plugin Name="qmake">
       <![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
@@ -26,24 +26,41 @@
  }]]]>
     </Plugin>
   </Plugins>
+  <Reconciliation>
+    <Regexes/>
+    <Excludepaths/>
+    <Ignorefiles/>
+    <Extensions>
+      <![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
+    </Extensions>
+    <Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
+  </Reconciliation>
   <VirtualDirectory Name="software">
     <VirtualDirectory Name="sys_controller_bsp">
       <VirtualDirectory Name="drivers">
         <VirtualDirectory Name="inc">
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller2_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller2.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/osd_generator_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/sc_config_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer_regs.h"/>
+          <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/ci_crc.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/crc.h"/>
-          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod_regs.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h"/>
-          <File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores_regs.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
           <File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_pio_regs.h"/>
         </VirtualDirectory>
         <VirtualDirectory Name="src">
-          <File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller_mod.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_vars.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c"/>
+          <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_sc.c"/>
           <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_read.c"/>
           <File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c"/>
           <File Name="software/sys_controller_bsp/drivers/src/ci_crc.c"/>
@@ -191,62 +208,6 @@
       <File Name="software/sys_controller_bsp/system.h"/>
     </VirtualDirectory>
   </VirtualDirectory>
-  <VirtualDirectory Name="ip">
-    <VirtualDirectory Name="i2c_opencores">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="inc">
-          <File Name="ip/i2c_opencores/HAL/inc/i2c_opencores.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/i2c_opencores/HAL/src/i2c_opencores.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-      <VirtualDirectory Name="Docs">
-        <File Name="ip/i2c_opencores/Docs/I2C_tests.c"/>
-      </VirtualDirectory>
-      <VirtualDirectory Name="inc">
-        <File Name="ip/i2c_opencores/inc/i2c_opencores_regs.h"/>
-      </VirtualDirectory>
-    </VirtualDirectory>
-    <VirtualDirectory Name="nios2_hw_crc">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="doc">
-          <File Name="ip/nios2_hw_crc/HAL/doc/crc_main.c"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="inc">
-          <File Name="ip/nios2_hw_crc/HAL/inc/ci_crc.h"/>
-          <File Name="ip/nios2_hw_crc/HAL/inc/crc.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/nios2_hw_crc/HAL/src/ci_crc.c"/>
-          <File Name="ip/nios2_hw_crc/HAL/src/crc.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-    </VirtualDirectory>
-    <VirtualDirectory Name="altera_up_sd_card_avalon_interface_mod">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="inc">
-          <File Name="ip/altera_up_sd_card_avalon_interface_mod/HAL/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/altera_up_sd_card_avalon_interface_mod/HAL/src/Altera_UP_SD_Card_Avalon_Interface_mod.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-    </VirtualDirectory>
-    <VirtualDirectory Name="altera_epcq_controller_mod">
-      <VirtualDirectory Name="HAL">
-        <VirtualDirectory Name="inc">
-          <File Name="ip/altera_epcq_controller_mod/HAL/inc/altera_epcq_controller_mod.h"/>
-        </VirtualDirectory>
-        <VirtualDirectory Name="src">
-          <File Name="ip/altera_epcq_controller_mod/HAL/src/altera_epcq_controller_mod.c"/>
-        </VirtualDirectory>
-      </VirtualDirectory>
-      <VirtualDirectory Name="inc">
-        <File Name="ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h"/>
-      </VirtualDirectory>
-    </VirtualDirectory>
-  </VirtualDirectory>
   <Description/>
   <Dependencies/>
   <Dependencies Name="Debug"/>
@@ -280,10 +241,9 @@
       <PreBuild/>
       <PostBuild/>
       <CustomBuild Enabled="yes">
-        <Target Name="nios2-bsp-editor">nios2-bsp-editor</Target>
         <RebuildCommand/>
         <CleanCommand>make clean</CleanCommand>
-        <BuildCommand>nios2-bsp-generate-files --bsp-dir . --settings settings.bsp</BuildCommand>
+        <BuildCommand>make</BuildCommand>
         <PreprocessFileCommand/>
         <SingleFileCommand/>
         <MakefileGenerationCommand/>
@@ -320,10 +280,9 @@
       <PreBuild/>
       <PostBuild/>
       <CustomBuild Enabled="yes">
-        <Target Name="nios2-bsp-editor">nios2-bsp-editor</Target>
         <RebuildCommand/>
         <CleanCommand>make clean</CleanCommand>
-        <BuildCommand>nios2-bsp-generate-files --bsp-dir ./ --settings settings.bsp</BuildCommand>
+        <BuildCommand>make</BuildCommand>
         <PreprocessFileCommand/>
         <SingleFileCommand/>
         <MakefileGenerationCommand/>

rtl/char_array.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_bb.v"]

rtl/char_array.v

@@ -0,0 +1,223 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: char_array.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module char_array (
+	byteena_a,
+	data,
+	rdaddress,
+	rdclock,
+	wraddress,
+	wrclock,
+	wren,
+	q);
+
+	input	[3:0]  byteena_a;
+	input	[31:0]  data;
+	input	[9:0]  rdaddress;
+	input	  rdclock;
+	input	[7:0]  wraddress;
+	input	  wrclock;
+	input	  wren;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	[3:0]  byteena_a;
+	tri1	  wrclock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.byteena_a (byteena_a),
+				.clock0 (wrclock),
+				.clock1 (rdclock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_b (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({8{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK1",
+		altsyncram_component.byte_size = 8,
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.numwords_b = 1024,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK1",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.widthad_b = 10,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 8,
+		altsyncram_component.width_byteena_a = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "1"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
+// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
+// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
+// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

rtl/char_rom.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_bb.v"]

rtl/char_rom.v

@@ -0,0 +1,165 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: char_rom.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module char_rom (
+	address,
+	clock,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	output	[63:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [63:0] sub_wire0;
+	wire [63:0] q = sub_wire0[63:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({64{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "./ip/osd_generator/bin/char_rom.rif"
+`else
+		altsyncram_component.init_file = "./ip/osd_generator/bin/char_rom.hex"
+`endif
+,
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 64,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./ip/osd_generator/bin/char_rom.hex"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "64"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./ip/osd_generator/bin/char_rom.hex"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

rtl/lat_tester.v

@@ -0,0 +1,111 @@
+//
+// Copyright (C) 2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+`define LT_STATE_IDLE       2'h0
+`define LT_STATE_LAT_MEAS   2'h1
+`define LT_STATE_STB_MEAS   2'h2
+`define LT_STATE_FINISHED   2'h3
+
+module lat_tester (
+    input clk27,
+    input pclk,
+    input active,
+    input armed,
+    input sensor,
+    input trigger,
+    input VSYNC_in,
+    input [1:0] mode_in,
+    output reg [2:0] mode_synced,
+    output reg [15:0] lat_result,
+    output reg [11:0] stb_result,
+    output trig_waiting,
+    output reg finished
+);
+
+reg VSYNC_in_L, VSYNC_in_LL, trigger_L, trigger_LL;
+reg [8:0] clk27_ctr;
+reg [1:0] state;
+
+assign trig_waiting = (state == `LT_STATE_LAT_MEAS);
+
+always @(posedge pclk) begin
+    VSYNC_in_L <= VSYNC_in;
+    VSYNC_in_LL <= VSYNC_in_L;
+end
+
+always @(posedge pclk) begin
+    if (VSYNC_in_LL && !VSYNC_in_L)
+        mode_synced <= mode_in;
+end
+
+always @(posedge clk27) begin
+    trigger_L <= trigger;
+    trigger_LL <= trigger_L;
+end
+
+always @(posedge clk27) begin
+    if (!active) begin
+        state <= `LT_STATE_IDLE;
+    end else begin
+        case (state)
+            default: begin //STATE_IDLE
+                finished <= 1'b0;
+                lat_result <= 0;
+                stb_result <= 0;
+                clk27_ctr <= 0;
+                if (armed && trigger_LL)
+                    state <= `LT_STATE_LAT_MEAS;
+            end
+            `LT_STATE_LAT_MEAS: begin
+                if (sensor==0) begin
+                    state <= `LT_STATE_STB_MEAS;
+                    clk27_ctr <= 0;
+                end else if (lat_result==16'hffff) begin
+                    state <= `LT_STATE_FINISHED;
+                end else begin
+                    if (clk27_ctr == 270-1) begin
+                        clk27_ctr <= 0;
+                        lat_result <= lat_result + 1'b1;
+                    end else begin
+                        clk27_ctr <= clk27_ctr + 1'b1;
+                    end
+                end
+            end    
+            `LT_STATE_STB_MEAS: begin
+                if (((sensor==1) && (stb_result >= 12'd100)) || (stb_result == 12'hfff)) begin
+                    state <= `LT_STATE_FINISHED;
+                end else begin
+                    if (clk27_ctr == 270-1) begin
+                        clk27_ctr <= 0;
+                        stb_result <= stb_result + 1'b1;
+                    end else begin
+                        clk27_ctr <= clk27_ctr + 1'b1;
+                    end
+                end
+            end
+            `LT_STATE_FINISHED: begin
+                finished <= 1'b1;
+                if (!armed)
+                    state <= `LT_STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+endmodule

rtl/lat_tester_includes.v

@@ -0,0 +1,26 @@
+//
+// Copyright (C) 2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
+//
+// This file is part of Open Source Scan Converter project.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+`define LT_POS_NONE         2'b00
+`define LT_POS_TOPLEFT      2'b01
+`define LT_POS_CENTER       2'b10
+`define LT_POS_BOTTOMRIGHT  2'b11
+
+`define LT_WIDTH_DIV        4'h8
+`define LT_HEIGHT_DIV       4'h8

rtl/linebuf.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.0"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]

rtl/linebuf.v

@@ -14,24 +14,24 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
 //to the terms and conditions of the Intel Program License 
 //Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other 
-//applicable license agreement, including, without limitation, 
-//that your use is for the sole purpose of programming logic 
-//devices manufactured by Intel and sold by Intel or its 
-//authorized distributors.  Please refer to the applicable 
-//agreement for further details.
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off

rtl/lpm_mult_4_hybr_ref.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_bb.v"]

rtl/lpm_mult_4_hybr_ref.v

@@ -0,0 +1,117 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpm_mult_4_hybr_ref.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpm_mult_4_hybr_ref (
+	clock,
+	dataa,
+	datab,
+	result);
+
+	input	  clock;
+	input	[8:0]  dataa;
+	input	[7:0]  datab;
+	output	[8:0]  result;
+
+	wire [8:0] sub_wire0;
+	wire [8:0] result = sub_wire0[8:0];
+
+	lpm_mult	lpm_mult_component (
+				.clock (clock),
+				.dataa (dataa),
+				.datab (datab),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
+		lpm_mult_component.lpm_pipeline = 1,
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 9,
+		lpm_mult_component.lpm_widthb = 8,
+		lpm_mult_component.lpm_widthp = 9;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "8"
+// Retrieval info: PRIVATE: WidthP NUMERIC "9"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
+// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
+// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

rtl/lpm_mult_4_hybr_ref_pre.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"]

rtl/lpm_mult_4_hybr_ref_pre.v

@@ -0,0 +1,117 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpm_mult_4_hybr_ref_pre.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpm_mult_4_hybr_ref_pre (
+	clock,
+	dataa,
+	datab,
+	result);
+
+	input	  clock;
+	input	[7:0]  dataa;
+	input	[4:0]  datab;
+	output	[8:0]  result;
+
+	wire [8:0] sub_wire0;
+	wire [8:0] result = sub_wire0[8:0];
+
+	lpm_mult	lpm_mult_component (
+				.clock (clock),
+				.dataa (dataa),
+				.datab (datab),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
+		lpm_mult_component.lpm_pipeline = 1,
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 8,
+		lpm_mult_component.lpm_widthb = 5,
+		lpm_mult_component.lpm_widthp = 9;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "8"
+// Retrieval info: PRIVATE: WidthB NUMERIC "5"
+// Retrieval info: PRIVATE: WidthP NUMERIC "9"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
+// Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL "datab[4..0]"
+// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
+// Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0
+// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

rtl/lpm_mult_4_sl.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "17.0"
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"]

rtl/lpm_mult_4_sl.v

@@ -0,0 +1,117 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpm_mult_4_sl.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpm_mult_4_sl (
+	clock,
+	dataa,
+	datab,
+	result);
+
+	input	  clock;
+	input	[7:0]  dataa;
+	input	[7:0]  datab;
+	output	[7:0]  result;
+
+	wire [7:0] sub_wire0;
+	wire [7:0] result = sub_wire0[7:0];
+
+	lpm_mult	lpm_mult_component (
+				.clock (clock),
+				.dataa (dataa),
+				.datab (datab),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
+		lpm_mult_component.lpm_pipeline = 1,
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 8,
+		lpm_mult_component.lpm_widthb = 8,
+		lpm_mult_component.lpm_widthp = 8;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "8"
+// Retrieval info: PRIVATE: WidthB NUMERIC "8"
+// Retrieval info: PRIVATE: WidthP NUMERIC "8"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "8"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
+// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
+// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
+// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
+// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

rtl/ossc.v

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -18,8 +18,7 @@
 //
 
 //`define DEBUG
-`define VIDEOGEN
-`define CPU_RESET_WIDTH 27  //1us
+`define PO_RESET_WIDTH 27  //1us
 
 module ossc (
     input clk27,
@@ -34,16 +33,16 @@ module ossc (
     input VSYNC_in,
     input HSYNC_in,
     input PCLK_in,
-    output [7:0] HDMI_TX_RD,
-    output [7:0] HDMI_TX_GD,
-    output [7:0] HDMI_TX_BD,
-    output HDMI_TX_DE,
-    output HDMI_TX_HS,
-    output HDMI_TX_VS,
     output HDMI_TX_PCLK,
+    output reg [7:0] HDMI_TX_RD,
+    output reg [7:0] HDMI_TX_GD,
+    output reg [7:0] HDMI_TX_BD,
+    output reg HDMI_TX_DE,
+    output reg HDMI_TX_HS,
+    output reg HDMI_TX_VS,
     input HDMI_TX_INT_N,
     input HDMI_TX_MODE,
-    output reset_n,
+    output hw_reset_n,
     output LED_G,
     output LED_R,
     output LCD_RS,
@@ -54,32 +53,34 @@ module ossc (
     inout [3:0] SD_DAT
 );
 
-wire [7:0] sys_ctrl;
-wire h_unstable;
-wire [1:0] pclk_lock;
-wire [1:0] pll_lock_lost;
-wire [31:0] h_info, h_info2, v_info, extra_info;
+
+wire [15:0] sys_ctrl;
+wire h_unstable, pll_lock_lost;
+wire [31:0] h_config, h_config2, v_config, misc_config, sl_config, sl_config2;
 wire [10:0] vmax, vmax_tvp;
 wire [1:0] fpga_vsyncgen;
+wire ilace_flag, vsync_flag;
+wire [19:0] pcnt_frame;
 
 wire [15:0] ir_code;
 wire [7:0] ir_code_cnt;
 
-wire [7:0] R_out, G_out, B_out;
-wire HSYNC_out;
-wire VSYNC_out;
+wire [7:0] R_out_sc, G_out_sc, B_out_sc;
+wire HSYNC_out_sc;
+wire VSYNC_out_sc;
 wire PCLK_out;
-wire DE_out;
+wire DE_out_sc;
 
-wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
-wire HSYNC_out_videogen;
-wire VSYNC_out_videogen;
-wire PCLK_out_videogen;
-wire DE_out_videogen;
+wire [7:0] R_out_vg, G_out_vg, B_out_vg;
+wire HSYNC_out_vg;
+wire VSYNC_out_vg;
+wire DE_out_vg;
 
 
-reg [7:0] cpu_reset_ctr = 0;
-reg cpu_reset_n = 1'b0;
+reg [7:0] po_reset_ctr = 0;
+reg po_reset_n = 1'b0;
+wire jtagm_reset_req;
+wire sys_reset_n = (po_reset_n & ~jtagm_reset_req);
 
 reg [7:0] R_in_L, G_in_L, B_in_L;
 reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
@@ -87,10 +88,35 @@ reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
 reg [1:0] btn_L, btn_LL;
 reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
 
+wire lt_sensor = btn_LL[1];
+wire lt_active = sys_ctrl[15];
+wire lt_armed = sys_ctrl[14];
+wire lt_trigger = HDMI_TX_DE & HDMI_TX_GD[0];
+wire [1:0] lt_mode = sys_ctrl[13:12];
+wire [1:0] lt_mode_synced;
+wire [15:0] lt_lat_result;
+wire [11:0] lt_stb_result;
+wire lt_trig_waiting;
+wire lt_finished;
+
+wire remote_event = sys_ctrl[8];
+reg remove_event_prev;
+reg [14:0] to_ctr, to_ctr_ms;
+wire lcd_bl_timeout;
+
+wire [1:0] osd_color;
+wire osd_enable_pre;
+wire osd_enable = osd_enable_pre & ~lt_active;
+wire [10:0] xpos, xpos_sc, xpos_vg;
+wire [10:0] ypos, ypos_sc, ypos_vg;
+
+wire pll_areset, pll_scanclk, pll_scanclkena, pll_configupdate, pll_scandata, pll_scandone, pll_activeclock;
+
+
 // Latch inputs from TVP7002 (synchronized to PCLK_in)
-always @(posedge PCLK_in or negedge reset_n)
+always @(posedge PCLK_in or negedge hw_reset_n)
 begin
-    if (!reset_n) begin
+    if (!hw_reset_n) begin
         R_in_L <= 8'h00;
         G_in_L <= 8'h00;
         B_in_L <= 8'h00;
@@ -108,9 +134,9 @@ begin
 end
 
 // Insert synchronizers to async inputs (synchronize to CPU clock)
-always @(posedge clk27 or negedge cpu_reset_n)
+always @(posedge clk27 or negedge po_reset_n)
 begin
-    if (!cpu_reset_n) begin
+    if (!po_reset_n) begin
         btn_L <= 2'b00;
         btn_LL <= 2'b00;
         ir_rx_L <= 1'b0;
@@ -131,56 +157,95 @@ begin
     end
 end
 
-// CPU reset pulse generation (is this really necessary?)
+// Power-on reset pulse generation (not strictly necessary)
 always @(posedge clk27)
 begin
-    if (cpu_reset_ctr == `CPU_RESET_WIDTH)
-        cpu_reset_n <= 1'b1;
+    if (po_reset_ctr == `PO_RESET_WIDTH)
+        po_reset_n <= 1'b1;
     else
-        cpu_reset_ctr <= cpu_reset_ctr + 1'b1;
+        po_reset_ctr <= po_reset_ctr + 1'b1;
 end
 
-assign reset_n = sys_ctrl[0];   //HDMI_TX_RST_N in v1.2 PCB
+assign hw_reset_n = sys_ctrl[0];   //HDMI_TX_RST_N in v1.2 PCB
 
 
 `ifdef DEBUG
 assign LED_R = HSYNC_in_L;
 assign LED_G = VSYNC_in_L;
 `else
-assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 2'h0)|h_unstable);
-assign LED_G = (ir_code == 0);
+assign LED_R = lt_active ? lt_trig_waiting : (pll_lock_lost|h_unstable);
+assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0);
 `endif
 
 assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
 assign LCD_CS_N = sys_ctrl[6];
 assign LCD_RS = sys_ctrl[5];
-assign LCD_BL = sys_ctrl[4];    //reset_n in v1.2 PCB
+wire lcd_bl_on = sys_ctrl[4];    //hw_reset_n in v1.2 PCB
+wire [1:0] lcd_bl_time = sys_ctrl[3:2];
+assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
 
-`ifdef VIDEOGEN
-wire videogen_sel;
-assign videogen_sel = ~sys_ctrl[1];
-assign HDMI_TX_RD = videogen_sel ? R_out_videogen : R_out;
-assign HDMI_TX_GD = videogen_sel ? G_out_videogen : G_out;
-assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
-assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
-assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
-assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
-assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
-`else
-wire videogen_sel;
-assign videogen_sel = 1'b0;
-assign HDMI_TX_RD = R_out;
-assign HDMI_TX_GD = G_out;
-assign HDMI_TX_BD = B_out;
-assign HDMI_TX_HS = HSYNC_out;
-assign HDMI_TX_VS = VSYNC_out;
+wire enable_sc = sys_ctrl[1];
+assign xpos = enable_sc ? xpos_sc : xpos_vg;
+assign ypos = enable_sc ? ypos_sc : ypos_vg;
 assign HDMI_TX_PCLK = PCLK_out;
-assign HDMI_TX_DE = DE_out;
-`endif
+
+always @(posedge PCLK_out) begin
+    if (osd_enable) begin
+        if (osd_color == 2'h0) begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h000000;
+        end else if (osd_color == 2'h1) begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h0000ff;
+        end else if (osd_color == 2'h2) begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffff00;
+        end else begin
+            {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffffff;
+        end
+    end else if (enable_sc) begin
+        {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_out_sc, G_out_sc, B_out_sc};
+    end else begin
+        {HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_out_vg, G_out_vg, B_out_vg};
+    end
+
+    HDMI_TX_HS <= enable_sc ? HSYNC_out_sc : HSYNC_out_vg;
+    HDMI_TX_VS <= enable_sc ? VSYNC_out_sc : VSYNC_out_vg;
+    HDMI_TX_DE <= enable_sc ? DE_out_sc : DE_out_vg;
+end
+
+// LCD backlight timeout counters
+always @(posedge clk27)
+begin
+    if (remote_event != remove_event_prev) begin
+        to_ctr <= 15'd0;
+        to_ctr_ms <= 15'd0;
+    end else begin
+        if (to_ctr == 27000-1) begin
+            to_ctr <= 0;
+            if (to_ctr_ms < 15'h7fff)
+                to_ctr_ms <= to_ctr_ms + 1'b1;
+        end else begin
+            to_ctr <= to_ctr + 1'b1;
+        end
+    end
+
+    case (lcd_bl_time)
+        default: lcd_bl_timeout <= 0; //off
+        2'b01:  lcd_bl_timeout <= (to_ctr_ms >= 3000);  //3s
+        2'b10:  lcd_bl_timeout <= (to_ctr_ms >= 10000); //10s
+        2'b11:  lcd_bl_timeout <= (to_ctr_ms >= 30000); //30s
+    endcase
+
+    remove_event_prev <= remote_event;
+end
+
 
 sys sys_inst(
     .clk_clk                                (clk27),
-    .reset_reset_n                          (cpu_reset_n),
+    .reset_reset_n                          (sys_reset_n),
+    .pulpino_0_config_testmode_i            (1'b0),
+    .pulpino_0_config_fetch_enable_i        (1'b1),
+    .pulpino_0_config_clock_gating_i        (1'b0),
+    .pulpino_0_config_boot_addr_i           (32'h00010000),
+    .master_0_master_reset_reset            (jtagm_reset_req),
     .i2c_opencores_0_export_scl_pad_io      (scl),
     .i2c_opencores_0_export_sda_pad_io      (sda),
     .i2c_opencores_0_export_spi_miso_pad_i  (1'b0),
@@ -188,64 +253,112 @@ sys sys_inst(
     .i2c_opencores_1_export_sda_pad_io      (SD_CMD),
     .i2c_opencores_1_export_spi_miso_pad_i  (SD_DAT[0]),
     .pio_0_sys_ctrl_out_export              (sys_ctrl),
-    .pio_1_controls_in_export               ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
-    .pio_2_status_in_export                 ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 5'h0, vmax}),
-    .pio_3_h_info_out_export                (h_info),
-    .pio_4_h_info2_out_export               (h_info2),
-    .pio_5_v_info_out_export                (v_info),
-    .pio_6_extra_info_out_export            (extra_info)
+    .pio_1_controls_in_export               ({ir_code_cnt, 4'b0000, pll_activeclock, HDMI_TX_MODE_LL, btn_LL, ir_code}),
+    .sc_config_0_sc_if_sc_status_i          ({vsync_flag, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}),
+    .sc_config_0_sc_if_sc_status2_i         ({12'h000, pcnt_frame}),
+    .sc_config_0_sc_if_lt_status_i          ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}),
+    .sc_config_0_sc_if_h_config_o           (h_config),
+    .sc_config_0_sc_if_h_config2_o          (h_config2),
+    .sc_config_0_sc_if_v_config_o           (v_config),
+    .sc_config_0_sc_if_misc_config_o        (misc_config),
+    .sc_config_0_sc_if_sl_config_o          (sl_config),
+    .sc_config_0_sc_if_sl_config2_o         (sl_config2),
+    .osd_generator_0_osd_if_vclk            (PCLK_out),
+    .osd_generator_0_osd_if_xpos            (xpos),
+    .osd_generator_0_osd_if_ypos            (ypos),
+    .osd_generator_0_osd_if_osd_enable      (osd_enable_pre),
+    .osd_generator_0_osd_if_osd_color       (osd_color),
+    .pll_reconfig_0_pll_reconfig_if_areset       (pll_areset),
+    .pll_reconfig_0_pll_reconfig_if_scanclk      (pll_scanclk),
+    .pll_reconfig_0_pll_reconfig_if_scanclkena   (pll_scanclkena),
+    .pll_reconfig_0_pll_reconfig_if_configupdate (pll_configupdate),
+    .pll_reconfig_0_pll_reconfig_if_scandata     (pll_scandata),
+    .pll_reconfig_0_pll_reconfig_if_scandone     (pll_scandone)
 );
 
 scanconverter scanconverter_inst (
-    .reset_n        (reset_n),
+    .reset_n        (hw_reset_n),
     .PCLK_in        (PCLK_in),
     .clk27          (clk27),
+    .enable_sc      (enable_sc),
     .HSYNC_in       (HSYNC_in_L),
     .VSYNC_in       (VSYNC_in_L),
     .FID_in         (FID_in_L),
     .R_in           (R_in_L),
     .G_in           (G_in_L),
     .B_in           (B_in_L),
-    .h_info         (h_info),
-    .h_info2        (h_info2),
-    .v_info         (v_info),
-    .extra_info     (extra_info),
-    .R_out          (R_out),
-    .G_out          (G_out),
-    .B_out          (B_out),
-    .HSYNC_out      (HSYNC_out),
-    .VSYNC_out      (VSYNC_out),
+    .h_config       (h_config),
+    .h_config2      (h_config2),
+    .v_config       (v_config),
+    .misc_config    (misc_config),
+    .sl_config      (sl_config),
+    .sl_config2     (sl_config2),
+    .R_out          (R_out_sc),
+    .G_out          (G_out_sc),
+    .B_out          (B_out_sc),
     .PCLK_out       (PCLK_out),
-    .DE_out         (DE_out),
+    .HSYNC_out      (HSYNC_out_sc),
+    .VSYNC_out      (VSYNC_out_sc),
+    .DE_out         (DE_out_sc),
     .h_unstable     (h_unstable),
     .fpga_vsyncgen  (fpga_vsyncgen),
-    .pclk_lock      (pclk_lock),
     .pll_lock_lost  (pll_lock_lost),
     .vmax           (vmax),
-    .vmax_tvp       (vmax_tvp)
+    .vmax_tvp       (vmax_tvp),
+    .pcnt_frame     (pcnt_frame),
+    .ilace_flag     (ilace_flag),
+    .vsync_flag     (vsync_flag),
+    .lt_active      (lt_active),
+    .lt_mode        (lt_mode_synced),
+    .xpos           (xpos_sc),
+    .ypos           (ypos_sc),
+    .pll_areset       (pll_areset),
+    .pll_scanclk      (pll_scanclk),
+    .pll_scanclkena   (pll_scanclkena),
+    .pll_configupdate (pll_configupdate),
+    .pll_scandata     (pll_scandata),
+    .pll_scandone     (pll_scandone),
+    .pll_activeclock  (pll_activeclock)
 );
 
 ir_rcv ir0 (
     .clk27          (clk27),
-    .reset_n        (cpu_reset_n),
+    .reset_n        (po_reset_n),
     .ir_rx          (ir_rx_LL),
     .ir_code        (ir_code),
     .ir_code_ack    (),
     .ir_code_cnt    (ir_code_cnt)
 );
 
-`ifdef VIDEOGEN
-videogen vg0 (
+lat_tester lt0 (
     .clk27          (clk27),
-    .reset_n        (cpu_reset_n & videogen_sel),
-    .R_out          (R_out_videogen),
-    .G_out          (G_out_videogen),
-    .B_out          (B_out_videogen),
-    .HSYNC_out      (HSYNC_out_videogen),
-    .VSYNC_out      (VSYNC_out_videogen),
-    .PCLK_out       (PCLK_out_videogen),
-    .ENABLE_out     (DE_out_videogen)
+    .pclk           (PCLK_out),
+    .active         (lt_active),
+    .armed          (lt_armed),
+    .sensor         (lt_sensor),
+    .trigger        (lt_trigger),
+    .VSYNC_in       (HDMI_TX_VS),
+    .mode_in        (lt_mode),
+    .mode_synced    (lt_mode_synced),
+    .lat_result     (lt_lat_result),
+    .stb_result     (lt_stb_result),
+    .trig_waiting   (lt_trig_waiting),
+    .finished       (lt_finished)
+);
+
+videogen vg0 (
+    .clk27          (PCLK_out),
+    .reset_n        (po_reset_n & ~enable_sc),
+    .lt_active      (lt_active),
+    .lt_mode        (lt_mode_synced),
+    .R_out          (R_out_vg),
+    .G_out          (G_out_vg),
+    .B_out          (B_out_vg),
+    .HSYNC_out      (HSYNC_out_vg),
+    .VSYNC_out      (VSYNC_out_vg),
+    .DE_out         (DE_out_vg),
+    .xpos           (xpos_vg),
+    .ypos           (ypos_vg)
 );
-`endif
 
 endmodule

rtl/pll_2x.ppf

@@ -3,10 +3,19 @@
 <pinplan intended_family="Cyclone IV E" variation_name="pll_2x" megafunction_name="ALTPLL" specifies="all_ports">
 <global>
 <pin name="areset" direction="input" scope="external"  />
+<pin name="clkswitch" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
 <pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="inclk1" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="activeclock" direction="output" scope="external"  />
 <pin name="c0" direction="output" scope="external" source="clock"  />
 <pin name="c1" direction="output" scope="external" source="clock"  />
 <pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
 
 </global>
 </pinplan>

rtl/pll_2x.qip

@@ -1,6 +1,7 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "17.0"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]

rtl/pll_2x.v

@@ -9,29 +9,29 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			
+// 			altera_mf
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
 //to the terms and conditions of the Intel Program License 
 //Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other 
-//applicable license agreement, including, without limitation, 
-//that your use is for the sole purpose of programming logic 
-//devices manufactured by Intel and sold by Intel or its 
-//authorized distributors.  Please refer to the applicable 
-//agreement for further details.
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
 
 
 // synopsys translate_off
@@ -39,46 +39,79 @@
 // synopsys translate_on
 module pll_2x (
 	areset,
+	clkswitch,
+	configupdate,
 	inclk0,
+	inclk1,
+	scanclk,
+	scanclkena,
+	scandata,
+	activeclock,
 	c0,
 	c1,
-	locked);
+	locked,
+	scandataout,
+	scandone);
 
 	input	  areset;
+	input	  clkswitch;
+	input	  configupdate;
 	input	  inclk0;
+	input	  inclk1;
+	input	  scanclk;
+	input	  scanclkena;
+	input	  scandata;
+	output	  activeclock;
 	output	  c0;
 	output	  c1;
 	output	  locked;
+	output	  scandataout;
+	output	  scandone;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
 	tri0	  areset;
+	tri0	  clkswitch;
+	tri0	  configupdate;
+	tri0	  scanclkena;
+	tri0	  scandata;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_on
 `endif
 
-	wire [4:0] sub_wire0;
-	wire  sub_wire3;
-	wire [0:0] sub_wire6 = 1'h0;
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  locked = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+	wire  sub_wire0;
+	wire [4:0] sub_wire1;
+	wire  sub_wire4;
+	wire  sub_wire5;
+	wire  sub_wire6;
+	wire  sub_wire9 = inclk1;
+	wire  activeclock = sub_wire0;
+	wire [1:1] sub_wire3 = sub_wire1[1:1];
+	wire [0:0] sub_wire2 = sub_wire1[0:0];
+	wire  c0 = sub_wire2;
+	wire  c1 = sub_wire3;
+	wire  locked = sub_wire4;
+	wire  scandataout = sub_wire5;
+	wire  scandone = sub_wire6;
+	wire  sub_wire7 = inclk0;
+	wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
 
 	altpll	altpll_component (
 				.areset (areset),
-				.inclk (sub_wire5),
-				.clk (sub_wire0),
-				.locked (sub_wire3),
-				.activeclock (),
+				.clkswitch (clkswitch),
+				.configupdate (configupdate),
+				.inclk (sub_wire8),
+				.scanclk (scanclk),
+				.scanclkena (scanclkena),
+				.scandata (scandata),
+				.activeclock (sub_wire0),
+				.clk (sub_wire1),
+				.locked (sub_wire4),
+				.scandataout (sub_wire5),
+				.scandone (sub_wire6),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
 				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
 				.enable0 (),
 				.enable1 (),
 				.extclk (),
@@ -95,11 +128,6 @@ module pll_2x (
 				.phaseupdown (1'b1),
 				.pllena (1'b1),
 				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
 				.scanread (1'b0),
 				.scanwrite (1'b0),
 				.sclkout0 (),
@@ -110,29 +138,30 @@ module pll_2x (
 		altpll_component.bandwidth_type = "HIGH",
 		altpll_component.clk0_divide_by = 1,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_multiply_by = 1,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.clk1_divide_by = 1,
 		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_multiply_by = 1,
 		altpll_component.clk1_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.inclk1_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone IV E",
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_2x",
 		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
+		altpll_component.operation_mode = "NORMAL",
 		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_activeclock = "PORT_USED",
 		altpll_component.port_areset = "PORT_USED",
 		altpll_component.port_clkbad0 = "PORT_UNUSED",
 		altpll_component.port_clkbad1 = "PORT_UNUSED",
 		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_USED",
+		altpll_component.port_configupdate = "PORT_USED",
 		altpll_component.port_fbin = "PORT_UNUSED",
 		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_inclk1 = "PORT_USED",
 		altpll_component.port_locked = "PORT_USED",
 		altpll_component.port_pfdena = "PORT_UNUSED",
 		altpll_component.port_phasecounterselect = "PORT_UNUSED",
@@ -141,11 +170,11 @@ module pll_2x (
 		altpll_component.port_phaseupdown = "PORT_UNUSED",
 		altpll_component.port_pllena = "PORT_UNUSED",
 		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_USED",
+		altpll_component.port_scanclkena = "PORT_USED",
+		altpll_component.port_scandata = "PORT_USED",
+		altpll_component.port_scandataout = "PORT_USED",
+		altpll_component.port_scandone = "PORT_USED",
 		altpll_component.port_scanread = "PORT_UNUSED",
 		altpll_component.port_scanwrite = "PORT_UNUSED",
 		altpll_component.port_clk0 = "PORT_USED",
@@ -164,8 +193,16 @@ module pll_2x (
 		altpll_component.port_extclk1 = "PORT_UNUSED",
 		altpll_component.port_extclk2 = "PORT_UNUSED",
 		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.primary_clock = "inclk0",
 		altpll_component.self_reset_on_loss_lock = "OFF",
-		altpll_component.width_clock = 5;
+		altpll_component.switch_over_type = "MANUAL",
+		altpll_component.width_clock = 5,
+`ifdef NO_PLI
+		altpll_component.scan_chain_mif_file = "pll_2x.rif"
+`else
+		altpll_component.scan_chain_mif_file = "pll_2x.hex"
+`endif
+;
 
 
 endmodule
@@ -173,7 +210,7 @@ endmodule
 // ============================================================
 // CNX file retrieval info
 // ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
@@ -185,16 +222,16 @@ endmodule
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "54.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "135.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "27.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -204,7 +241,7 @@ endmodule
 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
 // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
@@ -219,9 +256,9 @@ endmodule
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
@@ -245,8 +282,8 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.hex"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
@@ -255,7 +292,7 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
@@ -271,28 +308,29 @@ endmodule
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
@@ -301,11 +339,11 @@ endmodule
 // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
@@ -324,25 +362,48 @@ endmodule
 // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_2x.hex"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock"
 // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
+// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
+// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+// Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.ppf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.inc FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.cmp FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
+// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

rtl/pll_3x.ppf

@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone IV E" variation_name="pll_3x" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="areset" direction="input" scope="external"  />
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>

rtl/pll_3x.v

@@ -1,348 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: pll_3x.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other 
-//applicable license agreement, including, without limitation, 
-//that your use is for the sole purpose of programming logic 
-//devices manufactured by Intel and sold by Intel or its 
-//authorized distributors.  Please refer to the applicable 
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll_3x (
-	areset,
-	inclk0,
-	c0,
-	c1,
-	locked);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c0;
-	output	  c1;
-	output	  locked;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [4:0] sub_wire0;
-	wire  sub_wire3;
-	wire [0:0] sub_wire6 = 1'h0;
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  locked = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
-
-	altpll	altpll_component (
-				.areset (areset),
-				.inclk (sub_wire5),
-				.clk (sub_wire0),
-				.locked (sub_wire3),
-				.activeclock (),
-				.clkbad (),
-				.clkena ({6{1'b1}}),
-				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena ({4{1'b1}}),
-				.fbin (1'b1),
-				.fbmimicbidir (),
-				.fbout (),
-				.fref (),
-				.icdrclk (),
-				.pfdena (1'b1),
-				.phasecounterselect ({4{1'b1}}),
-				.phasedone (),
-				.phasestep (1'b1),
-				.phaseupdown (1'b1),
-				.pllena (1'b1),
-				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
-				.scanread (1'b0),
-				.scanwrite (1'b0),
-				.sclkout0 (),
-				.sclkout1 (),
-				.vcooverrange (),
-				.vcounderrange ());
-	defparam
-		altpll_component.bandwidth_type = "HIGH",
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 3,
-		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 1,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 4,
-		altpll_component.clk1_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.inclk0_input_frequency = 37037,
-		altpll_component.intended_device_family = "Cyclone IV E",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x",
-		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
-		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_USED",
-		altpll_component.port_clkbad0 = "PORT_UNUSED",
-		altpll_component.port_clkbad1 = "PORT_UNUSED",
-		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
-		altpll_component.port_fbin = "PORT_UNUSED",
-		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
-		altpll_component.port_locked = "PORT_USED",
-		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_UNUSED",
-		altpll_component.port_phasedone = "PORT_UNUSED",
-		altpll_component.port_phasestep = "PORT_UNUSED",
-		altpll_component.port_phaseupdown = "PORT_UNUSED",
-		altpll_component.port_pllena = "PORT_UNUSED",
-		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
-		altpll_component.port_scanread = "PORT_UNUSED",
-		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_USED",
-		altpll_component.port_clk2 = "PORT_UNUSED",
-		altpll_component.port_clk3 = "PORT_UNUSED",
-		altpll_component.port_clk4 = "PORT_UNUSED",
-		altpll_component.port_clk5 = "PORT_UNUSED",
-		altpll_component.port_clkena0 = "PORT_UNUSED",
-		altpll_component.port_clkena1 = "PORT_UNUSED",
-		altpll_component.port_clkena2 = "PORT_UNUSED",
-		altpll_component.port_clkena3 = "PORT_UNUSED",
-		altpll_component.port_clkena4 = "PORT_UNUSED",
-		altpll_component.port_clkena5 = "PORT_UNUSED",
-		altpll_component.port_extclk0 = "PORT_UNUSED",
-		altpll_component.port_extclk1 = "PORT_UNUSED",
-		altpll_component.port_extclk2 = "PORT_UNUSED",
-		altpll_component.port_extclk3 = "PORT_UNUSED",
-		altpll_component.self_reset_on_loss_lock = "OFF",
-		altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "81.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "108.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
-// Retrieval info: CBX_MODULE_PREFIX: ON

rtl/pll_config_2x_5x_data.mif

@@ -0,0 +1,174 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone IV E
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/markus/Code/ossc/rtl/pll_config_2x_5x_data.mif
+--    Generated: Sat Oct  5 23:56:40 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 15 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   1;
+	42   :   1;
+	43   :   1;
+	44   :   1;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 15 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   1;
+	51   :   1;
+	52   :   1;
+	53   :   1;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 8 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   0;
+	62   :   0;
+	63   :   1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 7 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   1;
+	70   :   1;
+	71   :   1;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 3 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   1;
+	80   :   1;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 3 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   1;
+	89   :   1;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;

rtl/pll_config_3x_4x_data.mif

@@ -0,0 +1,174 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone IV E
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/markus/Code/ossc/rtl/pll_config_3x_4x_data.mif
+--    Generated: Sat Oct  5 23:58:13 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 6 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   0;
+	42   :   1;
+	43   :   1;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 6 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   0;
+	51   :   1;
+	52   :   1;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 2 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   0;
+	61   :   1;
+	62   :   0;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 2 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   0;
+	70   :   1;
+	71   :   0;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 2 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   1;
+	80   :   0;
+	81   :   1; -- clk1 counter: Odd Division = 1 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 1 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   1;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;

rtl/pll_config_default_data.mif

@@ -0,0 +1,174 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone IV E
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/markus/Code/ossc/rtl/pll_config_default_data.mif
+--    Generated: Wed Oct  9 22:20:06 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 8 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   1;
+	42   :   0;
+	43   :   0;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 8 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   1;
+	51   :   0;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 8 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   0;
+	62   :   0;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 8 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   1;
+	69   :   0;
+	70   :   0;
+	71   :   0;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 8 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   1;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 8 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   1;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;

rtl/videogen.v

@@ -17,37 +17,45 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+`include "lat_tester_includes.v"
+
 module videogen (
     input clk27,
     input reset_n,
-    output [7:0] R_out,
-    output [7:0] G_out,
-    output [7:0] B_out,
+    input lt_active,
+    input [1:0] lt_mode,
+    output reg [7:0] R_out,
+    output reg [7:0] G_out,
+    output reg [7:0] B_out,
     output reg HSYNC_out,
     output reg VSYNC_out,
-    output PCLK_out,
-    output reg ENABLE_out
+    output reg DE_out,
+    output reg [9:0] xpos,
+    output reg [9:0] ypos
 );
 
 //Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
-parameter   H_SYNCLEN       =   62;
-parameter   H_BACKPORCH     =   60;
-parameter   H_ACTIVE        =   720;
-parameter   H_FRONTPORCH    =   16;
-parameter   H_TOTAL         =   858;
+parameter   H_SYNCLEN       =   10'd62;
+parameter   H_BACKPORCH     =   10'd60;
+parameter   H_ACTIVE        =   10'd720;
+parameter   H_FRONTPORCH    =   10'd16;
+parameter   H_TOTAL         =   10'd858;
 
-parameter   V_SYNCLEN       =   6;
-parameter   V_BACKPORCH     =   30;
-parameter   V_ACTIVE        =   480;
-parameter   V_FRONTPORCH    =   9;
-parameter   V_TOTAL         =   525;
+parameter   V_SYNCLEN       =   10'd6;
+parameter   V_BACKPORCH     =   10'd30;
+parameter   V_ACTIVE        =   10'd480;
+parameter   V_FRONTPORCH    =   10'd9;
+parameter   V_TOTAL         =   10'd525;
 
-parameter   H_OVERSCAN      =   40; //at both sides
-parameter   V_OVERSCAN      =   16; //top and bottom
-parameter   H_AREA          =   640;
-parameter   V_AREA          =   448;
-parameter   H_BORDER        =   (H_AREA-512)/2;
-parameter   V_BORDER        =   (V_AREA-256)/2;
+parameter   H_OVERSCAN      =   10'd40; //at both sides
+parameter   V_OVERSCAN      =   10'd16; //top and bottom
+parameter   H_AREA          =   10'd640;
+parameter   V_AREA          =   10'd448;
+parameter   H_GRADIENT      =   10'd512;
+parameter   V_GRADIENT      =   10'd256;
+parameter   V_GRAYRAMP      =   10'd84;
+parameter   H_BORDER        =   ((H_AREA-H_GRADIENT)>>1);
+parameter   V_BORDER        =   ((V_AREA-V_GRADIENT)>>1);
 
 parameter   X_START     =   H_SYNCLEN + H_BACKPORCH;
 parameter   Y_START     =   V_SYNCLEN + V_BACKPORCH;
@@ -56,31 +64,23 @@ parameter   Y_START     =   V_SYNCLEN + V_BACKPORCH;
 reg [9:0] h_cnt; //max. 1024
 reg [9:0] v_cnt; //max. 1024
 
-reg [9:0] xpos;
-reg [9:0] ypos;
-
-assign PCLK_out = clk27;
-
-//R, G and B should be 0 outside of active area
-assign R_out = ENABLE_out ? V_gen : 8'h00;
-assign G_out = ENABLE_out ? V_gen : 8'h00;
-assign B_out = ENABLE_out ? V_gen : 8'h00;
-
-reg [7:0] V_gen;
-
-
 //HSYNC gen (negative polarity)
 always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n) begin
         h_cnt <= 0;
+        xpos <= 0;
         HSYNC_out <= 0;
     end else begin
         //Hsync counter
-        if (h_cnt < H_TOTAL-1)
+        if (h_cnt < H_TOTAL-1) begin
             h_cnt <= h_cnt + 1'b1;
-        else
+            if (h_cnt >= X_START)
+                xpos <= xpos + 1'b1;
+        end else begin
             h_cnt <= 0;
+            xpos <= 0;
+        end
 
         //Hsync signal
         HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
@@ -92,14 +92,19 @@ always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n) begin
         v_cnt <= 0;
+        ypos <= 0;
         VSYNC_out <= 0;
     end else begin
         //Vsync counter
         if (h_cnt == H_TOTAL-1) begin
-            if (v_cnt < V_TOTAL-1)
+            if (v_cnt < V_TOTAL-1) begin
                 v_cnt <= v_cnt + 1'b1;
-            else
+                if (v_cnt >= Y_START)
+                    ypos <= ypos + 1'b1;
+            end else begin
                 v_cnt <= 0;
+                ypos <= 0;
+            end
         end
 
         //Vsync signal
@@ -111,17 +116,38 @@ end
 always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n) begin
-        V_gen <= 8'h00;
-        ENABLE_out <= 1'b0;
+        R_out <= 8'h00;
+        G_out <= 8'h00;
+        B_out <= 8'h00;
+        DE_out <= 1'b0;
     end else begin
-        if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
-            V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
-        else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
-            V_gen <= 8'h50;
-        else
-            V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
+        if (lt_active) begin
+            case (lt_mode)
+                default: begin
+                    {R_out, G_out, B_out} <= {3{8'h00}};
+                end
+                `LT_POS_TOPLEFT: begin
+                    {R_out, G_out, B_out} <= {3{((xpos < (H_ACTIVE/`LT_WIDTH_DIV)) && (ypos < (V_ACTIVE/`LT_HEIGHT_DIV))) ? 8'hff : 8'h00}};
+                end
+                `LT_POS_CENTER: begin
+                    {R_out, G_out, B_out} <= {3{((xpos >= ((H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (xpos < ((H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (ypos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (ypos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00}};
+                end
+                `LT_POS_BOTTOMRIGHT: begin
+                    {R_out, G_out, B_out} <= {3{((xpos >= (H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (ypos >= (V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00}};
+                end
+            endcase
+        end else begin
+            if ((xpos < H_OVERSCAN) || (xpos >= H_OVERSCAN+H_AREA) || (ypos < V_OVERSCAN) || (ypos >= V_OVERSCAN+V_AREA))
+                {R_out, G_out, B_out} <= {3{(xpos[0] ^ ypos[0]) ? 8'hff : 8'h00}};
+            else if ((xpos < H_OVERSCAN+H_BORDER) || (xpos >= H_OVERSCAN+H_AREA-H_BORDER) || (ypos < V_OVERSCAN+V_BORDER) || (ypos >= V_OVERSCAN+V_AREA-V_BORDER))
+                {R_out, G_out, B_out} <= {3{8'h50}};
+            else if (ypos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
+                {R_out, G_out, B_out} <= {3{8'((((xpos - (H_OVERSCAN+H_BORDER)) >> 4) << 3) + (xpos - (H_OVERSCAN+H_BORDER) >> 6))}};
+            else
+                {R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
+        end
 
-        ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
+        DE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
     end
 end
 

scripts/reprogram.sh

@@ -0,0 +1,7 @@
+#!/bin/sh
+
+make rv-reprogram
+
+if [ $# -eq 1 ] && [ $1 = "jtag_uart" ] && [ $(pgrep -c nios2-terminal) = 0 ]; then
+    nios2-terminal
+fi

scripts/rv-reprogram.tcl

@@ -0,0 +1,25 @@
+#Select the master service type and check for available service paths.
+set service_paths [get_service_paths master]
+
+#Set the master service path.
+set master_service_path [lindex $service_paths 0]
+
+#Open the master service.
+set claim_path [claim_service master $master_service_path mylib]
+
+puts "Halting CPU"
+master_write_32 $claim_path 0x0 0x1
+
+puts "Writing block RAM"
+master_write_from_file $claim_path mem_init/sys_onchip_memory2_0.bin 0x10000
+
+close_service master $claim_path
+
+
+set jtag_debug_list [get_service_paths jtag_debug]
+set jd [ lindex $jtag_debug_list 0 ]
+open_service jtag_debug $jd
+puts "Resetting system"
+jtag_debug_reset_system $jd
+close_service jtag_debug $jd
+puts "Done"

software/ossc_sw.project

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_sw" InternalType="" Version="10.0.0">
+<CodeLite_Project Name="ossc_sw" InternalType="" Version="11000">
   <Plugins>
     <Plugin Name="qmake">
       <![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
@@ -31,9 +31,9 @@
     <Excludepaths/>
     <Ignorefiles/>
     <Extensions>
-      <![CDATA[cpp;c;h;hpp;xrc;wxcp;fbp]]>
+      <![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
     </Extensions>
-    <Topleveldir>../software</Topleveldir>
+    <Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
   </Reconciliation>
   <VirtualDirectory Name="sys_controller">
     <VirtualDirectory Name="ths7353">
@@ -74,6 +74,8 @@
       <File Name="sys_controller/memory/sdcard.c"/>
     </VirtualDirectory>
     <VirtualDirectory Name="ossc">
+      <File Name="sys_controller/ossc/utils.h"/>
+      <File Name="sys_controller/ossc/utils.c"/>
       <File Name="sys_controller/ossc/menu.c"/>
       <File Name="sys_controller/ossc/menu.h"/>
       <File Name="sys_controller/ossc/sysconfig.h"/>
@@ -121,7 +123,7 @@
       </Compiler>
       <Linker Options="" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
-      <General OutputFile="" IntermediateDirectory="./Debug" Command="nios2-download -g --accept-bad-sysid sys_controller.elf &amp;&amp; nios2-terminal" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <General OutputFile="" IntermediateDirectory="./Debug" Command="../../scripts/reprogram.sh" CommandArguments="jtag_uart" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
       <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
@@ -134,10 +136,12 @@
       <PreBuild/>
       <PostBuild/>
       <CustomBuild Enabled="yes">
-        <Target Name="diy-audio-debug">make APP_CFLAGS_DEFINED_SYMBOLS="-DDEBUG -DENABLE_AUDIO"</Target>
+        <Target Name="compile_image_debug">make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex</Target>
+        <Target Name="compile_image_aud-debug">make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex</Target>
+        <Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch bsp_timestamp</Target>
         <RebuildCommand/>
         <CleanCommand>make clean</CleanCommand>
-        <BuildCommand>make APP_CFLAGS_DEFINED_SYMBOLS="-DDEBUG"</BuildCommand>
+        <BuildCommand>make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex</BuildCommand>
         <PreprocessFileCommand/>
         <SingleFileCommand/>
         <MakefileGenerationCommand/>
@@ -161,7 +165,7 @@
       </Compiler>
       <Linker Options="-O2" Required="yes"/>
       <ResourceCompiler Options="" Required="no"/>
-      <General OutputFile="" IntermediateDirectory="./Release" Command="nios2-download -g --accept-bad-sysid sys_controller.elf" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
+      <General OutputFile="" IntermediateDirectory="./Release" Command="../../scripts/reprogram.sh" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
       <BuildSystem Name="Default"/>
       <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
         <![CDATA[]]>
@@ -174,15 +178,16 @@
       <PreBuild/>
       <PostBuild/>
       <CustomBuild Enabled="yes">
-        <Target Name="compile_image_jp">make clean &amp;&amp; iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c &gt; ossc/menu_sjis.c &amp;&amp; make OSDLANG=JP mem_init_generate</Target>
-        <Target Name="compile_image_aud_jp">make clean &amp;&amp; iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c &gt; ossc/menu_sjis.c &amp;&amp; make ENABLE_AUDIO=y OSDLANG=JP mem_init_generate</Target>
-        <Target Name="compile_image_aud">make clean &amp;&amp; make ENABLE_AUDIO=y mem_init_generate</Target>
-        <Target Name="compile_image">make clean &amp;&amp; make mem_init_generate</Target>
-        <Target Name="Build_jp">iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c &gt; ossc/menu_sjis.c &amp;&amp; make OSDLANG=JP</Target>
+        <Target Name="compile_image_jp">make OSDLANG=JP generate_hex</Target>
+        <Target Name="compile_image_aud_jp">make ENABLE_AUDIO=y OSDLANG=JP generate_hex</Target>
+        <Target Name="compile_image_aud">make ENABLE_AUDIO=y generate_hex</Target>
+        <Target Name="compile_image">make generate_hex</Target>
+        <Target Name="Build_jp">make OSDLANG=JP</Target>
         <Target Name="Build_audio">make ENABLE_AUDIO=y</Target>
+        <Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch bsp_timestamp</Target>
         <RebuildCommand/>
         <CleanCommand>make clean</CleanCommand>
-        <BuildCommand>make</BuildCommand>
+        <BuildCommand>make ENABLE_AUDIO=y generate_hex</BuildCommand>
         <PreprocessFileCommand/>
         <SingleFileCommand/>
         <MakefileGenerationCommand/>

software/sys_controller/Makefile

@@ -17,7 +17,7 @@ ALT_LIBRARY_NAMES :=
 # List of library names for -msys-lib linker option (-msys-lib added when used).
 # These are libraries that might be located in the BSP and depend on the BSP
 # library, or vice versa
-ALT_BSP_DEP_LIBRARY_NAMES :=
+ALT_BSP_DEP_LIBRARY_NAMES := libhal_bsp.a
 
 # List of dependencies for the linker.  This is usually the full pathname
 # of each library (*.a) file.
@@ -159,16 +159,22 @@ C_SRCS += ossc/av_controller.c
 C_SRCS += ossc/avconfig.c
 C_SRCS += ossc/controls.c
 C_SRCS += ossc/firmware.c
+C_SRCS += ossc/fat16_export.c
 ifeq ($(OSDLANG),JP)
 C_SRCS += ossc/menu_sjis.c
 else
 C_SRCS += ossc/menu.c
 endif
+ifeq ($(OSDLANG),JP)
+C_SRCS += ossc/userdata_sjis.c
+else
 C_SRCS += ossc/userdata.c
+endif
+C_SRCS += ossc/utils.c
 C_SRCS += ulibSD/sd_io.c
 C_SRCS += ulibSD/spi_io.c
 CXX_SRCS :=
-ASM_SRCS :=
+ASM_SRCS := crt0.boot_E.S
 
 
 # Path to root of object file tree.
@@ -184,7 +190,7 @@ CREATE_ELF_DERIVED_FILES := 0
 CREATE_LINKER_MAP := 1
 
 # Common arguments for ALT_CFLAGSs
-APP_CFLAGS_DEFINED_SYMBOLS := -DNO_I2C_DEBUG -DNO_DEBUG
+APP_CFLAGS_DEFINED_SYMBOLS :=
 ifeq ($(ENABLE_AUDIO),y)
 APP_CFLAGS_DEFINED_SYMBOLS += -DENABLE_AUDIO
 endif
@@ -194,8 +200,8 @@ endif
 APP_CFLAGS_UNDEFINED_SYMBOLS :=
 APP_CFLAGS_OPTIMIZATION := -Os
 APP_CFLAGS_DEBUG_LEVEL :=
-APP_CFLAGS_WARNINGS := -Wall -Wno-unused-but-set-variable -Wno-unused-variable -Wno-unused-function
-APP_CFLAGS_USER_FLAGS := -fdata-sections -ffunction-sections -fshort-enums -fgnu89-inline
+APP_CFLAGS_WARNINGS := -Wall -Wno-unused-but-set-variable -Wno-unused-variable -Wno-unused-function -Wno-packed-bitfield-compat
+APP_CFLAGS_USER_FLAGS := -fdata-sections -ffunction-sections -fshort-enums -fgnu89-inline -flto
 
 APP_ASFLAGS_USER :=
 APP_LDFLAGS_USER := -Wl,--gc-sections
@@ -344,12 +350,12 @@ ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),)
 # Detect if small newlib C library is requested.
 # If yes, remove the -msmallc option because it is
 # now handled by other means.
-ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
-	ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
-	ALT_C_LIBRARY := smallc
-else
-	ALT_C_LIBRARY := c
-endif
+#ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),)
+	#ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS))
+	#ALT_C_LIBRARY := smallc
+#else
+	#ALT_C_LIBRARY := c
+#endif
 
 # Put each BSP dependent library in a group to avoid circular dependencies.
 APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group)
@@ -359,7 +365,8 @@ else # !AVOID_NIOS2_GCC3_OPTIONS
 #
 # Use Nios II GCC 3.X options.
 #
-APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
+#APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES))
+APP_BSP_DEP_LIBS := $(addprefix -l:, $(ALT_BSP_DEP_LIBRARY_NAMES))
 
 endif # !AVOID_NIOS2_GCC3_OPTIONS
 
@@ -389,7 +396,7 @@ APP_ASFLAGS := $(APP_ASM_INC_DIRS) \
                $(ASFLAGS)
 
 # Arguments only for the linker.
-APP_LDFLAGS := $(APP_LDFLAGS_USER)
+APP_LDFLAGS := $(APP_LDFLAGS_USER) --specs=nano.specs -nostartfiles
 
 ifneq ($(LINKER_SCRIPT),)
 APP_LDFLAGS += -T'$(LINKER_SCRIPT)'
@@ -410,17 +417,16 @@ else # !AVOID_NIOS2_GCC3_OPTIONS
 
 # Use Nios II GCC 3.x options.
 ifneq ($(CRT0),)
-APP_LDFLAGS += -msys-crt0='$(CRT0)'
+#APP_LDFLAGS += -msys-crt0='$(CRT0)'
 endif
 ifneq ($(SYS_LIB),)
-APP_LDFLAGS += -msys-lib=$(SYS_LIB)
+#APP_LDFLAGS += -msys-lib=$(SYS_LIB)
 endif
 
 endif # !AVOID_NIOS2_GCC3_OPTIONS
 
 APP_LDFLAGS += \
            $(APP_LIB_DIRS) \
-           $(ALT_LDFLAGS) \
            $(LDFLAGS)
 
 LINKER_MAP_NAME := $(APP_NAME).map
@@ -651,23 +657,24 @@ build_post_process :
 # included makefile fragment.
 #
 ifeq ($(DEFAULT_CROSS_COMPILE),)
-DEFAULT_CROSS_COMPILE := nios2-elf-
+DEFAULT_CROSS_COMPILE := riscv32-unknown-elf-
 endif
 
 ifeq ($(DEFAULT_STACKREPORT),)
-DEFAULT_STACKREPORT := nios2-stackreport
+DEFAULT_STACKREPORT := riscv32-unknown-elf-size
 endif
 
 ifeq ($(DEFAULT_DOWNLOAD),)
-DEFAULT_DOWNLOAD := nios2-download
+DEFAULT_DOWNLOAD := anios2-download
 endif
 
 ifeq ($(DEFAULT_FLASHPROG),)
-DEFAULT_FLASHPROG := nios2-flash-programmer
+DEFAULT_FLASHPROG := anios2-flash-programmer
 endif
 
+DISABLE_ELFPATCH 		:= 1
 ifeq ($(DEFAULT_ELFPATCH),)
-DEFAULT_ELFPATCH := nios2-elf-insert
+DEFAULT_ELFPATCH := anios2-elf-insert
 endif
 
 ifeq ($(DEFAULT_RM),)
@@ -732,7 +739,7 @@ OBJCOPY := $(CROSS_COMPILE)objcopy
 endif
 
 ifeq ($(STACKREPORT),)
-STACKREPORT := $(DEFAULT_STACKREPORT) --prefix $(CROSS_COMPILE)
+STACKREPORT := $(DEFAULT_STACKREPORT)
 else
 DISABLE_STACKREPORT := 1
 endif
@@ -753,6 +760,8 @@ ifeq ($(MKDIR),)
 MKDIR := $(DEFAULT_MKDIR)
 endif
 
+RV_OBJCOPY = riscv32-unknown-elf-objcopy
+
 #------------------------------------------------------------------------------
 #                     PATTERN RULES TO BUILD OBJECTS
 #------------------------------------------------------------------------------
@@ -966,7 +975,7 @@ clean : clean_elf_derived_files
 endif
 
 clean :
-	@$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) ossc/menu_sjis.c
+	@$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) ossc/menu_sjis.c ossc/userdata_sjis.c
 	@$(ECHO) [$(APP_NAME) clean complete]
 
 # Clean just the BSP.
@@ -1120,3 +1129,25 @@ print-elf-name:
 	@$(ECHO) $(ELF)
 
 
+#------------------------------------------------------------------------------
+#                         CUSTOM TARGETS
+#------------------------------------------------------------------------------
+ossc/menu_sjis.c: ossc/menu.c
+	iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c > ossc/menu_sjis.c
+
+ossc/userdata_sjis.c: ossc/userdata.c
+	iconv -f UTF-8 -t SHIFT-JIS ossc/userdata.c > ossc/userdata_sjis.c
+
+mem_init/sys_onchip_memory2_0.hex: sys_controller.elf
+	$(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin
+	../../tools/bin2hex 4 mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
+
+.PHONY: mem_init_generate_new
+mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex
+
+.PHONY: generate_hex
+generate_hex: clean mem_init_generate_new
+
+.PHONY: rv-reprogram
+rv-reprogram: mem_init_generate_new
+	system-console -cli --script ../../scripts/rv-reprogram.tcl

software/sys_controller/crt0.boot.S

@@ -0,0 +1,103 @@
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+#include "pulpino.h"
+
+#define EXCEPTION_STACK_SIZE 72
+
+
+/* ========================================================= [ entry ] === */
+  .section .text
+
+default_exc_handler:
+  jal x0, default_exc_handler
+
+reset_handler:
+  /* set all registers to zero */
+  mv  x1, x0
+  mv  x2, x1
+  mv  x3, x1
+  mv  x4, x1
+  mv  x5, x1
+  mv  x6, x1
+  mv  x7, x1
+  mv  x8, x1
+  mv  x9, x1
+  mv x10, x1
+  mv x11, x1
+  mv x12, x1
+  mv x13, x1
+  mv x14, x1
+  mv x15, x1
+  mv x16, x1
+  mv x17, x1
+  mv x18, x1
+  mv x19, x1
+  mv x20, x1
+  mv x21, x1
+  mv x22, x1
+  mv x23, x1
+  mv x24, x1
+  mv x25, x1
+  mv x26, x1
+  mv x27, x1
+  mv x28, x1
+  mv x29, x1
+  mv x30, x1
+  mv x31, x1
+
+  /* stack initilization */
+  la   x2, _stack_start
+
+_start:
+  .global _start
+
+  /* clear BSS */
+  la x26, _bss_start
+  la x27, _bss_end
+
+  bge x26, x27, zero_loop_end
+
+zero_loop:
+  sw x0, 0(x26)
+  addi x26, x26, 4
+  ble x26, x27, zero_loop
+zero_loop_end:
+
+
+main_entry:
+  /* jump to alt_main program entry point */
+  jal alt_main
+
+/* =================================================== [ exceptions ] === */
+/* This section has to be down here, since we have to disable rvc for it  */
+
+  .section .vectors, "ax"
+  .option norvc;
+
+  // external interrupts are handled by the same callback
+  // until compiler supports IRQ routines
+  .org 0x00
+  .rept 31
+  nop
+  .endr
+  jal x0, default_exc_handler
+
+  // reset vector
+  .org 0x80
+  jal x0, reset_handler
+
+  // illegal instruction exception
+  .org 0x84
+  jal x0, default_exc_handler
+
+  // ecall handler
+  .org 0x88
+  jal x0, default_exc_handler

software/sys_controller/crt0.boot_E.S

@@ -0,0 +1,87 @@
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+#include "pulpino.h"
+
+#define EXCEPTION_STACK_SIZE 72
+
+
+/* ========================================================= [ entry ] === */
+  .section .text
+
+default_exc_handler:
+  jal x0, default_exc_handler
+
+reset_handler:
+  /* set all registers to zero */
+  mv  x1, x0
+  mv  x2, x1
+  mv  x3, x1
+  mv  x4, x1
+  mv  x5, x1
+  mv  x6, x1
+  mv  x7, x1
+  mv  x8, x1
+  mv  x9, x1
+  mv x10, x1
+  mv x11, x1
+  mv x12, x1
+  mv x13, x1
+  mv x14, x1
+  mv x15, x1
+
+  /* stack initilization */
+  la   x2, _stack_start
+
+_start:
+  .global _start
+
+  /* clear BSS */
+  la x14, _bss_start
+  la x15, _bss_end
+
+  bge x14, x15, zero_loop_end
+
+zero_loop:
+  sw x0, 0(x14)
+  addi x14, x14, 4
+  ble x14, x15, zero_loop
+zero_loop_end:
+
+
+main_entry:
+  /* jump to alt_main program entry point */
+  jal alt_main
+
+/* =================================================== [ exceptions ] === */
+/* This section has to be down here, since we have to disable rvc for it  */
+
+  .section .vectors, "ax"
+  .option norvc;
+
+  // external interrupts are handled by the same callback
+  // until compiler supports IRQ routines
+  .org 0x00
+  .rept 31
+  nop
+  .endr
+  jal x0, default_exc_handler
+
+  // reset vector
+  .org 0x80
+  jal x0, reset_handler
+
+  // illegal instruction exception
+  .org 0x84
+  jal x0, default_exc_handler
+
+  // ecall handler
+  .org 0x88
+  jal x0, default_exc_handler

software/sys_controller/it6613/HDMI_TX.c

@@ -78,18 +78,18 @@ bool HDMITX_HPD(void){
 }
 
 
-void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep)
+void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep)
 {
     AVI_InfoFrame AviInfo;
 
-    OS_PRINTF("HDMITX_SetAVIInfoFrame: VIC=%d, Aspect-Ratio=%s, ITU709=%s, ITC=%s, pixelrep=%u\n",
-        VIC, b16x9?"16:9":"4:3", ITU709?"Yes":"No", ITC?"Yes":"No", pixelrep);
+    OS_PRINTF("HDMITX_SetAVIInfoFrame: VIC=%d, ColorMode=%d, Aspect-Ratio=%s, ITU709=%s, ITC=%s, pixelrep=%u\n",
+        VIC, OutputColorMode, b16x9?"16:9":"4:3", ITU709?"Yes":"No", ITC?"Yes":"No", pixelrep);
 
     AviInfo.pktbyte.AVI_HB[0] = AVI_INFOFRAME_TYPE|0x80 ; 
     AviInfo.pktbyte.AVI_HB[1] = AVI_INFOFRAME_VER ; 
     AviInfo.pktbyte.AVI_HB[2] = AVI_INFOFRAME_LEN ; 
     
-    /*switch(OutputColorMode)
+    switch(OutputColorMode)
     {
     case F_MODE_YUV444:
         // AviInfo.info.ColorMode = 2 ;
@@ -104,8 +104,8 @@ void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u
         // AviInfo.info.ColorMode = 0 ;
         AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ;
         break ;
-    }*/
-    AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ;
+    }
+    //AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ;
     AviInfo.pktbyte.AVI_DB[0] |= 2; // indicate "no overscan"
     AviInfo.pktbyte.AVI_DB[1] = 8 ;
     //AviInfo.pktbyte.AVI_DB[1] |= (!b16x9)?(1<<4):(2<<4) ; // 4:3 or 16:9
@@ -314,19 +314,28 @@ bool HDMITX_DevLoopProc()
 
 void HDMITX_SetAudioInfoFrame(BYTE bAudioDwSampling)
 {
+    int i;
     Audio_InfoFrame AudioInfo;
 
     AudioInfo.info.Type = AUDIO_INFOFRAME_TYPE;
     AudioInfo.info.Ver = AUDIO_INFOFRAME_VER;
     AudioInfo.info.Len = AUDIO_INFOFRAME_LEN;
 
+    for (i=0; i<AUDIO_INFOFRAME_LEN; i++) {
+        AudioInfo.pktbyte.AUD_DB[i] = 0;
+    }
+
     AudioInfo.info.AudioChannelCount = 1; // 2 channels
-    AudioInfo.info.AudioCodingType = 1; // PCM
-    AudioInfo.info.SampleSize = 3; // 24bit
-    AudioInfo.info.SampleFreq = bAudioDwSampling ? 3 : 5; //48kHz or 96kHz
-    AudioInfo.info.SpeakerPlacement = 0; // Front left and front right
-    AudioInfo.info.LevelShiftValue = 0;
-    AudioInfo.info.DM_INH = 0; // Down-mix Inhibit Flag; 0=Permitted or no information about any assertion of this
+
+    // HDMI requires that CT, SS and SF fields are set to 0
+    //AudioInfo.info.AudioCodingType = 1; // PCM
+    //AudioInfo.info.SampleSize = 3; // 24bit
+    //AudioInfo.info.SampleFreq = bAudioDwSampling ? 3 : 5; //48kHz or 96kHz
+
+    // default value assignments omitted
+    //AudioInfo.info.SpeakerPlacement = 0; // Front left and front right
+    //AudioInfo.info.LevelShiftValue = 0;
+    //AudioInfo.info.DM_INH = 0; // Down-mix Inhibit Flag; 0=Permitted or no information about any assertion of this
 
     EnableAudioInfoFrame(TRUE, (BYTE *) &AudioInfo);
 }

software/sys_controller/it6613/HDMI_TX.h

@@ -12,7 +12,7 @@ bool HDMITX_ChipVerify(void);
 bool HDMITX_HPD(void);
 void HDMITX_ChangeVideoTiming(int VIC);
 void HDMITX_ChangeVideoTimingAndColor(int VIC, COLOR_TYPE Color);
-void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep);
+void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep);
 
 void HDMITX_DisableVideoOutput(void);
 void HDMITX_EnableVideoOutput(void);

software/sys_controller/it6613/hdmitx.h

@@ -52,7 +52,7 @@
 //#define NULL 0
 
 //typedef unsigned char bool;
-#include "Altera_UP_SD_Card_Avalon_Interface_mod.h"
+typedef unsigned char  bool;
 #include "sysconfig.h"
 
 // Hardwired to CPU reset

software/sys_controller/it6613/it6613_drv.c

@@ -572,14 +572,14 @@ BOOL EnableAudioOutput4OSSC(ULONG VideoPixelClock,BYTE bAudioDwSampl,BYTE bAudio
     HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL1,Instance[0].bOutputAudioMode);
     HDMITX_WriteI2C_Byte(REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
     HDMITX_WriteI2C_Byte(REG_TX_AUDIO_CTRL3,(Instance[0].bAudioChannelSwap&0xF)|(AudioEnable&B_AUD_SPDIF));
-    HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,B_AUD_SPXFLAT_SRC3|B_AUD_SPXFLAT_SRC2|B_AUD_SPXFLAT_SRC1|B_AUD_ERR2FLAT); // only two channels
+    HDMITX_WriteI2C_Byte(REG_TX_AUD_SRCVALID_FLAT,B_AUD_ERR2FLAT); // only two channels
 
     Switch_HDMITX_Bank(1) ;
-    HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_MODE,0); // 2 audio channel without pre-emphasis
+    HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_MODE,(1<<3)); // 2 audio channel without pre-emphasis, no copyright
     HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CAT,0);
     HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_SRCNUM,1);
     HDMITX_WriteI2C_Byte(REG_TX_AUD0CHST_CHTNUM,0);
-    HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CA_FS,0xC0|fs); // choose clock
+    HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_CA_FS,0x00|fs); // choose clock
     fs = ~fs; // OFS is the one's complement of FS
     HDMITX_WriteI2C_Byte(REG_TX_AUDCHST_OFS_WL,(fs<<4)|AUD_SWL_24); // 24 bit Audio
 

software/sys_controller/it6613/it6613_sys.c

@@ -220,7 +220,7 @@ HDMITX_ChangeDisplayOption(HDMI_Video_Type OutputVideoTiming, HDMI_OutputColorMo
         aspec = HDMI_16x9 ;
         Colorimetry = HDMI_ITU709 ;
         break ;
-    case HDMI_1080p24:
+/*    case HDMI_1080p24:
         VIC = 32 ;
         VideoPixelClock = 74250000 ;
         pixelrep = 0 ;
@@ -247,7 +247,7 @@ HDMITX_ChangeDisplayOption(HDMI_Video_Type OutputVideoTiming, HDMI_OutputColorMo
         pixelrep = 0 ;
         aspec = HDMI_16x9 ;
         Colorimetry = HDMI_ITU601 ;
-        break ;
+        break ;*/
         
         
     default:

software/sys_controller/it6613/it6613_sys.h

@@ -5,7 +5,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 
 typedef enum tagHDMI_Video_Type {
-    HDMI_Unkown = 0 ,
+    HDMI_Unknown = 0 ,
     HDMI_640x480p60 = 1 ,
     HDMI_480p60,
     HDMI_480p60_16x9,
@@ -13,6 +13,7 @@ typedef enum tagHDMI_Video_Type {
     HDMI_1080i60,
     HDMI_480i60,
     HDMI_480i60_16x9,
+    HDMI_240p60,
     HDMI_1080p60 = 16,
     HDMI_576p50,
     HDMI_576p50_16x9,
@@ -20,11 +21,12 @@ typedef enum tagHDMI_Video_Type {
     HDMI_1080i50,
     HDMI_576i50,
     HDMI_576i50_16x9,
+    HDMI_288p50,
     HDMI_1080p50 = 31,
-    HDMI_1080p24,
+    /*HDMI_1080p24,
     HDMI_1080p25,
     HDMI_1080p30,
-    HDMI_1080i120 = 46, // richard add
+    HDMI_1080i120 = 46,*/ // richard add
 } HDMI_Video_Type ;
 
 typedef enum tagHDMI_Aspec {

software/sys_controller/link.common.ld

@@ -0,0 +1,135 @@
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+MEMORY
+{
+    dataram    : ORIGIN = 0x00010000, LENGTH = 0xa000
+}
+
+/* Stack information variables */
+_min_stack      = 0x400;   /* 1K - minimum stack space to reserve */
+_stack_start   = ORIGIN(dataram) + LENGTH(dataram);
+
+/* We have to align each sector to word boundaries as our current s19->slm
+ * conversion scripts are not able to handle non-word aligned sections. */
+
+SECTIONS
+{
+    .vectors :
+    {
+        . = ALIGN(4);
+        KEEP(*(.vectors))
+    } > dataram
+
+    .text : {
+        . = ALIGN(4);
+        _stext = .;
+        *(.text)
+        *(.text.*)
+        _etext  =  .;
+        __CTOR_LIST__ = .;
+        LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+        *(.ctors)
+        LONG(0)
+        __CTOR_END__ = .;
+        __DTOR_LIST__ = .;
+        LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+        *(.dtors)
+        LONG(0)
+        __DTOR_END__ = .;
+        *(.lit)
+        *(.shdata)
+        _endtext = .;
+    }  > dataram
+
+    /*--------------------------------------------------------------------*/
+    /* Global constructor/destructor segement                             */
+    /*--------------------------------------------------------------------*/
+
+    .preinit_array     :
+    {
+      PROVIDE_HIDDEN (__preinit_array_start = .);
+      KEEP (*(.preinit_array))
+      PROVIDE_HIDDEN (__preinit_array_end = .);
+    } > dataram
+
+    .init_array     :
+    {
+      PROVIDE_HIDDEN (__init_array_start = .);
+      KEEP (*(SORT(.init_array.*)))
+      KEEP (*(.init_array ))
+      PROVIDE_HIDDEN (__init_array_end = .);
+    } > dataram
+
+    .fini_array     :
+    {
+      PROVIDE_HIDDEN (__fini_array_start = .);
+      KEEP (*(SORT(.fini_array.*)))
+      KEEP (*(.fini_array ))
+      PROVIDE_HIDDEN (__fini_array_end = .);
+    } > dataram
+
+    .rodata : {
+        . = ALIGN(4);
+        *(.rodata);
+        *(.rodata.*)
+    } > dataram
+
+    .shbss :
+    {
+        . = ALIGN(4);
+        *(.shbss)
+    } > dataram
+
+    .data : {
+        . = ALIGN(4);
+        sdata  =  .;
+        _sdata  =  .;
+        *(.data);
+        *(.data.*)
+        *(.sdata);
+        *(.sdata.*)
+        *(.sdata2);
+        *(.sdata2.*)
+        edata  =  .;
+        _edata  =  .;
+    } > dataram
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss_start = .;
+        *(.bss)
+        *(.bss.*)
+        *(.sbss)
+        *(.sbss.*)
+        *(COMMON)
+        _bss_end = .;
+    } > dataram
+
+    /* ensure there is enough room for stack */
+    .stack (NOLOAD): {
+        . = ALIGN(4);
+        . = . + _min_stack ;
+        . = ALIGN(4);
+        stack = . ;
+        _stack = . ;
+    } > dataram
+
+    .stab  0 (NOLOAD) :
+    {
+        [ .stab ]
+    }
+
+    .stabstr  0 (NOLOAD) :
+    {
+        [ .stabstr ]
+    }
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _end = .;
+    } > dataram
+}
+

software/sys_controller/link.riscv.ld

@@ -0,0 +1,7 @@
+/* not needed, but we need separate linker scripts anyway */
+OUTPUT_ARCH(riscv)
+
+/* required to correctly link newlib */
+GROUP( -lc -lgloss -lgcc -lsupc++ )
+
+INCLUDE link.common.ld

software/sys_controller/memory/flash.c

@@ -19,96 +19,51 @@
 
 #include <unistd.h>
 #include <string.h>
+#include "system.h"
 #include "flash.h"
-#include "lcd.h"
-#include "ci_crc.h"
+#include "utils.h"
 
-extern alt_epcq_controller_dev epcq_controller_0;
-extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
+// save some code space
+#define SINGLE_FLASH_INSTANCE
 
-alt_epcq_controller_dev *epcq_controller_dev;
+alt_flash_dev *epcq_dev;
 
 
-int check_flash()
+int init_flash()
 {
-    epcq_controller_dev = &epcq_controller_0;
+#ifdef SINGLE_FLASH_INSTANCE
+    extern alt_llist alt_flash_dev_list;
+    epcq_dev = (alt_flash_dev*)alt_flash_dev_list.next;
+#else
+    epcq_dev = alt_flash_open_dev(EPCQ_CONTROLLER2_0_AVL_MEM_NAME);
+#endif
 
-    if ((epcq_controller_dev == NULL) || !(epcq_controller_dev->is_epcs && (epcq_controller_dev->page_size == PAGESIZE)))
+    if (epcq_dev == NULL)
         return -1;
 
-    printf("Flash size in bytes: %lu\nSector size: %lu (%lu pages)\nPage size: %lu\n",
-            epcq_controller_dev->size_in_bytes, epcq_controller_dev->sector_size, epcq_controller_dev->sector_size/epcq_controller_dev->page_size, epcq_controller_dev->page_size);
-
     return 0;
 }
 
-int read_flash(alt_u32 offset, alt_u32 length, alt_u8 *dstbuf)
-{
-    int retval, i;
-
-    retval = alt_epcq_controller_read(&epcq_controller_dev->dev, offset, dstbuf, length);
-    if (retval != 0)
-        return -1;
-
-    for (i=0; i<length; i++)
-        dstbuf[i] = ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(dstbuf[i]) >> 24;
-
-    return 0;
-}
-
-int write_flash_page(alt_u8 *pagedata, alt_u32 length, alt_u32 pagenum)
-{
-    int retval, i;
-
-    if ((pagenum % PAGES_PER_SECTOR) == 0) {
-        printf("Erasing sector %u\n", (unsigned)(pagenum/PAGES_PER_SECTOR));
-        retval = alt_epcq_controller_erase_block(&epcq_controller_dev->dev, pagenum*PAGESIZE);
-
-        if (retval != 0) {
-            strncpy(menu_row1, "Flash erase", LCD_ROW_LEN+1);
-            sniprintf(menu_row1, LCD_ROW_LEN+1, "error %d", retval);
-            menu_row2[0] = '\0';
-            printf("Flash erase error, sector %u\nRetval %d\n", (unsigned)(pagenum/PAGES_PER_SECTOR), retval);
-            return -200;
-        }
-    }
-
-    // Bit-reverse bytes for flash
-    for (i=0; i<length; i++)
-        pagedata[i] = ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(pagedata[i]) >> 24;
-
-    retval = alt_epcq_controller_write_block(&epcq_controller_dev->dev, (pagenum/PAGES_PER_SECTOR)*PAGES_PER_SECTOR*PAGESIZE, pagenum*PAGESIZE, pagedata, length);
-
-    if (retval != 0) {
-        strncpy(menu_row1, "Flash write", LCD_ROW_LEN+1);
-        strncpy(menu_row2, "error", LCD_ROW_LEN+1);
-        printf("Flash write error, page %u\nRetval %d\n", (unsigned)pagenum, retval);
-        return -201;
-    }
-
-    return retval;
-}
-
 int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf)
 {
-    alt_u32 crcval=0, i, bytes_to_read;
+    alt_u32 crcval=0, i, j, bytes_to_read;
     int retval;
 
     for (i=0; i<length; i=i+PAGESIZE) {
         bytes_to_read = ((length-i < PAGESIZE) ? (length-i) : PAGESIZE);
 
-        retval = read_flash(i, bytes_to_read, tmpbuf);
+        //retval = read_flash(i, bytes_to_read, tmpbuf);
+        retval = alt_epcq_controller2_read(epcq_dev, offset+i, tmpbuf, bytes_to_read);
+        for (j=0; j<bytes_to_read; j++)
+            tmpbuf[j] = bitswap8(tmpbuf[j]);
         if (retval != 0)
-            return -202;
+            return retval;
 
-        crcval = crcCI(tmpbuf, bytes_to_read, (i==0));
+        crcval = crc32(tmpbuf, bytes_to_read, (i==0));
     }
 
-    if (crcval != golden_crc) {
-        sniprintf(menu_row1, LCD_ROW_LEN+1, "Flash verif fail");
-        menu_row2[0] = '\0';
-        return -203;
-    }
+    if (crcval != golden_crc)
+        return -FLASH_VERIFY_ERROR;
 
     return 0;
 }

software/sys_controller/memory/flash.h

@@ -22,7 +22,7 @@
 
 #include "alt_types.h"
 #include "sysconfig.h"
-#include "altera_epcq_controller_mod.h"
+#include "altera_epcq_controller2.h"
 
 // EPCS16 pagesize is 256 bytes
 // Flash is split 50-50 to FW and userdata, 1MB each
@@ -32,12 +32,10 @@
 #define USERDATA_OFFSET 0x100000
 #define MAX_USERDATA_ENTRY 15    // 16 sectors for userdata
 
-int check_flash();
+#define FLASH_VERIFY_ERROR      204
 
-int read_flash(alt_u32 offset, alt_u32 length, alt_u8 *dstbuf);
-
-int write_flash_page(alt_u8 *pagedata, alt_u32 length, alt_u32 pagenum);
 
+int init_flash();
 int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf);
 
 #endif /* FLASH_H_ */

software/sys_controller/memory/sdcard.c

@@ -18,10 +18,12 @@
 //
 
 #include <io.h>
+#include <string.h>
 #include "sdcard.h"
-#include "lcd.h"
+#include "flash.h"
+#include "utils.h"
 
-extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
+extern alt_flash_dev *epcq_dev;
 
 SD_DEV sdcard_dev;
 
@@ -31,11 +33,74 @@ int check_sdcard(alt_u8 *databuf)
 
     res = SD_Init(&sdcard_dev);
     printf("SD det status: %u\n", res);
-    if (res) {
-        sniprintf(menu_row1, LCD_ROW_LEN+1, "No SD card det.");
-        menu_row2[0] = '\0';
-        return 1;
+    if (res == SD_OK)
+        res = SD_Read(&sdcard_dev, databuf, 0, 0, 512);
+
+    return -res;
+}
+
+int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, alt_u8 *tmpbuf)
+{
+    SDRESULTS res;
+    int retval, i;
+    alt_u32 bytes_to_rw;
+
+    while (length > 0) {
+        bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
+        res = SD_Read(&sdcard_dev, tmpbuf, sd_blknum, 0, bytes_to_rw);
+        if (res != SD_OK) {
+            printf("Failed to read SD card\n");
+            return -res;
+        }
+
+        if ((flash_pagenum % PAGES_PER_SECTOR) == 0) {
+            retval = alt_epcq_controller2_erase_block(epcq_dev, flash_pagenum*PAGESIZE);
+            if (retval != 0)
+                return retval;
+        }
+
+        for (i=0; i<bytes_to_rw; i++)
+            tmpbuf[i] = bitswap8(tmpbuf[i]);
+        retval = alt_epcq_controller2_write_block(epcq_dev, ((flash_pagenum/PAGES_PER_SECTOR)*SECTORSIZE), flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
+        if (retval != 0)
+            return retval;
+
+        ++sd_blknum;
+        flash_pagenum += bytes_to_rw/PAGESIZE;
+        length -= bytes_to_rw;
     }
 
-    return SD_Read(&sdcard_dev, databuf, 0, 0, 512);
+    return 0;
+}
+
+int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, alt_u8 *tmpbuf)
+{
+    SDRESULTS res;
+    int retval, i;
+    alt_u32 bytes_to_rw;
+
+    while (length > 0) {
+        bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
+        retval = alt_epcq_controller2_read(epcq_dev, flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
+        for (i=0; i<bytes_to_rw; i++)
+            tmpbuf[i] = bitswap8(tmpbuf[i]);
+        if (retval != 0)
+            return retval;
+
+        if (bytes_to_rw < SD_BLK_SIZE)
+            memset(tmpbuf+bytes_to_rw, 0, SD_BLK_SIZE-bytes_to_rw);
+
+        res = SD_Write(&sdcard_dev, tmpbuf, sd_blknum);
+        if (res != SD_OK) {
+            printf("Failed to write to SD card\n");
+            return -res;
+        }
+
+        ++sd_blknum;
+        flash_pagenum += bytes_to_rw/PAGESIZE;
+        length -= bytes_to_rw;
+    }
+
+    return 0;
+
 }

software/sys_controller/memory/sdcard.h

@@ -25,5 +25,7 @@
 #include "sd_io.h"
 
 int check_sdcard(alt_u8 *databuf);
+int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, alt_u8 *tmpbuf);
+int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, alt_u8 *tmpbuf);
 
 #endif /* SDCARD_H_ */

software/sys_controller/ossc/av_controller.h

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2016  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -22,18 +22,30 @@
 
 #include "avconfig.h"
 #include "sysconfig.h"
+#include "sc_config_regs.h"
+#include "osd_generator_regs.h"
+#include "pll_reconfig_regs.h"
 
 // sys_ctrl bits
-#define SD_SPI_SS_N (1<<7)
-#define LCD_CS_N    (1<<6)
-#define LCD_RS      (1<<5)
-#define LCD_BL      (1<<4)
-#define VIDGEN_OFF  (1<<1)
-#define AV_RESET_N  (1<<0)
+#define LT_ACTIVE                   (1<<15)
+#define LT_ARMED                    (1<<14)
+#define LT_MODE_OFFS                12
+#define REMOTE_EVENT                (1<<8)
+#define SD_SPI_SS_N                 (1<<7)
+#define LCD_CS_N                    (1<<6)
+#define LCD_RS                      (1<<5)
+#define LCD_BL                      (1<<4)
+#define LCD_BL_TIMEOUT_OFFS         2
+#define VIDGEN_OFF                  (1<<1)
+#define AV_RESET_N                  (1<<0)
+
+#define LT_CTRL_MASK    0xf000
 
 // HDMI_TX definitions
 #define HDMITX_MODE_MASK            0x00040000
 
+#define PLL_ACTIVECLK_MASK          0x00080000
+
 #define TX_PIXELREP_DISABLE         0
 #define TX_PIXELREP_2X              1
 #define TX_PIXELREP_4X              3
@@ -48,42 +60,36 @@
 #define FPGA_H_MULTMODE_FULLWIDTH   0
 #define FPGA_H_MULTMODE_ASPECTFIX   1
 #define FPGA_H_MULTMODE_OPTIMIZED   2
+#define FPGA_H_MULTMODE_OPTIMIZED_1X 3
 
-#define FPGA_SCANLINEMODE_OFF       0
-#define FPGA_SCANLINEMODE_H         1
-#define FPGA_SCANLINEMODE_V         2
-#define FPGA_SCANLINEMODE_ALT       3
+#define AUTO_OFF                    0
+#define AUTO_CURRENT_INPUT          1
+#define AUTO_MAX_COUNT            100
+#define AUTO_CURRENT_MAX_COUNT      6
 
-static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr", "Last used" };
-
-typedef enum {
-    AV_KEEP         = 0,
-    AV1_RGBs        = 1,
-    AV1_RGsB        = 2,
-    AV1_YPBPR       = 3,
-    AV2_YPBPR       = 4,
-    AV2_RGsB        = 5,
-    AV3_RGBHV       = 6,
-    AV3_RGBs        = 7,
-    AV3_RGsB        = 8,
-    AV3_YPBPR       = 9,
-    AV_LAST         = 10
-} avinput_t;
+#define PLL_CONFIG_VG               0
+#define PLL_CONFIG_2X_5X            1
+#define PLL_CONFIG_3X_4X            2
 
 // In reverse order of importance
 typedef enum {
     NO_CHANGE           = 0,
-    INFO_CHANGE         = 1,
+    SC_CONFIG_CHANGE    = 1,
     MODE_CHANGE         = 2,
     TX_MODE_CHANGE      = 3,
     ACTIVITY_CHANGE     = 4
 } status_t;
 
 typedef enum {
-    TX_HDMI             = 0,
-    TX_DVI              = 1
+    TX_HDMI_RGB         = 0,
+    TX_HDMI_YCBCR444    = 1,
+    TX_DVI              = 2
 } tx_mode_t;
 
+typedef struct {
+    alt_u32 data[5];
+} pll_config_t;
+
 //TODO: transform binary values into flags
 typedef struct {
     alt_u32 totlines;
@@ -96,21 +102,25 @@ typedef struct {
     alt_u8 fpga_hmultmode;
     alt_u8 tx_pixelrep;
     alt_u8 hdmitx_pixr_ifr;
+    alt_u8 hdmitx_pclk_level;
+    HDMI_Video_Type hdmitx_vic;
     alt_u8 sample_mult;
     alt_u8 sample_sel;
     alt_u8 hsync_cut;
+    alt_u16 h_mult_total;
     mode_flags target_lm;
     avinput_t avinput;
+    alt_u8 pll_config;
     // Current configuration
     avconfig_t cc;
 } avmode_t;
 
-inline void lcd_write_menu();
-inline void lcd_write_status();
+void ui_disp_menu(alt_u8 osd_mode);
+void ui_disp_status(alt_u8 refresh_osd_timer);
 
-void vm_display(alt_u8 code);
-void vm_tweak(alt_u16 v);
-void load_profile_disp(alt_u8 code);
-void save_profile_disp(alt_u8 code);
+int load_profile();
+int save_profile();
+
+int latency_test();
 
 #endif

software/sys_controller/ossc/avconfig.c

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -25,13 +25,6 @@
 #include "tvp7002.h"
 
 #define DEFAULT_ON              1
-#define DEFAULT_PRE_COAST       1
-#define DEFAULT_POST_COAST      0
-#define DEFAULT_SAMPLER_PHASE   16
-#define DEFAULT_SYNC_LPF        3
-#define DEFAULT_SYNC_VTH        11
-#define DEFAULT_FINE_GAIN       26
-#define DEFAULT_FINE_OFFSET     0x80
 
 extern mode_data_t video_modes[], video_modes_default[];
 extern alt_u8 update_cur_vm;
@@ -46,17 +39,18 @@ const avconfig_t tc_default = {
     .pm_384p = 1,
     .pm_480i = 1,
     .pm_1080i = 1,
-    .tvp_hpll2x = 1,
-    .sampler_phase = DEFAULT_SAMPLER_PHASE,
+    .tvp_hpll2x = DEFAULT_ON,
     .sync_vth = DEFAULT_SYNC_VTH,
     .linelen_tol = DEFAULT_LINELEN_TOL,
     .vsync_thold = DEFAULT_VSYNC_THOLD,
     .sync_lpf = DEFAULT_SYNC_LPF,
     .pre_coast = DEFAULT_PRE_COAST,
     .post_coast = DEFAULT_POST_COAST,
+    .sl_altern = 1,
 #ifdef ENABLE_AUDIO
     .audio_dw_sampl = DEFAULT_ON,
-    .tx_mode = TX_HDMI,
+    .tx_mode = TX_HDMI_RGB,
+    .audio_gain = AUDIO_GAIN_0DB,
 #endif
     .col = {
         .r_f_gain = DEFAULT_FINE_GAIN,
@@ -65,14 +59,19 @@ const avconfig_t tc_default = {
         .r_f_off = DEFAULT_FINE_OFFSET,
         .g_f_off = DEFAULT_FINE_OFFSET,
         .b_f_off = DEFAULT_FINE_OFFSET,
+        .c_gain = DEFAULT_COARSE_GAIN,
     },
+    .link_av = AV_LAST,
+    .clamp_offset = SIGNED_NUMVAL_ZERO,
+    .alc_h_filter = DEFAULT_ALC_H_FILTER,
+    .alc_v_filter = DEFAULT_ALC_V_FILTER,
 };
 
 int set_default_avconfig()
 {
     memcpy(&tc, &tc_default, sizeof(avconfig_t));
 #ifndef ENABLE_AUDIO
-    tc.tx_mode = !!(IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & HDMITX_MODE_MASK);
+    tc.tx_mode = (IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & HDMITX_MODE_MASK) ? TX_DVI : TX_HDMI_RGB;
 #endif
 
     memcpy(video_modes, video_modes_default, VIDEO_MODES_SIZE);

software/sys_controller/ossc/avconfig.h

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -23,8 +23,12 @@
 #include "alt_types.h"
 #include "tvp7002.h"
 
+#define SIGNED_NUMVAL_ZERO  128
+
 #define SCANLINESTR_MAX     15
-#define HV_MASK_MAX         63
+#define SL_HYBRIDSTR_MAX    28
+#define H_MASK_MAX          255
+#define V_MASK_MAX          63
 #define HV_MASK_MAX_BR      15
 #define VIDEO_LPF_MAX       5
 #define SAMPLER_PHASE_MAX   31
@@ -33,19 +37,52 @@
 #define VSYNC_THOLD_MAX     200
 #define SD_SYNC_WIN_MAX     255
 #define PLL_COAST_MAX       5
+#define REVERSE_LPF_MAX     31
+#define COARSE_GAIN_MAX     15
+#define ALC_H_FILTER_MAX    7
+#define ALC_V_FILTER_MAX    10
+#define CLAMP_OFFSET_MIN    (SIGNED_NUMVAL_ZERO-100)
+#define CLAMP_OFFSET_MAX    (SIGNED_NUMVAL_ZERO+100)
 
 #define SL_MODE_MAX         2
 #define SL_TYPE_MAX         2
 
+#define AUDIO_GAIN_M12DB    0
+#define AUDIO_GAIN_0DB      12
+#define AUDIO_GAIN_12DB     24
+#define AUDIO_GAIN_MAX      AUDIO_GAIN_12DB
+
 #define L5FMT_1920x1080     0
 #define L5FMT_1600x1200     1
 #define L5FMT_1920x1200     2
 
+static const char *avinput_str[] = { "Test pattern", "AV1_RGBS", "AV1_RGsB", "AV1_YPbPr", "AV2_YPbPr", "AV2_RGsB", "AV3_RGBHV", "AV3_RGBS", "AV3_RGsB", "AV3_YPbPr", "Last used" };
+
+typedef enum {
+    AV_TESTPAT      = 0,
+    AV1_RGBs        = 1,
+    AV1_RGsB        = 2,
+    AV1_YPBPR       = 3,
+    AV2_YPBPR       = 4,
+    AV2_RGsB        = 5,
+    AV3_RGBHV       = 6,
+    AV3_RGBs        = 7,
+    AV3_RGsB        = 8,
+    AV3_YPBPR       = 9,
+    AV_LAST         = 10
+} avinput_t;
+
 typedef struct {
     alt_u8 sl_mode;
     alt_u8 sl_type;
+    alt_u8 sl_hybr_str;
+    alt_u8 sl_method;
+    alt_u8 sl_altern;
+    alt_u8 sl_altiv;
     alt_u8 sl_str;
     alt_u8 sl_id;
+    alt_u8 sl_cust_l_str[5];
+    alt_u8 sl_cust_c_str[6];
     alt_u8 linemult_target;
     alt_u8 l2_mode;
     alt_u8 l3_mode;
@@ -61,10 +98,11 @@ typedef struct {
     alt_u8 h_mask;
     alt_u8 v_mask;
     alt_u8 mask_br;
+    alt_u8 mask_color;
     alt_u8 tx_mode;
     alt_u8 hdmi_itc;
     alt_u8 s480p_mode;
-    alt_u8 sampler_phase;
+    alt_u8 s400p_mode;
     alt_u8 tvp_hpll2x;
     alt_u8 upsample2x;
     alt_u8 ypbpr_cs;
@@ -72,17 +110,24 @@ typedef struct {
     alt_u8 linelen_tol;
     alt_u8 vsync_thold;
     alt_u8 sync_lpf;
+    alt_u8 stc_lpf;
     alt_u8 video_lpf;
     alt_u8 pre_coast;
     alt_u8 post_coast;
     alt_u8 full_tx_setup;
     alt_u8 vga_ilace_fix;
-#ifdef ENABLE_AUDIO
+    alt_u8 av3_alt_rgb;
+    alt_u8 panasonic_hack;
+    alt_u8 reverse_lpf;
     alt_u8 audio_dw_sampl;
     alt_u8 audio_swap_lr;
-#endif
-    alt_u8 def_input;
+    alt_u8 audio_gain;
+    alt_u8 default_vic;
+    alt_u8 clamp_offset;
+    alt_u8 alc_h_filter;
+    alt_u8 alc_v_filter;
     color_setup_t col;
+    avinput_t link_av;
 } __attribute__((packed)) avconfig_t;
 
 int set_default_avconfig();

software/sys_controller/ossc/controls.c

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2016  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2019  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -25,6 +25,7 @@
 #include "av_controller.h"
 #include "video_modes.h"
 #include "userdata.h"
+#include "firmware.h"
 #include "lcd.h"
 #include "altera_avalon_pio_regs.h"
 
@@ -37,13 +38,21 @@ const alt_u16 rc_keymap_default[REMOTE_MAX_KEYS] = {0x3E29, 0x3EA9, 0x3E69, 0x3E
 alt_u16 rc_keymap[REMOTE_MAX_KEYS];
 
 extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
-extern const mode_data_t video_modes[];
+extern mode_data_t video_modes[];
 extern avmode_t cm;
 extern avconfig_t tc;
-extern avinput_t target_mode;
+extern avinput_t target_input;
 extern alt_u8 menu_active;
-extern alt_u8 sys_ctrl;
-extern alt_u8 profile_sel;
+extern alt_u16 sys_ctrl;
+extern alt_u16 tc_sampler_phase;
+extern alt_u8 profile_sel, profile_sel_menu;
+extern alt_u8 lcd_bl_timeout;
+extern alt_u8 update_cur_vm, vm_edit;
+extern volatile sc_regs *sc;
+extern volatile osd_regs *osd;
+
+extern menu_t menu_scanlines, menu_advtiming;
+extern char target_profile_name[PROFILE_NAME_LEN+1];
 
 alt_u32 remote_code;
 alt_u8 remote_rpt, remote_rpt_prev;
@@ -57,7 +66,8 @@ void setup_rc()
     for (i=0; i<REMOTE_MAX_KEYS; i++) {
         strncpy(menu_row1, "Press", LCD_ROW_LEN+1);
         strncpy(menu_row2, rc_keydesc[i], LCD_ROW_LEN+1);
-        lcd_write_menu();
+        osd->osd_config.menu_active = 1;
+        ui_disp_menu(1);
         confirm = 0;
 
         while (1) {
@@ -68,14 +78,14 @@ void setup_rc()
                 if (confirm == 0) {
                     rc_keymap[i] = remote_code;
                     strncpy(menu_row1, "Confirm", LCD_ROW_LEN+1);
-                    lcd_write_menu();
+                    ui_disp_menu(1);
                     confirm = 1;
                 } else {
                     if (remote_code == rc_keymap[i]) {
                         confirm = 2;
                     } else {
                         strncpy(menu_row1, "Mismatch, retry", LCD_ROW_LEN+1);
-                        lcd_write_menu();
+                        ui_disp_menu(1);
                         confirm = 0;
                     }
                 }
@@ -101,22 +111,31 @@ void setup_rc()
         }
     }
     write_userdata(INIT_CONFIG_SLOT);
+
+    osd->osd_config.menu_active = 0;
 }
 
-void parse_control()
+int parse_control()
 {
-    int i;
-    alt_u32 btn_vec;
+    int i, prof_x10=0, ret=0, retval;
+    alt_u32 btn_vec, btn_vec_prev=1;
     alt_u8 pt_only = 0;
+    avinput_t man_target_input = AV_LAST;
+
+    sc_status_reg sc_status;
+    sc_status2_reg sc_status2;
+    alt_u32 fpga_v_hz_x100;
 
     // one for each video_group
     alt_u8* pmcfg_ptr[] = { &pt_only, &tc.pm_240p, &tc.pm_384p, &tc.pm_480i, &tc.pm_480p, &tc.pm_480p, &tc.pm_1080i };
     alt_u8 valid_pm[] = { 0x1, 0x1f, 0x3, 0xf, 0x3, 0x3, 0x3 };
 
+    avinput_t next_input = (cm.avinput == AV3_YPBPR) ? AV1_RGBs : (cm.avinput+1);
+
     if (remote_code)
         printf("RCODE: 0x%.4lx, %d\n", remote_code, remote_rpt);
 
-    if (btn_code_prev == 0 && btn_code != 0)
+    if (btn_code)
         printf("BCODE: 0x%.2lx\n", btn_code>>16);
 
     for (i = RC_BTN1; i < REMOTE_MAX_KEYS; i++) {
@@ -127,43 +146,111 @@ void parse_control()
     }
 
     switch (i) {
-        case RC_BTN1: target_mode = AV1_RGBs; break;
-        case RC_BTN4: target_mode = AV1_RGsB; break;
-        case RC_BTN7: target_mode = AV1_YPBPR; break;
-        case RC_BTN2: target_mode = AV2_YPBPR; break;
-        case RC_BTN5: target_mode = AV2_RGsB; break;
-        case RC_BTN3: target_mode = AV3_RGBHV; break;
-        case RC_BTN6: target_mode = AV3_RGBs; break;
-        case RC_BTN9: target_mode = AV3_RGsB; break;
-        case RC_BTN0: target_mode = AV3_YPBPR; break;
+        case RC_BTN1: man_target_input = AV1_RGBs; break;
+        case RC_BTN4: man_target_input = AV1_RGsB; break;
+        case RC_BTN7: man_target_input = AV1_YPBPR; break;
+        case RC_BTN2: man_target_input = AV2_YPBPR; break;
+        case RC_BTN5: man_target_input = AV2_RGsB; break;
+        case RC_BTN3: man_target_input = AV3_RGBHV; break;
+        case RC_BTN6: man_target_input = AV3_RGBs; break;
+        case RC_BTN9: man_target_input = AV3_RGsB; break;
+        case RC_BTN0: man_target_input = AV3_YPBPR; break;
         case RC_MENU:
             menu_active = !menu_active;
+            osd->osd_config.menu_active = menu_active;
+            profile_sel_menu = profile_sel;
 
-            if (menu_active)
+            if (menu_active) {
+                render_osd_page();
                 display_menu(1);
-            else
-                lcd_write_status();
+            } else {
+                ui_disp_status(0);
+            }
 
             break;
         case RC_INFO:
-            sniprintf(menu_row1, LCD_ROW_LEN+1, "VMod: %s", video_modes[cm.id].name);
-            sniprintf(menu_row2, LCD_ROW_LEN+1, "LC: %u VSM: %u", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3);
-            lcd_write_menu();
-            printf("Mod: %s\n", video_modes[cm.id].name);
-            printf("Lines: %u M: %u\n", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, cm.macrovis);
+            sc_status = sc->sc_status;
+            sc_status2 = sc->sc_status2;
+            fpga_v_hz_x100 = (100*TVP_EXTCLK_HZ)/sc_status2.pcnt_frame;
+
+            if (!menu_active) {
+                memset((void*)osd->osd_array.data, 0, sizeof(osd_char_array));
+                read_userdata(profile_sel, 1);
+                sniprintf((char*)osd->osd_array.data[0][0], OSD_CHAR_COLS, "Profile:");
+                sniprintf((char*)osd->osd_array.data[0][1], OSD_CHAR_COLS, "%u: %s", profile_sel, (target_profile_name[0] == 0) ? "<empty>" : target_profile_name);
+                if (cm.sync_active) {
+                    sniprintf((char*)osd->osd_array.data[1][0], OSD_CHAR_COLS, "Mode preset:");
+                    sniprintf((char*)osd->osd_array.data[1][1], OSD_CHAR_COLS, "%s", video_modes[cm.id].name);
+                    sniprintf((char*)osd->osd_array.data[2][0], OSD_CHAR_COLS, "Imode (FPGA):");
+                    sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
+                                                                             sc_status.interlace_flag ? 'i' : 'p',
+                                                                             sc_status.fpga_vsyncgen ? '*' : ' ',
+                                                                             fpga_v_hz_x100/100,
+                                                                             fpga_v_hz_x100%100);
+                    sniprintf((char*)osd->osd_array.data[3][0], OSD_CHAR_COLS, "Ccnt / frame:");
+                    sniprintf((char*)osd->osd_array.data[3][1], OSD_CHAR_COLS, "%lu", (unsigned long)sc_status2.pcnt_frame);
+                }
+                sniprintf((char*)osd->osd_array.data[4][0], OSD_CHAR_COLS, "Firmware:");
+                sniprintf((char*)osd->osd_array.data[4][1], OSD_CHAR_COLS, "%u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 0x1f;
+                osd->osd_sec_enable[1].mask = 0x1f;
+            }
             break;
         case RC_LCDBL:
             sys_ctrl ^= LCD_BL;
-            IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
             break;
-        case RC_SL_MODE: tc.sl_mode = (tc.sl_mode < SL_MODE_MAX) ? (tc.sl_mode + 1) : 0; break;
-        case RC_SL_TYPE: tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0; break;
-        case RC_SL_MINUS: tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0; break;
-        case RC_SL_PLUS: tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX; break;
+        case RC_SL_MODE:
+            tc.sl_mode = (tc.sl_mode < SL_MODE_MAX) ? (tc.sl_mode + 1) : 0;
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_scanlines.items[0].name, OSD_CHAR_COLS);
+                strncpy((char*)osd->osd_array.data[1][0], menu_scanlines.items[0].sel.setting_str[tc.sl_mode], OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_scanlines) {
+                render_osd_page();
+            }
+            break;
+        case RC_SL_TYPE:
+            tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0;
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_scanlines.items[7].name, OSD_CHAR_COLS);
+                strncpy((char*)osd->osd_array.data[1][0], menu_scanlines.items[7].sel.setting_str[tc.sl_type], OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_scanlines) {
+                render_osd_page();
+            }
+            break;
+        case RC_SL_MINUS:
+        case RC_SL_PLUS:
+            if (i == RC_SL_MINUS)
+                tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0;
+            else
+                tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX;
+
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_scanlines.items[1].name, OSD_CHAR_COLS);
+                menu_scanlines.items[1].num.df(tc.sl_str);
+                strncpy((char*)osd->osd_array.data[1][0], menu_row2, OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_scanlines) {
+                render_osd_page();
+            }
+            break;
         case RC_LM_MODE:
             strncpy(menu_row1, "Linemult mode:", LCD_ROW_LEN+1);
             strncpy(menu_row2, "press 1-5", LCD_ROW_LEN+1);
-            lcd_write_menu();
+            osd->osd_config.menu_active = 1;
+            ui_disp_menu(1);
 
             while (1) {
                 btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
@@ -182,7 +269,7 @@ void parse_control()
                         *pmcfg_ptr[video_modes[cm.id].group] = i;
                     } else {
                         sniprintf(menu_row2, LCD_ROW_LEN+1, "%ux unsupported", i+1);
-                        lcd_write_menu();
+                        ui_disp_menu(1);
                         usleep(500000);
                     }
                     break;
@@ -192,44 +279,98 @@ void parse_control()
 
                 usleep(WAITLOOP_SLEEP_US);
             }
-            lcd_write_status();
             menu_active = 0;
+            osd->osd_config.menu_active = 0;
+            ui_disp_status(0);
+            break;
+        case RC_PHASE_MINUS:
+        case RC_PHASE_PLUS:
+            if (i == RC_PHASE_MINUS)
+                video_modes[cm.id].sampler_phase = video_modes[cm.id].sampler_phase ? (video_modes[cm.id].sampler_phase - 1) : SAMPLER_PHASE_MAX;
+            else
+                video_modes[cm.id].sampler_phase = (video_modes[cm.id].sampler_phase < SAMPLER_PHASE_MAX) ? (video_modes[cm.id].sampler_phase + 1) : 0;
+
+            update_cur_vm = 1;
+            if (cm.id == vm_edit)
+                tc_sampler_phase = video_modes[vm_edit].sampler_phase;
+
+            if (!menu_active) {
+                strncpy((char*)osd->osd_array.data[0][0], menu_advtiming.items[8].name, OSD_CHAR_COLS);
+                sniprintf(menu_row2, LCD_ROW_LEN+1, "%d deg", (video_modes[cm.id].sampler_phase*1125)/100);
+                strncpy((char*)osd->osd_array.data[1][0], menu_row2, OSD_CHAR_COLS);
+                osd->osd_config.status_refresh = 1;
+                osd->osd_row_color.mask = 0;
+                osd->osd_sec_enable[0].mask = 3;
+                osd->osd_sec_enable[1].mask = 0;
+            } else if (get_current_menunavi()->m == &menu_advtiming) {
+                render_osd_page();
+            }
             break;
-        case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : 0; break;
-        case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : SAMPLER_PHASE_MAX; break;
         case RC_PROF_HOTKEY:
+Prof_Hotkey_Prompt:
             strncpy(menu_row1, "Profile load:", LCD_ROW_LEN+1);
-            strncpy(menu_row2, "press 0-9", LCD_ROW_LEN+1);
-            lcd_write_menu();
+            sniprintf(menu_row2, LCD_ROW_LEN+1, "press %u-%u", prof_x10*10, ((prof_x10*10+9) > MAX_PROFILE) ? MAX_PROFILE : (prof_x10*10+9));
+            osd->osd_config.menu_active = 1;
+            ui_disp_menu(1);
 
             while (1) {
                 btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
-                for (i = RC_BTN1; i < REMOTE_MAX_KEYS; i++) {
-                    if (btn_vec == rc_keymap[i])
+
+                if ((btn_vec_prev == 0) && (btn_vec != 0)) {
+                    for (i = RC_BTN1; i < REMOTE_MAX_KEYS; i++) {
+                        if (btn_vec == rc_keymap[i])
+                            break;
+                    }
+
+                    if ((i == RC_BTN0) || (i < (RC_BTN1 + (prof_x10 == (MAX_PROFILE/10)) ? (MAX_PROFILE%10) : 9))) {
+                        profile_sel_menu = prof_x10*10 + ((i+1)%10);
+                        retval = load_profile();
+                        sniprintf(menu_row2, LCD_ROW_LEN+1, "%s", (retval==0) ? "Done" : "Failed");
+                        ui_disp_menu(1);
+                        usleep(500000);
                         break;
+                    } else if (i == RC_PROF_HOTKEY) {
+                        prof_x10 = (prof_x10+1) % ((MAX_PROFILE/10)+1);
+                        btn_vec_prev = btn_vec;
+                        goto Prof_Hotkey_Prompt;
+                    } else if (i == RC_BACK) {
+                        break;
+                    }
                 }
 
-                if (i <= RC_BTN0) {
-                    profile_sel = (i+1)%10;
-                    load_profile_disp(OPT_SELECT);
-                    break;
-                } else if (i == RC_BACK) {
-                    break;
-                }
-
+                btn_vec_prev = btn_vec;
                 usleep(WAITLOOP_SLEEP_US);
             }
-            lcd_write_status();
+
             menu_active = 0;
+            osd->osd_config.menu_active = 0;
+            ui_disp_status(0);
+            break;
+        case RC_RIGHT:
+            if (!menu_active)
+                man_target_input = next_input;
             break;
         default: break;
     }
 
+    sys_ctrl ^= REMOTE_EVENT;
+
 Button_Check:
-    if (btn_code_prev == 0) {
-        if (btn_code & PB0_BIT)
-            target_mode = (cm.avinput == AV3_YPBPR) ? AV1_RGBs : (cm.avinput+1);
-        if (btn_code & PB1_BIT)
-            tc.sl_mode = tc.sl_mode < SL_MODE_MAX ? tc.sl_mode + 1 : 0;
+    if (btn_code & PB0_BIT)
+        man_target_input = next_input;
+    if (btn_code & PB1_BIT)
+        tc.sl_mode = tc.sl_mode < SL_MODE_MAX ? tc.sl_mode + 1 : 0;
+
+    if (man_target_input != AV_LAST) {
+        target_input = man_target_input;
+        ret = 1;
     }
+
+    sys_ctrl &= ~(3<<LCD_BL_TIMEOUT_OFFS);
+    if (!menu_active)
+        sys_ctrl |= (lcd_bl_timeout << LCD_BL_TIMEOUT_OFFS);
+
+    IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
+
+    return ret;
 }

software/sys_controller/ossc/controls.h

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2016  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2018  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -60,6 +60,6 @@ typedef enum {
 #define REMOTE_MAX_KEYS (RC_PROF_HOTKEY-RC_BTN1+1)
 
 void setup_rc();
-void parse_control();
+int parse_control();
 
 #endif

software/sys_controller/ossc/fat16_export.c

@@ -0,0 +1,133 @@
+//
+// Copyright (C) 2020 Ari Sundholm <megari@iki.fi>
+//
+// This file has been contributed to the Open Source Scan Converter project
+// developed by Markus Hiienkari Markus Hiienkari <mhiienka@niksula.hut.fi>
+// and other members of the retro gaming community.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <string.h>
+#include "fat16_export.h"
+
+/*
+ * The beginning of the boot sector, along with the BPB.
+ */
+static const alt_u8 bootsec_beg_bpb_16[27] = {
+    0xeb, 0x00, 0x90,                               /* 0x000: Code (x86 short jump + NOP) */
+    0x4d, 0x53, 0x57, 0x49, 0x4e, 0x34, 0x2e, 0x31, /* 0x003: OS Name */
+    0x00, 0x02, 0x04, 0x80, 0x00, 0x02, 0x00, 0x08, /* 0x00B: Bios Parameter Block */
+    0x00, 0x80, 0xf8, 0x20, 0x00, 0x3f, 0x00, 0xff,
+};
+
+/*
+ * The rest of the boot sector before the boot code and terminator.
+ * Offsets 0x024 to 0x03d, inclusive.
+ */
+static const alt_u8 bootsec_after_bpb_16[26] = {
+    /* Zeros             */ 0x80, 0x00, 0x29, 0xf4, /* 0x024...0x027 */
+    0xcf, 0xc6, 0x04, 0x4f, 0x53, 0x53, 0x43, 0x50, /* 0x028...0x02f */
+    0x52, 0x4f, 0x46, 0x49, 0x4c, 0x53, 0x46, 0x41, /* 0x030...0x037 */
+    0x54, 0x31, 0x36, 0x20, 0x20, 0x20, /* Zeros */ /* 0x038...0x03d */
+};
+
+/*
+ * After this, we have the boot code (448 bytes) and sector terminator
+ * (2 bytes). The former will be left zeroed-out and the latter will
+ * be generated.
+ */
+
+/* Generates a FAT16 boot sector.
+ * buf must be at least FAT16_SECTOR_SIZE bytes long,
+ * and is assumed to be pre-zeroed.
+ */
+void generate_boot_sector_16(alt_u8 *const buf) {
+    /* Initial FAT16 boot sector contents + the BPB. */
+    memcpy(buf, bootsec_beg_bpb_16, sizeof(bootsec_beg_bpb_16));
+
+    /*
+     * Then the rest of the boot sector.
+     *
+     * The boot code is supposed to be 448 bytes filled with 0xf4,
+     * but leave it zeroed out to keep the code smaller. This may
+     * be a deviation from the FAT16 spec, but should be harmless
+     * for our purposes.
+     */
+    memcpy(buf + 36, bootsec_after_bpb_16, sizeof(bootsec_after_bpb_16));
+
+    /* RISC-V is little-endian, so do a 16-bit write instead. */
+    *((alt_u16*)(buf + 510)) = 0xaa55U;
+}
+
+/* The fixed 'preamble' of a FAT on a FAT16 volume. */
+static const alt_u32 fat16_preamble = 0xfffffff8U;
+
+/*
+ * Generate a FAT.
+ * The buffer is assumed to be zeroed out and have a size of at least
+ * FAT16_SECTOR_SIZE bytes.
+ * The number of clusters already written is given as an argument.
+ * The function returns the total number of clusters written so far.
+ *
+ * The intention is to be able to generate and write the FAT in chunks
+ * that do not exhaust all the remaining RAM.
+ */
+alt_u16 generate_fat16(void *const buf, const alt_u16 written) {
+	alt_u16 cur_ofs = 0;
+    const alt_u16 start_cluster = 3U + written;
+    alt_u16 *const fat = buf;
+
+    /*
+     * The total number of FAT entries to write consists of:
+     * 1. The FAT "preamble" (2 entries),
+     * 2. The cluster chain of the file (512 entries).
+     *
+     * The latter needs to contain the chain terminator.
+     */
+    const alt_u16 clusters_remaining = PROF_16_CLUSTER_COUNT - written;
+    const alt_u16 preamble_compensation = written ? 0 : 2U;
+    const alt_u16 clusters_to_write =
+        ((clusters_remaining > FAT16_ENTRIES_PER_SECTOR)
+            ? FAT16_ENTRIES_PER_SECTOR
+            : clusters_remaining) - preamble_compensation;
+    const alt_u16 end_cluster = start_cluster + clusters_to_write;
+    const alt_u16 last_fat_cluster = PROF_16_CLUSTER_COUNT + 2U;
+
+    if (!written) {
+        *((alt_u32*)fat) = fat16_preamble;
+        cur_ofs += sizeof(fat16_preamble)/sizeof(alt_u16);
+    }
+
+    for (alt_u16 cluster = start_cluster; cluster < end_cluster; ++cluster) {
+        alt_u16 *const cur_entry = fat + cur_ofs;
+        /* FAT16 entries are 16-bit little-endian. */
+        if (cluster == last_fat_cluster) {
+            /* At the last cluster, write the chain terminator. */
+            *cur_entry = 0xffffU;
+        }
+        else {
+            *cur_entry = cluster;
+        }
+        ++cur_ofs;
+    }
+
+    return end_cluster - 3U;
+}
+
+const alt_u8 prof_dirent_16[PROF_DIRENT_16_SIZE] = {
+    0x4f, 0x53, 0x53, 0x43, 0x50, 0x52, 0x4f, 0x46, 0x42, 0x49, 0x4e, 0x20,
+    0x00, 0x8e, 0x04, 0xb5, 0x6f, 0x51, 0x6f, 0x51, 0x00, 0x00, 0x17, 0x89,
+    0x6f, 0x51, 0x02, 0x00, 0x00, 0x02, 0x10, 0x00,
+};

software/sys_controller/ossc/fat16_export.h

@@ -0,0 +1,83 @@
+//
+// Copyright (C) 2020 Ari Sundholm <megari@iki.fi>
+//
+// This file has been contributed to the Open Source Scan Converter project
+// developed by Markus Hiienkari Markus Hiienkari <mhiienka@niksula.hut.fi>
+// and other members of the retro gaming community.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef FAT16_EXPORT_H_
+#define FAT16_EXPORT_H_
+
+#include "alt_types.h"
+
+/* Use a sector size of 512 bytes. */
+#define FAT16_SECTOR_SIZE 512U
+
+/* This volume has 2048-byte clusters. */
+#define FAT16_CLUSTER_SIZE 2048U
+#define FAT16_SECTORS_PER_CLUSTER (FAT16_CLUSTER_SIZE/FAT16_SECTOR_SIZE)
+
+/* Offsets of the two File Allocation Tables. */
+#define FAT16_1_OFS 0x10000UL
+#define FAT16_2_OFS 0x14000UL
+
+/* Each FAT16 entry is a 16-bit little-endian integer. */
+#define FAT16_ENTRY_SIZE 2U
+#define FAT16_ENTRY_SHIFT 1U
+#define FAT16_ENTRIES_PER_SECTOR (FAT16_SECTOR_SIZE >> FAT16_ENTRY_SHIFT)
+
+/* On this volume, each FAT will be 16 kiB in size. */
+#define FAT16_SIZE 0x04000UL
+
+/* The first sector of the root directory. */
+#define FAT16_ROOT_DIR_FIRST_SECTOR 192U
+
+/* The length of the root directory in sectors. */
+#define FAT16_ROOT_DIR_SECTORS 128U
+
+/*
+ * Define the properties and contents of the directory entry for the
+ * settings file.
+ */
+#define PROF_DIRENT_16_OFS  0x18000UL
+#define PROF_DIRENT_16_SIZE 32U
+
+extern const alt_u8 prof_dirent_16[PROF_DIRENT_16_SIZE];
+
+#define PROF_16_DATA_OFS  0x028000UL
+#define PROF_16_DATA_SIZE 0x100200UL
+#define PROF_16_CLUSTER_COUNT ((PROF_16_DATA_SIZE/FAT16_CLUSTER_SIZE)+!!(PROF_16_DATA_SIZE%FAT16_CLUSTER_SIZE))
+/* Profile file data starts at offset 0x00028000 */
+/* Profile file data  ends  at offset 0x00128200 */
+/* Profile file data is 1049088 bytes long. */
+
+
+/* Generate a FAT16 boot sector.
+ * buf must be at least FAT16_BOOT_SECTOR_SIZE bytes long,
+ * and is assumed to be pre-zeroed.
+ */
+void generate_boot_sector_16(alt_u8 *buf);
+
+/*
+ * Generate a FAT of a FAT16 volume.
+ * The buffer is assumed to be zeroed out and have a size of at least 512 bytes.
+ * The number of clusters already written are given as an argument.
+ * The function returns the total number of clusters written so far.
+ */
+alt_u16 generate_fat16(void *buf, alt_u16 written);
+
+#endif // FAT16_EXPORT_H_

software/sys_controller/ossc/firmware.c

@@ -1,5 +1,5 @@
 //
-// Copyright (C) 2015-2016  Markus Hiienkari <mhiienka@niksula.hut.fi>
+// Copyright (C) 2015-2018  Markus Hiienkari <mhiienka@niksula.hut.fi>
 //
 // This file is part of Open Source Scan Converter project.
 //
@@ -26,24 +26,22 @@
 #include "tvp7002.h"
 #include "av_controller.h"
 #include "lcd.h"
-#include "ci_crc.h"
+#include "utils.h"
+#include "menu.h"
 #include "altera_avalon_pio_regs.h"
 
 extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
 extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
 extern SD_DEV sdcard_dev;
-extern alt_u8 sys_ctrl;
+extern alt_u16 sys_ctrl;
 
 static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
 {
     alt_u32 crcval, tmp;
 
     strncpy(hdr->fw_key, (char*)databuf, 4);
-    if (strncmp(hdr->fw_key, "OSSC", 4)) {
-        sniprintf(menu_row1, LCD_ROW_LEN+1, "Invalid image");
-        menu_row2[0] = '\0';
-        return 1;
-    }
+    if (strncmp(hdr->fw_key, "OSSC", 4))
+        return FW_IMAGE_ERROR;
 
     hdr->version_major = databuf[4];
     hdr->version_minor = databuf[5];
@@ -51,28 +49,22 @@ static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
     hdr->version_suffix[7] = 0;
 
     memcpy(&tmp, databuf+14, 4);
-    hdr->hdr_len = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
+    hdr->hdr_len = bswap32(tmp);
     memcpy(&tmp, databuf+18, 4);
-    hdr->data_len = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
+    hdr->data_len = bswap32(tmp);
     memcpy(&tmp, databuf+22, 4);
-    hdr->data_crc = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
+    hdr->data_crc = bswap32(tmp);
     // Always at bytes [508-511]
     memcpy(&tmp, databuf+508, 4);
-    hdr->hdr_crc = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
+    hdr->hdr_crc = bswap32(tmp);
 
-    if (hdr->hdr_len < 26 || hdr->hdr_len > 508) {
-        sniprintf(menu_row1, LCD_ROW_LEN+1, "Invalid header");
-        menu_row2[0] = '\0';
-        return -1;
-    }
+    if (hdr->hdr_len < 26 || hdr->hdr_len > 508)
+        return FW_HDR_ERROR;
 
-    crcval = crcCI(databuf, hdr->hdr_len, 1);
+    crcval = crc32(databuf, hdr->hdr_len, 1);
 
-    if (crcval != hdr->hdr_crc) {
-        sniprintf(menu_row1, LCD_ROW_LEN+1, "Invalid hdr CRC");
-        menu_row2[0] = '\0';
-        return -2;
-    }
+    if (crcval != hdr->hdr_crc)
+        return FW_HDR_CRC_ERROR;
 
     return 0;
 }
@@ -80,50 +72,50 @@ static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
 static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_u8 *tmpbuf)
 {
     alt_u32 crcval=0, i, bytes_to_read;
-    int retval;
+    SDRESULTS res;
 
     for (i=0; i<size; i=i+SD_BLK_SIZE) {
         bytes_to_read = ((size-i < SD_BLK_SIZE) ? (size-i) : SD_BLK_SIZE);
-        retval = SD_Read(&sdcard_dev, tmpbuf, (offset+i)/SD_BLK_SIZE, 0, bytes_to_read);
-        //retval = read_sd_block(offset+i, bytes_to_read, tmpbuf);
+        res = SD_Read(&sdcard_dev, tmpbuf, (offset+i)/SD_BLK_SIZE, 0, bytes_to_read);
 
-        if (retval != 0)
-            return -2;
+        if (res != SD_OK)
+            return -res;
 
-        crcval = crcCI(tmpbuf, bytes_to_read, (i==0));
+        crcval = crc32(tmpbuf, bytes_to_read, (i==0));
     }
 
-    if (crcval != golden_crc) {
-        sniprintf(menu_row1, LCD_ROW_LEN+1, "Invalid data CRC");
-        menu_row2[0] = '\0';
-        return -3;
-    }
+    if (crcval != golden_crc)
+        return FW_DATA_CRC_ERROR;
 
     return 0;
 }
 
-#ifdef DEBUG
-int fw_update()
-{
-    sniprintf(menu_row2, LCD_ROW_LEN+1, "Unavailable");
-    lcd_write_menu();
-    usleep(1000000);
-    return -1;
-}
-#else
 int fw_update()
 {
     int retval, i;
     int retries = FW_UPDATE_RETRIES;
+    char *errmsg;
     alt_u8 databuf[SD_BLK_SIZE];
     alt_u32 btn_vec;
     alt_u32 bytes_to_rw;
     fw_hdr fw_header;
 
+#ifdef CHECK_STACK_USE
+    // estimate stack usage, assuming around here is the worst case (due to 512B databuf)
+    alt_u32 sp;
+    asm volatile("mov %0, sp" : "=r"(sp));
+    sniprintf(menu_row1, LCD_ROW_LEN+1, "Stack size:");
+    sniprintf(menu_row2, LCD_ROW_LEN+1, "%lu bytes", (ONCHIP_MEMORY2_0_BASE+ONCHIP_MEMORY2_0_SIZE_VALUE)-sp);
+    ui_disp_menu(1);
+    usleep(1000000);
+#endif
+
     retval = check_sdcard(databuf);
     SPI_CS_High();
-    if (retval != 0)
+    if (retval != 0) {
+        retval = -retval;
         goto failure;
+    }
 
     retval = check_fw_header(databuf, &fw_header);
     if (retval != 0)
@@ -131,14 +123,14 @@ int fw_update()
 
     sniprintf(menu_row1, LCD_ROW_LEN+1, "Validating data");
     sniprintf(menu_row2, LCD_ROW_LEN+1, "%u bytes", (unsigned)fw_header.data_len);
-    lcd_write_menu();
+    ui_disp_menu(1);
     retval = check_fw_image(512, fw_header.data_len, fw_header.data_crc, databuf);
     if (retval != 0)
         goto failure;
 
     sniprintf(menu_row1, LCD_ROW_LEN+1, "%u.%.2u%s%s", fw_header.version_major, fw_header.version_minor, (fw_header.version_suffix[0] == 0) ? "" : "-", fw_header.version_suffix);
     strncpy(menu_row2, "Update? 1=Y, 2=N", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
 
     while (1) {
         btn_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
@@ -146,8 +138,7 @@ int fw_update()
         if (btn_vec == rc_keymap[RC_BTN1]) {
             break;
         } else if (btn_vec == rc_keymap[RC_BTN2]) {
-            retval = 2;
-            strncpy(menu_row1, "Cancelled", LCD_ROW_LEN+1);
+            retval = FW_UPD_CANCELLED;
             goto failure;
         }
 
@@ -163,47 +154,68 @@ int fw_update()
     strncpy(menu_row1, "Updating FW", LCD_ROW_LEN+1);
 update_init:
     strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
 
-    for (i=0; i<fw_header.data_len; i=i+SD_BLK_SIZE) {
-        bytes_to_rw = ((fw_header.data_len-i < SD_BLK_SIZE) ? (fw_header.data_len-i) : SD_BLK_SIZE);
-        retval = SD_Read(&sdcard_dev, databuf, (512+i)/SD_BLK_SIZE, 0, bytes_to_rw);
-        if (retval != 0)
-            goto failure;
-
-        retval = write_flash_page(databuf, ((bytes_to_rw < PAGESIZE) ? bytes_to_rw : PAGESIZE), (i/PAGESIZE));
-        if (retval != 0)
-            goto failure;
-        //TODO: support multiple page sizes
-        if (bytes_to_rw > PAGESIZE) {
-            retval = write_flash_page(databuf+PAGESIZE, (bytes_to_rw-PAGESIZE), (i/PAGESIZE)+1);
-            if (retval != 0)
-                goto failure;
-        }
-    }
+    retval = copy_sd_to_flash(512/SD_BLK_SIZE, 0, fw_header.data_len, databuf);
+    if (retval != 0)
+        goto failure;
 
     strncpy(menu_row1, "Verifying flash", LCD_ROW_LEN+1);
     strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
-    lcd_write_menu();
+    ui_disp_menu(1);
     retval = verify_flash(0, fw_header.data_len, fw_header.data_crc, databuf);
     if (retval != 0)
         goto failure;
 
     SPI_CS_High();
+
+    strncpy(menu_row1, "Firmware updated", LCD_ROW_LEN+1);
+    strncpy(menu_row2, "please restart", LCD_ROW_LEN+1);
+    ui_disp_menu(1);
+    while (1) {}
+
     return 0;
 
 failure:
     SPI_CS_High();
-    lcd_write_menu();
+
+    switch (retval) {
+        case SD_NOINIT:
+            errmsg = "No SD card det.";
+            break;
+        case FW_IMAGE_ERROR:
+            errmsg = "Invalid image";
+            break;
+        case FW_HDR_ERROR:
+            errmsg = "Invalid header";
+            break;
+        case FW_HDR_CRC_ERROR:
+            errmsg = "Invalid hdr CRC";
+            break;
+        case FW_DATA_CRC_ERROR:
+            errmsg = "Invalid data CRC";
+            break;
+        case FW_UPD_CANCELLED:
+            errmsg = "Update cancelled";
+            break;
+        case -FLASH_VERIFY_ERROR:
+            errmsg = "Flash verif fail";
+            break;
+        default:
+            errmsg = "SD/Flash error";
+            break;
+    }
+    strncpy(menu_row2, errmsg, LCD_ROW_LEN+1);
+    ui_disp_menu(1);
     usleep(1000000);
 
-    // Probable rw error, retry update
-    if ((retval <= -200) && (retries > 0)) {
+    // Critical error, retry update
+    if ((retval < 0) && (retries > 0)) {
         sniprintf(menu_row1, LCD_ROW_LEN+1, "Retrying update");
         retries--;
         goto update_init;
     }
 
+    render_osd_page();
     return -1;
 }
-#endif