Bruno Cardoso Lopes
2e64ae4101
Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move
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a convert pattern close to the instruction definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 01:26:39 +00:00
Kevin Enderby
c37d4bbf1f
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
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llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 23:01:50 +00:00
Bruno Cardoso Lopes
cea34e41fa
The vpermilps and vpermilpd have different behaviour regarding the
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usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:56:34 +00:00
Bruno Cardoso Lopes
4ea496846a
Recognize unpckh* masks and match 256-bit versions. The new versions are
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different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 22:03:40 +00:00
Bruno Cardoso Lopes
cf128eab90
Remove now unused patterns. 0 insertions(+), 98 deletions(-)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:22:39 +00:00
Bruno Cardoso Lopes
5e3267dac9
Cleanup old matching for PUNPCK* variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:22:27 +00:00
Bruno Cardoso Lopes
5d348b4dc4
Add 256-bit isel for movsldup/movshdup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:32 +00:00
Bruno Cardoso Lopes
cc1c3526a7
Add 128-bit AVX versions of movshdup/mosldup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:23 +00:00
Bruno Cardoso Lopes
3e9235c720
Cleanup movsldup/movshdup matching.
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27 insertions(+), 62 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:13 +00:00
Bruno Cardoso Lopes
863bd9d5cf
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
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This also fixes PR10452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:32 +00:00
Bruno Cardoso Lopes
51e92e8e41
Add remaining 256-bit vector bitcasts. This also fixes PR10451
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:28 +00:00
Bruno Cardoso Lopes
6a32adc4e5
- Handle special scalar_to_vector case: splats. Using a native 128-bit
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shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:25 +00:00
Bruno Cardoso Lopes
8360b5fa81
Add v8f32->v8i32 bitcast. Fixes PR10440
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 19:51:02 +00:00
Bruno Cardoso Lopes
dbd4fe2b0a
- Register v16i16 as valid VR256 register class
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- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
65b74e1d00
Add support for 256-bit versions of VPERMIL instruction. This is a new
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instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
Bruno Cardoso Lopes
0e87805074
Add aditional patterns for vextractf128 instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:39 +00:00
Bruno Cardoso Lopes
df0e03ceb8
Add aditional patterns for vinsertf128 instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:36 +00:00
Bruno Cardoso Lopes
bca4781b61
Move code around. No functionality changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:30 +00:00
Bruno Cardoso Lopes
3f6a8dd4ce
Be more smart with VCVTSS2SD. Also place the patterns close to the
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definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 18:11:25 +00:00
Bruno Cardoso Lopes
3aaa010ece
Add AVX 128-bit sqrt versions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 17:51:40 +00:00
Bruno Cardoso Lopes
4201ecae92
Add AVX 128-bit patterns for sint_to_fp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 00:50:20 +00:00
Bruno Cardoso Lopes
983d19dd10
Add a few patterns for 256-bit bitcasts. No testcases now, they are
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comming together with other tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135312 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 22:24:17 +00:00
Bruno Cardoso Lopes
62f67f86fe
Add 256-bit load/store recognition and matching in several places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:50:58 +00:00
Bruno Cardoso Lopes
466b022c99
Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
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general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes
c1af4772f1
The target specific node PANDN name is misleading. That happens because
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it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:47 +00:00
Bruno Cardoso Lopes
61905f0139
AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 01:15:33 +00:00
Eli Friedman
af45b3d8cb
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 18:21:20 +00:00
Eli Friedman
a390a1aa48
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23 21:07:47 +00:00
Nick Lewycky
94d4c91bc5
Add support for assembling "movq" when it's correct to do so, while continuing
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to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 22:45:41 +00:00
Bob Wilson
38c892624b
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
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This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 17:35:13 +00:00
Nick Lewycky
1bd15700a0
Emit movq for 64-bit register to XMM register moves, but continue to accept
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movd when assembling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20 18:33:26 +00:00
Bruno Cardoso Lopes
d381a7a91e
Add AVX suport for fpextend.
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Original patch by Syoyo Fujita with more comments by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 07:03:21 +00:00
Bruno Cardoso Lopes
9a767330f5
Add one more argument to the prefetch intrinsic to indicate whether it's a data
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or instruction cache access. Update the targets to match it and also teach
autoupgrade.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 04:58:37 +00:00
Stuart Hastings
865f09334f
Reapply 132424 with fixes. This fixes PR10068.
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rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 23:53:54 +00:00
Rafael Espindola
251b4a0405
Revert 132424 to fix PR10068.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 19:57:47 +00:00
Stuart Hastings
ec880283b3
Recommit 132404 with fixes. rdar://problem/5993888
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 21:33:14 +00:00
Stuart Hastings
4abc5fea9c
Revert 132404 to appease a buildbot. rdar://problem/5993888
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 19:52:20 +00:00
Stuart Hastings
10ff0bbdfb
Add support for x86 CMPEQSS and friends. These instructions do a
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floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs. Only profitable when the user wants a materialized 0
or 1 at runtime. rdar://problem/5993888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 17:17:45 +00:00
Stuart Hastings
4fd0dee3bf
FGETSIGN support for x86, using movmskps/pd. Will be enabled with a
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patch to TargetLowering.cpp. rdar://problem/5660695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01 04:39:42 +00:00
Chad Rosier
62660310d9
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
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crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
Rafael Espindola
a3f88148e6
Don't produce a vmovntdq if we don't have AVX support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:30:01 +00:00
Bill Wendling
9493a285d1
Replace the "movnt" intrinsics with a native store + nontemporal metadata bit.
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<rdar://problem/8460511>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 21:11:17 +00:00
Eric Christopher
2fc496fcf5
xmm0 is an implicit parameter in this and so shouldn't be in the
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string template.
Fixes rdar://8493866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 01:28:32 +00:00
Chris Lattner
bb0fff0cb4
clean up after Sean's r127646 patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 05:40:18 +00:00
Bill Wendling
f93f7b2446
Reapply r129401 with patch for clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 00:36:11 +00:00
Bill Wendling
f9b2dc66c8
Revert r129401 for now. Clang is using the old way of doing things.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129403 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 22:59:27 +00:00
Bill Wendling
d5f323d70b
Remove the unaligned load intrinsics in favor of using native unaligned loads.
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Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.
First part of <rdar://problem/8460511>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129401 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 22:46:31 +00:00
Sean Callanan
f88896b2a9
Enabled disassembler support for AVX instructions
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in the instruction tables and fixed a few bugs that
were causing decode conflicts. Rudimentary tests
are coming up in the next patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127646 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:28:15 +00:00
David Greene
a20244d1ba
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
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missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 17:23:43 +00:00
Joerg Sonnenberger
5ad596f9d2
Recognize monitor/mwait with explicit register arguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 00:48:11 +00:00
David Greene
ccacdc1952
[AVX] Support VSINSERTF128 with more patterns and appropriate
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infrastructure. This makes lowering 256-bit vectors to 128-bit
vectors simple when 256-bit vector support is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04 16:08:29 +00:00
David Greene
c38a03eeca
[AVX] VEXTRACTF128 support. This commit includes patterns for
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matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines
to examine and translate index values. VINSERTF128 comes next. With
these two in place we can begin supporting more AVX operations as
INSERT/EXTRACT can be used as a fallback when 256-bit support is not
available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03 15:50:00 +00:00
Chris Lattner
ccea167db5
fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24 03:42:46 +00:00
Chris Lattner
3a5004dc3e
Fix PR8946, a missing reg/reg form of movdqu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11 17:04:55 +00:00
Chris Lattner
c010e61ae1
fix PR8900, a shuffle miscompilation. Patch by Nadav Rotem!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-05 22:28:46 +00:00
Nate Begeman
672fb6225b
Implement feedback from Bruno on making pblendvb an x86-specific ISD node in addition to being an intrinsic, and convert
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lowering to use it. Hopefully the pattern fragment is doing the right thing with XMM0, looks correct in testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20 22:04:24 +00:00
Nate Begeman
b65c175d32
Add support for matching psign & plendvb to the x86 target
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Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 22:55:37 +00:00
Nate Begeman
d191751f0e
Add some missing predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 00:54:26 +00:00
Nate Begeman
2ea8ee7c76
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 00:26:57 +00:00
Nate Begeman
3c49706a61
Add support for AVX to materialize +0.0 when doing scalar FP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 21:43:51 +00:00
Benjamin Kramer
1292c22645
Add patterns for the x86 popcnt instruction.
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- Also adds a new POPCNT subtarget feature that is currently enabled if the target
supports SSE4.2 (nehalem) or SSE4A (barcelona).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-04 20:32:23 +00:00
Nate Begeman
07c21d85b4
Scalar f32/f64 are also subregs of ymm regs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 21:54:39 +00:00
Eric Christopher
d872f144e2
Implement a PseudoI class and transfer the sse instructions over to use
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it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 08:57:23 +00:00
Eric Christopher
228232b282
Rewrite mwait and monitor support and custom lower arguments.
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Fixes PR8573.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 07:20:12 +00:00
Bruno Cardoso Lopes
a84ad90c06
Fix PR8211
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:24:59 +00:00
Dale Johannesen
e49406fd63
Fix pastos in handling of AVX cvttsd2si, PR8491.
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Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 00:35:54 +00:00
Chris Lattner
a228376185
simplify some map operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:57:02 +00:00
Evan Cheng
835580fc3a
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:50:20 +00:00
Chris Lattner
c7252ce743
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
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where !cast is just as short.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 00:19:21 +00:00
Chris Lattner
8d978a75b4
allow !strconcat to take more than two operands to eliminate
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!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 23:58:18 +00:00
Chris Lattner
748a2fe917
distribute the rest of the contents of X86Instr64bit.td out to
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the right places. X86Instr64bit.td now dies, long live x86-64!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 20:49:15 +00:00
Chris Lattner
5673e1d314
move CMOV_FR32 and friends to InstrCompiler, since they are
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pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 06:41:40 +00:00
Chris Lattner
6f42027263
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 05:05:03 +00:00
Chris Lattner
f3654db458
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 04:55:40 +00:00
Chris Lattner
b2ef4c1235
add basic avx support to the disassembler, also teach it about ssmem/sdmem
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operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:57:56 +00:00
Chris Lattner
bf6018ac5a
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
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Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:36:32 +00:00
Chris Lattner
0c04e4f58f
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:24:57 +00:00
Dale Johannesen
e5db19ebd5
Fix typos. 128-bit PSHUFB takes 128-bit memory op.
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v8i16 is not an MMX type; put it where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 21:15:43 +00:00
Bruno Cardoso Lopes
ae4f7421c0
Add one more pattern to fallback movddup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:48:34 +00:00
Dale Johannesen
f73c5587fa
Move remaining MMX instructions from SSE to MMX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 17:13:07 +00:00
Dale Johannesen
4efb0feac8
Move most MMX instructions (defined as anything that
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uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX. No (intended) functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 01:02:39 +00:00
Bruno Cardoso Lopes
1485cc2bb3
x86 vector shuffle lowering now relies only on target specific
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nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 17:43:25 +00:00
Dale Johannesen
86097c384f
Add patterns for MMX that use the new intrinsics.
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Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:10:56 +00:00
Bruno Cardoso Lopes
70e81f1517
Remove unused target specific node
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 17:38:55 +00:00
Dale Johannesen
caa9ba228d
Remove the rest of the nonexistent 64-bit AVX instructions.
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Bruno, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 21:23:00 +00:00
Bruno Cardoso Lopes
190d0a54c1
Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 20:44:26 +00:00
Daniel Dunbar
3139422058
Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced
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some infinite loop and select failures.
- Apologies for eager reverting, but its branch day.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 19:38:11 +00:00
Bruno Cardoso Lopes
95f1e2d6b5
AVX doesn't support mm operations neither its instrinsics.
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The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 02:08:45 +00:00
Bruno Cardoso Lopes
5e5342b0a8
- Use specific nodes to match unpckl masks.
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- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:24:00 +00:00
Bruno Cardoso Lopes
d00bfe1f8d
become more strict about when it's safe to use X86ISD::MOVLPS
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 02:35:51 +00:00
Bruno Cardoso Lopes
29c353b9c3
Using target specific nodes for shuffle nodes makes the mask
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check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:
movaps (%rdi), %xmm0
movaps (%rax), %xmm1
movaps %xmm0, %xmm2
movss %xmm1, %xmm2
shufps $36, %xmm2, %xmm0
now is generated as:
movaps (%rdi), %xmm0
movaps %xmm0, %xmm1
movlps (%rax), %xmm1
shufps $36, %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:33:20 +00:00
Bruno Cardoso Lopes
56098f5d26
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 05:08:25 +00:00
Bruno Cardoso Lopes
013bb3dee9
Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:35:05 +00:00
Bruno Cardoso Lopes
5023ef281c
Use x86 specific MOVSHDUP node and add more patterns to match it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:22:11 +00:00
Bruno Cardoso Lopes
f2db5b48d0
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 21:15:21 +00:00
Bruno Cardoso Lopes
8878e21fe6
Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:16:15 +00:00
Bruno Cardoso Lopes
3157ef1c13
This is the first step towards refactoring the x86 vector shuffle code. The
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general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 22:55:05 +00:00
Dale Johannesen
1b4051095d
Revert 110491. While not wrong, it was based on a
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misanalysis and is undesirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
bbadd39bbb
Improve comment to make explicit why not to touch this could before JIT goes MC
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 17:44:10 +00:00
Eric Christopher
63f02ac349
Revert last patch and r110954 as I meant to.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 02:37:50 +00:00
Bruno Cardoso Lopes
64baddc0f2
Some small clean-up: use of pseudo instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:55:18 +00:00
Bruno Cardoso Lopes
642eb02045
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
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- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
6da9cee0f1
Define AVX 128-bit pattern versions of SET0PS/PD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes
8c05a850f4
Begin to support some vector operations for AVX 256-bit intructions. The long
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term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 02:06:36 +00:00
Bruno Cardoso Lopes
045573ce21
Add AVX matching patterns to Packed Bit Test intrinsics.
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Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 23:25:42 +00:00
Bruno Cardoso Lopes
9f798e9a9e
Add AVX movnt{pd,ps,dq} 256-bit intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 02:49:24 +00:00
Bruno Cardoso Lopes
fcfcca1d9b
Add AVX movmsk 256-bit intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 02:34:56 +00:00
Bruno Cardoso Lopes
405f11b300
Support AVX 256-bit load and store intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 01:43:16 +00:00
Bruno Cardoso Lopes
6719784148
Patterns to match AVX cmp instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 00:13:20 +00:00
Bruno Cardoso Lopes
533a7df02d
Add matching patterns for vblend AVX intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 00:02:05 +00:00
Bruno Cardoso Lopes
93f6c1ec6e
Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ 256-bit conversion intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 21:51:56 +00:00
Bruno Cardoso Lopes
8468157278
Add patterns to AVX conversions instructions. Do that instead of declaring more intructions whenever is possible, more coming
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 21:24:59 +00:00
Bruno Cardoso Lopes
ad4910429c
Memory version of vcvtdq2pd intrinsic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 18:20:14 +00:00
Bruno Cardoso Lopes
251871ca66
Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 18:03:43 +00:00
Dale Johannesen
7f6eb639bd
Use sdmem and sse_load_f64 (etc.) for the vector
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form of CMPSD (etc.) Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.) 8193553.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-07 00:33:42 +00:00
Bruno Cardoso Lopes
4945dd8314
Patterns to match AVX 256-bit vzero intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 22:10:01 +00:00
Bruno Cardoso Lopes
bd2d90f5a5
Patterns to match AVX 256-bit permutation intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 20:03:27 +00:00
Bruno Cardoso Lopes
9c3806461c
Patterns to match AVX 256-bit horizontal arithmetic intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 02:10:30 +00:00
Bruno Cardoso Lopes
9c09f16a53
Patterns to match AVX 256-bit arithmetic intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110425 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 01:52:29 +00:00
Bruno Cardoso Lopes
98f985607b
Support all 128-bit AVX vector intrinsics. Most part of them I already
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declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 19:54:33 +00:00
Bruno Cardoso Lopes
f528d2b438
Add AVX version of CLMUL instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
06e6e101a0
Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 00:14:54 +00:00
Bruno Cardoso Lopes
fb583a9842
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:18:49 +00:00
Eric Christopher
9a9d275dc7
Custom lower the memory barrier instructions and add support
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for lowering without sse2. Add a couple of new testcases.
Fixes a few libgomp tests and latent bugs. Remove a few todos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 02:48:34 +00:00
Bruno Cardoso Lopes
2b69143083
Add more 256-bit forms for a bunch of regular AVX instructions
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Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 23:53:50 +00:00
Bruno Cardoso Lopes
e29f37f6a1
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 21:37:59 +00:00
Bruno Cardoso Lopes
928fc3b4a0
Avoid AVX instructions to be selected instead of its SSE form
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 20:38:42 +00:00
Bruno Cardoso Lopes
cf6ca03128
Add AVX only vzeroall and vzeroupper instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
7d7d15a159
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
4b13f3cf3d
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
1154f426d7
Add new AVX vextractf128 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 23:19:02 +00:00
Bruno Cardoso Lopes
e1c29be6f0
Add new AVX instruction vinsertf128
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 19:44:51 +00:00
Bruno Cardoso Lopes
43945d99de
Add AVX vbroadcast new instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes
94143ee625
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 23:32:44 +00:00
Bruno Cardoso Lopes
7dbf7d8b1c
Add AVX 256-bit compare instructions and a bunch of testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
87a85c7ef0
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes
fd920fa59a
Add AVX 256-bit packed logical forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
6991623dd7
Add AVX 256-bit unop arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
4344d85769
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 00:38:47 +00:00
David Greene
8f17bc4fbd
Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
...
utility classes can be used from multiple files. This will aid
transitioning to a new refactored x86 SIMD specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 23:41:28 +00:00
Bruno Cardoso Lopes
a0d09a85e2
Add AVX 256 binary arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
f428fee70d
More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 22:41:32 +00:00
Dan Gohman
cfbf0ed8b0
Apply the SSE dependence idiom for SSE unary operations to
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SD instructions too, in addition to SS instructions. And
add a comment about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:46:04 +00:00
Bruno Cardoso Lopes
aa099be71f
Add AVX 256-bit MOVMSK forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:06:32 +00:00
Bruno Cardoso Lopes
d52e78efac
Add AVX 256-bit packed MOVNT variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
2bfb8f6ef8
Add AVX 256-bit unpack and interleave
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
e86b01c153
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:27:43 +00:00
Bruno Cardoso Lopes
ced9ec9bac
Add AVX AES instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
4f6bdf9042
Add AVX SSE4.2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
332fce49e3
Use only one multiclass to pinsrq instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
5e9fa98523
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
09df2ae0d0
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312
Add AVX SSE4.1 extractps and pinsr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
4fd32db6a6
Add AVX SSE4.1 Extract Integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
ee94e8297e
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
36869b69b0
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
07de40629f
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:36:24 +00:00
Chris Lattner
a5b412581c
rip out even more sporadic v2f32 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 04:38:33 +00:00
Bill Wendling
f43f6bc3ec
Revert r107583. I no longer think that this is the way to solve the problem.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 09:16:57 +00:00
Bill Wendling
4a991a6fa6
Mark sse_load_f32 and sse_load_f64 as having memory operands
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(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 08:59:55 +00:00
Bruno Cardoso Lopes
68b559e5f3
Add AVX SSE4.1 blend, mpsadbw and vdp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
2c70d4ad35
Add AVX SSE4.1 round instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
03560600b4
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
f5cd8c51e3
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
f12ad66741
Shrink down SSE3 code by more multiclass refactoring
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
944facac2e
Shrink down SSE3 code by some multiclass refactoring - 1st part
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61
Add AVX SSE3 packed addsub instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
79b634c244
Add AVX SSE3 replicate and convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
6596a62076
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a
Move MOVD/MODQ code around, creating sections for each of them
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150
Add AVX SSE2 mask creation and conditional store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20
Add AVX SSE2 packed integer extract/insert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
876085dcfa
Add AVX SSE2 integer unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae
Add AVX SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd
Small refactoring of SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2
Add AVX SSE2 pack with saturation integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c
Add AVX SSE2 integer packed compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750
- Add AVX form of all SSE2 logical instructions
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- Add VEX encoding bits to x86 MRM0r-MRM7r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716
Add *several* AVX integer packed binop instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
2c818072cc
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e
Add AVX Move Aligned/Unaligned packed integers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes
147b7cad2f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
721ef73d88
Add AVX non-temporal stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb
Move non-temporal movs to their own section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes
ea86423cbd
Add sqrt, rsqrt and rcp AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
b22dc70a5c
Refactoring of arithmetic instruction classes with unary operator
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes
4548260ab5
Described the missing AVX forms of SSE2 convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
bdffc16d65
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
161476ec34
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
95325b08a3
revert this now, it's using avx instead of sse :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
544a95d716
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:27:51 +00:00
Dan Gohman
ca5b8553ea
pcmpeqd and friends are Commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:05:35 +00:00
Bruno Cardoso Lopes
39afa908de
Move the last piece of SSE2 convert instructions to the Convert Instructions section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4
More SSE refactoring, this time with different types of MOVs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:22:12 +00:00
Bruno Cardoso Lopes
0491e132fc
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 18:06:22 +00:00
Bruno Cardoso Lopes
a0ae87fd5d
Add some AVX convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727
Refactoring of SSE convert intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792
Refactoring of SSE conversion instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
e0c437333e
Refactor SSE cmp intrinsics and declare the same for AVX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
788184365a
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:48:23 +00:00
Bruno Cardoso Lopes
6539dc6e6c
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
34a491bd8e
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:15:50 +00:00
Bruno Cardoso Lopes
e93e300ad0
Add AVX MOVMSK{PS,PD}rr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
7dbfd07e32
Add AVX SHUF{PS,PD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:07:15 +00:00
Bruno Cardoso Lopes
62a76c6401
Add AVX compare packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b
Reapply support for AVX unpack and interleave instructions, with
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testcases this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c
Add AVX MOV{SS,SD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:38:56 +00:00
Bruno Cardoso Lopes
d3a067bbc2
Reorganize logical and arithmetic SSE 1 & 2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 18:17:40 +00:00
Bruno Cardoso Lopes
f23919b3e9
Reorganize SSE instructions, making easier to see oportunities for refactoring
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 18:09:32 +00:00
Bruno Cardoso Lopes
c27d1e4d17
revert r106482
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 22:59:03 +00:00
Bruno Cardoso Lopes
b7cc3f6ae6
change parameter name to avoid confusion with global definition
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:28:07 +00:00
Bruno Cardoso Lopes
b44e8b2d11
Add unpack and interleave AVX instructions, encoding tests cooming soon
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:48 +00:00
Bruno Cardoso Lopes
c79e43aee3
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:36:04 +00:00
Bruno Cardoso Lopes
59bb6fae9a
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106436 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:22:54 +00:00
Bruno Cardoso Lopes
f6ff003043
Refactoring of regular logical packed instructions to prepare for AVX ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
f4f4bad696
Refactor aliased packed logical instructions, also add
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AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
1e8d06282f
Move new sse 1 & 2 generic classes to a more appropriate place
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
efc9b69deb
Remove unnecessary arguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
17227db062
Add AVX packed intrinsics for MIN, MAX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:17:05 +00:00
Bruno Cardoso Lopes
be4d595afd
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:31 +00:00
Bruno Cardoso Lopes
fda1acb389
Clean up: remove now unnecessary Constraints
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:09:27 +00:00
Bruno Cardoso Lopes
c82f199892
more refactoring! yay! big win over the intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:00:22 +00:00
Bruno Cardoso Lopes
8af5ed9e15
Apply some refactor to packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:13:35 +00:00
Bruno Cardoso Lopes
4b8921d1c7
Use the new 'defm' class inheritance in SSE
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:10:11 +00:00
Bruno Cardoso Lopes
d7f9cc4de7
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:12:56 +00:00
Bruno Cardoso Lopes
597ec8ed51
Use new tablegen resources in SSE tablegen code. This will
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be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 23:05:30 +00:00
Bruno Cardoso Lopes
2dcf6d6019
make the avx intrinsics 3 address
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 03:12:14 +00:00
Bruno Cardoso Lopes
11ae95c175
Add some basic fp intrinsics for AVX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105873 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 02:38:32 +00:00
Bruno Cardoso Lopes
cf125d02a0
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
7be0d2c8e9
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
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Handle OpSize TSFlag for AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
c902a59f4c
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
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Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes
99405df044
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Chris Lattner
1087f54ddb
revert r105521, which is breaking the buildbots with stuff like this:
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In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a
Initial AVX support for some instructions. No patterns matched
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yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 03:53:24 +00:00
Bruno Cardoso Lopes
7f5b0d8099
Refactor some SSE 2 unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 17:02:50 +00:00
Bruno Cardoso Lopes
f39e0ce4ec
More SSE 1 & 2 merge, this time with logical instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 22:47:03 +00:00
Bruno Cardoso Lopes
aa02ff1a2b
Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring
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common code between SSE versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 18:17:40 +00:00
Dan Gohman
d9c2af5409
Fix a typo in a comment that Gabor noticed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:03:53 +00:00
Daniel Dunbar
79373680ed
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
Eric Christopher
7e2f5aaa67
Make sure aeskeygenassist uses an unsigned immediate field.
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Fixes rdar://8017638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Dan Gohman
14aaeac5cf
Define the x86 pause instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:35:50 +00:00
Dan Gohman
ee5673b622
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:23:41 +00:00
Eric Christopher
6d972fd087
Remove the palignr intrinsics now that we lower them to vector shuffles,
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shifts and null vectors. Autoupgrade these to what we'd lower them to.
Add a testcase to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:59:54 +00:00
Chris Lattner
65de1b9eb3
a bunch of ssse3 instructions are misencoded to think they have an
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i8 field when they really do not. This fixes rdar://7840289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 07:38:24 +00:00
Eric Christopher
cff6f85454
Allow lowering for palignr instructions for mmx sized vectors. Add
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patterns to handle the lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:40:20 +00:00