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4039 Commits

Author SHA1 Message Date
Jim Grosbach
cd3c7cb915 Nuke a FIXME. No need to be fancier here, as ARM handles constant pools 
locations and formatting specially. rdar://7353441

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 23:09:20 +00:00
Owen Anderson
75579f739f Provide Thumb2 encodings for basic loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:44:32 +00:00
Evan Cheng
1e0eab122b Mark Darwin call instructions as using "r7" to prevent the frame-register 
assignment instructions from being moved below / above calls.
rdar://8690640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:43:27 +00:00
Jim Grosbach
a0bb253119 Nuke dead isCodeGenOnly annotation and extraneous comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:40:58 +00:00
Jim Grosbach
fbf0cb18cb tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120335 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:38:48 +00:00
Bill Wendling
9b0e92ca5b Thumb encodings for conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120334 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:37:46 +00:00
Jim Grosbach
5ca66696e7 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:37:40 +00:00
Bill Wendling
a46a493c02 Refactor some of the "disassembly-only" instructions into a base class. This 
reduces some code duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:15:03 +00:00
Eric Christopher
7bb5996e47 Update fastisel for the changes in r120272. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 21:56:23 +00:00
Jim Grosbach
d092a87ba3 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 21:28:32 +00:00
Owen Anderson
5404c2b36e Improving the factoring of several instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 20:38:48 +00:00
Bob Wilson
86c6d80a7a Add support for NEON VLD3-dup instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:35:29 +00:00
Bob Wilson
2fcda63763 Fix copy-and-paste errors in VLD2-dup scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:35:23 +00:00
Jim Grosbach
f1aa47dc1a ARM Pseudo-ize tBR_JTr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:32:47 +00:00
Owen Anderson
00a035f74f Thumb2 encodings for MSR and MRS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:29:15 +00:00
Owen Anderson
d18a9c9b9d Thumb2 encodings for system instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:22:08 +00:00
Owen Anderson
05bf595122 Thumb2 encodings for branches and IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:54:38 +00:00
Jim Grosbach
11fbff8085 The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to 
get the pretty-printer. That's handled explicityly by the MC lowering now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120305 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:53:24 +00:00
Michael J. Spencer
3cc52ea33c I swear I did a make clean and make before committing all this... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120304 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:47:54 +00:00
Jim Grosbach
2dc7768d73 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:37:44 +00:00
Bill Wendling
2f17bf2a44 Add more Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 01:07:48 +00:00
Bill Wendling
5cbbf68e35 More Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 01:00:43 +00:00
Bill Wendling
d19ac0c75a Add Thumb encodings for REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 00:42:50 +00:00
Bill Wendling
849f2e381e Add more Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 00:18:15 +00:00
Bob Wilson
b1dfa7a8e0 Add support for NEON VLD2-dup instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:26 +00:00
Bob Wilson
f3d2f9d4be Another minor refactoring for VLD1DUP instructions. 
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:15 +00:00
Bob Wilson
364a72a8e5 Add entry in getTargetNodeName() for ARMISD::VBICIMM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 06:51:11 +00:00
Anton Korobeynikov
94c5ae0875 Move more PEI-related hooks to TFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
cd775ceff0 Move callee-saved regs spills / reloads to TFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 23:05:03 +00:00
Bob Wilson
bce55776af Refactor. Set alignment bit in VLD1-dup instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 07:12:02 +00:00
Bob Wilson
2a0e97431e Add NEON VLD1-dup instructions (load 1 element to all lanes). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 06:35:16 +00:00
Bob Wilson
8d41294664 Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. 
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from.  As far as I can tell now,
these instruction stages are clearly intended to overlap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 06:35:09 +00:00
Daniel Dunbar
36d76a8dbc MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 04:38:36 +00:00
Rafael Espindola
fd46797d0d Remove the unused TheTarget member. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-26 04:24:21 +00:00
Jason W Kim
13534672de Move the ARM reloc constants to Support/ELF.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 19:40:36 +00:00
Bob Wilson
626613d5e8 Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations. 
We need to check if the individual vector elements are sign/zero-extended
values.  For now this only handles constants values.  Radar 8687140.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 19:38:38 +00:00
Wesley Peck
bf17cfa3f9 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-23 03:31:01 +00:00
Evan Cheng
ab5c703fdb Fix epilogue codegen to avoid leaving the stack pointer in an invalid 
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 18:12:04 +00:00
Duncan Sands
3d93893895 Fix a compiler warning about Kind being used uninitialized 
when assertions are disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-22 09:38:00 +00:00
Eric Christopher
9d89311df8 Pseudos default to 4byte size, let the instruction size field notice 
that branch tables are special.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 23:38:19 +00:00
Bill Wendling
dcf0a47b76 More Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:49:36 +00:00
Bill Wendling
af2b573614 Add encoding for ARM "trap" instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:05:29 +00:00
Bill Wendling
9717fa9f29 The "trap" instruction is one of this which doesn't have a condition code. Hack 
the code to not add a "condition code" if it's trap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 10:56:05 +00:00
Bill Wendling
7d0affdf02 - Give "trap" the correct encoding, at least according to Darwin's assembler. 
- Add comments saying where the encodings for other instructions came from.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 10:55:23 +00:00
Owen Anderson
aa54524a44 Use by-name rather than by-order operand matching for some NEON encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 06:47:06 +00:00
Jim Grosbach
0eb49c57f0 BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119918 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 01:26:01 +00:00
Bill Wendling
5cc88a205d A few more thumb instruction MC encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119913 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:52:33 +00:00
Eric Christopher
827656dab4 Rewrite address handling to use a structure with all the possible address 
mode variables. Handle frame indexes in load/store and allocas again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:38:27 +00:00
Eric Christopher
13df1a0bac STRH only needs the additional operand, not t2STRH. Also invert conditional 
to match the one from the load emitter above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 22:01:38 +00:00
Anton Korobeynikov
82f58740c7 Move some more hooks to TargetFrameInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 15:59:32 +00:00
Bill Wendling
a09cc2b429 Add more Thumb add instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 01:18:47 +00:00
Bill Wendling
95a6d1759d Add Thumb encodings for some add instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119882 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 01:00:29 +00:00
Bill Wendling
6179c31e07 Add more encodings for Thumb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 00:53:35 +00:00
Bill Wendling
20272a7c5a Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same 
value that the one in ARMMCCodeEmitter.cpp does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-20 00:26:37 +00:00
Jim Grosbach
078e239f69 Fix ARM LDR* post-indexed operand encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:14:43 +00:00
Bill Wendling
1228038ed9 Encodings for the compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119868 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:14:32 +00:00
Owen Anderson
b16926940e The Vm and Vn register fields must be the same for a register-register vmov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:12:43 +00:00
Evan Cheng
ff96b63d6f Fix a cut-n-paste-error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:01:16 +00:00
Jim Grosbach
7b6ab402fe Operand names 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:43:08 +00:00
Jim Grosbach
a30a51b16a trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119863 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:42:55 +00:00
Eric Christopher
b371658083 Don't need to save piecemeal now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:39:56 +00:00
Eric Christopher
2d630d7bc9 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:37:58 +00:00
Bill Wendling
0ae28e4447 Add encodings for some of the thumb ADD instructions. Tests will come once the 
asm parser can handle them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:37:33 +00:00
Eric Christopher
88de86b550 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:36:41 +00:00
Jim Grosbach
efaeb41aec Clarify operand names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:36:02 +00:00
Eric Christopher
0d58122e12 Refactor address mode handling into a single struct (ala x86), this 
should give allow a wider range of addressing modes.

No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:30:02 +00:00
Jim Grosbach
6571101cb7 Fix encoding for ARM MLS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:22:37 +00:00
Jim Grosbach
2aeb6121a1 Add ARM encoding information for STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:14:31 +00:00
Jim Grosbach
a1b4175b8e Shuffle things around a bit to keep like things together. Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:06:57 +00:00
Bill Wendling
ba46dc06e6 Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:06:18 +00:00
Bill Wendling
a898166d38 Change long binary encodings to use hex instead. It's more readable. Also 
initialize missing bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:02:18 +00:00
Jim Grosbach
953557f445 Factor out operand encoding bits for ARM addressing mode 2 store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:35:06 +00:00
Jim Grosbach
e2d54af47f Delete another dead class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:16:08 +00:00
Jim Grosbach
fc0cb4b906 whitespace tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:14:37 +00:00
Jim Grosbach
9ef65cbbc6 Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119841 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:14:02 +00:00
Jim Grosbach
9558b4cdc4 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:07:51 +00:00
Jim Grosbach
9cb15b5be5 Add ARM binary encoding information for the rest of the indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119821 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 19:41:26 +00:00
Jim Grosbach
0c2283a910 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:18:37 +00:00
Jim Grosbach
f1ce7cc1d1 ARM LDRD binary encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:16:46 +00:00
Jim Grosbach
3ea4daaf50 Remove hard tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119810 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:01:37 +00:00
Jim Grosbach
7a08864860 Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 17:11:02 +00:00
Benjamin Kramer
7920d96964 Avoid release build warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 16:36:02 +00:00
Owen Anderson
8b8640a964 Fix decoding ambiguities of stdrex and ldrex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 13:11:50 +00:00
Evan Cheng
1f190c8bdf These instructions are thumb2 only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 06:28:11 +00:00
Evan Cheng
e8e67e13d4 Fix an obvious oversight. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 06:15:10 +00:00
Bill Wendling
602890dd8e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx 
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 01:33:10 +00:00
Bill Wendling
cb21d1c9fd Use array_pod_sort because the list is contiguous. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:38:19 +00:00
Owen Anderson
91a7c59134 Provide Thumb2 encodings for strex and ldrex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:28:38 +00:00
Jim Grosbach
817c1a6ddd Minor cleanups to a few llvm_unreachable() calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:27:09 +00:00
Bill Wendling
d1fadd8c5d An 'unreachable' shouldn't have a '0 &&' prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:05:15 +00:00
Bill Wendling
50d0f58944 Add support for parsing the writeback ("!") token. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:43:05 +00:00
Jason W Kim
837caa9313 Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. 
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:37:15 +00:00
Owen Anderson
71c11825bf Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:29:56 +00:00
Jim Grosbach
75b7b879c0 ARM Encoding information for UXTAH and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:24:22 +00:00
Tanya Lattner
9684a7c128 Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first). 
Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 22:06:46 +00:00
Bill Wendling
24d22d2764 Don't allocate the SmallVector of Registers. It gets messy figuring out who 
should delete what when the object gets copied around. It's also making valgrind
upset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:50:54 +00:00
Owen Anderson
8ee9779658 Provide Thumb2 encodings for mov's that come from MOVCC SDNodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:46:31 +00:00
Jim Grosbach
c884aff5f4 Add ARM encoding information for LDRH post-increment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119743 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:43:37 +00:00
Anton Korobeynikov
d0c3817669 Move hasFP() and few related hooks to TargetFrameInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:19:35 +00:00
Bob Wilson
d5448bb6e8 Split up ARM LowerShift function. 
This function was being called from two different places for completely
unrelated reasons.  During type legalization, it was called to expand 64-bit
shift operations.  During operation legalization, it was called to handle
Neon vector shifts.  The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function.  I don't have a particular testcase for this; I just noticed it
by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:16:28 +00:00
Owen Anderson
612fb5b9a6 More Thumb2 encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119737 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 21:15:19 +00:00
Owen Anderson
821752e2e6 Fill out the set of Thumb2 multiplication operator encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 20:32:18 +00:00
Bill Wendling
707120047e Missed the _RET versions of LDMIA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 19:44:29 +00:00
Eric Christopher
8b3ca6216d Rewrite stack callee saved spills and restores to use push/pop instructions. 
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.

Adjust all testcases accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 19:40:05 +00:00
Jim Grosbach
056ab107ff ARMPseudoInst instructions should default to being considered a single 4-byte 
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119713 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 18:01:40 +00:00
Evan Cheng
5c71c7a137 Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119610 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:43:23 +00:00
Jim Grosbach
1251e1a8df Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:39:50 +00:00
Jim Grosbach
99594eb1de ARM PseudoInst instructions don't need or use an assembler string. Get rid of 
the operand to the pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119607 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:38:26 +00:00
Evan Cheng
1b4886dd00 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:28:51 +00:00
Jim Grosbach
c6961f140a Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:20:48 +00:00
Jim Grosbach
53694265a9 Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 
just pretend to be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:15:56 +00:00
Owen Anderson
35141a9ba3 Try again at providing Thumb2 encodings for basic multiplication operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:08:42 +00:00
Jim Grosbach
160f8f0e67 Refactor a few ARM load instructions to better parameterize things and re-use 
common encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:46:58 +00:00
Owen Anderson
424216453f Revert r119593 while I figure out my testing disagrees with the buildbot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:42:51 +00:00
Owen Anderson
18333616cd Provide correct Thumb2 encodings for basic multiplication operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:19:10 +00:00
Jim Grosbach
85eb54cf0c Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark 
it as such. Add some encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 23:33:14 +00:00
Owen Anderson
2f7aed39a3 Second attempt at correct encodings for Thumb2 bitfield instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 22:16:31 +00:00
Jim Grosbach
0129be281e Fix comment typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:57:51 +00:00
Bob Wilson
05646099a0 Change ARMGlobalMerge to keep BSS globals in separate pools. 
This completes the fixes for Radar 8673120.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:39 +00:00
Bob Wilson
619a372617 Fix ARMGlobalMerge pass to check if globals are entirely within range. 
It is generally not sufficient to check if the starting offset is in range
of the maximum offset that can be efficiently used for the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:36 +00:00
Bob Wilson
72831dc905 Change the symbol for merged globals from "merged" to "_MergedGlobals". 
This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:33 +00:00
Bob Wilson
edf046716c Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes. 
It was mistakenly looking at the pointer type when checking for the size of
global variables.  This is a partial fix for Radar 8673120.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:25:27 +00:00
Jim Grosbach
f8dabac604 Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly 
in the MC lowering process.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:05:55 +00:00
Evan Cheng
6b19491468 Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119558 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:56:30 +00:00
Owen Anderson
5aba9f694f Revert r119551, which broke buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119555 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:48:51 +00:00
Owen Anderson
23465a06f4 Provide Thumb2 encodings for bitfield instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119551 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:35:29 +00:00
Evan Cheng
c4af4638df Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, 
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:13:28 +00:00
Rafael Espindola
f2dc4aa562 make isVirtualSection a virtual method on MCSection. Chris' suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:03:54 +00:00
Owen Anderson
46c478e802 More miscellaneous Thumb2 encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 19:57:38 +00:00
Bill Wendling
df8d94da01 Add missing opcodes now that this function's used in more than one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119539 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 19:16:20 +00:00
Jim Grosbach
89e14c7579 More ARM encoding bits. LDRH now encodes properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 18:11:11 +00:00
Evan Cheng
baa45f7298 Revert r119109 for now. It's breaking 176.gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 09:31:04 +00:00
Evan Cheng
3642e64c11 Simplify code that toggle optional operand to ARM::CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 08:06:50 +00:00
Chris Lattner
b75c651e22 tidy up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 05:41:32 +00:00
Bill Wendling
2567eec423 The machine instruction no longer encodes the submode as a separate operand. We 
should get the submode from the load/store multiple instruction's opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 05:31:09 +00:00
Bill Wendling
0f63075613 Proper encoding for VLDM and VSTM instructions. The register lists for these 
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 04:32:08 +00:00
Bill Wendling
6bc105a7b9 Add binary emission stuff for VLDM/VSTM. This reuses the 
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 00:45:23 +00:00
Bill Wendling
3380f6a4d0 Use the correct variable names so that the encodings will be correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 23:44:49 +00:00
Jim Grosbach
7911916cf7 ARM conditional mov encoding fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 18:13:42 +00:00
Bill Wendling
1eeb2806cb L_bit doesn't work here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119325 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 02:20:22 +00:00
Bill Wendling
7b71878d9f - Remove dead patterns. 
- Add encodings to the *LDMIA_RET instrs. Probably not needed...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 02:08:45 +00:00
Bill Wendling
73c57e149c vldm and vstm are mnemonics for vldmia and vstmia resp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 02:00:24 +00:00
Bill Wendling
73fe34a3ee Encode the multi-load/store instructions with their respective modes ('ia', 
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 01:16:36 +00:00
Owen Anderson
c56dcbf641 Add Thumb2 encodings for mov and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 00:29:56 +00:00
Owen Anderson
da663f7b51 Attempt to provide encodings for some miscellaneous Thumb2 encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 21:30:39 +00:00
Evan Cheng
eb96a2f6c0 Code clean up. The peephole pass should be the one updating the instruction 
iterator, not TII->OptimizeCompareInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 21:20:45 +00:00
Owen Anderson
2c4c45deb6 Provide Thumb2 encodings for sxtb and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 21:12:05 +00:00
Eric Christopher
76dda7ec1d Recommit this change and remove the failing part of the test - it didn't 
pass in the first place and was masked by earlier failures not warning
and aborting the block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 21:11:06 +00:00
Jim Grosbach
99f53d13ef ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 20:47:07 +00:00
Owen Anderson
bb6315d1e4 Add Thumb2 encodings for comparison and shift operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 19:58:36 +00:00
Owen Anderson
a99e778ed8 Add correct Thumb2 encodings for mvn and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 18:45:17 +00:00
Jim Grosbach
11bbeecdf1 Add FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 18:36:48 +00:00
Jim Grosbach
17e967eac2 Nuke redundant encoding bit set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 18:17:24 +00:00
Chris Lattner
2ac190238e add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 05:19:05 +00:00
Evan Cheng
fbc8c67992 Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119109 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 03:30:30 +00:00
Chris Lattner
65a0adb597 silence a ton of warnings from clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 01:45:44 +00:00
Anton Korobeynikov
a460e4a142 Attempt to unbreak cmake-based builds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 00:48:12 +00:00
Anton Korobeynikov
3346491223 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 00:06:54 +00:00
Chris Lattner
77ec256be6 trim #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119075 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 21:16:04 +00:00
Chris Lattner
30e2cc254b rename LowerToMCInst -> LowerARMMachineInstrToMCInst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 21:00:02 +00:00
Chris Lattner
1612a619f1 even more simplifications. ARM MCInstLowering is now just 
a single function instead of a class.  It doesn't need the
complexity that X86 does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 20:58:38 +00:00
Chris Lattner
b16ddb1fb3 more shrinkification 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 20:41:53 +00:00
Chris Lattner
de36af4c15 more simplifications. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 20:40:08 +00:00
Chris Lattner
112f2390e1 simplify and tidy up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 20:31:06 +00:00
Chris Lattner
60d5b5fdee stub out a powerpc MCInstPrinter implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 19:40:38 +00:00
Owen Anderson
83da6cd5e2 Second attempt at providing correct encodings for Thumb2 binary operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-14 05:37:38 +00:00
Bill Wendling
c93989a060 Comment out the defms until they're activated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 11:20:05 +00:00
Bill Wendling
ddc918b379 Add uses of the *_ldst_multi multiclasses. These aren't used yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 10:57:02 +00:00
Bill Wendling
1f4abcfa5c Convert the modes to lower case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 10:43:34 +00:00
Bill Wendling
04863d06fb Minor cleanups: 
- Get the opcode once.
- Add a ParserMatchClass to reglist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 10:40:19 +00:00
Bill Wendling
6c470b806f Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the 
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 09:09:38 +00:00
Daniel Dunbar
115a3dd066 MC: Simplify Mach-O and ELF object writer implementations. 
- What was I thinking?????

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118992 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 07:33:40 +00:00
Evan Cheng
c47f7d643e Conditional moves are slightly more expensive than moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 05:14:20 +00:00
Evan Cheng
63f3544a7f Add conditional move of large immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 02:25:14 +00:00
Jim Grosbach
df7e0f8d5d Swap multiclass operand order for consistency with other patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 01:28:30 +00:00
Jim Grosbach
0f6e33b0c8 Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 01:07:20 +00:00
Jim Grosbach
9e0bfb5829 More ARM load/store indexed refactoring. Also fix an incorrect IndexMode 
flag for the LDRT/STRT family instructions as a side effect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 00:35:48 +00:00
Evan Cheng
e5e0ef180e Fix an obvious typo which inverted an immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 00:27:47 +00:00
Eric Christopher
84e86c0156 Temporarily revert this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118946 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:50:48 +00:00
Evan Cheng
11c11f8ab0 For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:46:13 +00:00
Owen Anderson
b9a643e2cd Revert r118939 while I work out why it broke some buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:36:03 +00:00
Owen Anderson
7a6b810dcb Attemt to provide correct encodings for Thumb2 binary operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:18:11 +00:00
Evan Cheng
893d7fe209 Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:03:38 +00:00
Eric Christopher
c0394c0b8c Make this happen for ARM like x86. Don't entirely bail out when 
an address is in a different block, get it into a register and go
from there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 22:52:32 +00:00
Evan Cheng
875a6ac09a Add conditional mvn instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 22:42:47 +00:00
Jim Grosbach
e1634e9351 Zap a copy/paste-o bit of dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:29:10 +00:00
Jim Grosbach
2716e25c2c Refactor to parameterize some ARM load/store encoding patterns. Preparatory 
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:28:15 +00:00
Owen Anderson
5de6d841a5 First stab at providing correct Thumb2 encodings, start with adc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:12:40 +00:00
Evan Cheng
529916ca4a Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 20:32:20 +00:00
Jim Grosbach
b39e6488ee Kill more unused stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 19:27:45 +00:00
Jim Grosbach
a0a6a47c02 Remove unused class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 19:24:53 +00:00
Jim Grosbach
d75c3f136b Fill in the default predication bits for ARM unconditional branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 18:13:26 +00:00
Jim Grosbach
80f9e6724f Encoding for ARM LDRSB instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 17:52:59 +00:00
Eric Christopher
d0c82a683e Fix up a few more spots of addrmode2 (or not) changes that were 
missed. Update some comments accordingly.

Fixes rdar://8652289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 09:48:30 +00:00
Jim Grosbach
e50e6bcd90 Start of support for binary emit of 16-it Thumb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 23:41:09 +00:00
Owen Anderson
8f14391314 Fill out support for Thumb2 encodings of NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 23:12:55 +00:00
Owen Anderson
57dac88f77 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 21:36:43 +00:00
Eric Christopher
79ab2fe01a Revert the accidental commit I made reverting the previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:50:14 +00:00
Jim Grosbach
d1d5a39cad ARM fixup encoding for direct call instructions (BL). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:05:40 +00:00
Eric Christopher
6c50119ba3 Revert this temporarily. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:47:02 +00:00
Eric Christopher
391f228e7e Change the prologue and epilogue to use push/pop for the low ARM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:26:03 +00:00
Owen Anderson
c7139a6f0d Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:07:48 +00:00
Jim Grosbach
c466b937db Encoding of destination fixup for ARM branch and conditional branch 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:04:49 +00:00
Jim Grosbach
7eab97f260 Encoding for ARM LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 16:55:29 +00:00
Jim Grosbach
928f3325a7 Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616 Fix encoding of Ra register for ARM smla* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691 ARM STRH encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381 ARM LDM encoding for the mode (ia, ib, da, db) operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e Fix ARM encoding of non-return LDM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca Fix ARM encoding of LDM+Return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:12:48 +00:00
Nate Begeman
bf5be2654e Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 21:35:41 +00:00
Jim Grosbach
7c7ddb21c3 Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes 
double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7 Update ARMConstantPoolValue to not use a modifier string. Use an explicit 
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 03:26:07 +00:00
Bill Wendling
8ea974039a Emit a '!' if this is a "writeback" register or memory address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
cc8d10e1a8 Rename a parameter to avoid confusion with a local variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 00:08:58 +00:00
Bill Wendling
8e8b18bcfa Emit the warning about the register list not being in ascending order only once. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 23:45:59 +00:00
Bill Wendling
5fa22a1975 s/std::vector/SmallVector/ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 23:28:44 +00:00
Bill Wendling
c3236753d6 Delete the allocated vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:51:42 +00:00
Bob Wilson
66f6c79450 Define the subtarget feature for the architecture version, 
as derived from the target triple.  This is important for enabling
features that are implied based on the architecture version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:50:47 +00:00
Bob Wilson
54f9256380 Do not use MEMBARRIER_MCR for any Thumb code. 
It is only supported for ARM code.  Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled.  This prevents a "cannot select MEMBARRIER_MCR" error in that
situation.  Radar 8644195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:50:44 +00:00
Bill Wendling
7729e06c12 Two types of instructions have register lists: 
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.

The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:44:22 +00:00
Jim Grosbach
3a2429a86c Change the ARMConstantPoolValue modifier string to an enumeration. This will 
help in MC'izing the references that use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 21:36:17 +00:00
Jim Grosbach
c9962aca8f Handle ARM constant pool values that need an explicit reference to the '.' 
pseudo-label. (TLS stuff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 19:40:22 +00:00
Jim Grosbach
16cb3763c5 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 19:22:26 +00:00
Jim Grosbach
5df08d8f55 Further MCize ARM constant pool values. This allows basic PIC references for 
object file emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 18:45:04 +00:00
Jim Grosbach
e0ee08e367 Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 18:43:54 +00:00
Jim Grosbach
d92354c574 For ARM load/store instructions, encode [reg+reg] with no shifter immediate as 
a left shift by zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:38:15 +00:00
Jim Grosbach
a9a0dde872 ARM .word data fixups don't need an adjustment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:36:59 +00:00
Jim Grosbach
54fea632b1 Add encoder method for ARM load/store shifted register offset operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:20:53 +00:00
Jim Grosbach
679cbd3b21 Add support for a few simple fixups to the ARM Darwin asm backend. This allows 
constant pool references and global variable refernces to resolve properly
for object file generation. For example,

int x;
void foo(unsigned a, unsigned *p) {
  p[a] = x;
}

can now be successfully compiled directly to an (ARM mode) object file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 01:37:15 +00:00
Bill Wendling
5e559a22c1 Revert r118457 and r118458. These won't hold for GPRs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 00:30:18 +00:00
Bill Wendling
4b97c55648 Get the register and count from the register list operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:51:20 +00:00
Bill Wendling
3734ef3fb4 reglist has two operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:50:20 +00:00
Bill Wendling
87f4f9a946 The "addRegListOperands()" function returns the start register and the total 
number of registers in the list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:49:57 +00:00
Owen Anderson
c24cb3551e Add support for ARM's specialized vector-compare-against-zero instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:21:22 +00:00
Bill Wendling
85c3f24da3 Add "write back" bit encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 21:28:03 +00:00
Dale Johannesen
7179d1e5c0 Revert 118422 in search of bot verdancy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 19:17:22 +00:00
Jason W Kim
69ad7138b7 Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 17:58:07 +00:00
Jason W Kim
6cecceb2f6 Complete listing of ARM/MC/ELF relocation enums 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 16:47:27 +00:00
Bill Wendling
5991487c10 Make RegList an ASM operand so that TableGen will generate code for it. This is 
an initial implementation and may change once reglists are fully fleshed out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 00:39:58 +00:00
Bill Wendling
b32e7844e9 Revert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 00:32:40 +00:00
Bill Wendling
e8399c6e01 In this context, a reglist is a reg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-07 13:08:28 +00:00
Bill Wendling
e717610f53 Add support for parsing register lists. We can't use a bitfield to keep track of 
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 22:36:58 +00:00
Bill Wendling
8155e5b753 Return the base register of a register list for the "getReg()" method. This is 
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 22:19:43 +00:00
Bill Wendling
146018fc64 General cleanup: 
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 21:42:12 +00:00
Bill Wendling
8d5acb7007 Add a RegList (register list) object to ARMOperand. It will be used soon to hold 
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 19:56:04 +00:00
Bill Wendling
12f40e9a63 Fix grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 10:51:53 +00:00
Bill Wendling
a60f157b7c Fix grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 10:48:18 +00:00
Bill Wendling
d68fd9c79e MatchRegisterName() returns 0 if it can't match the register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-06 10:45:34 +00:00