Chris Lattner
f95705163f
Compile X > -1 -> text X,X; js dest
...
This implements CodeGen/X86/jump_sign.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30283 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-13 03:22:10 +00:00
Evan Cheng
c356a572e3
Reflects MachineConstantPoolEntry changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-12 21:04:05 +00:00
Evan Cheng
734503be59
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
...
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30241 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-11 02:19:56 +00:00
Evan Cheng
25ab690a43
Committing X86-64 support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08 06:48:29 +00:00
Evan Cheng
8cf723d8eb
- Identify a vector_shuffle that can be turned into an undef, e.g.
...
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30171 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08 01:50:06 +00:00
Chris Lattner
ffc0b2663e
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
...
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30156 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-07 20:33:45 +00:00
Chris Lattner
5ea7a68e15
Revert this patch, the front-end has been fixed to make it unneccesary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29752 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 18:43:24 +00:00
Chris Lattner
b5bc04d38a
'g' is handled by the front-end.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29751 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 18:12:28 +00:00
Andrew Lenharth
ad1ed016ce
Fix handling of 'g'. Closes 883
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29750 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 17:50:12 +00:00
Andrew Lenharth
d337295fb0
Add the 'c' constraint as needed by the linux kernel
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29747 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 16:07:50 +00:00
Andrew Lenharth
c63e56ee5f
Add support for S and D constraints, as needed to compile the linux kernel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29746 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 15:35:43 +00:00
Chris Lattner
e219945348
Eliminate use of getNode that takes a vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-11 17:38:39 +00:00
Evan Cheng
64a752f7c7
Match tablegen changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-11 09:08:15 +00:00
Evan Cheng
311ace0391
Convert more calls of getNode() that takes a vector to pass in the start of an array.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29601 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-11 07:35:45 +00:00
Chris Lattner
bd564bfc63
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29566 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-08 02:23:42 +00:00
Chris Lattner
f76d180c95
Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll.
...
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29420 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-31 23:26:50 +00:00
Chris Lattner
35d86fef1f
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29307 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-26 21:12:04 +00:00
Evan Cheng
625518002d
This opt is now handled in DAG combine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29243 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-21 08:26:46 +00:00
Evan Cheng
1e1a88e8cc
A splat of a vector constant of all zero or all one is the vector constant.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29234 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-20 23:09:47 +00:00
Chris Lattner
6d3465793f
Add information preventing several register class constraints from working.
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This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29118 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-12 16:59:49 +00:00
Chris Lattner
f4dff84c86
Implement the inline asm 'A' constraint. This implements PR825 and
...
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29101 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 02:54:03 +00:00
Evan Cheng
1e60c098cc
Fixed stack objects do not specify alignments, but their offsets are known.
...
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29090 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-10 21:37:44 +00:00
Chris Lattner
5c5f4ca6f1
Mark internal function static
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29085 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-10 19:53:12 +00:00
Evan Cheng
206ee9d86c
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
...
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29042 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-07 08:33:52 +00:00
Evan Cheng
60c07e1aea
Reorg. No functionality change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28999 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-05 22:17:51 +00:00
Evan Cheng
da08d2c39a
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28910 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-24 08:36:10 +00:00
Evan Cheng
015188ffbc
Type of vector extract / insert index operand should be iPTR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28796 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15 08:14:54 +00:00
Evan Cheng
b69d113201
Add argument registers to the end of call operand list (partial fix).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28783 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-14 18:17:40 +00:00
Evan Cheng
b12223e284
Minor compilation speed improvement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28736 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-09 06:24:42 +00:00
Evan Cheng
e8bd0a332a
Added X86FunctionInfo subclass of MachineFunction to record whether the
...
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28703 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-06 23:30:24 +00:00
Evan Cheng
2675534b7f
Typos
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28617 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-01 05:53:27 +00:00
Evan Cheng
04b2562502
Remove a warning
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28607 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-01 00:30:39 +00:00
Evan Cheng
8f692e2457
Remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28581 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-31 00:50:42 +00:00
Evan Cheng
6848be1a27
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 23:10:12 +00:00
Evan Cheng
3fddf241d8
Vector argument must be passed in memory location aligned on 16-byte boundary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28505 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 20:37:47 +00:00
Evan Cheng
1d6a9b3b6c
Mac OS X ABI document lied. The first four XMM registers are used to pass
...
vector arguments, not three.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28504 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 19:22:06 +00:00
Evan Cheng
052fb5110f
Minor update to make the code more clear
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28499 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 18:39:59 +00:00
Evan Cheng
f9d62dc6e5
Update more comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28498 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 18:37:16 +00:00
Evan Cheng
f9ff7c54be
Fix some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28497 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 18:25:43 +00:00
Evan Cheng
6f707999a1
No need to handle illegal types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28496 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26 18:22:49 +00:00
Evan Cheng
cc1fc220a0
Consistency
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28488 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 23:31:23 +00:00
Evan Cheng
25e71d10a0
Some clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28483 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 22:38:31 +00:00
Evan Cheng
a9bb445db0
Remove some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28481 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 22:25:52 +00:00
Evan Cheng
6b5783d0b1
Build breakage.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28475 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 18:56:34 +00:00
Evan Cheng
32fe1035a7
Switch X86 over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28463 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 00:59:30 +00:00
Chris Lattner
c6d0567324
Fix file header comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28441 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-23 23:20:42 +00:00
Evan Cheng
4db3af3511
Better way to check for vararg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28440 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-23 21:08:24 +00:00
Evan Cheng
25caf63cd2
Remove PreprocessCCCArguments and PreprocessFastCCArguments now that
...
FORMAL_ARGUMENTS nodes include a token operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28439 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-23 21:06:34 +00:00
Chris Lattner
2d2970905c
Implement an annoying part of the Darwin/X86 abi: the callee of a struct
...
return argument pops the hidden struct pointer if present, not the caller.
For example, in this testcase:
struct X { int D, E, F, G; };
struct X bar() {
struct X a;
a.D = 0;
a.E = 1;
a.F = 2;
a.G = 3;
return a;
}
void foo(struct X *P) {
*P = bar();
}
We used to emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
addl $28, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
ret
This is correct on Linux/X86 but not Darwin/X86. With this patch, we now
emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
*** addl $24, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
*** ret $4
For the record, GCC emits (which is functionally equivalent to our new code):
_bar:
movl 4(%esp), %eax
movl $3, 12(%eax)
movl $2, 8(%eax)
movl $1, 4(%eax)
movl $0, (%eax)
ret $4
_foo:
pushl %esi
subl $40, %esp
movl 48(%esp), %esi
leal 16(%esp), %eax
movl %eax, (%esp)
call _bar
subl $4, %esp
movl 16(%esp), %eax
movl %eax, (%esi)
movl 20(%esp), %eax
movl %eax, 4(%esi)
movl 24(%esp), %eax
movl %eax, 8(%esi)
movl 28(%esp), %eax
movl %eax, 12(%esi)
addl $40, %esp
popl %esi
ret
This fixes SingleSource/Benchmarks/CoyoteBench/fftbench with LLC and the
JIT, and fixes the X86-backend portion of PR729. The CBE still needs to
be updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28438 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-23 18:50:38 +00:00
Chris Lattner
cdbaeb52ae
CSRet allows varargs
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28409 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-19 21:34:04 +00:00
Evan Cheng
4ac8974d02
Should pass by reference.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28357 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 19:07:40 +00:00
Chris Lattner
aa9406b0c4
Implement the custom lowering hook right, returning values for all of the
...
arguments at once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28327 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 17:14:26 +00:00
Chris Lattner
e7746c9084
Fix a bug I introduced yesterday, which broke functions with *no* arguments.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28326 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 17:08:35 +00:00
Evan Cheng
069287d460
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 07:21:53 +00:00
Chris Lattner
8c0c10c2b9
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28320 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 06:45:34 +00:00
Chris Lattner
03ea4c8326
Dead variable
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28265 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 21:12:22 +00:00
Chris Lattner
80a7ecc923
Teach the X86 backend about non-i32 inline asm register classes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28139 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 00:29:37 +00:00
Chris Lattner
bd04aa5796
Teach the code generator to use cvtss2sd as extload f32 -> f64
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28131 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-05 21:35:18 +00:00
Owen Anderson
a69571c799
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-03 01:29:57 +00:00
Evan Cheng
347d5f789a
Initial caller side support (for CCC only, not FastCC) of 128-bit vector
...
passing by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28015 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 21:29:37 +00:00
Evan Cheng
43f3bd310b
Implement four-wide shuffle with 2 shufps if no more than two elements come
...
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28011 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 07:03:38 +00:00
Evan Cheng
020c41f21e
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 05:25:15 +00:00
Evan Cheng
fea89c14ec
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
...
for now.
Patch contributed by Alexander Friedman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27994 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:40:39 +00:00
Evan Cheng
2fdd95eee7
Support for passing 128-bit vector arguments via XMM registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27992 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:31:10 +00:00
Evan Cheng
5fb03ce905
Oops
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27989 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 05:44:50 +00:00
Evan Cheng
85e3800e42
Bug fix: not updating NumIntRegs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27988 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 05:35:28 +00:00
Evan Cheng
eda65fa20b
- Clean up formal argument lowering code. Prepare for vector pass by value work.
...
- Fixed vararg support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 01:32:22 +00:00
Evan Cheng
9191dbba8e
Fix fastcc failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27980 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-26 18:21:31 +00:00
Evan Cheng
1bc7804e4c
Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27975 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-26 01:20:17 +00:00
Evan Cheng
0db9fe6775
Separate LowerOperation() into multiple functions, one per opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27972 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-25 20:13:52 +00:00
Evan Cheng
37d1d9bc66
Special case handling two wide build_vector(0, x).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27961 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-24 22:58:52 +00:00
Evan Cheng
c78d3b43f5
A little bit more build_vector enhancement for v8i16 cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27959 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-24 18:01:45 +00:00
Evan Cheng
9293451e3f
MOVL shuffle (i.e. movd or movss / movsd from memory) of undef, V2 == V2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27953 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-23 06:35:19 +00:00
Nate Begeman
37efe67645
JumpTable support! What this represents is working asm and jit support for
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x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-22 18:53:45 +00:00
Evan Cheng
1900c012f5
Don't do all the lowering stuff for 2-wide build_vector's. Also, minor optimization for shuffle of undef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27946 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-22 08:34:05 +00:00
Evan Cheng
a083af14c8
Fix a performance regression. Use {p}shuf* when there are only two distinct elements in a build_vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-22 06:21:46 +00:00
Evan Cheng
ba05f728b5
Revamp build_vector lowering to take advantage of movss and movd instructions.
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movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
Evan Cheng
017dcc6e55
Now generating perfect (I think) code for "vector set" with a single non-zero
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scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
Evan Cheng
39623daef6
- Added support to turn "vector clear elements", e.g. pand V, <-1, -1, 0, -1>
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to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27875 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-20 08:58:49 +00:00
Evan Cheng
72cd9a9439
Handle v2i64 BUILD_VECTOR custom lowering correctly. v2i64 is a legal type,
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but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27849 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-20 00:11:39 +00:00
Evan Cheng
94fe5eb14a
isSplatMask() bug: first element can be an undef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27847 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 23:28:59 +00:00
Evan Cheng
80d428c370
- Added support to do aribitrary 4 wide shuffle with no more than three
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instructions.
- Fixed a commute vector_shuff bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27845 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 22:48:17 +00:00
Evan Cheng
533a0aa9ba
Commute vector_shuffle to match more movlhps, movlp{s|d} cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27840 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 20:35:22 +00:00
Evan Cheng
cdfc3c82a7
Use movss to insert_vector_elt(v, s, 0).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27782 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 22:45:49 +00:00
Evan Cheng
5edb8d270c
Use two pinsrw to insert an element into v4i32 / v4f32 vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27779 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 22:04:06 +00:00
Evan Cheng
c575ca22ea
Implement v8i16, v16i8 splat using unpckl + pshufd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27768 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 20:43:08 +00:00
Chris Lattner
b2be4032c5
implement returns of a vector, testcase here: CodeGen/X86/vec_return.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27767 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 20:32:50 +00:00
Evan Cheng
5001ea1078
FP SETOLT, SETOLT, SETUGE, SETUGT conditions were implemented incorrectly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27755 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 07:24:10 +00:00
Evan Cheng
57ebe9fbf0
Silly bug
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27719 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-15 05:37:34 +00:00
Evan Cheng
39fc145995
Do not use movs{h|l}dup for a shuffle with a single non-undef node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27718 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-15 03:13:24 +00:00
Evan Cheng
d953947d26
Last few SSE3 intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
Evan Cheng
f99898453d
X86 SSE2 supports v8i16 multiplication
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27644 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:10:25 +00:00
Evan Cheng
2c3ae37213
All "integer" logical ops (pand, por, pxor) are now promoted to v2i64.
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Clean up and fix various logical ops issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27633 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 21:21:57 +00:00
Evan Cheng
91b740da12
Promote v4i32, v8i16, v16i8 load to v2i64 load.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27612 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 17:12:36 +00:00
Evan Cheng
d6d1cbd692
Added support for _mm_move_ss and _mm_move_sd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27575 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 00:19:04 +00:00
Evan Cheng
f7c378e9ea
Conditional move of vector types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27556 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 07:23:14 +00:00
Evan Cheng
c5cdff2341
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27501 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-07 21:53:05 +00:00
Evan Cheng
5ced1d812e
- movlp{s|d} and movhp{s|d} support.
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- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27474 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-06 23:23:56 +00:00
Evan Cheng
6be2c58c8c
Support for comi / ucomi intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27444 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:38:46 +00:00
Evan Cheng
1d5a8cca00
Handle canonical form of e.g.
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vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 07:20:06 +00:00
Evan Cheng
865f0606f7
Bogus assert
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27434 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 06:11:20 +00:00
Evan Cheng
278158b487
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27433 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 06:09:26 +00:00
Evan Cheng
c21a053729
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27427 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 01:47:37 +00:00
Evan Cheng
20e3ed102b
Use movlpd to: store lower f64 extracted from v2f64.
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Use movhpd to: store upper f64 extracted from v2f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27382 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 22:30:54 +00:00
Evan Cheng
11e15b38e9
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
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- Some bug fixes and naming inconsistency fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27377 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 20:53:28 +00:00
Evan Cheng
653159f4aa
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
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INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:55:24 +00:00
Evan Cheng
b067a1e7e6
Add support to use pextrw and pinsrw to extract and insert a word element
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from a 128-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27304 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 19:22:53 +00:00
Evan Cheng
33e85ca7b6
Expand all INSERT_VECTOR_ELT (obviously bad) for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27275 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 01:30:39 +00:00
Evan Cheng
fb47a9b1c8
Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27272 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 00:33:57 +00:00
Evan Cheng
ef698ca30d
Ok for vector_shuffle mask to contain undef elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27271 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 00:30:29 +00:00
Evan Cheng
7d9061e300
Make sure all possible shuffles are matched.
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Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27259 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-30 19:54:57 +00:00
Evan Cheng
506d3dfa90
- Added some SSE2 128-bit packed integer ops.
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- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:07:14 +00:00
Evan Cheng
691c923e47
Need to special case splat after all. Make the second operand of splat
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vector_shuffle undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 19:02:40 +00:00
Evan Cheng
475aecf467
- More shuffle related bug fixes.
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- Whenever possible use ops of the right packed types for vector shuffles /
splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27246 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 03:04:49 +00:00
Evan Cheng
4f5633883b
- Only use pshufd for v4i32 vector shuffles.
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- Other shuffle related fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27244 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 01:30:51 +00:00
Evan Cheng
36b27f3cde
Fixing buggy code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27239 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 23:41:33 +00:00
Jim Laskey
2d2a6131da
Added missing paren on behalf of Ramana Radhakrishnan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27223 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 10:17:11 +00:00
Evan Cheng
ed4ca7f6c3
Missed X86::isUNPCKHMask
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27222 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 08:27:15 +00:00
Evan Cheng
2064a2b47e
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
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* Bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27218 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 06:50:32 +00:00
Evan Cheng
4fcb922c70
- Clean up / consoladate various shuffle masks.
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- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27210 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 02:43:26 +00:00
Evan Cheng
0038e59803
Model unpack lower and interleave as vector_shuffle so we can lower the
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intrinsics as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27200 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 00:39:58 +00:00
Evan Cheng
a0b3afbe14
Use pcmpeq to generate vector of all ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27167 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 07:00:16 +00:00
Nate Begeman
f15485a8d0
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 01:32:24 +00:00
Evan Cheng
ffea91e522
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 09:53:12 +00:00
Evan Cheng
c60bd97b94
Build arbitrary vector with more than 2 distinct scalar elements with a
...
series of unpack and interleave ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 09:37:23 +00:00
Evan Cheng
7b1d34bc6c
Added 128-bit packed integer subtraction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 01:33:37 +00:00
Evan Cheng
bc4832bc64
Support for scalar to vector with zero extension.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 23:15:12 +00:00
Evan Cheng
386031a06f
Handle BUILD_VECTOR with all zero elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:29:27 +00:00
Chris Lattner
9d5da1d96c
Gabor points out that we can't spell. :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:12:19 +00:00
Evan Cheng
5217a5b58c
All v2f64 shuffle cases can be handled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27044 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 06:40:32 +00:00
Evan Cheng
2c0dbd01d2
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 02:58:06 +00:00
Evan Cheng
14aed5e66b
Handle more shuffle cases with SHUFP* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 01:18:28 +00:00
Evan Cheng
8fc23cd0e9
Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26997 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 20:26:04 +00:00
Evan Cheng
a971f6f967
Add 128-bit integer vector load and add (for testing).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 01:57:24 +00:00
Evan Cheng
ca6e8eafd2
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
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64-bit vector shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 22:07:06 +00:00
Evan Cheng
a88973f826
Some clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26957 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 19:22:18 +00:00
Evan Cheng
1bffadd7fb
- Supposely movlhps is faster / better than unpcklpd.
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- Don't forget pshufd is only available with sse2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26956 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 19:16:21 +00:00
Evan Cheng
0188ecba85
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
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splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 18:59:22 +00:00
Evan Cheng
63d3300da1
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
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PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 08:01:21 +00:00
Chris Lattner
6df1154644
fix a warning
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26941 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 04:18:34 +00:00
Evan Cheng
b9df0ca67b
Some splat and shuffle support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 02:53:00 +00:00
Evan Cheng
48090aa814
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 23:01:21 +00:00
Chris Lattner
9b3bd467d0
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 20:51:05 +00:00
Chris Lattner
39afef3150
Add a build_vector node
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26895 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 06:18:01 +00:00
Chris Lattner
a064d28843
rename these nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 01:13:28 +00:00
Evan Cheng
df57fa0c7d
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26833 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 20:31:41 +00:00
Chris Lattner
89fad2c3b2
Disable x86 fastcc from passing args in registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26824 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 17:27:47 +00:00
Chris Lattner
1c636e9d98
Parameterize the number of integer arguments to pass in registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26818 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 05:10:20 +00:00
Nate Begeman
81e8097377
Remove BRTWOWAY*
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Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 01:40:33 +00:00
Evan Cheng
2221de9cc1
Bug fix: condition inverted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 22:02:48 +00:00
Evan Cheng
714554d707
Added a way for TargetLowering to specify what values can be used as the
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scale component of the target addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 21:47:42 +00:00
Evan Cheng
30b37b5f29
Add LSR hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 23:18:16 +00:00
Evan Cheng
ff909926e2
Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
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and variable value.
Similarly for memcpy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-07 23:29:39 +00:00
Evan Cheng
3c992d291b
Enable Dwarf debugging info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26581 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-07 02:02:57 +00:00
Chris Lattner
9601a86a64
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
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implement copysign as a native op if they have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 05:08:37 +00:00
Evan Cheng
62bec2ca4c
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
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rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26517 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 02:48:56 +00:00
Evan Cheng
8df346b4e8
Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26512 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 01:12:00 +00:00
Chris Lattner
41edaa0529
remove the read/write port/io intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 00:19:58 +00:00
Evan Cheng
d30bf01e90
Vector op lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:11:20 +00:00
Evan Cheng
bbbb2fbbde
Added a common about the need for X86ISD::Wrapper.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 09:55:19 +00:00
Evan Cheng
020d2e8e7a
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
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and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 20:41:18 +00:00
Evan Cheng
a0ea0539e3
PIC related bug fixes.
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1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 02:43:52 +00:00
Evan Cheng
4c1aa86657
- Added option -relocation-model to set relocation model. Valid values include static, pic,
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dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 20:19:42 +00:00
Evan Cheng
470a6adc78
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
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Fixed some existing bugs (wrong predicates, prefixes) at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 02:26:30 +00:00
Chris Lattner
1efa40f6a4
split register class handling from explicit physreg handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 00:56:39 +00:00
Chris Lattner
4217ca8dc1
Updates to match change of getRegForInlineAsmConstraint prototype
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 23:11:00 +00:00
Evan Cheng
45af8fd8c2
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
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advantage of fisttpll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26288 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 07:26:17 +00:00
Evan Cheng
7ccced634a
x86 / Darwin PIC support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 00:15:05 +00:00
Chris Lattner
c2fe97e726
unbreak the build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26260 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 07:09:27 +00:00
Evan Cheng
5298bcc722
Unbreak x86 be
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26259 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 07:01:52 +00:00
Nate Begeman
551bf3f800
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
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and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 05:43:56 +00:00
Nate Begeman
4c5dcf54ff
Kill the x86 pattern isel. boom.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 00:03:04 +00:00
Nate Begeman
368e18d56a
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 21:11:51 +00:00
Evan Cheng
18a8452f3d
A bit more memset / memcpy optimization.
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Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 00:21:07 +00:00
Evan Cheng
a03a5dc7ce
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:38:30 +00:00
Evan Cheng
87ed716d21
Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and
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maxStoresPerMemMove. Although the last one is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:25:08 +00:00
Chris Lattner
94dd29216c
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
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CALLSEQ_START nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26143 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-13 09:00:43 +00:00
Evan Cheng
2338c5cb0e
Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete.
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Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26038 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-07 08:38:37 +00:00
Evan Cheng
e3de85b447
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
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flag so it can be flagged to a FST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25953 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 02:20:30 +00:00
Evan Cheng
d25e9e8294
Fix a erroneous comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:28:23 +00:00
Nate Begeman
750ac1bdfa
Fix some of the stuff in the PPC README file, and clean up legalization
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of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25875 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 07:19:44 +00:00
Evan Cheng
760df29881
Return's chain should be matching either the chain produced by the
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value or the chain going into the load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25863 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 01:19:32 +00:00
Evan Cheng
0d084c9e4a
When folding a load into a return of SSE value, check the chain to
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ensure the memory location has not been clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25861 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 00:20:21 +00:00
Evan Cheng
0e8671bf4a
Be smarter about whether to store the SSE return value in memory. If
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it is already available in memory, do a fld directly from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25859 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 23:19:54 +00:00
Evan Cheng
223547ab31
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
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- Use XORP* to implement fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 22:28:30 +00:00
Chris Lattner
259e97cc72
* Fix 80-column violations
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* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 19:43:35 +00:00
Evan Cheng
ef6ffb17c7
Added custom lowering of fabs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25831 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 03:14:29 +00:00
Evan Cheng
6dfa999c01
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
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the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25824 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 23:41:35 +00:00
Evan Cheng
02568ff48d
i64 -> f32, f32 -> i64 and some clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25818 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 22:13:22 +00:00
Evan Cheng
6dab05363f
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
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conversions. SSE does not have instructions to handle these tasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 08:02:57 +00:00
Chris Lattner
c6fd6cd65c
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 04:09:27 +00:00
Chris Lattner
87c890a9c2
adjust prototype
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25798 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 03:49:07 +00:00
Chris Lattner
44d9b9bb86
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
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instead of lying and saying we have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25775 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:44:22 +00:00
Chris Lattner
a54aa94197
Targets all now request ConstantFP to be legalized into TargetConstantFP.
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'fpimm' in .td files is now TargetConstantFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:26:08 +00:00
Chris Lattner
6b2469c1ad
silence a warning
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25745 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 10:34:47 +00:00
Evan Cheng
8e44f0756f
Bye bye Pattern ISel, hello DAG ISel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25700 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 21:26:54 +00:00
Nate Begeman
ee625573b5
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 21:09:22 +00:00
Evan Cheng
559806f575
x86 CPU detection and proper subtarget support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 08:10:46 +00:00
Evan Cheng
9bba894596
When trying to fold X86::SETCC into a Select, make a copy if it has more than
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one use. This allows more CMOV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25634 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 02:13:10 +00:00
Nate Begeman
acc398c195
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 18:21:52 +00:00
Evan Cheng
0b2afbd58a
X86 prefer scheduling for reduced register pressure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25602 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 09:15:17 +00:00
Evan Cheng
0d718e9afc
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25596 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 09:05:09 +00:00
Chris Lattner
91cacc810b
use ESP directly, not a copy of ESP into some other register for fastcc calls
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25584 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-24 06:14:44 +00:00
Chris Lattner
af63bb03c5
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
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node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25580 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-24 05:17:12 +00:00
Chris Lattner
1f16ff6f0a
LowerReturn now doesn't have to handle f32 returns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25484 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-20 18:41:25 +00:00
Evan Cheng
dc8d2ab3e9
Avoid generating a redundant setcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25457 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-19 08:52:46 +00:00
Evan Cheng
b7b5706340
A obvious typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25435 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-19 01:46:14 +00:00
Evan Cheng
99fa0a102a
SRA shift amount must be in i8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25416 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-18 09:26:46 +00:00
Evan Cheng
68e5d084f1
If a call return type is i1, insert a truncate from X86::AL to i1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25415 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-18 08:08:38 +00:00
Evan Cheng
357c58efde
Fix lowering of calls which return f32 values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25413 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 21:58:21 +00:00
Evan Cheng
6892f28e99
SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom
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expand it), so ask legalizer to expand i32 UINT_TO_FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25386 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 02:32:49 +00:00
Evan Cheng
2059f884aa
Added a FIXME comment about why FST is currently flagged to fpGETRESULT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25381 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 00:37:42 +00:00
Evan Cheng
42ef0bc6fb
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
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read a flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 00:19:47 +00:00
Evan Cheng
0cc3945efe
Fix FP_TO_INT**_IN_MEM lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25368 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:21:29 +00:00
Chris Lattner
e112552b5a
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25333 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-15 09:00:21 +00:00
Nate Begeman
d88fc03602
bswap implementation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-14 03:14:10 +00:00
Evan Cheng
e90da97f3e
LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be
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flipped around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25290 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 19:51:46 +00:00
Chris Lattner
9edba7605e
Enable X86 support for savestack/restorestack
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25278 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 18:00:54 +00:00
Chris Lattner
b99329e8a0
expand unsupported stacksave/stackrestore nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25272 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 02:42:53 +00:00
Evan Cheng
80ebe38118
More typo's. I need new eye glasses...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25261 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 01:17:24 +00:00
Evan Cheng
189d01e8cc
Oops. Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25260 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 01:06:49 +00:00
Evan Cheng
1bcee3602e
Fix a SETCC / BRCOND folding bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25259 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 01:03:02 +00:00
Evan Cheng
a3195e8643
Fix sint_to_fp (fild*) support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25257 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 22:54:21 +00:00
Evan Cheng
5ee4ccce5b
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
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linked together).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 08:27:59 +00:00
Evan Cheng
002fe9baf2
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
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LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25246 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 07:56:47 +00:00
Evan Cheng
eb422a7234
Added ROTL and ROTR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 23:20:05 +00:00
Evan Cheng
67f92a7649
Support for MEMCPY and MEMSET.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25226 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 22:15:48 +00:00
Nate Begeman
35ef913ec2
Add bswap, rotl, and rotr nodes
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Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 21:21:00 +00:00
Evan Cheng
8700e14ba1
* Add special entry code main() (to set x87 to 64-bit precision).
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* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25207 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 06:09:51 +00:00
Evan Cheng
4a46080fe0
SSE cmov support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25190 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 00:33:36 +00:00
Evan Cheng
aaca22ca91
FP_TO_INT*_IN_MEM and x87 FP Select support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25188 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-10 20:26:56 +00:00
Evan Cheng
910cd3cfa2
More typos
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25162 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 22:29:54 +00:00
Evan Cheng
82a24b9813
typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25160 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 20:49:21 +00:00
Evan Cheng
e3413160ca
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25158 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 18:33:28 +00:00
Evan Cheng
d9558e0ba6
* Fast call support.
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* FP cmp, setcc, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25117 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-06 00:43:03 +00:00
Jim Laskey
e0bce71c42
Had expand logic backward.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25105 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-05 01:47:43 +00:00
Jim Laskey
abf6d1784b
Added initial support for DEBUG_LABEL allowing debug specific labels to be
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inserted in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-05 01:25:28 +00:00
Evan Cheng
d90eb7fb24
DAG based isel call support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-05 00:27:02 +00:00
Chris Lattner
f31d193cce
Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25024 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-27 03:02:18 +00:00
Evan Cheng
38bcbaf23e
More X86 floating point patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24990 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 07:31:11 +00:00
Chris Lattner
21f66859e4
make sure bit_convert's are expanded
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24979 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:15:23 +00:00
Evan Cheng
3a03ebb377
* Fix a GlobalAddress lowering bug.
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* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 23:05:39 +00:00
Jim Laskey
e81aecbae6
Disengage DEBUG_LOC from non-PPC targets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 20:51:37 +00:00
Evan Cheng
d5781fca4f
* Added support for X86 RET with an additional operand to specify number of
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bytes to pop off stack.
* Added support for X86 SETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24917 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 20:21:51 +00:00
Evan Cheng
b077b842b6
* Added lowering hook for external weak global address. It inserts a load
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for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 02:39:21 +00:00
Evan Cheng
7226158d7e
Added a hook to print out names of target specific DAG nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24877 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 06:22:03 +00:00
Evan Cheng
898101c15f
X86 conditional branch support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24870 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-19 23:12:38 +00:00
Evan Cheng
433dbdaa63
Remove a few lines of dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24768 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 07:18:44 +00:00
Evan Cheng
7df96d6672
X86 lowers SELECT to a cmp / test followed by a conditional move.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24754 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 01:21:05 +00:00
Evan Cheng
cb17bac3a3
* Promote all 1 bit entities to 8 bit.
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* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-15 19:49:23 +00:00
Chris Lattner
e80242a948
X86 doesn't support sextinreg for 8-bit things either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24631 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-07 17:59:14 +00:00
Chris Lattner
f73bae1b73
No targets support line number info yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 06:16:21 +00:00
Chris Lattner
81f803df80
Lower READCYCLECOUNTER correctly, preserving the chain result
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24438 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-20 22:57:19 +00:00
Chris Lattner
81363c3871
use chain operands to ensure the copies don't wander from the rdtsc instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24434 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-20 22:01:40 +00:00
Andrew Lenharth
b873ff322c
The second patch of X86 support for read cycle counter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24430 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-20 21:41:10 +00:00
Chris Lattner
dbdbf0ce2e
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch
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contributed by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24358 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-15 00:40:23 +00:00