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20861 Commits

Author SHA1 Message Date
Justin Holewinski
4c7ffb6a7e PTX: Continue to fix up the register mess. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:39:48 +00:00
Justin Holewinski
e37a83f66b PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:39:46 +00:00
Craig Topper
fe03315925 Add X86ISD::HADD/HSUB to getTargetNodeName 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:31:36 +00:00
Craig Topper
cb6bd11bd6 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:04:59 +00:00
Craig Topper
34671b812a Merge floating point and integer UNPCK X86ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 08:21:25 +00:00
Craig Topper
3d8c2ce3e4 Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:31:16 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
ff452f5349 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
2bcc789a9d Add register HWR29 numbering. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:36 +00:00
Bill Wendling
80caf9c273 Add a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:57:48 +00:00
Jim Grosbach
cb86509e7a Tidy up value checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
6482e91149 MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:48:32 +00:00
Chad Rosier
ed42c5f778 [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
8c741b8064 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:19 +00:00
Bill Wendling
79df986c60 The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:14 +00:00
Jim Grosbach
d9a6e8978d Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e80fba0e6c Use an existing function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:51:12 +00:00
Jim Grosbach
370b78d795 Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:47:03 +00:00
Jim Grosbach
f503ef6800 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 23:45:46 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6 Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:16:39 +00:00
Akira Hatanaka
d6bc5237d8 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:26:34 +00:00
Akira Hatanaka
cee46abc16 Split ExtIns into two base classes and have instructions EXT and INS derive from 
them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:14:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
2bf08ec854 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:03:03 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
422faab909 Fix previous commit. Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:12:26 +00:00
Jim Grosbach
45755a77ec Tidy up. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:09:44 +00:00
Jim Grosbach
afb500ace1 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 19:55:46 +00:00
Hal Finkel
3fd0018af1 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:17 +00:00
Hal Finkel
9489487f98 don't include CR bit subregs in callee-saved list 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:12 +00:00
Hal Finkel
2e313caa36 add register pressure for CR regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:54:17 +00:00
Craig Topper
1dc0fbc168 Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 07:27:14 +00:00
Craig Topper
beabc6cc6d Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 06:56:46 +00:00
Bob Wilson
6ce2deacef Fix 80-column issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov
0cb2a45cce Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
80b1ae9292 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 21:24:48 +00:00
Sanjoy Das
199ce33b3b Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:32:07 +00:00
Sanjoy Das
40f8222e1e Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:21:07 +00:00
Nick Lewycky
3604924799 Creating multiple JITs on X86 in multiple threads causes multiple writes (of 
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 02:45:50 +00:00
Chad Rosier
9eff1e33f6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 02:21:57 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 23:34:39 +00:00
Jim Grosbach
e40ab244c1 ARM VEXT tighten up operand classes a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:57:57 +00:00
Jim Grosbach
84defb51ca ARM VST1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:34:51 +00:00
Nick Lewycky
8a8d479214 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:16:29 +00:00
Jim Grosbach
872eedbb3a ARM VLD1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:52 +00:00
Jim Grosbach
204aa64f30 ARM encoder method needs the physical register number, not the enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:25 +00:00
Chad Rosier
b74c865841 [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 20:25:18 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Jan Sjödin
ce25d26b40 Add XOP feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 15:14:37 +00:00
Craig Topper
f8363305eb Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145681 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 08:18:41 +00:00
Craig Topper
138a5c66b9 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 07:16:01 +00:00
Hal Finkel
826941a0af remove unneeded FIXME comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:17 +00:00
Hal Finkel
64c34e2535 update PPC 940 hazard rec. to function in postRA mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:02 +00:00
Jim Grosbach
7636bf6530 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 00:35:16 +00:00
Sanjoy Das
fc9261279a Dummy commit to check commit access. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 19:15:08 +00:00
Chad Rosier
fbd828d8e1 Add missing functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:26:19 +00:00
Chad Rosier
32b6c59ad0 Add a few more functions to TargetLibraryInfo. More of rdar://10500969. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 17:54:37 +00:00
Eric Christopher
7d5a61e975 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 08:12:41 +00:00
Eli Friedman
522fb8cc01 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 04:49:21 +00:00
Eli Friedman
32e698cc10 Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 01:43:47 +00:00
Jan Sjödin
dd649e35e5 Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 22:09:42 +00:00
Matt Beaumont-Gay
7b8e121520 Remove unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:53:11 +00:00
Jim Grosbach
096334e25e ARM parsing for VLD1 all lanes, with writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:35:44 +00:00
Chad Rosier
8ff4115ef0 Add a few functions to TargetLibraryInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145508 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:19:00 +00:00
Jim Grosbach
13af222bab ARM parsing for VLD1 two register all lanes, no writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 18:21:25 +00:00
Benjamin Kramer
5f794df76e X86: Turns out bulldozer also supports sse42 and lzcnt. 
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 15:48:16 +00:00
Benjamin Kramer
2a6cf70650 X86: Add subtargets for AMD's bulldozer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145493 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 15:27:46 +00:00
Nadav Rotem
18197d7425 X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 10:13:37 +00:00
Craig Topper
b72039cf52 Add instruction selection support for AVX2 horizontal add/sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145487 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 09:10:50 +00:00
Craig Topper
ec24e61ab0 Merge VPERM2F128/VPERM2I128 ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 07:47:51 +00:00
Craig Topper
316cd2a2c5 Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 06:25:25 +00:00
Chad Rosier
683e47b1dd Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional 
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:51:49 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:09:44 +00:00
Chad Rosier
3d925d24e8 Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable 
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145460 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:57:10 +00:00
Jim Grosbach
6029b6ddaf Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:51:09 +00:00
Jim Grosbach
bd1cff5b2c Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:33:40 +00:00
Jim Grosbach
1ec7bf0c0d ARM parsing aliases for data-size suffices on VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:21:31 +00:00
Akira Hatanaka
ed2a7d2780 Change names for MIPS "generic" processors defined in Mips.td to match what GNU 
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:08:41 +00:00
Jim Grosbach
4c7edb3ad8 ARM assembly parsing and encoding for four-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:58:48 +00:00
Evan Cheng
a3438cf48b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:48:34 +00:00
Jim Grosbach
d5ca201891 ARM assembly parsing and encoding for three-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen
0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:27:25 +00:00
Andrew Trick
7d8867d453 comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:33:49 +00:00
Daniel Dunbar
d782bae970 build/CMake: Finish removal of add_llvm_library_dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:25:30 +00:00
Michael J. Spencer
116bc795da MC/X86/COFF: Allow quotes in names when targeting MS/Windows, 
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 18:00:06 +00:00
Elena Demikhovsky
f68b214e2d Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 15:00:45 +00:00
Craig Topper
f267972d28 Fix shuffle decoding for memory forms for (V)SHUFPS/D. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 07:58:09 +00:00
Craig Topper
36e36ace77 Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 07:49:05 +00:00
Craig Topper
fe2a6c584a Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 05:37:58 +00:00
Craig Topper
108126cfc6 Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 03:57:34 +00:00
Jim Grosbach
6200611dff Better fix for ARM MOVT relocation encoding of thumb bit. 
Replaces r145318 with a more targetted fix for the relocation handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145346 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 01:15:25 +00:00
Evan Cheng
678cda052c Add missing avx pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 20:27:23 +00:00
Duncan Sands
4c0c5451c7 Silence wrong warnings from GCC about variables possibly being used 
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145239 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 10:31:27 +00:00
Craig Topper
70b883b3a7 Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 10:14:51 +00:00
Craig Topper
71c4c12232 Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 01:14:24 +00:00
Craig Topper
9d7025b56b Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 21:41:12 +00:00
Wesley Peck
4c729f1152 Add several new instructions supported by the latest MicroBlaze. 
These instructions are not generated by the backend yet, this will come in a later commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 05:16:58 +00:00
Wesley Peck
a0aa45c759 Optimize comparison against 0 in conditional instructions. 
Fix a couple of 80-column violations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-27 01:36:20 +00:00
Benjamin Kramer
0861f5793a Move code into anonymous namespaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 23:01:57 +00:00
Craig Topper
38034c568c Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 22:55:48 +00:00
Wesley Peck
a18f08318a Rename a couple of options and fix some simple typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 21:50:38 +00:00
Craig Topper
06cb680779 Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-26 20:47:44 +00:00
Bruno Cardoso Lopes
1b9b377975 This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-25 19:33:42 +00:00
NAKAMURA Takumi
70aaf37c11 ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-25 09:19:57 +00:00
Craig Topper
705f2431a0 Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 22:57:10 +00:00
Craig Topper
f475a55bd4 Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 22:20:08 +00:00
Benjamin Kramer
9d399b1fc2 X86: alias cqo to cqto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-24 12:02:46 +00:00
Akira Hatanaka
421455f1ea This patch makes the following changes necessary for MIPS' direct code emission. 
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 22:19:28 +00:00
Akira Hatanaka
84bfc2f090 This patch addresses gp relative fixups/relocations for jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 22:18:04 +00:00
Benjamin Kramer
f238f50aaf X86: Use btq for bit tests if the immediate can't be encoded in 32 bits. 
Before:
	movabsq	$4294967296, %rax       ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
	testq	%rax, %rdi              ## encoding: [0x48,0x85,0xf8]
	jne	LBB0_2                  ## encoding: [0x75,A]

After:
	btq	$32, %rdi               ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
	jb	LBB0_2                  ## encoding: [0x72,A]

btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 13:54:17 +00:00
Elena Demikhovsky
52a35a89e6 I added several lines in X86 code generator that allow to choose 
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.

The patch was reviewed by Bruno.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 10:23:16 +00:00
Jakob Stoklund Olesen
7f5e43f61d Fix PR11422. 
This was a bug in keeping track of the available domains when merging
domain values.

The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.

Also add an assertion to catch future attempts at emitting AVX2
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 04:03:08 +00:00
Hal Finkel
768c65f677 add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 16:21:04 +00:00
Craig Topper
796c193768 More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 14:27:57 +00:00
Craig Topper
f7de577a08 Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 01:57:35 +00:00
Craig Topper
c0d82857e0 Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-22 00:44:41 +00:00
Craig Topper
6fa583d787 Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 08:26:50 +00:00
Craig Topper
6347e8662c Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 06:57:39 +00:00
Craig Topper
a124f94952 Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-21 01:12:36 +00:00
Craig Topper
0d86d462f8 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-20 00:12:05 +00:00
Craig Topper
745a86bac9 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 22:34:59 +00:00
Craig Topper
ba798c5e51 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 21:01:54 +00:00
Craig Topper
98fc72940b Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 17:46:46 +00:00
Craig Topper
54f952afac Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 09:02:40 +00:00
Craig Topper
3113384a34 Collapse X86 PSIGNB/PSIGNW/PSIGND node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 07:33:10 +00:00
Craig Topper
1666cb6d63 Extend VPBLENDVB and VPSIGN lowering to work for AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 07:07:26 +00:00
Craig Topper
60d9a9206e Remove unused parameters from the AVX maskmov classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144985 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 04:49:22 +00:00
Nadav Rotem
cbbe33fde4 Add AVX2 vpbroadcast support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-18 02:49:55 +00:00
Chad Rosier
424fe0e422 Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-18 01:17:34 +00:00
Chad Rosier
944d82ba06 Add TODO comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 21:46:13 +00:00
Craig Topper
d90a191685 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 07:49:38 +00:00
Chad Rosier
2fb82ce75d Dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 07:24:49 +00:00
Craig Topper
ec43d1f553 Remove seemingly unnecessary duplicate VROUND definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 07:04:00 +00:00
Eli Friedman
9d434dbff3 Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom 
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 01:27:36 +00:00
Chad Rosier
3bdb3c9b51 Don't unconditionally set the kill flag. 
rdar://10456186


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 01:16:53 +00:00
Eli Friedman
d224c7879a Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144867 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 00:21:52 +00:00
Jim Grosbach
2abba8496c Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:48:37 +00:00
Akira Hatanaka
620db8947a Lower 64-bit constant pool node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144849 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:44:38 +00:00
Akira Hatanaka
9b944a8da2 Lower 64-bit block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144847 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:42:10 +00:00
Jim Grosbach
b84acd2468 Fix encoding of NOP used for padding in ARM mode .align. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:40:25 +00:00
Akira Hatanaka
74c76347d3 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool 
nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:39:56 +00:00
Akira Hatanaka
4fd40b3604 64-bit jump register instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:36:01 +00:00
Evan Cheng
2b89498979 Another missing X86ISD::MOVLPD pattern. rdar://10450317 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 22:24:44 +00:00
Jim Grosbach
40a86ee20f ARM assembly parsing for shifted register operands for MOV instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 21:50:05 +00:00
Jim Grosbach
efed3d1f58 Clean up debug printing of ARM shifted operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 21:46:50 +00:00
Jim Grosbach
b598b04409 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 19:12:24 +00:00
Jim Grosbach
48b368bcd5 ARM assembly parsing for RRX mnemonic. 
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 19:05:59 +00:00
Pete Cooper
cd75e44173 Added missing comment about new custom lowering of DEC64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 19:03:23 +00:00
Chad Rosier
508a1f4db1 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 18:39:44 +00:00
Jim Grosbach
23f220705a ARM mode aliases for bitwise instructions w/ register operands. 
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 18:31:45 +00:00
Bob Wilson
d0405aaabc Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
5c283e98c9 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 09:18:28 +00:00
Evan Cheng
b95fc31aa2 Sink codegen optimization level into MCCodeGenInfo along side relocation model 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 08:38:26 +00:00
Craig Topper
12755b07ab Fix the execution domain on a bunch of SSE/AVX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144784 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 07:30:46 +00:00
Bob Wilson
eaab6ef6eb Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> 
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 07:11:57 +00:00
Craig Topper
2713d045e3 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144777 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 05:02:04 +00:00
Chad Rosier
f56c60b571 Add FIXME comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen
3805d85e38 Enable -widen-vmovs by default. 
This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 23:53:18 +00:00
Jim Grosbach
e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 23:19:15 +00:00
Jim Grosbach
5b2fb2083c ARM assembly parsing for data type suffices on NEON VMOV aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:54:42 +00:00
Nadav Rotem
f8c10e5cb1 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144720 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:50:37 +00:00
Jim Grosbach
9f302c4fb3 ARM assembly parsing two operand forms for shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:27:54 +00:00
Jim Grosbach
88d012a9c3 ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:15:10 +00:00
Jim Grosbach
6cb4b08182 ARM accept an immediate offset in memory operands w/o the '#'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:14:41 +00:00
Pete Cooper
2d49689793 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used 
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:57:53 +00:00
Jim Grosbach
5c984e451d ARM enclosing curly braces optional on one-register VLD/VST instruction lists. 
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:45:55 +00:00
Jim Grosbach
eaf2056709 ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:18:35 +00:00
Jim Grosbach
25e0a87e91 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:01:30 +00:00
Jim Grosbach
19885de61d ARM alternate size suffices for VTRN instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:49:46 +00:00
Owen Anderson
22925d93e9 Fix a misplaced paren bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:30:41 +00:00
Jim Grosbach
a68e90c36e ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06 ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:02:06 +00:00
Jim Grosbach
7f1ec9570d Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:16 +00:00
Owen Anderson
b589be9334 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:00 +00:00
Jim Grosbach
1de0bd1945 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:29:45 +00:00
Akira Hatanaka
1b71950812 Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit 
registers and instructions when ABI is N64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 18:53:55 +00:00
Akira Hatanaka
ac20aad81c Set nomacro before emitting the sequence of instructions that set global pointer 
register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 18:44:44 +00:00
Akira Hatanaka
160408546c Simplify function PassByValArg64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 18:42:25 +00:00
Akira Hatanaka
870b3b2dd4 Delete files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 18:22:48 +00:00
Akira Hatanaka
73c38f0aa2 Remove MipsMCSymbolRefExpr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 18:20:08 +00:00
Jim Grosbach
c5a6a687fd ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 17:49:59 +00:00
Jay Foad
bf8356b37c Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 07:50:05 +00:00
Jay Foad
978e0dfe46 Make use of MachinePointerInfo::getFixedStack. This removes all mention 
of PseudoSourceValue from lib/Target/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 07:34:52 +00:00
Jay Foad
d9190c0f14 Remove some unnecessary includes of PseudoSourceValue.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 07:24:32 +00:00
Craig Topper
44ec9fddc2 Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 06:39:01 +00:00
Craig Topper
4c077a1f04 Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 05:55:35 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:46:57 +00:00
Jakob Stoklund Olesen
c2ecf3efbf Break false dependencies before partial register updates. 
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:15:30 +00:00
Jim Grosbach
dd47e0b5d4 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:32:59 +00:00
Jim Grosbach
04db7f7a7d Add explanatory comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:21:09 +00:00
Jim Grosbach
0530d0d5d9 Split out the plain '.{8|16|32|64}' suffix handling. 
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:20:14 +00:00
Jim Grosbach
ef448767a3 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:11:19 +00:00
Chad Rosier
2c42b8c912 Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:04:09 +00:00
Jim Grosbach
ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Chad Rosier
909cb4f2f2 Add support for inlining small memcpys. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:34:48 +00:00
Jim Grosbach
02e3d9268f ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:28:39 +00:00
Evan Cheng
76c8f08567 Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:35:52 +00:00
Chad Rosier
57b2997966 Add support for Thumb load/stores with negative offsets. 
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 20:22:27 +00:00
Benjamin Kramer
6296ee3ee2 Unbreak Release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:51:48 +00:00
Pete Cooper
a77214a4c4 Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered 
Constant idx case is still done in tablegen but other cases are then expanded

Fixes <rdar://problem/10435460>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:38:42 +00:00
Akira Hatanaka
788dc0f4e5 32-to-64-bit extended load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144554 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:06:14 +00:00
Akira Hatanaka
4961709688 AnalyzeCallOperands function for N32/64. 
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:02:54 +00:00
Akira Hatanaka
bad53f41c2 Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 19:01:09 +00:00
Justin Holewinski
a3f7e229b6 PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 18:58:20 +00:00
Akira Hatanaka
47a4ab84fe Remove variable that keeps the size of area used to save byval or variable 
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144549 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 18:56:20 +00:00
Jim Grosbach
430052b084 Tidy up. 80 column. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 17:52:47 +00:00
Craig Topper
dcce244dd8 Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 08:07:55 +00:00
Craig Topper
3426a3efef Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 06:46:21 +00:00
Chad Rosier
dc9205d9c2 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 04:09:28 +00:00
Craig Topper
e6a6277d36 Add BLSI, BLSMSK, and BLSR to getTargetNodeName. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 17:31:07 +00:00
Chad Rosier
9eb674880b The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 04:25:02 +00:00
Chad Rosier
b29b950bf2 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-13 02:23:59 +00:00
Craig Topper
7be5dfd1a1 Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 09:58:49 +00:00
Akira Hatanaka
7386612a16 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144453 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:38:12 +00:00
Akira Hatanaka
6df3e7b162 Implement Mips64's handling of byval arguments in LowerCall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:34:50 +00:00
Akira Hatanaka
3a5257de21 Implement Mips64's handling of byval arguments in LowerFormalArguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144449 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:29:58 +00:00
Akira Hatanaka
deab22a556 64-bit arbitrary immediate pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:25:00 +00:00
Akira Hatanaka
2c5d65202e Function for handling byval arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144447 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:20:46 +00:00
Daniel Dunbar
b8ebca83f4 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:10:57 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:58:43 +00:00
Jim Grosbach
742c4bac07 Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:31:53 +00:00
Jim Grosbach
4d06138d53 Oops. Missed the isel half of this. revert while I sort that out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:51:31 +00:00
Jim Grosbach
10a630dea6 ARM assembly parsing for VST1 two-register encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:45:47 +00:00
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2 Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:31:03 +00:00
Daniel Dunbar
b12f97534c CMake: Fix CMake build for new Mips tblgen file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144423 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:12:56 +00:00
Jim Grosbach
7aef99b677 ARM vldm and vstm VFP instructions can take a data type suffix. 
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:08:10 +00:00
Daniel Dunbar
f779757ceb Target/LLVMBuild: Order components alphabetically. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:59:16 +00:00
Bruno Cardoso Lopes
47b92f3d83 Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:58:42 +00:00
Jim Grosbach
c3937b97c0 Nuke no longer accurate comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:30:06 +00:00
Andrew Trick
95bc85e4ee Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:18:09 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Dan Bailey
96e6458903 allow non-device function calls in PTX when natively handling device-side printf 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144388 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 14:45:12 +00:00
Dan Bailey
b812ee6d78 add rules in tabgen for PTX COPY_ADDRESS of frameindex 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 14:45:06 +00:00
Benjamin Kramer
eea66f63d9 Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 12:39:41 +00:00
Benjamin Kramer
7fb12ef5a6 Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 12:39:35 +00:00
Craig Topper
46154eb6fd Add lowering for AVX2 shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 07:39:23 +00:00
Chad Rosier
1c47de87c7 Rename variables to avoid confusion. No functionallity change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 06:27:41 +00:00
Chad Rosier
a07d3fc693 Add support for using immediates with select instructions. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 06:20:39 +00:00
Akira Hatanaka
e184fec550 Do not try to detect DAG combine patterns for integer multiply-add/sub if value 
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 04:18:21 +00:00
Akira Hatanaka
59068067cb 64-bit atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 04:14:30 +00:00
Akira Hatanaka
46ac4399b1 Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 04:11:56 +00:00
Akira Hatanaka
c742e4fc90 Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 04:06:38 +00:00
Akira Hatanaka
642b109713 64-bit versions of jal, jalr and bal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 04:03:54 +00:00
Akira Hatanaka
a1fa08f66a Emit Mips64's sequence of instructions that set global register in prologue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 04:00:29 +00:00
Akira Hatanaka
d5cf5a631f Fix printing of MCSymbolRegExpr. Needs three closing parentheses for 
VK_Mips_GPOFF_HI/LO.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 03:58:36 +00:00
Eli Friedman
15f58c56e9 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 03:16:38 +00:00
Chad Rosier
646abbfa30 When loading a value, treat an i1 as an i8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 02:38:59 +00:00
Bill Wendling
c739577d3c If we have to reset the calculation of the compact encoding, then also reset the 
"saved register" index.
<rdar://problem/10430076>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144350 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:59:14 +00:00
Chad Rosier
4e89d97e3a Add support for using MVN to materialize negative constants. 
rdar://10412592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:36:21 +00:00
Daniel Dunbar
5ed5506f18 LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:23:56 +00:00
Jim Grosbach
0352b4679e Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. 
rdar://10429490

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:58:34 +00:00
Jim Grosbach
83ec87755e ARM let processInstruction() tranforms chain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:42:14 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Jim Grosbach
fae02597bb Thumb1 diagnostics for reglist on PUSH/POP fix. 
Was not checking the first register in the register list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:01:27 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Daniel Dunbar
eaf4221cef build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler 
that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:00:37 +00:00
Chad Rosier
16455ce1a4 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 21:09:49 +00:00
Jim Grosbach
d475f8612b ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 20:48:53 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
Daniel Dunbar
977665c24a build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for 
consistency with other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 15:35:14 +00:00
Nadav Rotem
4dbe96e22f AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 06:54:20 +00:00
Chad Rosier
6cba97c555 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 01:30:39 +00:00
Daniel Dunbar
8333730259 build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 01:16:48 +00:00
Daniel Dunbar
affc6cf9d2 llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:50:07 +00:00
Daniel Dunbar
6852b69e15 llvm-build: Change CBackend and CppBackend to not use library_name. This will 
change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:49:55 +00:00
Daniel Dunbar
c352caf168 llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:49:51 +00:00
Jim Grosbach
c27f6725b9 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:02:33 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Eli Friedman
14e809c872 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:36:02 +00:00
Chad Rosier
7346347674 The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:30:12 +00:00
Nadav Rotem
c6c7e85a71 AVX2: Add patterns for variable shift operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:22:13 +00:00
Devang Patel
f4e0d5d83d Remove unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:11:02 +00:00
Nadav Rotem
bb539bf973 Add AVX2 support for vselect of v32i8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 13:21:28 +00:00
Craig Topper
b80ada98c5 Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 09:37:21 +00:00
Craig Topper
0a15035f52 Add instruction selection for AVX2 integer comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 08:06:13 +00:00
Craig Topper
aaa643c70e Add AVX2 instruction lowering for add, sub, and mul. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 07:28:55 +00:00
Chad Rosier
2f2fe417f9 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 03:22:02 +00:00
Evan Cheng
44ee4714a8 Hide cpu name checking in ARMSubtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 01:57:03 +00:00
Bruno Cardoso Lopes
ce1a538ab5 Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 22:26:47 +00:00
Evan Cheng
3568a1051e Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:21:09 +00:00
Chad Rosier
66dc8ca04b ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:12:00 +00:00
Lang Hames
5207bf2177 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:56:23 +00:00
Pete Cooper
d752e0f7e6 Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:42:53 +00:00
Bruno Cardoso Lopes
ad6eef4a65 This patch handles unaligned loads and stores in Mips JIT. Mips backend 
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).

Patch by Petar Jovanovic and Sasa Stankovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 12:47:11 +00:00
NAKAMURA Takumi
0839033cbc PPCInstrInfo.cpp: Fix one "unused" warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 04:00:07 +00:00
Eli Friedman
9f1f26aefa Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 01:43:53 +00:00
Evan Cheng
7bc389b6b0 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:31:58 +00:00