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Author SHA1 Message Date
Evan Cheng
eed0ff147c Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77967 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 08:41:59 +00:00
Anton Korobeynikov
cf6b739d3d Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 08:12:53 +00:00
Rafael Espindola
8d632c1e98 Use movd instead of movq 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77956 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 05:21:05 +00:00
Daniel Dunbar
3c2d4bf97f Pass target triple string in to TargetMachine constructor. 
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.

This has one important change in the way behavior of the JIT and llc.

For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.

For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.

The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77946 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 04:03:51 +00:00
Rafael Espindola
def390a30a Use movq to move 64 bits in and out of mmx registers. 
Fixes PR4669



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 02:45:34 +00:00
Evan Cheng
a8e8984ee4 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 02:38:06 +00:00
Richard Osborne
d558ea5e0a Add extra SEXT pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 22:45:24 +00:00
Jakob Stoklund Olesen
1391cc19d0 Remove unneeded intrinsics from Blackfin backend. 
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.

__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.

We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 21:49:05 +00:00
Jakob Stoklund Olesen
b36eb9df20 Fix issue in regscavenger when scavenging a callee-saved register that has not been spilled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77912 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 20:29:41 +00:00
Jakob Stoklund Olesen
ece4818516 Never add a kill flag to a constrained physical register in a two-addr instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77906 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 19:13:03 +00:00
Jakob Stoklund Olesen
0e6a4efdd4 Scavenger asserts. 
Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 18:28:41 +00:00
Jakob Stoklund Olesen
6b30f5c867 Add some basic blackfin intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77903 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 18:28:11 +00:00
Jakob Stoklund Olesen
63cc527fbc Inline assembly support for Blackfin. 
We use the same constraints as GCC, including those that are slightly insane for inline assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77899 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 17:39:17 +00:00
Jakob Stoklund Olesen
d950941e13 Analog Devices Blackfin back-end. 
Generate code for the Blackfin family of DSPs from Analog Devices:

  http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
  
We aim to be compatible with the exsisting GNU toolchain found at:

  http://blackfin.uclinux.org/gf/project/toolchain
  
The back-end is experimental.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 17:32:10 +00:00
Evan Cheng
b9bcdd9ca4 Test both darwin and linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 02:54:34 +00:00
Chris Lattner
f9f1adbcbb switch to filecheck format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77841 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 00:32:26 +00:00
Chris Lattner
c19ee610f6 fix a problem Eli noticed where we would compile the attached ptrtoint 
to:

.quad X

even on a 32-bit system, where X is not 64-bits.  There isn't much that
we can do here, so we just print:

.quad	((X) & 4294967295)

instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77818 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 22:25:12 +00:00
Dan Gohman
5f9b69f345 Add nounwind to this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77792 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 19:11:04 +00:00
Eli Friedman
f67e84edef Hack to make this test work on platforms which aren't Macs. Fixing this 
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 16:37:18 +00:00
Evan Cheng
25f7cfc3cc Workaround a couple of Darwin assembler bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 06:13:52 +00:00
Evan Cheng
13f8b36205 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 01:43:45 +00:00
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:16:10 +00:00
David Greene
bef8768bd0 Simplify operand padding by keying off tabs in the asm stream. If 
padding is disabled, tabs get replaced by spaces except in the case of
the first operand, where the tab is output to line up the operands after
the mnemonics.

Add some better comments and eliminate redundant code.

Fix some testcases to not assume tabs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77740 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 21:57:10 +00:00
Chris Lattner
a87dea4f8c switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:48:30 +00:00
Evan Cheng
ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:35:56 +00:00
Chris Lattner
82987bfe9b fix PR4650: we only track sizes for certain objects, so only put something 
into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77679 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 16:17:13 +00:00
Evan Cheng
ee42fd309e When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 23:29:25 +00:00
David Goodwin
8f65253236 Darwin assembler now recognizes "orn", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:51:41 +00:00
David Goodwin
7c92f3ac99 Darwin assembler now supports "rrx", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:38:40 +00:00
David Goodwin
d8c95b5ac2 Cleanup and include code selection for some frame index cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 18:56:48 +00:00
Evan Cheng
37b7387da9 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 08:33:02 +00:00
Dan Gohman
a4714e025d Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 01:56:29 +00:00
Evan Cheng
8770f747a9 tbb / tbh instructions only branch forward, not backwards. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:20:20 +00:00
Evan Cheng
d600522608 Add VFP3 D registers to the DPR register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:03:41 +00:00
Bob Wilson
b7d0c90c44 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 16:39:22 +00:00
Chris Lattner
b8f396bdbb fix PR4584 with a trivial patch now that the pieces are in place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 05:20:33 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 02:18:14 +00:00
Eric Christopher
c841fe5fd1 Add a couple more tests for the ptest intrinsics to make sure we're 
grabbing them all correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:51:15 +00:00
Eric Christopher
71c6753d03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:28:05 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
David Goodwin
6340632d3b Remove support for ORN to workaround <rdar://problem/7096522>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:51:25 +00:00
David Goodwin
5743854f47 Add workaround for <rdar://problem/7098328>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:15:38 +00:00
Chris Lattner
3e23d42dee fix testcase for previous patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77338 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:04:18 +00:00
Chris Lattner
bf15e433b9 Fix PR4639, a ELF-TLS regression from some of my refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:57:51 +00:00
David Goodwin
3583df7676 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:06:49 +00:00
Evan Cheng
bae20a6353 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 07:38:35 +00:00
Evan Cheng
6495f63945 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 05:48:47 +00:00
David Goodwin
1f0962756d ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 23:34:12 +00:00
David Goodwin
af0d08d55c Add ".w" suffix for wide thumb-2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:31:55 +00:00
Sanjiv Gupta
c3ee7960d9 Test case to check that separate section is created for a global variable specified with section attribute. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77195 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:20:41 +00:00
Chris Lattner
a759135168 update testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 15:52:58 +00:00
Chris Lattner
abb477f663 put normal data into .data instead of .data.rel on elf systems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77116 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 03:06:11 +00:00
Chris Lattner
30c4a3b9a8 finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal 
for now.  Make the section switching directives more consistent
by not including \n and including \t for them all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 01:24:18 +00:00
Chris Lattner
e3577da6d9 simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit 
and make it more aggressive, we now put:

const int G2 __attribute__((weak)) = 42;

into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:51:36 +00:00
Bob Wilson
8bb9e48752 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:39:34 +00:00
Chris Lattner
10cf6a6a4b add the most expedient hack to fix PR4619, along with a testcase. 
Thanks to Rafael for the great example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77083 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 17:57:37 +00:00
Evan Cheng
b140f4907c I've lost my mind. PR4572 has not been fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77031 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 01:11:46 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Evan Cheng
b2fa93dc1c Remove a duplicated test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77020 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:24:40 +00:00
Evan Cheng
caca2b659f Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 22:42:45 +00:00
Evan Cheng
0bc116192d Fix these tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 22:42:22 +00:00
Eric Christopher
a1a491c094 Move insertps tests to sse41 combo test file, convert to filecheck 
format and add an extract/insert test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 19:24:26 +00:00
Evan Cheng
f631a68cf8 Convert a test to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 06:01:46 +00:00
Chris Lattner
013e6b6309 Remove SectionKind::Small*. This was only used on mips, and is apparently 
a sad mistake that is regretted. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 03:11:51 +00:00
Richard Osborne
e23e0976c7 Add tests for handling of globals and tls on the XCore. These currently fail 
but pass when run against r76652.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:38:20 +00:00
Dan Gohman
d2cb3d2c32 Remove the IA-64 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:30:09 +00:00
Evan Cheng
eee839dd3c Thumb2 does not allow the use of "pc" register as part of the load / store address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 23:09:51 +00:00
Evan Cheng
d3d9d66dd2 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 18:27:47 +00:00
Chris Lattner
d58fb250bb merge one more sse41 test into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76853 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:49:39 +00:00
Chris Lattner
052876957c merge another sse41 test into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:43:48 +00:00
Chris Lattner
ca6883b007 merge sse41-pmovx.ll into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:39:09 +00:00
Chris Lattner
5fe2b03779 change a test to run in filecheck style. Rename it to be a general 
dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file.  Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the 
reg and mem forms of these instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:33:02 +00:00
Eric Christopher
1e5cdea9d7 Support insertps via the intrinsic and add a couple of simple 
testcases to make sure it's being generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 02:22:41 +00:00
Eric Christopher
3091719b90 Add test for pinsrd and pinsrb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76840 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 01:58:04 +00:00
Dan Gohman
608ad24ac3 Revert r75663 (and r76805), as it is causing regressions on powerpc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76823 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 00:09:46 +00:00
Dan Gohman
41d0b9d952 x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76817 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 23:26:55 +00:00
Dan Gohman
1c88efff02 Add -march=ppc32 lines so that this test doesn't ever default to ppc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76805 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:08:31 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Dan Gohman
784025039f Make the grep line in this test more specific, to avoid 
unintended matches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76802 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:02:42 +00:00
Evan Cheng
1e0c1588b1 Ignore undef uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76799 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 21:51:42 +00:00
Duncan Sands
ed4b2dc313 Revert commit 76707, it was breaking the llvm-gcc build 
on linux platforms.  The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 10:35:05 +00:00
Chris Lattner
828f704c10 set the ELF "small" flag on objects that end up in .rodata.cst4 consistently, 
updating a mips testcase to expect it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76707 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 00:41:56 +00:00
Evan Cheng
47b1e2afd0 Remove a big test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76669 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 22:52:04 +00:00
Evan Cheng
3ecadc816d Do not select tSXTB / tSXTH in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 18:15:26 +00:00
Chris Lattner
74625023a8 convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76591 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 17:36:24 +00:00
Chris Lattner
99bd8bf8a2 add a testcase for the pic16 section handling stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 16:48:20 +00:00
Evan Cheng
5d885023fe Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 09:15:00 +00:00
Chris Lattner
634d61b135 remove a very large testcase for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76537 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 06:28:36 +00:00
Evan Cheng
d101a72d79 Fix a dagga combiner bug: avoid creating illegal constant. 
Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76535 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 05:40:15 +00:00
Evan Cheng
af9e7a7c20 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:31:12 +00:00
Evan Cheng
c95be59371 Cross RC coalescing is now on by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:22:59 +00:00
David Greene
76081c4ef7 Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes 
next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 22:02:59 +00:00
Evan Cheng
87faa1fc67 Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:46:42 +00:00
Evan Cheng
33d0474bf5 Use TII->findCommutedOpIndices to find the commute operands (rather than guessing). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76472 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:16:08 +00:00
Evan Cheng
753480ad20 Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76458 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 19:47:55 +00:00
Dan Gohman
f241174421 Revert the addition of hasNoPointerOverflow to GEPOperator. 
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.

Remove a few optimizations that depended on this flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76437 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 17:43:30 +00:00
Chris Lattner
401e10c4fb implement a new magic global "llvm.compiler.used" which is like llvm.used, but 
doesn't cause ".no_dead_strip" to be emitted on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76399 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:14:25 +00:00
Evan Cheng
ba8dc03935 Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76398 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:10:07 +00:00
Jakob Stoklund Olesen
45d34fe358 Fix http://llvm.org/bugs/show_bug.cgi?id=4583 
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76373 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-19 19:09:59 +00:00
Evan Cheng
438d9900c0 Catch more coalescing opportunities. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76282 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 04:52:23 +00:00
Evan Cheng
5248468473 Enable cross register class coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 02:10:10 +00:00
Evan Cheng
59959cd966 Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76258 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:42:51 +00:00
Evan Cheng
47e9fab158 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76248 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:13:25 +00:00
Chris Lattner
a9af7e626c rename test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 18:05:55 +00:00
Eli Friedman
a64eb92fe3 Make promotion in operation legalization for SETCC work correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76153 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 05:16:04 +00:00
Anton Korobeynikov
b8e9ac834a Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 23:26:06 +00:00
Dale Johannesen
423ccfe51d Assume an inline asm might be a call, so we get 
stack alignment right when it is.  This is not
ideal but conservatively correct.  Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76120 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 22:34:45 +00:00
Jakob Stoklund Olesen
57e599a46b Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands. 
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:58:34 +00:00
Evan Cheng
5f15992b77 Changed my mind. We now allow remat of instructions whose defs have subreg indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76100 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:15:00 +00:00
Evan Cheng
2b48ab947c With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76094 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 18:44:05 +00:00
Anton Korobeynikov
ebfe2b2722 Make xfail proper 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:53:47 +00:00
Anton Korobeynikov
c975180624 Temporary disable 16 bit bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov
6ff3f2c710 Add bswap patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov
54681eca69 Fix logic inversion for RI-mode address selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:31:14 +00:00
Anton Korobeynikov
9419a0d13d Unbreak the test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76051 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:49 +00:00
Anton Korobeynikov
bb8a04806d Expand 32-bit bitconverts via memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:29 +00:00
Anton Korobeynikov
f2fd8ea1c9 Fix incomin arg stack frame offset in case we need to generate stack frame 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:29:57 +00:00
Anton Korobeynikov
5dd38de2c2 Revert the commit, it just hides the real bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov
75eef89ddb Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov
8bd0db7615 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:18:17 +00:00
Anton Korobeynikov
6fe326c713 Implement 'large' PIC model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov
48e8b3cc58 Implement shifts properly (hopefilly - finally!) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov
0a42d2b437 Properly handle divides. As a bonus - implement memory versions of them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov
014d4639d8 32 bit shifts have only 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov
1ed1e3ecd4 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov
720e3b00b8 Add support for 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:09:35 +00:00
Anton Korobeynikov
980d5503c3 Emit proper lowering of load from arg stack slot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:42 +00:00
Anton Korobeynikov
c772c4408e Implement dynamic allocas 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:15 +00:00
Anton Korobeynikov
c16cdc5de7 Add jump tables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:07:50 +00:00
Anton Korobeynikov
759205d1ac Add rotates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:49 +00:00
Anton Korobeynikov
cfca8b1f62 Add patterns for integer negate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:27 +00:00
Anton Korobeynikov
8c993e1632 Provide proper patterns for and with imm instructions. Tune the tests accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:00 +00:00
Anton Korobeynikov
25af73303f Add 32 bit and reg-imm and disable invalid patterns for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:32 +00:00
Anton Korobeynikov
747052c1a5 Add z9 and z10 target processors. Mark z10-only instructions as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:00 +00:00
Anton Korobeynikov
22836d1b31 Proper lower 'small' results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:58:24 +00:00
Anton Korobeynikov
eb68f1c661 Completel forgot about unconditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:52 +00:00
Anton Korobeynikov
bad769f11a Lower addresses of globals 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75960 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:27 +00:00
Anton Korobeynikov
ed1a6d4cad Test (incomplete) for easy muls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75959 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:03 +00:00
Anton Korobeynikov
8d1837d9be Provide "wide" muls and divs/rems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75958 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:56:42 +00:00
Anton Korobeynikov
ecf22d5bdc Tests for cmp / br_cc / select_cc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:53:15 +00:00
Anton Korobeynikov
ef5decab53 Emit callee-saved regs spills / restores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov
ba249e41f3 Some preliminary call lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov
3c98c616c5 Prologue / epilogue emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov
51f613fb2b Add simple frame index elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:25 +00:00
Anton Korobeynikov
81c0325cdf Provide proper test :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75938 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:48:59 +00:00
Anton Korobeynikov
711d5b68e0 Add address computation stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov
c8301d17a8 Add mem-imm stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:14 +00:00
Anton Korobeynikov
961bb6f430 Add stores and truncstores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:45:00 +00:00
Anton Korobeynikov
dc28955b3f Add patterns for various extloads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:44:30 +00:00
Anton Korobeynikov
9e4816e09f Add shifts and reg-imm address matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:43:18 +00:00
Anton Korobeynikov
a51752cbea Add bunch of 32-bit patterns... Uffff :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:42:31 +00:00
Anton Korobeynikov
da308c9a67 Add bunch of reg-imm movs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:34:50 +00:00
Anton Korobeynikov
89edcd0927 Provide masked reg-imm 'or' and 'and' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:57 +00:00
Anton Korobeynikov
c79629536a Fix test running lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:33:21 +00:00
Anton Korobeynikov
e6220fb230 Add reg-reg and pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:49 +00:00
Anton Korobeynikov
bdc9081693 Add sub reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:32:16 +00:00
Anton Korobeynikov
b573f99ab7 Add xor reg-reg pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:31:28 +00:00
Anton Korobeynikov
26ba0b1ec5 Add or reg-reg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:53 +00:00
Anton Korobeynikov
0676d2887a Add add reg-reg and reg-imm patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:30:15 +00:00
Anton Korobeynikov
1cc9dc7267 Add simple reg-reg and reg-imm moves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:29:38 +00:00
Anton Korobeynikov
87a24e3ee4 Minimal lowering for formal_arguments / ret 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:59 +00:00
Anton Korobeynikov
b24f97dd74 Add testsuite dir for systemz stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:28:22 +00:00
Richard Osborne
db9e697725 Combine an unaligned store of unaligned load into a memmove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 12:50:48 +00:00
Richard Osborne
ccb7e96ef0 Expand unaligned 32 bit loads from an address which is a constant 
offset from a 32 bit aligned base as follows:

  ldw low, base[offset >> 2]
  ldw high, base[(offset >> 2) + 1]
  shr low_shifted, low, (offset & 0x3) * 8
  shl high_shifted, high, 32 - (offset & 0x3) * 8
  or result, low_shifted, high_shifted

Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662 Custom lower unaligned 32 bit stores and loads into libcalls. This is 
a big code size win since before they were expanding to upto 16
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:21:18 +00:00
Evan Cheng
378445303b Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 09:20:10 +00:00
Evan Cheng
a499effd3b ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill situations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75838 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 21:39:50 +00:00
Richard Osborne
1d05b237a5 Fix pattern for LD16S_3r, add basic tests to check load / store instructions 
are being properly selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 17:06:59 +00:00
Richard Osborne
3af282f16a Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 15:46:56 +00:00
Chris Lattner
4fb63d088b fix an arm codegen bug (the same as PR4482 on ppc) where available_externally 
symbols were not getting stubs.  While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 04:12:33 +00:00
Chris Lattner
392db3e11d get the PPC stub temporary label from the mangler instead of 
using horrible string hacking.  This gives us a different label,
but it's just an assembler temporary, so the name doesn't matter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 02:56:53 +00:00
Chris Lattner
a9aa3523bf convert this to filecheck style and make it a test of darwin/PPC's 
extremely elaborate pic/nopic stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75726 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 01:43:31 +00:00
Chris Lattner
0bc26723c5 simplify this test to test the esentials. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75725 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 01:32:33 +00:00
Chris Lattner
9e3152b381 convert to filecheck style, simplify RUN line, and add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75667 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 19:49:11 +00:00
Chris Lattner
8be6cb5b0f convert this test to filecheck style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75663 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 18:57:40 +00:00
Chris Lattner
b8158acc23 Reapply my previous asmprinter changes now with more testing and two 
additional bug fixes:

1. The bug that everyone hit was a problem in the asmprinter where it
   would remove $stub but keep the L prefix on a name when emitting the
   indirect symbol.  This is easy to fix by keeping the name of the stub
   and the name of the symbol in a StringMap instead of just keeping a
   StringSet and trying to reconstruct it late.

2. There was a problem printing the personality function.  The current
   logic to print out the personality function from the DWARF information
   is a bit of a cesspool right now that duplicates a bunch of other 
   logic in the asm printer.  The short version of it is that it depends
   on emitting both the L and _ prefix for symbols (at least on darwin)
   and until I can untangle it, it is best to switch the mangler back to
   emitting both prefixes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75646 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 18:17:16 +00:00
Daniel Dunbar
41ffe6c7af Revert r75610 (and r75620, which was blocking the revert), in the hopes of 
unbreaking llvm-gcc (on Darwin).

--- Reverse-merging r75620 into '.':
U    include/llvm/Support/Mangler.h
--- Reverse-merging r75610 into '.':
U    test/CodeGen/X86/loop-hoist.ll
G    include/llvm/Support/Mangler.h
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/VMCore/Mangler.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75636 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 15:57:55 +00:00
Chris Lattner
03e9dd9ffa Change the X86 asmprinter to use the mangler to apply suffixes like "$non_lazy_ptr" 
to symbols instead of doing it with "printSuffixedName".  This gets us to the point
where there is a real separation between computing a symbol name and printing it,
something I need for MC printer stuff.

This patch also fixes a corner case bug where unnamed private globals wouldn't get
the private label prefix.

Next up, rename all uses of getValueName -> getMangledName for better greppability,
and then tackle the ppc/arm backends to eliminate "printSuffixedName".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 06:04:35 +00:00
Chris Lattner
1cda87c3a0 Change the internal interface to makeNameProper to take a bool that 
indicates whether the label is private or not, instead of taking
prefix stuff.  One effect of this is that symbols will be generated
with *just* the private prefix, instead of both the private prefix
*and* the user-label-prefix, but this doesn't matter as long as it
is consistent.  For example we'll now get "Lfoo" instead of "L_foo".
These are just assembler temporary labels anyway, so they never even
make it into the .o file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75607 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 04:50:12 +00:00
David Goodwin
c2ffd286af Fix detection of valid BFC immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75576 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:57:56 +00:00
Bill Wendling
91267547f7 Check for the correct unnamed name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75573 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:53:58 +00:00
Dan Gohman
45f91b70c4 Check in a reduced version of this testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75544 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-13 23:04:44 +00:00
Chris Lattner
d4f53b373e Two changes: 
1) unique globals with the existing "Count" local in Mangler, not with
atomic nonsense.  Using atomics will give us nondeterminstic output
from the compiler when using multiple threads, which is bad.

2) Do not mangle an unknown global name with a type suffix.  We don't
   need this anymore now that llvm ir doesn't have type planes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75541 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-13 22:48:46 +00:00
Dan Gohman
08d4ec0b20 Add testcases for PR4538, PR4537, and PR4534. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-13 22:30:31 +00:00
Chris Lattner
4cef7db13f remove tests for removed intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75433 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-12 21:30:06 +00:00
Chris Lattner
0df3b369a5 add nounwind 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-12 00:46:16 +00:00
Nick Lewycky
f5c21ecfa6 Darwin prepends an _ to internal globals, Linux doesn't. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75405 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 23:48:59 +00:00
Chris Lattner
65a7a6f7a3 fix x86-64 static codegen to materialize the address of a global with movl instead 
of lea.  It is better for code size (and presumably efficiency) to use:

  movl $foo, %eax

rather than:

  leal foo, eax

Both give a nice zero extending "move immediate" instruction, the former is just
smaller.  Note that global addresses should be handled different by the x86
backend, but I chose to follow the style already in place and add more fixme's.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75403 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 23:17:29 +00:00
Chris Lattner
8ddb9989e6 this test was incorrect for x86-64 static. It passed on darwin, because darwin 
doesn't have static x86-64 mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75392 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 22:30:05 +00:00
Chris Lattner
4f06649497 Fix PR4533, which is about buggy codegen in x86-64 -static mode. 
Basically, using:
  lea symbol(%rip), %rax

is not valid in -static mode, because the current RIP may not be
within 32-bits of "symbol" when an app is built partially pic and
partially static.  The fix for this is to compile it to:

  lea symbol, %rax

It would be better to codegen this as:

  movq $symbol, %rax

but that will come next.


The hard part of fixing this bug was fixing abi-isel, which was actively
testing for the wrong behavior.  Also, the RUN lines are completely impossible
to understand what they are testing.  To help with this, convert the -static 
x86-64 codegen tests to use filecheck.  This is much more stable and makes it
more clear what the codegen is expected to be.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75382 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 20:29:19 +00:00
Chris Lattner
238f5100c6 We get the P modifier wrong in a lot of cases, just add some more rigorous testing. 
In addition to fixing this, I still need to do some more testing on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 08:30:22 +00:00
Evan Cheng
ed338e80f9 Don't put IT instruction before conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:26:20 +00:00
Evan Cheng
2f297df02e Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:08:13 +00:00
Evan Cheng
446c428bf3 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:43:01 +00:00
Chris Lattner
84232681cc convert test to use FileCheck, which is much more precise and faster than 
the previous RUN lines.  Hopefully this will be an inspiration for future
tests :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75261 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 18:34:47 +00:00
Evan Cheng
06e16587eb Add a thumb2 pass to insert IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 01:54:42 +00:00
Evan Cheng
9c06178e35 Remove a bogus assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 00:23:48 +00:00
Bob Wilson
9b4b00ad43 Handle 'a' modifier on inline assembly operands. 
This is part of the fix for pr4521.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75201 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 23:54:51 +00:00
Eli Friedman
c680ac9003 Make EXTRACT_VECTOR_ELT a bit more flexible in terms of the returned 
value.  Adjust other code to deal with that correctly.  Make 
DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT take advantage of 
this new flexibility to simplify the code and make it deal with unusual 
vectors (like <4 x i1>) correctly.  Fixes PR3037.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75176 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 22:01:03 +00:00
Evan Cheng
910139f9ca Targets sometimes assign fixed stack object to spill certain callee-saved 
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 06:53:48 +00:00
Lang Hames
ffd1326ff8 Improved tracking of value number kills. VN kills are now represented 
as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75097 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 03:57:02 +00:00
Chris Lattner
39f56b6d16 remove eh, convert to FileCheck style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75087 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 01:07:22 +00:00
Chris Lattner
f4a9774e2b we have no tests for dllimport/export. Add one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 00:53:44 +00:00
Chris Lattner
9f44b3a411 * add some assertions for sanity checking. 
* remove some old code that was needed when we'd put ESP in the scale instead of 
  the base of some instructions.
* Fix a bug with the P modifier in inline asm that caused us to drop it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75077 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 00:27:29 +00:00
Chris Lattner
600f175834 add a test for dale's recent change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75074 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 00:00:16 +00:00
Chris Lattner
ab711cc593 switch test to FileCheck-style and test the P and non-P cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75071 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:44:06 +00:00
Chris Lattner
e5646ccf66 rename a test to make it a feature test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75070 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:40:57 +00:00
David Goodwin
f1daf7d8ab Use common code for both ARM and Thumb-2 instruction and register info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:10:31 +00:00
Bob Wilson
2ed334694f Implement NEON vst1 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 20:32:02 +00:00
Chris Lattner
515cdbe49d add some more check for vector compares. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 18:51:25 +00:00
Chris Lattner
57e56cd72a convert a test to "FileCheck" style. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75023 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 18:48:24 +00:00
Bob Wilson
205a5ca6cf Implement NEON vld1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 18:11:30 +00:00
David Goodwin
a928f27d23 Add rev16 test... xfail for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75012 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 16:15:06 +00:00
David Goodwin
334c26473b Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 16:09:28 +00:00
Chris Lattner
a47d9669b7 eliminate the v[if]cmp versions of these tests, now that [if]cmp+sext works. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 00:49:35 +00:00
Chris Lattner
b2773e1ada Change these tests to use [fi]cmp+sext instead of v[fi]cmp. No 
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 00:46:57 +00:00
Chris Lattner
2b7a271c71 dag combine sext(setcc) -> vsetcc before legalize. To make this safe, 
VSETCC must define all bits, which is different than it was documented
to before.  Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the 
documentation.  We now get nice code for vec_compare.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74978 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 00:31:33 +00:00
Chris Lattner
c2c27b3627 add support for legalizing an icmp where the result is illegal (4xi1) but 
the input is legal (4 x i32)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74964 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 23:03:54 +00:00
Chris Lattner
cb178c61e4 add a trivial test that vector compares work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74963 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 22:51:09 +00:00
Chris Lattner
5962ed0a36 implement support for spliting and scalarizing vector setcc's. This 
finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 22:47:46 +00:00
Chris Lattner
33d6a3451b verify that the fcmp version of this works just as well as the 
vfcmp version.  We actually get better code for this silly testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 22:07:47 +00:00
Evan Cheng
e253c951b3 Add Thumb2 movcc instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 20:39:03 +00:00
Evan Cheng
35bd43da76 Add missing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74945 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 20:38:08 +00:00
Evan Cheng
40289b041a Add Thumb2 pkhbt / pkhtb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74895 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 05:35:52 +00:00
Evan Cheng
5b9fcd1c8e Add some more Thumb2 multiplication instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 01:17:28 +00:00
Evan Cheng
36a0aebac2 Add bfc to armv6t2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 22:23:46 +00:00
Evan Cheng
edcbada3d0 Added ARM::mls for armv6t2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 22:05:45 +00:00
Evan Cheng
2c4d96dfe9 Avoid adding a duplicate def. This fixes PR4478. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74857 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 21:34:05 +00:00
Evan Cheng
d27c9fc403 Add thumb2 sign / zero extend with rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-03 01:43:10 +00:00
Evan Cheng
6d94f11196 Added indexed stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-03 00:06:39 +00:00
Evan Cheng
4fbb9960ad Sign extending pre/post indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 23:16:11 +00:00
Evan Cheng
e88d5cee9d Thumb2 pre/post indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 07:28:31 +00:00
Chris Lattner
cd714b12fc @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing. 
This fixes an llvm-gcc bootstrap problem I introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74691 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 04:22:01 +00:00
Chris Lattner
27598ec1e2 Fix yet-another bug I introduced into fastisel, this time handling 
constant pool references that weren't getting properly rip-relative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74689 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 03:14:25 +00:00
Chris Lattner
4fb75e5425 Fix codegen for references to available_externally symbols. This fixes 
PR4482.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74613 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 16:53:44 +00:00
Evan Cheng
498c2903e2 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 08:29:08 +00:00
Evan Cheng
459a7c6b6a Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. 
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 08:19:36 +00:00
Chris Lattner
35c28eca62 Fix some fast-isel problems selecting global variable addressing in 
pic mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 03:27:19 +00:00
Evan Cheng
2578ba26e7 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 01:59:31 +00:00
David Goodwin
d1fa120aee Add PIC load and store patterns for Thumb-2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 00:01:13 +00:00
David Goodwin
73b8f16b36 Add thumb-2 store word, halfword, and byte. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 22:11:34 +00:00
David Goodwin
c9a59b5960 Improve Thumb-2 jump table support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 19:50:22 +00:00
Rafael Espindola
af5f6ba32d Fix PR4485. 
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74534 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 16:40:03 +00:00
Rafael Espindola
f55715c5c7 Fix PR4484. 
This was caused by me confounding FP0 and ST(0).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74523 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 12:18:16 +00:00
Evan Cheng
50564ebc9e Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 09:19:42 +00:00
Evan Cheng
4784f1fc73 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. 
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 08:49:04 +00:00
Evan Cheng
f3c21b857b A few more load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 02:15:48 +00:00
David Goodwin
4ff863c257 Enhance tests to include shifted-register operand testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74490 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 01:02:20 +00:00
David Goodwin
baeb911d60 Add Thumb-2 support for TEQ amd TST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 22:49:42 +00:00
David Goodwin
8ba221d5c5 Thumb-2 tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74464 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 22:25:22 +00:00