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6979 Commits

Author SHA1 Message Date
Duncan Sands
4590766580 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 13:21:44 +00:00
Duncan Sands
e26032d5b2 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 13:02:38 +00:00
Chris Lattner
0f899c78e1 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 19:38:20 +00:00
Chris Lattner
693173feef Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 19:23:13 +00:00
Chris Lattner
a47b265b1a really zap alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 18:23:25 +00:00
Chris Lattner
b3c417845d move fcompi alias to .td file and zap some useless code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117823 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 18:22:53 +00:00
Chris Lattner
6f96b0899b move rep aliases to td file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 18:17:33 +00:00
Chris Lattner
a17a9a00dc move sal aliases to .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117821 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 18:14:54 +00:00
Chris Lattner
1a1ecc9f3c fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 18:13:10 +00:00
Chris Lattner
8b260a7644 move a bunch more aliases from .cpp -> .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 18:07:17 +00:00
Chris Lattner
8cb441c9e0 move cmov aliases to .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117818 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 17:56:50 +00:00
Chris Lattner
b69fc28e92 move setcc and jcc aliases from .cpp to .td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 17:51:45 +00:00
Chris Lattner
537ca844dd move some code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117816 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 17:38:55 +00:00
Chris Lattner
674c1dcca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 17:36:36 +00:00
Jim Grosbach
604cdf6ea7 Clean up comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 13:48:28 +00:00
Chris Lattner
9a82e70275 stay out of the reserved namespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117773 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 04:57:14 +00:00
John Thompson
44ab89eb37 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 17:29:13 +00:00
Dale Johannesen
e49406fd63 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 00:35:54 +00:00
Kevin Enderby
529b1a4398 Added the x86 instruction ud2b (2nd official undefined instruction). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:46:49 +00:00
Michael J. Spencer
6dad10ed66 x86-Win32: Switch ftol2 calling convention from stdcall to C. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 18:52:38 +00:00
Kevin Enderby
e460890351 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 03:01:02 +00:00
Kevin Enderby
5a378076a4 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 02:53:04 +00:00
Kevin Enderby
f4630ecc3f Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 02:32:19 +00:00
Kevin Enderby
41e8cc73cf Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:59:28 +00:00
Dale Johannesen
1de4aa904e Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 23:11:10 +00:00
Rafael Espindola
de42e5c09b handle X86::EH_RETURN64 and X86::EH_RETURN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 18:09:55 +00:00
Rafael Espindola
e4f506ff4b Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 14:09:12 +00:00
Dale Johannesen
d155d7e428 An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 22:17:05 +00:00
Rafael Espindola
24ba4f7f5f Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-24 17:35:42 +00:00
Benjamin Kramer
4d1dca92bd Make the disassembler tables const so they end up in read-only memory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 09:10:44 +00:00
Michael J. Spencer
c527407010 X86: Emit _fltused instead of __fltused on Windows x64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 09:06:59 +00:00
Chandler Carruth
5117709a1d Remove a define which is never referenced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117202 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 08:25:16 +00:00
Chandler Carruth
100c267249 Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 08:10:43 +00:00
Wesley Peck
eecb858ca8 Making the e_machine configurable by the target backend in ELFObjectWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 15:52:49 +00:00
Andrew Trick
0966ec0861 Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 03:58:29 +00:00
Sean Callanan
751752e7ca Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 01:24:11 +00:00
Kevin Enderby
0b9325c97d More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 17:16:46 +00:00
Duncan Sands
6abfa46987 Remove some variables that are never really used 
(gcc-4.6 warns about these).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 16:03:28 +00:00
Duncan Sands
1e1ca0b56d Add parentheses to pacify gcc, which warns otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 16:02:12 +00:00
Michael J. Spencer
e9c253e0bc X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 01:41:01 +00:00
Michael J. Spencer
dd0a00a6e3 CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args. 
This should be the minimum set of functions that could possibly need it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 00:08:21 +00:00
Michael J. Spencer
6e56b18e57 Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 23:40:27 +00:00
Dale Johannesen
e93d99cf07 Remove Synthesizable from the Type system; as MMX vector 
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 21:32:10 +00:00
Rafael Espindola
64e6719ee8 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 16:46:08 +00:00
Evan Cheng
2312842de0 Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 18:58:51 +00:00
Daniel Dunbar
9869413802 Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 17:14:24 +00:00
Michael J. Spencer
94f7eeb84d X86: Add MS-CRT libcalls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 07:32:52 +00:00
Michael J. Spencer
87b8665878 Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116800 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 07:32:42 +00:00
Evan Cheng
11e8b74a7a - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 00:55:07 +00:00
Kevin Enderby
87f4a1a433 Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 00:01:44 +00:00
Rafael Espindola
aa85c21633 Produce ELF::R_386_GOTPC relocations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116728 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 18:36:12 +00:00
Kevin Enderby
7aef62ff8c Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 17:04:36 +00:00
Rafael Espindola
f230df9af4 Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-16 18:23:53 +00:00
Michael J. Spencer
84ac4d5a2a X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116665 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-16 08:25:41 +00:00
Rafael Espindola
6d8628061b Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 13:31:20 +00:00
Evan Cheng
3f490f3469 Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:19:28 +00:00
Eric Christopher
52b45056b2 Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 19:44:17 +00:00
Nick Lewycky
65b65d6ca4 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:18:03 +00:00
Dan Gohman
320afb8c81 Initial va_arg support for x86-64. Patch by David Meyer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:00:49 +00:00
Jakob Stoklund Olesen
d0eeeeb558 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:15:00 +00:00
Andrew Trick
1a2cf3b4d9 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 19:02:04 +00:00
Michael J. Spencer
335b806c62 X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 05:29:15 +00:00
Michael J. Spencer
92bf38c956 X86: MinGW should always use libgcc on Windows. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 23:11:06 +00:00
Michael J. Spencer
1802a9f8fe X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 22:04:34 +00:00
Michael J. Spencer
ec38de2ca8 Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 22:04:20 +00:00
Michael J. Spencer
c0c8df3cea Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 11:00:50 +00:00
Chris Lattner
0d9a0865c6 add jit support for the new psuedo instructions I added for 
the add/or xform.  The JIT isn't mcized yet, boo.

This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116125 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:59:27 +00:00
Chris Lattner
8dae787db4 machine a mutable machineinstr down into emitInstruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:54:01 +00:00
Cameron Esfahani
ec37b00b17 Recommit 116056, now with the missing file... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 19:24:18 +00:00
Andrew Trick
5900201aa7 reverting 116056: win64_params.ll may need to be conditionalized? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:22:42 +00:00
Cameron Esfahani
d7b8d91d4a Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 10:31:30 +00:00
Chris Lattner
d043529b34 fix a subtle bug I introduced in my refactoring, where we stopped preferring 
the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 05:12:14 +00:00
Chris Lattner
15df55d8c2 reapply: Use the new TB_NOT_REVERSABLE flag instead of special 
reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 03:57:25 +00:00
Chris Lattner
99ae6659da reapply the patch reverted in r116033: 
"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 03:54:52 +00:00
Daniel Dunbar
b88b00ba2b Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into 
'add'", which seems to have broken just about everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:32 +00:00
Daniel Dunbar
b38109fc2d Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends 
on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:29 +00:00
Daniel Dunbar
32f0cdba30 Revert "reimplement the second half of the or/add optimization. We should now", 
which depends on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:26 +00:00
Chris Lattner
cd3167b281 reimplement the second half of the or/add optimization. We should now 
only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 01:05:10 +00:00
Chris Lattner
05e27c5786 Use the new TB_NOT_REVERSABLE flag instead of special 
casing FsMOVAPDrr/FsMOVAPSrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:03:02 +00:00
Chris Lattner
a228376185 simplify some map operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:57:02 +00:00
Chris Lattner
122e2ea043 Reimplement (part of) the or -> add optimization. Matching 'or' into 'add' 
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies.  However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).

While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA.  This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.

This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20

the add r/i cases are coming next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:36:18 +00:00
Chris Lattner
45a1cb26a3 Reduce casting in various tables by defining the table 
with the right types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:08:41 +00:00
Chris Lattner
afcd543a55 simplify code: don't build up vector only to assert it is empty. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 22:26:19 +00:00
Chris Lattner
9649e9acdd convert test to use the existing classes that the multipatterns 
use.  Since TEST is completely different than all other binops,
don't define a multipattern for it.

This completes factorization of binops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 21:31:03 +00:00
Chris Lattner
00e94baf4e convert cmp to use a multipattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:56:25 +00:00
Evan Cheng
835580fc3a Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:50:20 +00:00
Chris Lattner
9e94000c16 reduce redundancy between pattern copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:14:23 +00:00
Chris Lattner
a2b8b16c7e the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:06:24 +00:00
Chris Lattner
a3208e122c convert adc/sbb to a multipattern. Because the adde/sube nodes 
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.

This could be handled through better instantiation support in tblgen,
but it isn't meta enough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:01:55 +00:00
Jakob Stoklund Olesen
8456c4f957 Fix obvious mistake pointed out by Michael Spencer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 18:47:10 +00:00
Chris Lattner
b046810fe4 add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS, 
allowing us to convert ADD over.  deletes 160 lines of .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:37:01 +00:00
Chris Lattner
521ff704a1 Fix a few issues in ArithBinOpEFLAGS that made it specific to and. 
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:26:27 +00:00
Chris Lattner
4b181c87de Convert 'and' to single instance of a multipattern 
which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:10:20 +00:00
Chris Lattner
511c686f76 add a new BinOpAI class to represent the immediate form that directly acts on EAX. 
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:43:39 +00:00
Chris Lattner
1bb9adae4c add a bunch of classes for other common patterns. 
As usual, no change in generated .inc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:35:28 +00:00
Chris Lattner
2b8d30d080 Define a new BinOpRI8 class and use it to define the imm8 versions of and. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6 Constrain the offset register to a *_NOSP register class when inserting LEA 
instructions.

This unbreaks the machine code verifier and fixes PR8317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf add the pattern operator to match to X86TypeInfo, use this to 
convert AND64ri32 to use BinOpRI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0 Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass. 
This function looks like it is about ready to be generated by TebleGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 23:56:46 +00:00
Chris Lattner
b2fc409827 enhance X86TypeInfo to include information about the encoding and 
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:55:42 +00:00
Chris Lattner
3ab0b59aad add a class for _REV nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:35:22 +00:00
Chris Lattner
08808f9733 sink more intelligence into the ITy base class. Now it knows 
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:28:38 +00:00
Chris Lattner
44402c0701 refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:20:57 +00:00
Chris Lattner
da4b361726 with tblgen suitably extended, we can now get the load node from typeinfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 04:58:43 +00:00
Chris Lattner
417b54354b lets go all meta and define new X86 type wrappers that declare the associated 
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:45:24 +00:00
Chris Lattner
ff27af206e introduce a new BinOpRM class and use it to factor AND*rm. This points out 
that I need a heavier handed approach to get ultimate factorization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:30:49 +00:00
Chris Lattner
c7252ce743 remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places 
where !cast is just as short.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:19:21 +00:00
Chris Lattner
8d978a75b4 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:58:18 +00:00
Chris Lattner
20b2499a7c associate the instruction suffix letter with the integer gpr 
register class, and use this to simplify use of BinOpRR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:43:04 +00:00
Chris Lattner
e00047c906 introduce a new BinOpRR class, and convert 4 and instructions to use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:32:05 +00:00
Chris Lattner
6dbbff9172 Move cmov pseudo instructions to InstrCompiler, 
convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:09:10 +00:00
Chris Lattner
25cbf504fe Use #NAME# to have the CMOV multiclass define things with the same names as before 
(e.g. CMOVBE16rr instead of CMOVBErr16).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:00:14 +00:00
Chris Lattner
df72eaef3d enhance tblgen to support anonymous defm's, use this to 
simplify the X86 CMOVmr's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:51:56 +00:00
Chris Lattner
286997c745 convert cmov mr patterns to use a multipattern. Death to redundancy 
and verbosity


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115701 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:42:54 +00:00
Chris Lattner
d350e4757e switch CMOVBE to the multipattern: 
21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:23:58 +00:00
Chris Lattner
e583c892d8 fix a bug I introduced in r115669, which ended up with MOV64mr_TC 
not getting marked as mayStore.  This fixes llvm-gcc bootstrap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:16:48 +00:00
Chris Lattner
b484213d1b add a multiclass for cmov's, but don't start using it yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:01:02 +00:00
Chris Lattner
d244699067 use a multipattern to define setcc instructions: 
X86InstrCMovSetCC.td |  200 ++++++---------------------------------------------
 1 file changed, 27 insertions(+), 173 deletions(-)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:34:29 +00:00
Chris Lattner
2c383d8c4d move SETB pseudos into the same place in InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:18:04 +00:00
Chris Lattner
508fc4708b Replace a gross hack (the MOV64ri_alt instruction) with a slightly less 
gross hack (having the asmmatcher handle the alias).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:09:45 +00:00
Chris Lattner
748a2fe917 distribute the rest of the contents of X86Instr64bit.td out to 
the right places.  X86Instr64bit.td now dies, long live x86-64!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:49:15 +00:00
Chris Lattner
10701928ff move the rest of the simple 64-bit arithmetic into InstrArithmetic.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115663 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:35:37 +00:00
Chris Lattner
5bbbcdb1d8 continue moving 64-bit stuff into X86InstrArithmetic.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:23:31 +00:00
Chris Lattner
64227940e7 move 64-bit add and adc to InstrArithmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:59:08 +00:00
Chris Lattner
c7d4655b57 rewrote two addr constraints so that they are only set, not set and then nestedly cleared. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:52:25 +00:00
Chris Lattner
6367cfc470 split the 32-bit integer arithmetic instructions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:39:12 +00:00
Chris Lattner
5249ff34fb integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 07:13:35 +00:00
Chris Lattner
5f58e84af8 move 32-bit shift and rotates out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115607 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 07:00:12 +00:00
Chris Lattner
2c065e1c86 add new file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115606 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:52:35 +00:00
Chris Lattner
8917cd3d67 move sign and zero extensions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:52:26 +00:00
Chris Lattner
d8cc2722a4 move some instructions from Instr64Bit -> InstrInfo. 
bswap32 doesn't read eflags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:47:35 +00:00
Chris Lattner
5673e1d314 move CMOV_FR32 and friends to InstrCompiler, since they are 
pseudo instructions.

Move POPCNT to InstrSSE since they are SSE4 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:41:40 +00:00
Chris Lattner
41efbfaa66 move various pattern matching support goop out of X86Instr64Bit, to live 
with the 32-bit stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:37:31 +00:00
Chris Lattner
35649fc3dd split conditional moves and setcc's out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:33:16 +00:00
Chris Lattner
d3f033d969 move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:27:48 +00:00
Chris Lattner
010496c6a7 move the atomic pseudo instructions out to X86InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115599 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:22:35 +00:00
Chris Lattner
8af88ef157 move more pseudo instructions out to X86InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:10:16 +00:00
Chris Lattner
d071b83b5d move VMX instructions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:06:53 +00:00
Chris Lattner
87be16a9e1 continue moving stuff out to X86InstrSystem.td. Move 
control flow stuff out to X86InstrControl.td.  Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:04:14 +00:00
Chris Lattner
434c7cb8a1 refactor .td files a bit, moving system instructions out to X86InstrSystem.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 05:32:15 +00:00
Bill Wendling
6cf6c79e82 The pshufw instruction came about in MMX2 when SSE was introduced. Don't place 
it in with the SSSE3 instructions.

Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-04 20:24:01 +00:00
Anton Korobeynikov
e7beda183d va_args support for Win64. 
Patch by Cameron!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 22:52:07 +00:00
Anton Korobeynikov
6af61ca789 Properly emit stack probe on win64 (for non-mingw targets). 
Based on the patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115479 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 22:02:38 +00:00
Eli Friedman
d32d85e5ba Add 3DNowA instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115477 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 20:23:13 +00:00
Chris Lattner
591d76ea5a the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 19:09:13 +00:00
Rafael Espindola
0febc4657b Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do 
so and also change X86 for consistency.

Investigating if this can be improved a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:59:45 +00:00
Chris Lattner
cc07d7116a add support for the prefetch/prefetchw instructions, move femms into 
the right file.  The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:42:30 +00:00
Chris Lattner
f132fa0e74 what the heck, add support for the rest of the 3dNow! binary operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:24:18 +00:00
Chris Lattner
548abfcbd6 Implement support for the bizarre 3DNow! encoding (which is unlike anything 
else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:08:05 +00:00
Chris Lattner
7330d97069 stub out a header to put 3dNow! instructions into. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 23:06:23 +00:00
Chris Lattner
d476914607 fix a regression introduced in r115243, in which the instruction 
backing int_x86_ssse3_pshuf_w got removed.  This caused PR8280.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 21:32:15 +00:00
Jim Grosbach
7ac1609a3b Rename the AsmPrinter directory to InstPrinter for those targets that have 
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:39:28 +00:00
Benjamin Kramer
b0f96facd6 Delete token *after* reading from it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 12:25:27 +00:00
Dale Johannesen
0488fb649a Massive rewrite of MMX: 
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 23:57:10 +00:00
Jim Grosbach
ddcf859851 Clean up asm writer usage for x86 and msp430 to flag that the writer should 
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 23:40:25 +00:00
Chris Lattner
905f2e0669 preemptively add the rest of the non-n fpstack instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 17:11:29 +00:00
Chris Lattner
9ee4aed3b6 implement support for finit, PR8258 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 16:42:53 +00:00
Chris Lattner
0bb83a84d4 add support for fstcw, PR8259 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 16:39:29 +00:00
Kevin Enderby
8ebf66236e Adds getPointerSize() to the AsmBackend which will be needed by the final patch 
for the dwarf .loc support to emit dwarf line number tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 16:38:07 +00:00
Rafael Espindola
a8c02c3bdd Correctly produce R_X86_64_32 or R_X86_64_32S. 
With this patch in

movq    $foo, foo(%rip)
foo:
.long   foo

We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 03:11:42 +00:00
Eric Christopher
e487b017e9 Noticed by inspection when looking for other cmov bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115100 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 23:00:29 +00:00
Nick Lewycky
8892b033e4 Add parens to fix GCC warning: 
lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 18:56:57 +00:00
Chris Lattner
a25f933396 implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115061 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 18:39:16 +00:00
Chris Lattner
6f42027263 fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 05:05:03 +00:00
Chris Lattner
f3654db458 add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 04:55:40 +00:00
Chris Lattner
78a194693b make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same 
order as cctools for diffability.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 03:43:43 +00:00
Chris Lattner
8a5072903e implement support for 32-bit address operands in 64-bit mode, which 
are defined to emit the 0x67 prefix byte.  rdar://8482675


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 03:33:25 +00:00
Chris Lattner
b2ef4c1235 add basic avx support to the disassembler, also teach it about ssmem/sdmem 
operands.

With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up.  This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 02:57:56 +00:00
Chris Lattner
bf6018ac5a add asmparser support for cvttpd2dq by removing some Int_ prefixes. 
Clean up cvttps2dq by removing some redundant implementations of the
same instruction.  rdar://8456382


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 02:36:32 +00:00
Chris Lattner
0c04e4f58f implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 02:24:57 +00:00
Chris Lattner
7c51a3172c implement rdar://8456378 and PR7557 - support for the fstsw, 
an instruction that requires a WHOLE NEW wonderful kind of alias.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 01:50:45 +00:00
Chris Lattner
7036f8be4d change the protocol TargetAsmPArser::MatchInstruction method to take an 
MCStreamer to emit into instead of an MCInst to fill in.  This allows the
matcher extra flexibility and is more convenient.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 01:42:58 +00:00
Dale Johannesen
a8bd1ff8c5 MMX parameters aren't handled here yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 17:29:47 +00:00
Chris Lattner
2956462742 yet more aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 07:24:57 +00:00
Chris Lattner
b1162fc05e add a couple more aliases, rdar://8456378 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114821 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 07:21:41 +00:00
Chris Lattner
df967d6137 fix rdar://8470918 - llvm-mc can't assemble smovl 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 07:11:53 +00:00
Chris Lattner
cb296ec0b6 Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands. 
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd.  Instruction set orthogonality is overrated or 
something.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114818 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 07:08:21 +00:00
Chris Lattner
80945784f9 improve indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 06:34:01 +00:00
Eric Christopher
722d315ac9 This code should never fire on non-darwin subtargets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114811 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 06:01:51 +00:00
Chris Lattner
fd8fddd830 implement support for 'clr' alias. This is part of rdar://8416805, 
but balrog was wanting it on irc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 04:23:03 +00:00
Rafael Espindola
73ffea47d2 Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put 
symbols defined in merge sections in independent atoms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 05:42:19 +00:00
Dale Johannesen
c451051157 We can't return SSE/MMX vectors if SSE is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 19:05:48 +00:00
Owen Anderson
f523e476c2 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further 
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:45:25 +00:00
Owen Anderson
71e416ac3a Add isConditionalMove bits to X86 and ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 22:57:01 +00:00
Cameron Esfahani
4af1eaee70 Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 22:35:21 +00:00
Eric Christopher
56a8b817b1 Temporarily work around new address lowering while I figure out what 
needs to happen for darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 20:42:08 +00:00
Bob Wilson
eafca4e2b2 Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an 
ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114554 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 17:35:14 +00:00
Chris Lattner
2c5291b563 fix rdar://8456371 - Handle commutable instructions written backward. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 06:26:39 +00:00
Chris Lattner
1eb1b68e3a Fix an inconsistency in the x86 backend that led it to reject "calll foo" on 
x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 05:49:14 +00:00
Chris Lattner
bc57c6db4a fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8" 
Teaching the code generator about CR8-15, how to rex them up, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 05:29:50 +00:00
Chris Lattner
c2b942acf6 add the missing aliases for fp stack cmovs, rdar://8456391 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 04:56:20 +00:00
Chris Lattner
f93b90c5df reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 04:39:11 +00:00
Chris Lattner
33d60d5e56 Fix rdar://8456364 - llvm-mc rejects '%CS' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114528 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 04:11:10 +00:00
Chris Lattner
0c289c140e fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp' 
-This line, and those below, will be ignored--

M    test/MC/AsmParser/X86/x86_instructions.s
M    lib/Target/X86/AsmParser/X86AsmParser.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 04:04:03 +00:00
Chris Lattner
61129252e4 fix rdar://8456361 - llvm-mc rejects 'rep movsd' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 03:50:32 +00:00
Chris Lattner
492a43e6f6 convert the last 4 X86ISD nodes that should have memoperands to have them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 01:28:21 +00:00
Chris Lattner
2156b79c49 give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only 
can access the stack due to how it is generated though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114522 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 01:11:26 +00:00
Chris Lattner
0729093cd7 give FP_TO_INT16_IN_MEM and friends a memoperand. They are only 
used with stack slots, but hey, lets be safe.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 01:05:16 +00:00
Chris Lattner
8864155a35 give VZEXT_LOAD a memory operand, it now works with segment registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 00:34:38 +00:00
Chris Lattner
0b79cfee15 revert r114386 now that address modes work correctly, we get a nice 
call through gs-relative memory now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7 give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 23:59:42 +00:00
Chris Lattner
b86faa17a4 reimplement support for GS and FS relative address space matching 
by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.

This makes FS and GS relative accesses *far* more predictable and
work much better.  It also simplifies the X86 backend a bit, more
to come.

There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114491 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 22:07:31 +00:00
Owen Anderson
bc146b0a4d Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using 
the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 20:42:50 +00:00
Chris Lattner
52a261b3c1 fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 20:31:19 +00:00
Chris Lattner
701cd62297 even though I'm about to rip it out, simplify the address mode stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114468 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 19:41:58 +00:00
Chris Lattner
fc448ff89b convert a couple more places to use the new getStore() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 18:51:21 +00:00
Owen Anderson
c004eec71b When adding the carry bit to another value on X86, exploit the fact that the carry-materialization 
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 18:41:19 +00:00
Chris Lattner
8026a9d3ee eliminate some uses of the getStore overload. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 17:50:43 +00:00
Chris Lattner
3d6ccfba31 propagate MachinePointerInfo through various uses of the old 
SelectionDAG::getExtLoad overload, and eliminate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 17:04:51 +00:00
Chris Lattner
d1c24ed81c convert the targets off the non-MachinePointerInfo of getLoad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 06:44:06 +00:00
Chris Lattner
e8639036b1 it's more elegant to put the "getConstantPool" and 
"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 06:22:23 +00:00
Chris Lattner
51abfe490b update the X86 backend to use the MachinePointerInfo version of one 
of the getLoad methods.  This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 06:02:19 +00:00
Chris Lattner
e54b482d1c Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations 
into non-segment-relative copies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 05:43:34 +00:00
Chris Lattner
e72f2027e9 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo 
instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4 convert targets to the new MF.getMachineMemOperand interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 04:39:43 +00:00
Chris Lattner
08bad54baf fix rdar://8453210, a crash handling a call through a GS relative load. 
For now, just disable folding the load into the call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 03:37:00 +00:00
NAKAMURA Takumi
cd458be047 X86Subtarget.h: Fix Cygwin's TD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 19:50:42 +00:00
Dan Gohman
d8c0a51362 Avoid emitting a PIC base register if no PIC addresses are needed. 
This fixes rdar://8396318.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 20:24:24 +00:00
Chris Lattner
40cc3f8783 fix rdar://8444631 - encoder crash on 'enter' 
What a weird instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 18:02:29 +00:00
Chris Lattner
35aa94b229 fix rdar://8438816 - unrecognized 'fildq' instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 20:46:38 +00:00
Chris Lattner
d0bcc9a015 lcall and ljmp always default to lcalll and ljmpl. This finally 
wraps up r8418316


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 05:30:20 +00:00
Chris Lattner
cbb442640f apparently jmpl $1,$2 is an alias for ljmpl, similiarly 
for call.  Add this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 05:25:21 +00:00
Chris Lattner
250b948f21 Disambiguate lcall/ljmp to the 32-bit version. This happens 
even in 64-bit mode apparently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 05:14:54 +00:00
Chris Lattner
6c1b3b1e32 fix the encoding of sldt GR16 to have the 0x66 prefix, and 
add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 04:45:10 +00:00
Chris Lattner
cfad564043 implement aliases for shld/shrd, part of rdar://8418316 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 04:37:18 +00:00
Chris Lattner
e9e16a36d9 fix rdar://8431880 - rcl/rcr with no shift amount not recognized 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 04:33:27 +00:00
Chris Lattner
84f362d891 add various broken forms of fnstsw. I didn't add the %rax 
version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 04:15:16 +00:00
Chris Lattner
8f777a205e add some aliases for f[u]comi, part of rdar://8431422 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113930 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 04:08:38 +00:00
Chris Lattner
2d592d10a5 add a bunch of aliases for fp operations with no operand, 
rdar://8431422


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 04:04:33 +00:00
Chris Lattner
f884012c93 Diagnose invalid instructions like "incl" with "too few operands for instruction" 
instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 03:50:11 +00:00
Jim Grosbach
22854b777e trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 01:01:45 +00:00
Chris Lattner
ef63c9a9b6 add a terrible hack to allow out with dx is parens, a gas bug. 
This fixes PR8114


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113894 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 23:34:29 +00:00
Michael J. Spencer
3a210e2d30 Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally." 
This reverts commit r113632

Conflicts:

	cmake/modules/AddLLVM.cmake

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-13 23:59:48 +00:00
Dale Johannesen
e5db19ebd5 Fix typos. 128-bit PSHUFB takes 128-bit memory op. 
v8i16 is not an MMX type; put it where it belongs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-13 21:15:43 +00:00
John Thompson
eac6e1d0c7 Added skeleton for inline asm multiple alternative constraint support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-13 18:15:37 +00:00
Chris Lattner
0989d29d09 add a missed cmov alias, part of rdar://8416805 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-11 17:08:22 +00:00
Chris Lattner
697d37a436 add support for all the setCC aliases. Part of rdar://8416805 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-11 17:06:05 +00:00
Chris Lattner
dfa3c9d982 add support for pushfd/popfd which are aliases for pushfl/popfl. 
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113690 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-11 16:39:16 +00:00
Chris Lattner
ee211d0ed6 implement rdar://8407928 - support for in/out with a missing "a" register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-11 16:32:12 +00:00
Chris Lattner
cbf8a98c7c fix the asmparser so that the target is responsible for skipping to 
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors.  Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:

  foo %eax
  bar %al

This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-11 16:18:25 +00:00
Michael J. Spencer
4e9c939312 CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 21:14:25 +00:00
Bill Wendling
1ec2ee6526 Reapply r113585. The msvc machine is mercurial. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113610 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 20:20:28 +00:00
Bill Wendling
b28f579200 r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't 
understand (the log file was no help).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 19:20:47 +00:00
Bill Wendling
81781ed939 Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so 
that the memoperands are properly set after DAG building and general mucking
about.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 10:34:22 +00:00
Bruno Cardoso Lopes
ae4f7421c0 Add one more pattern to fallback movddup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113522 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-09 18:48:34 +00:00
Roman Divacky
5baf79edc0 Make ELF OS ABI dependent on the OS from target triple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113508 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-09 17:57:50 +00:00
Dale Johannesen
f73c5587fa Move remaining MMX instructions from SSE to MMX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-09 17:13:07 +00:00
Dale Johannesen
4efb0feac8 Move most MMX instructions (defined as anything that 
uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX.  No (intended) functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-09 01:02:39 +00:00
Chris Lattner
90b54547d9 fix rdar://8407548, I missed the commuted form of xchg/test without a suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 22:27:05 +00:00
Chris Lattner
a7f08b4970 fix wonky formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113426 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 22:22:10 +00:00
Chris Lattner
373c458850 fix bugs in push/pop segment support, rdar://8407242 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 22:13:08 +00:00
Dale Johannesen
52664c8efe Add intrinsic-based patterns for MMX PINSRW and PEXTRW. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113420 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 22:08:40 +00:00
Dale Johannesen
ab1deb998e Check in forgotten file. Should fix build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 21:09:48 +00:00
Dale Johannesen
246658f158 Slight cleanup, use only one form of MMXI_binop_rm_int. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113406 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 20:54:00 +00:00
Dale Johannesen
af4748168c Add intrinsic forms of mmx<->sse conversions. Notes: 
Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 19:15:38 +00:00
Bruno Cardoso Lopes
0a7dd4fa40 Minor change. Fix comments and remove unused and redundant code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 18:12:31 +00:00
Bruno Cardoso Lopes
1485cc2bb3 x86 vector shuffle lowering now relies only on target specific 
nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113369 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 17:43:25 +00:00
Chris Lattner
c8ae35a8e8 add support for the commuted form of the test instruction, rdar://8018260. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113352 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:51:12 +00:00
Chris Lattner
ba8e81cca2 implement proper support for sysret{,l,q}, rdar://8403907 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:45:34 +00:00
Chris Lattner
ba8cea450f implement the iret suite of instructions properly, 
fixing rdar://8403974



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:38:31 +00:00
Chris Lattner
2544f42692 add support for instruction prefixes on the same line as the instruction, 
implementing rdar://8033482 and PR7254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:17:37 +00:00
Chris Lattner
34e53140c2 change the MC "ParseInstruction" interface to make it the 
implementation's job to check for and lex the EndOfStatement
marker.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 05:10:46 +00:00
Chris Lattner
9607c40601 gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>. 
Add this to the mc assembler, fixing PR8061


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113346 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 04:53:27 +00:00
Chris Lattner
a247685b30 fix the encoding of the "jump on *cx" family of instructions, 
rdar://8061602


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 04:30:51 +00:00
Bruno Cardoso Lopes
90462b4ae1 Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 21:03:14 +00:00
Bruno Cardoso Lopes
0d1340b181 Move code around to prepare for moving some of the logic together to another function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:20:27 +00:00
Bill Wendling
d8dd5757e0 Add an MVT::x86mmx type. It will take the place of all current MMX vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:03:56 +00:00
Evan Cheng
dc0b06c815 Remove a dead comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:01:10 +00:00
Bruno Cardoso Lopes
58277b17c3 decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113247 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:41:45 +00:00
Bruno Cardoso Lopes
673bf78bb5 Remove now useless check, because the code can be matched below, no need to leave it for isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113242 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:29:03 +00:00
Bruno Cardoso Lopes
67fc1e76d4 Minor change. Since the checks are equivalent, use isMMX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113239 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:24:00 +00:00
Dale Johannesen
86097c384f Add patterns for MMX that use the new intrinsics. 
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:10:56 +00:00
Bruno Cardoso Lopes
70e81f1517 Remove unused target specific node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 17:38:55 +00:00
Benjamin Kramer
aceeb3a4e2 Don't leak the old operand when transforming "sldt" into "sldtw". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113200 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 14:40:58 +00:00
Chris Lattner
e9e0fc5eed add missing cmov aliases, this resolves rdar://8208499 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 00:05:45 +00:00
Chris Lattner
7d284de955 remove duplicated entry 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:57:24 +00:00
Chris Lattner
c5cebeb3cb "sldt <mem>" is ambiguous in 64-bit mode, but should 
always be disambiguated as sldtw.  sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact.  Force it to sldtw, resolving rdar://8017530


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:51:44 +00:00
Chris Lattner
d68c474ec5 fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:40:56 +00:00
Chris Lattner
9389b60a03 fix the operand constraints of the immediate form of in/out, 
allowing unsigned 8-bit operands.  This fixes rdar://8208481



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 23:29:05 +00:00
Chris Lattner
ce4a3355d9 in the case where an instruction only has one implementation 
of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 22:11:18 +00:00
Chris Lattner
a008e8ac73 Now that we know if we had a total fail on the instruction mnemonic, 
give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 21:54:15 +00:00
Chris Lattner
69c7249a6f simplify the hacks around jrcxz. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 20:10:12 +00:00
Chris Lattner
ec6789f4f9 have tblgen detect when an instruction would have matched, but 
failed because a subtarget feature was not enabled.  Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode.  Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.

This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 20:08:02 +00:00
Chris Lattner
79ed3f77e8 change MatchInstructionImpl to return an enum instead of bool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113165 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 19:22:17 +00:00
Chris Lattner
0692ee676f have AsmMatcherEmitter.cpp produce the hunk of code that gets included 
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 19:11:01 +00:00
Roman Divacky
436c54a186 Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 18:43:14 +00:00
Chris Lattner
47ab90bfa8 random cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-06 18:32:06 +00:00
Chris Lattner
f0f5780b39 update this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-05 20:22:09 +00:00
Chris Lattner
beac75da37 implement rdar://6653118 - fastisel should fold loads where possible. 
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-05 02:18:34 +00:00
Chris Lattner
17aa68055b zap dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 18:12:00 +00:00
Bruno Cardoso Lopes
2eb63dfa0a Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:58:56 +00:00
Bruno Cardoso Lopes
828f6ae03c make explicit that we not handle several mmx shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:50:13 +00:00
Bruno Cardoso Lopes
aace0f295b Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:36:07 +00:00
Bruno Cardoso Lopes
c800c0d25f Emit target specific nodes to handle splats starting at zero indicies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 02:02:14 +00:00
Bruno Cardoso Lopes
bbfc31012b Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113050 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 01:36:45 +00:00
Bruno Cardoso Lopes
4c827f5ae1 Emit target specific nodes for isSHUFPMask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113048 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 01:22:57 +00:00
Bruno Cardoso Lopes
d344f28b9d Previous isMOVLMask matching already emits targets nodes, remove check 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:50:08 +00:00
Bruno Cardoso Lopes
e09abcd3c4 One more check from the original isShuffleMaskLegal goes away 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113045 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:46:16 +00:00
Bruno Cardoso Lopes
b733996110 Remove a duplicated but useless check that i've inserted in the previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113044 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:43:12 +00:00
Bruno Cardoso Lopes
a22c84571a Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-04 00:39:43 +00:00
Bruno Cardoso Lopes
43c05744b5 Remove check for unpckh mask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 23:32:47 +00:00
Bruno Cardoso Lopes
ef3adb3243 Remove check for unpckl mask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 23:31:50 +00:00
Bruno Cardoso Lopes
7256e22f77 Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start 
checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 23:24:06 +00:00
Bruno Cardoso Lopes
e8f279cbd4 Reapply considered harmfull part of rr112934 and r112942. 
"Use target specific nodes instead of relying in unpckl and
unpckh pattern fragments during isel time. Also place a
depth limit in getShuffleScalarElt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 22:09:41 +00:00
Dale Johannesen
caa9ba228d Remove the rest of the nonexistent 64-bit AVX instructions. 
Bruno, please review.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 21:23:00 +00:00
Bruno Cardoso Lopes
190d0a54c1 Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113009 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:44:26 +00:00
Bruno Cardoso Lopes
2a4460606e Reintroduce a simple function refactoring done in r112934, also without any functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:20:02 +00:00
Bruno Cardoso Lopes
be8b084d8a Reapply piecies of r112942 and r112934 which don't do 
functional changes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 20:10:35 +00:00
Bruno Cardoso Lopes
b3e0669b8e Reapply Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:55:05 +00:00
Daniel Dunbar
3139422058 Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced 
some infinite loop and select failures.
 - Apologies for eager reverting, but its branch day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:11 +00:00
Daniel Dunbar
78541f258c Revert r112938 "Fix comment", which depends on r112934, which introduced some 
infinite loop and select failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:08 +00:00
Daniel Dunbar
a87ccce95b Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh 
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112998 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 19:38:05 +00:00
Bruno Cardoso Lopes
95f1e2d6b5 AVX doesn't support mm operations neither its instrinsics. 
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 02:08:45 +00:00
Bruno Cardoso Lopes
4b0c9f3e73 Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:39:08 +00:00
Bruno Cardoso Lopes
01f0847ce8 Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:28:51 +00:00
Bruno Cardoso Lopes
5e5342b0a8 - Use specific nodes to match unpckl masks. 
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 01:24:00 +00:00
Jakob Stoklund Olesen
3061c4442e Don't call Predicate_* from X86 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:18 +00:00
Anton Korobeynikov
ace53f2fbc Properly emit __chkstk call instead of __alloca on non-mingw windows targets. 
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
ed5c711a6e Move insertps mask decoding to header file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:43:39 +00:00
Anton Korobeynikov
c7c62bb3ca Revert win64 changes. They seem to be incomplete 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:31:32 +00:00
Anton Korobeynikov
2f4fad99ea Properly allocate win64 shadow reg area. 
Patch by Jan Sjodin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:16:28 +00:00
Bruno Cardoso Lopes
5594560766 Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 21:51:11 +00:00
Dan Gohman
24bde5bce1 Don't narrow the load and store in a load+twiddle+store sequence unless 
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 21:18:42 +00:00
Bruno Cardoso Lopes
6b1d0a3b36 Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 18:40:13 +00:00
Bruno Cardoso Lopes
3722f007b6 Replace unpckl_undef and unpckh_undef matching with target specific opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 05:23:12 +00:00
Bruno Cardoso Lopes
dd69db858c Move condition out to prepare for more matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 04:20:26 +00:00
Bruno Cardoso Lopes
ad10fb2b56 Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 03:57:58 +00:00
Bruno Cardoso Lopes
d00bfe1f8d become more strict about when it's safe to use X86ISD::MOVLPS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 02:35:51 +00:00
Bruno Cardoso Lopes
4783a3ee13 Revert r112689, avoid those kind of checks cause they mess up with mmx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 22:59:03 +00:00
Bruno Cardoso Lopes
29c353b9c3 Using target specific nodes for shuffle nodes makes the mask 
check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:

  movaps  (%rdi), %xmm0
  movaps  (%rax), %xmm1
  movaps  %xmm0, %xmm2
  movss %xmm1, %xmm2
  shufps  $36, %xmm2, %xmm0

now is generated as:

  movaps  (%rdi), %xmm0
  movaps  %xmm0, %xmm1
  movlps  (%rax), %xmm1
  shufps  $36, %xmm1, %xmm0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 22:33:20 +00:00
Bruno Cardoso Lopes
56098f5d26 Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 05:08:25 +00:00
Bruno Cardoso Lopes
9cfad89a68 minor change, simplify some logic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 00:57:08 +00:00
Bruno Cardoso Lopes
e654b56eb1 Move some functions around so they can be used for some other to come function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 00:51:36 +00:00
Bruno Cardoso Lopes
013bb3dee9 Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 22:35:05 +00:00
Bruno Cardoso Lopes
5023ef281c Use x86 specific MOVSHDUP node and add more patterns to match it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 22:22:11 +00:00
Jakob Stoklund Olesen
63b1dbaadd Make %EFLAGS unallocatable. 
No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 21:51:07 +00:00
Bruno Cardoso Lopes
7ff30bb1a5 Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 21:38:49 +00:00
Bruno Cardoso Lopes
f2db5b48d0 Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 21:15:21 +00:00
Bruno Cardoso Lopes
20a07f422d Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 02:26:40 +00:00
Eli Friedman
5033f64694 A couple of small missed optimizations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-29 05:07:40 +00:00
Chris Lattner
4644a936dc add a bunch more common shuffles to the instprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112397 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-29 03:08:08 +00:00
Chris Lattner
6aa928d57a I have manually decoded the imm field of an insertps one too many 
times.  This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle 
instructions which indicates the shuffle mask, e.g.:

	insertps	$113, %xmm3, %xmm0     ## xmm0 = zero,xmm0[1,2],xmm3[1]
	unpcklps	%xmm1, %xmm0    ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
	pshufd	$1, %xmm1, %xmm1        ## xmm1 = xmm1[1,0,0,0]

This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic.  I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 20:42:31 +00:00
Chris Lattner
24faf611a3 fix the buildvector->insertp[sd] logic to not always create a redundant 
insertp[sd] $0, which is a noop.  Before:

_f32:                                   ## @f32
	pshufd	$1, %xmm1, %xmm2
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm2, %xmm3
	addss	%xmm1, %xmm0
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
	insertps	$0, %xmm0, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

after:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movdqa	%xmm2, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

The extra movs are due to a random (poor) scheduling decision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 17:59:08 +00:00
Chris Lattner
3ddcc43040 fix the BuildVector -> unpcklps logic to not do pointless shuffles 
when the top elements of a vector are undefined.  This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined.  For example, on:

_Complex float f32(_Complex float A, _Complex float B) {
  return A+B;
}

We used to produce (with SSE2, SSE4.1+ uses insertps):

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$16, %xmm2, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm0
	addss	%xmm1, %xmm0
	pshufd	$16, %xmm0, %xmm1
	movdqa	%xmm2, %xmm0
	unpcklps	%xmm1, %xmm0
	ret

We now produce:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movaps	%xmm2, %xmm0
	unpcklps	%xmm3, %xmm0
	ret

This implements rdar://8368414


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 17:28:30 +00:00
Chris Lattner
6e80e44926 improve comments in the unpcklps generating logic, introduce 
a new EltStride variable instead of reusing NumElems variable
for a non-obvious purpose.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 17:15:43 +00:00
Bruno Cardoso Lopes
27f1279411 Clean up the logic of vector shuffles -> vector shifts. 
Also teach this logic how to handle target specific shuffles if
needed, this is necessary while searching recursively for zeroed
scalar elements in vector shuffle operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-28 02:46:39 +00:00
Anton Korobeynikov
c52bedba54 Properly handle passing of FP stuff to varargs function on Win64: 
value should be copied to the corresponding shadow reg as well.
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-27 14:43:06 +00:00
Daniel Dunbar
d8d36e61fd X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112250 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-27 01:30:14 +00:00
Jim Grosbach
fcb4a8ead3 Simplify eliminateFrameIndex() interface back down now that PEI doesn't need 
to try to re-use scavenged frame index reference registers. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 23:32:16 +00:00