Bill Wendling
d336de318e
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
...
(movzx/movsx) because they give more information. Revert that part of the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:46:37 +00:00
Bill Wendling
c6df9883da
Have the X86 back-end emit the alias instead of what's being aliased. In most
...
cases, it's much nicer and more informative reading the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
Bill Wendling
eef965f04b
Add an option to not print the alias of an instruction. It defaults to "print
...
the alias".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 23:36:21 +00:00
Johnny Chen
e8d087ad35
Thumb disassembler did not handle tBRIND (indirect branch) properly.
...
rdar://problem/9280370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:59:01 +00:00
Johnny Chen
6c7e4147dc
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
...
rdar://problem/9280470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:35:49 +00:00
Johnny Chen
471d73d5d3
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
...
rdar://problem/9279440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:04:32 +00:00
Cameron Zwarich
5af60ce2a8
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:01:19 +00:00
Cameron Zwarich
1335022e19
Fix a regression caused by r102515 where explicit alignment on globals is
...
ignored. There was a test to catch this, but it was just blindly updated in
a large change. This fixes another part of <rdar://problem/9275290>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 20:36:04 +00:00
Johnny Chen
9bb386a933
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
...
rdar://problem/9276651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 19:46:05 +00:00
Johnny Chen
119af20c7b
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
...
rdar://problem/9276427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 17:51:02 +00:00
Johnny Chen
6e3ccc3c85
Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387 .
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 16:56:08 +00:00
Cameron Zwarich
eb04a33dc7
Fix an obvious problem with an alignment computation. AsmPrinter actually does
...
the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 09:02:43 +00:00
Cameron Zwarich
5876db7a66
Fix a typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 06:39:16 +00:00
Cameron Zwarich
d8b88d8558
If a global variable has a specified alignment that is less than the preferred
...
alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129428 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 06:03:16 +00:00
Bill Wendling
f93f7b2446
Reapply r129401 with patch for clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 00:36:11 +00:00
Johnny Chen
55e6419b12
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
...
rdar://problem/9273947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 23:31:00 +00:00
Jakob Stoklund Olesen
836a7de159
Add @earlyclobber constraints to the writeback register of all ARM store instructions.
...
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 23:27:48 +00:00
Bill Wendling
f9b2dc66c8
Revert r129401 for now. Clang is using the old way of doing things.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129403 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 22:59:27 +00:00
Bill Wendling
d5f323d70b
Remove the unaligned load intrinsics in favor of using native unaligned loads.
...
Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.
First part of <rdar://problem/8460511>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129401 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 22:46:31 +00:00
Johnny Chen
ec51a6225c
The Thumb2 RFE instructions need to have their second halfword fully specified.
...
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 21:41:51 +00:00
Johnny Chen
32cefad4b3
Add bad register checks for Thumb2 Ld/St instructions.
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rdar://problem/9269047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 21:17:51 +00:00
Johnny Chen
f9ce2cba42
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
...
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 18:48:00 +00:00
Johnny Chen
49fdfe3ce5
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 17:09:04 +00:00
Cameron Zwarich
d0aacbcc2e
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
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stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 02:24:17 +00:00
Johnny Chen
e77f72d7d2
A8.6.16 B
...
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 00:14:49 +00:00
Johnny Chen
de16508955
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 23:33:30 +00:00
Wesley Peck
ef9d9fdde1
Fix an error in the MBlaze delay slot filler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 22:45:02 +00:00
Wesley Peck
3d820baf19
Add scheduling information for the MBlaze backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 22:31:52 +00:00
Wesley Peck
e53060fdf4
Don't crash on invalid instructions when disassembling MBlaze code.
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This fixes http://llvm.org/bugs/show_bug.cgi?id=9653
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 21:35:21 +00:00
Johnny Chen
35563fee7b
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
...
rdar://problem/9266265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 21:14:35 +00:00
Owen Anderson
78a546936d
Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 20:12:19 +00:00
Johnny Chen
f18dfc3a31
Trivial comment fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 18:51:50 +00:00
Johnny Chen
e679d3331b
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
...
invalid instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 18:34:12 +00:00
Kevin Enderby
bd3327654b
Adding support for printing operands symbolically to llvm's public 'C'
...
disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 18:08:50 +00:00
Jay Foad
562b84b3ae
Don't include Operator.h from InstrTypes.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129271 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 09:35:34 +00:00
Nicolas Geoffray
c6cf197315
Bugfix in the Cpp backend after API change on PHINode::Create.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-10 17:39:40 +00:00
Chris Lattner
15f8951799
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
...
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 19:41:05 +00:00
Matt Beaumont-Gay
7c90e46622
Fix an apparent typo that made GCC complain
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 21:59:49 +00:00
Evan Cheng
4da0c7c0c9
Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 21:37:21 +00:00
Johnny Chen
ee10b13a44
Check opcoe (dmb, dsb) instead of bitfields matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 20:03:46 +00:00
Johnny Chen
c636074afc
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
...
PR9650
rdar://problem/9257565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15
Sanity check the option operand for DMB/DSB.
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PR9648
rdar://problem/9257634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 19:18:07 +00:00
Jim Grosbach
5b03a3a59a
Mark hasExtraDefRegAllocReq=1 on LDRD.
...
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.
rdar://9244161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 18:47:05 +00:00
Johnny Chen
97fdff1d3f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
...
Add more test cases to exercise the logical branches related to the above change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 00:29:09 +00:00
Bill Wendling
44dcfd3625
Replace the old algorithm that emitted the "print the alias for an instruction"
...
with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.
There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 21:20:06 +00:00
Evan Cheng
274d8d4eba
Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 20:31:12 +00:00
Akira Hatanaka
8d580659f9
Fix indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 20:25:10 +00:00
Akira Hatanaka
3f92b439d9
Update ATUsed every time after expandRegLargeImmPair is called.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 20:23:26 +00:00
Mon P Wang
e32cdef38e
Fixed encoding for VEXTqf
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:56:12 +00:00
Akira Hatanaka
9777e7afd4
Fix handling of functions with internal linkage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:51:44 +00:00
Johnny Chen
22dc4d9f59
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
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Add some test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b
Add sanity checking for invalid register encodings for saturating instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b
Add some more comments about checkings of invalid register numbers.
...
And two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 18:33:19 +00:00
Tanya Lattner
0433b21c98
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 15:24:20 +00:00
Johnny Chen
f16f4e09ec
Sanity check MSRi for invalid mask values and reject it as invalid.
...
rdar://problem/9246844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:37:34 +00:00
Johnny Chen
8424a60fc9
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
...
for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:05:52 +00:00
Evan Cheng
2c69f8eec6
Change -arm-divmod-libcall to a target neutral option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 00:58:44 +00:00
Johnny Chen
2455268cdd
Should also check SMLAD for invalid register values.
...
rdar://problem/9246650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 00:50:25 +00:00
Owen Anderson
df298c9ea6
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 23:35:59 +00:00
Owen Anderson
ef7fb17936
Cleanups from Jim: remove redundant constraints and a dead FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129036 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:45:55 +00:00
Jim Grosbach
f22eefba68
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:35:47 +00:00
Johnny Chen
d8b4c4d74f
A8.6.393
...
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
...
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 18:27:46 +00:00
Rafael Espindola
3d195faaad
Add another case we are not optimizing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 17:35:32 +00:00
Rafael Espindola
8617897aaa
The original issue has been fixed by not doing unnecessary sign extensions.
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Change the test to force a sign extension and expose the problem again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 17:19:35 +00:00
Johnny Chen
6a1220eeca
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
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Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 01:18:32 +00:00
Owen Anderson
b48c791515
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:55:28 +00:00
Johnny Chen
2c868d1eef
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
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encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:28:00 +00:00
Bob Wilson
61f3cf3bc9
Clean up some code for clarity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:03:25 +00:00
Owen Anderson
493cba1b32
Revert r128946 while I figure out why it broke the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:03:06 +00:00
Johnny Chen
c3281c10c9
A7.3 register encoding
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Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:57:07 +00:00
Owen Anderson
76634dfabb
Give RSBS and RSCS the pseudo treatment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:42:54 +00:00
Johnny Chen
5438d76416
ARM disassembler was erroneously accepting an invalid RSC instruction.
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Added checks for regs which should not be 15.
rdar://problem/9237734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:18:07 +00:00
Johnny Chen
c584e317e9
ARM disassembler was erroneously accepting an invalid LSL instruction.
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For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:49:44 +00:00
Owen Anderson
7670601313
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:48:57 +00:00
Johnny Chen
2c2130bc64
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
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Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 20:32:23 +00:00
Johnny Chen
bbc65bbb90
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 19:42:11 +00:00
Jim Grosbach
215e4fdbf9
Make second source operand of LDRD pre/post explicit.
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Finish what r128736 started.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:40:13 +00:00
Johnny Chen
12bb2958c4
Constants with multiple encodings (ARM):
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An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:02:46 +00:00
Johnny Chen
b26d8d7c49
Check for invalid register encodings for UMAAL and friends where:
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if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 17:43:10 +00:00
Owen Anderson
15b81b51d6
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 17:24:25 +00:00
Bill Wendling
f05b1dcf87
Revamp the SjLj "dispatch setup" intrinsic.
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It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 01:37:43 +00:00
Eric Christopher
0435661582
Just use BL all the time. It's safer that way.
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Fixes rdar://9184526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:39:26 +00:00
Johnny Chen
157536b1fb
Fix SRS/SRSW encoding bits.
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rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:16:18 +00:00
Johnny Chen
597028cc28
A8.6.105 MUL
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Inst{15-12} should be specified as 0b0000.
rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 23:57:05 +00:00
Johnny Chen
670a456c83
RFE encoding should also specify the "should be" encoding bits.
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rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 23:39:08 +00:00
Joerg Sonnenberger
c15a91dfc8
Make OpcodeMask an unsigned long long literal to deal with overflow.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 21:38:17 +00:00
Johnny Chen
2d66cec9dd
Fix incorrect alignment for NEON VST2b32_UPD.
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rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
Jakob Stoklund Olesen
5fcb81dace
Insert code in the right location when lowering PowerPC atomics.
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This causes defs to dominate uses, no instructions after terminators, and other
goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes
ac79e4c82f
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
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also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:18:19 +00:00
Akira Hatanaka
f49fde2877
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen
cf3a74824f
PowerPC atomic pseudos clobber CR0, they don't read it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:09 +00:00
Jakob Stoklund Olesen
2684c5db84
Use X0 instead of R0 for the zero register on ppc64.
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The 32-bit R0 cannot be used where a 64-bit register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:06 +00:00
Joerg Sonnenberger
4a8ac8de1d
Add support for the VIA PadLock instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
229e4523f2
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
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Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 15:58:30 +00:00
Jay Foad
3e2f74e6d6
Remove some support for ReturnInsts with multiple operands, and for
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returning a scalar value in a function whose return type is a single-
element structure or array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 07:44:02 +00:00
Che-Liang Chiou
357be5e4ae
ptx: support setp's 4-operand format
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 08:51:39 +00:00
Cameron Zwarich
4071a71112
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
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registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:40:43 +00:00
Johnny Chen
04187ecd57
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
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instead of the second operand in addrmode_imm12.
rdar://problem/9225289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:24:54 +00:00
Akira Hatanaka
ad8ffad60a
Undo changes mistakenly made in revision 128750.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 00:26:12 +00:00
Akira Hatanaka
dc1652fd31
Insert space before ';' to prevent warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 00:15:58 +00:00
Johnny Chen
103bf951a4
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
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rdar://problem/9224276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
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rdar://problem/9224120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
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all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 22:32:51 +00:00
Evan Cheng
0539c159fb
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 22:09:28 +00:00
Akira Hatanaka
ad8180a0b8
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:56:02 +00:00
Akira Hatanaka
e2e436a6bc
Simplifies logic for printing target flags.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:41:06 +00:00
Owen Anderson
1721324d97
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:07:39 +00:00
Jim Grosbach
9a3507f091
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 20:26:57 +00:00
Johnny Chen
ec30f6f5e5
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
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as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 20:21:38 +00:00
Akira Hatanaka
a4485c4964
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 18:57:38 +00:00
Johnny Chen
5307da994a
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
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rdar://problem/9219356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 18:26:38 +00:00
Akira Hatanaka
20ada98de8
Add code for analyzing FP branches. Clean up branch Analysis functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 17:39:08 +00:00
Benjamin Kramer
0e3ee43ea0
Initialize HasVMLxForwarding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 09:20:31 +00:00
Evan Cheng
8e23e815ad
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
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rdar://8911343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
e3662cca5d
Remove unused variables
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes
ae0855401b
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
1db952d0c6
Provide a legal pointer register class when targeting thumb1.
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The LocalStackSlotAllocation pass was creating illegal registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:02:15 +00:00
Evan Cheng
463d358f1d
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
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accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 19:38:48 +00:00
Johnny Chen
a52d7da1d8
Fix single word and unsigned byte data transfer instruction encodings so that
...
Inst{4} = 0.
rdar://problem/9213022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 19:28:35 +00:00
Akira Hatanaka
1d6b38d9d3
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:26:17 +00:00
Johnny Chen
8901e6ff3d
Add BLXi to the instruction table for disassembly purpose.
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A8.6.23 BLX (immediate)
rdar://problem/9212921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 17:53:50 +00:00
Bruno Cardoso Lopes
b41aaab5a1
Revert r128632 again, until I figure out what break the tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:54:36 +00:00
Richard Osborne
e8f3533323
Add XCore intrinsics for initializing / starting / synchronizing threads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:13:13 +00:00
Bruno Cardoso Lopes
bcd3a9cd84
Reapply r128585 without generating a lib depedency cycle. An updated log:
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- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
e4345c9977
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
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This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 00:39:16 +00:00
Owen Anderson
6a7d36a320
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:45:29 +00:00
Evan Cheng
ee2e0e347e
Don't try to create zero-sized stack objects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:44:13 +00:00
Bruno Cardoso Lopes
40829ed6f5
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
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{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:32:32 +00:00
Cameron Zwarich
c0e6d780cd
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
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can be recognized. This fixes <rdar://problem/9183078>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:01:21 +00:00
Akira Hatanaka
81bd78b897
fixed typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 21:15:35 +00:00
Jay Foad
3ecfc861b4
Remove PHINode::reserveOperandSpace(). Instead, add a parameter to
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PHINode::Create() giving the (known or expected) number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 11:28:46 +00:00
Evan Cheng
92e3916c3b
Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
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was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.
Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.
First part of rdar://8832507, rdar://9203134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 23:06:19 +00:00
Cameron Zwarich
3007d3331b
Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes
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<rdar://problem/8875309> and <rdar://problem/9057191>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 21:41:55 +00:00
Owen Anderson
d0cfc99b30
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 20:27:38 +00:00
Johnny Chen
9eda569a74
A8.6.188 STC, STC2
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The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 19:49:38 +00:00
Owen Anderson
9eae80051b
Add safety check that didn't show up in testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 17:42:25 +00:00
Owen Anderson
848b0c39b1
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 16:45:53 +00:00
Evan Cheng
78fe9ababe
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
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isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 01:56:09 +00:00
Daniel Dunbar
a7b8c2b6a4
Integrated-As: Add support for setting the AllowTemporaryLabels flag via
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integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 22:49:19 +00:00
Johnny Chen
d560a80925
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
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Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 18:41:58 +00:00
Che-Liang Chiou
fb4a8344b6
ptx: clean up branch code a bit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 10:23:13 +00:00
Benjamin Kramer
050db52276
Make helper static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 12:38:19 +00:00
Johnny Chen
eca915fb52
Fixed the t2PLD and friends disassembly and add two test cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 01:32:48 +00:00
Eric Christopher
29aeed1bf8
Fix the bfi handling for or (and a mask) (and b mask). We need the two
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masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1 , #1
not #0 , however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 01:21:03 +00:00
Johnny Chen
a2755b9829
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
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Also add some test cases.
rdar://problem/9189829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 22:19:07 +00:00
Johnny Chen
abeea57639
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
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rdar://problem/9182892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 19:35:37 +00:00
Johnny Chen
ceceabd4b1
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
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t2LDREX/t2STREX instructions. Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 18:29:49 +00:00
Benjamin Kramer
ef7b8d9e5a
Add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:32:40 +00:00
Johnny Chen
6c3891067b
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
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rdar://problem/9184053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:31:16 +00:00
Johnny Chen
f14d5cf33a
Also need to handle invalid imod values for CPS2p.
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rdar://problem/9186136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:03:12 +00:00
Jakob Stoklund Olesen
eb5067e0d9
Ignore special ARM allocation hints for unexpected register classes.
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Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:48:18 +00:00
Johnny Chen
a7078c4f27
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
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modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:09:48 +00:00
Matt Beaumont-Gay
1866af4a98
Suppress an unused variable warning in -asserts builds
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:05:48 +00:00
Johnny Chen
c39b6271be
Handle the added VBICiv*i* NEON instructions, too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:04:39 +00:00
Johnny Chen
8cb988686d
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:42:55 +00:00
Johnny Chen
9091bf25d9
T2 Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f
Plug a leak in the arm disassembler and put the tests back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296
Add asm parsing support w/ testcases for strex/ldrex family of instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:04:58 +00:00
Johnny Chen
e6d69e7dbe
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
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Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 20:42:48 +00:00
Jim Grosbach
d31d304f83
Clean up assembly statement separator support.
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The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:46:34 +00:00
Johnny Chen
b4ac342ea0
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
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VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
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a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 17:04:22 +00:00
NAKAMURA Takumi
a2e0762fae
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
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FIXME: Some cleanups would be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 07:07:00 +00:00
Evan Cheng
d700617193
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
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entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 06:20:03 +00:00
Johnny Chen
e4000595fb
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
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Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 02:24:36 +00:00
Johnny Chen
3d793962be
Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444
The r128103 fix to cope with the removal of addressing modes from the MC instructions
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were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 00:28:38 +00:00
Devang Patel
36dca60f5c
Enable GlobalMerge on darwin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 23:34:19 +00:00
Andrew Trick
f6c39412dd
Revert r128175.
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I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 23:11:02 +00:00
Evan Cheng
2c33915628
Cmp peephole optimization isn't always safe for signed arithmetics.
...
int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0 .
rdar://9172742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:52:04 +00:00
Andrew Trick
d8fa01fbd7
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
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(target-specific branchless method for double-width relational comparisons on x86)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:16:02 +00:00
Owen Anderson
741ad15e26
The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
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This fixes 464.h264ref with the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:03:44 +00:00
Justin Holewinski
d662576671
PTX: Improve support for 64-bit addressing
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- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 16:58:51 +00:00
Johnny Chen
c59c87c322
For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
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Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 23:49:46 +00:00
Johnny Chen
27c6baeca2
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 22:28:49 +00:00
Eli Friedman
97ab5803df
A bit more analysis of a memset-related README entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:49:53 +00:00
Johnny Chen
758df29741
A8.6.399 VSTM:
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VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:00:10 +00:00
Eric Christopher
7244d7cbce
Migrate the fix in r128041 to ARM's fastisel support as well.
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Fixes rdar://9169640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 19:39:17 +00:00
Bruno Cardoso Lopes
026a42b170
Change MRC and MRC2 instructions to model the output register properly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 15:06:24 +00:00
Che-Liang Chiou
5e0872e099
ptx: add analyze/insert/remove branch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 14:12:00 +00:00
Matt Beaumont-Gay
ddb657c63d
Avoid -Wunused-variable in -asserts builds
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:37:28 +00:00
Dan Gohman
b55d6b6a7e
Fix fast-isel address mode folding to avoid folding instructions
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outside of the current basic block. This fixes PR9500, rdar://9156159.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:04:35 +00:00
Bill Wendling
a5c177e70a
We need to pass the TargetMachine object to the InstPrinter if we are printing
...
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.
This is part of a work-in-progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 04:13:46 +00:00
Eli Friedman
ddfa02ba24
This README entry was fixed recently.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 01:33:03 +00:00
Evan Cheng
485fafc840
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 01:19:09 +00:00
Daniel Dunbar
7a90e04fc7
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
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to canonicalize IR", it broke a lot of things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 21:47:14 +00:00
Evan Cheng
ae16d6b972
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
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to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 17:17:39 +00:00
Nadav Rotem
06cc324b9d
Add support for legalizing UINT_TO_FP of vectors on platforms which do
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not have native support for this operation (such as X86).
The legalized code uses two vector INT_TO_FP operations and is faster
than scalarizing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 13:09:10 +00:00
Johnny Chen
94dad03a96
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
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The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 01:16:20 +00:00
Owen Anderson
0082830cb2
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 22:50:18 +00:00
Evan Cheng
3f30af3f45
Match a few more obvious patterns to revsh. rdar://9147637.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 21:52:42 +00:00
Eli Friedman
b6192d2a9f
Revert r127852; it's apparently causing an ICE on mingw.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 21:12:29 +00:00
Owen Anderson
19f6f503d6
Clean whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 19:47:14 +00:00
Owen Anderson
099e5553eb
Reduce code duplication.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 19:46:58 +00:00
Justin Holewinski
8af78c9cf8
PTX: Fix various codegen issues
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- Emit mad instead of mad.rn for shader model 1.0
- Emit explicit mov.u32 instructions for reading global variables
- (most PTX instructions cannot take global variable immediates)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 19:24:28 +00:00
Owen Anderson
c9bd496aa2
Thumb2 PC-relative loads require a fixup rather than just an immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 17:42:55 +00:00
Joerg Sonnenberger
96622aa063
Support explicit argument forms for the X86 string instructions.
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For now, only the default segments are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:59:40 +00:00
Che-Liang Chiou
8902ecb682
ptx: fix parameter order that is reversed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:23:56 +00:00
Che-Liang Chiou
88d3367baa
ptx: add unconditional and conditional branch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:08:52 +00:00
Eli Friedman
b4b8b0cc90
Add a target-specific branchless method for double-width relational
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comparisons on x86. Essentially, the way this works is that SUB+SBB sets
the relevant flags the same way a double-width CMP would.
This is a substantial improvement over the generic lowering in LLVM. The output
is also shorter than the gcc-generated output; I haven't done any detailed
benchmarking, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 02:34:11 +00:00
Johnny Chen
5e5a40867a
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
...
Remove the offending logic and update the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 00:38:03 +00:00
Owen Anderson
670350bb78
There are two pseudos in this case that are Thumb mode, not one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 23:52:05 +00:00
Johnny Chen
e68d8ec252
It used to be that t_addrmode_s4 was used for both:
...
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 22:04:05 +00:00
Richard Osborne
11bd0784d9
Add XCore intrinsic for setpsc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 18:42:05 +00:00
Cameron Zwarich
7bbf0ee97c
Move more logic into getTypeForExtArgOrReturn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 14:53:37 +00:00
Cameron Zwarich
4457968011
Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127807 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 14:21:56 +00:00
Nick Lewycky
e27fa74d5f
Add "swi" which is an obsolete mnemonic for "svc".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 01:46:14 +00:00
Eli Friedman
3d831381a9
A couple new README entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 01:22:09 +00:00
Cameron Zwarich
ebe8173941
The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
...
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 22:20:18 +00:00
Richard Osborne
e17139b3e9
Add XCore intrinsics for setclk, setrdy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 21:56:00 +00:00
Richard Osborne
bb057453db
Add checkevent intrinsic to check if any resources owned by the current thread
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can event.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 18:34:00 +00:00
Johnny Chen
276f6f9cf9
There were two issues fixed:
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1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 22:27:33 +00:00
Bill Wendling
0d4c9d94f6
The VTBL (and VTBX) instructions are rather permissive concerning the masks they
...
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127700 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 21:15:20 +00:00
Bill Wendling
a24cb40be2
Some minor cleanups based on feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 20:47:26 +00:00
Evan Cheng
0191952296
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 18:41:52 +00:00
Richard Osborne
59f727e57e
Don't indent cases in a switch, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127681 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 15:55:30 +00:00
Richard Osborne
8ae8cf4559
On the XCore the scavenging slot should be closest to the SP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 15:10:11 +00:00
Richard Osborne
5aad8b3e78
Add XCore intrinsics for getps, setps, setsr and clrsr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:45:47 +00:00
Justin Holewinski
625eec10fe
PTX: Set PTX 2.0 as the minimum supported version
...
- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:24:15 +00:00
Duncan Sands
75548de301
Avoid a compiler warning about reg possibly being used uninitialized
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when building with assertions disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 08:41:24 +00:00
Sean Callanan
f88896b2a9
Enabled disassembler support for AVX instructions
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in the instruction tables and fixed a few bugs that
were causing decode conflicts. Rudimentary tests
are coming up in the next patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127646 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:28:15 +00:00
Sean Callanan
a21e2eae3d
X86 table-generator and disassembler support for the AVX
...
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:23:15 +00:00
Johnny Chen
085ea1b633
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
...
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:13:17 +00:00
Jim Grosbach
5edf24efac
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
...
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:30:40 +00:00
Bill Wendling
69a05a7b92
Generate a VTBL instruction instead of a series of loads and stores when we
...
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 23:02:38 +00:00
Jim Grosbach
e2189144d4
Remove some dead patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:34:35 +00:00
Evan Cheng
21a6179c9d
Indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:02:30 +00:00
Justin Holewinski
ae3ce17bac
PTX: Emit global arrays with proper sizes
...
- Emit all arrays as type .b8 and proper sizes in bytes to conform
to the output of nvcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 15:40:11 +00:00
Justin Holewinski
ba02495a57
PTX: Add support for sqrt/sin/cos intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 14:09:33 +00:00
Che-Liang Chiou
f78847ee7b
ptx: add set.p instruction and related changes to predicate execution
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 11:26:01 +00:00
Che-Liang Chiou
c2ec0f974d
ptx: add basic support of predicate execution
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-13 17:26:00 +00:00
Eric Christopher
af3dce5149
Sometimes isPredicable lies to us and tells us we don't need the operands.
...
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:09:29 +00:00
Jim Grosbach
34e98e968f
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 00:51:00 +00:00
Jim Grosbach
f859a545de
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
...
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 00:45:26 +00:00
Jim Grosbach
cea5afc985
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:25:21 +00:00
Jim Grosbach
72422d38ba
Pseudo-ize the ARM 'B' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:24:15 +00:00
Jim Grosbach
3c5edaaf59
Remove dead code. These ARM instruction definitions no longer exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:15:02 +00:00
Jim Grosbach
f219f3135d
Pseudo-ize VMOVDcc and VMOVScc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:09:50 +00:00
Jim Grosbach
b181ad3486
80 columns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:00:16 +00:00
Jim Grosbach
dd11988c99
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
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effect that we get proper instruction printing using the "pop" mnemonic for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 22:51:41 +00:00
Jim Grosbach
958108ad14
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:44:08 +00:00
Jim Grosbach
8b8515c225
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:31:17 +00:00
Jim Grosbach
1558df79b4
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:18:05 +00:00
Jim Grosbach
f0112a224f
This FIXME has been fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:07:37 +00:00
Jim Grosbach
e672ff8430
Properly pseudo-ize ARM MVNCCi.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:55:55 +00:00
Jim Grosbach
eb582d7ba2
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 18:00:42 +00:00
Chris Lattner
109d6dbe50
silence a conditional assignment -Wuninitialized warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 02:12:51 +00:00
Jim Grosbach
3906276a8d
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:09:28 +00:00
Eric Christopher
de5e101b0d
Change the x86 32-bit scheduler to register pressure and fix up the
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corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:05:58 +00:00
Jim Grosbach
d4a16ad85d
Properly pseudo-ize MOVCCr and MOVCCs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 23:56:09 +00:00
Jim Grosbach
a4f809d8db
DMB can just be a pat referencing MCR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 19:27:17 +00:00
Jim Grosbach
bc908cfcc1
Reorganize a bit. No functional change, just moving patterns up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 19:21:08 +00:00
Jim Grosbach
a768c3d45f
Pseudo-instructions are codegenonly by definition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 19:06:39 +00:00
Justin Holewinski
fca9efcbc4
PTX: Add preliminary support for floating-point divide and multiply-and-add
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 16:57:18 +00:00
Che-Liang Chiou
2f5565d21c
ptx: add the rest of special registers of ISA version 2.0
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 04:05:57 +00:00
Stuart Hastings
03d5826164
Revert 127359; it broke lencod.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 00:25:53 +00:00
Evan Cheng
b0519e15f7
Re-commit 127368 and 127371. They are exonerated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 00:16:32 +00:00
Evan Cheng
02d7c92982
Revert 127368 and 127371 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 23:53:17 +00:00
Evan Cheng
17adafc6c1
Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
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flexible.
If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 22:47:38 +00:00
Benjamin Kramer
b64b497000
Fix a pasto that broke all x86_64-elf targets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 22:07:13 +00:00
Stuart Hastings
2f26fa4838
X86 byval copies no longer always_inline. <rdar://problem/8706628>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 21:10:30 +00:00
Johnny Chen
18b475f954
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
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The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 20:01:14 +00:00
Bruno Cardoso Lopes
954dac0f88
Improve varags handling, with testcases. Patch by Sasa Stankovic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 19:22:22 +00:00
Jan Sjödin
d1cba8727a
Add createELFObjectTargetWriter method to TargetAsmBackend, which enables construction of non-standard ELFObjectWriters that can be used in MCJIT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 18:44:41 +00:00
NAKAMURA Takumi
3ca99435e9
Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 11:33:15 +00:00
Bill Wendling
620d0cc7ac
* Correct encoding for VSRI.
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* Add tests for VSRI and VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 00:33:17 +00:00
Bill Wendling
c04a9dea78
Correct the encoding for VRSRA and VSRA instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09 00:00:35 +00:00
Bill Wendling
7c6b608a7c
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
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* Update the NEON shift instruction test to expect what 'as' produces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 23:48:09 +00:00
Benjamin Kramer
c175a4bd7e
X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1.
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Found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 15:20:20 +00:00
Justin Holewinski
c6f24f4086
PTX: Add intrinsic support for ntid, ctaid, and nctaid registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 14:10:18 +00:00
Eric Christopher
7c2cdb1c05
Turn on list-ilp scheduling by default on x86 and x86-64, fix up
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testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 02:42:25 +00:00
Bob Wilson
79f56c9618
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 01:17:20 +00:00
Bob Wilson
1b772f9962
Fix comment typos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08 01:17:16 +00:00
Bill Wendling
3116dce338
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
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expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07 23:38:41 +00:00
Cameron Zwarich
be2119e8e2
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07 21:56:36 +00:00
Anton Korobeynikov
e516379d2a
ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:44:00 +00:00
Anton Korobeynikov
b3fcc06d21
In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:55 +00:00
Anton Korobeynikov
3daccd82d3
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:50 +00:00
Anton Korobeynikov
7a764168b9
Add unwind information emission for thumb stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:43 +00:00
Anton Korobeynikov
7503fcb890
Handle MI flags inside Thumb2SizeReduction pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:38 +00:00
Anton Korobeynikov
57caad7a33
Preliminary support for ARM frame save directives emission via MI flags.
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This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:32 +00:00
Anton Korobeynikov
b5e16af9ea
Some first rudimentary support for ARM EHABI: print exception table in "text mode".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:15 +00:00
Bob Wilson
4faa0e1952
Remove unused conditional negate operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 16:54:31 +00:00
Che-Liang Chiou
0df2c50c2b
ptx: add basic intrinsic support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 14:17:37 +00:00
Andrew Trick
e0ef509aeb
Increased the register pressure limit on x86_64 from 8 to 12
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regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 08:00:22 +00:00
Andrew Trick
8d4a422513
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 06:31:54 +00:00
Bill Wendling
0546f7396a
Initialize variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 21:38:47 +00:00
Bruno Cardoso Lopes
38b5e86b9c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
99027d76f3
Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:48:08 +00:00
Bruno Cardoso Lopes
c42fb5f81c
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:27:44 +00:00
Bruno Cardoso Lopes
ca8a2aa921
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
49eaf76c53
Fix an old copy-n-paste
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127020 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 19:20:24 +00:00
Devang Patel
53dc40a45f
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 19:11:05 +00:00
Bruno Cardoso Lopes
5d6fb5db90
Expands FCOS and FSIN nodes when type is f64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 18:54:14 +00:00
Bruno Cardoso Lopes
911a992c33
Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes
81092dc20a
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 17:51:39 +00:00
Kalle Raiskila
31cbac1cfe
Allow vector shifts (shl,lshr,ashr) on SPU.
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There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 13:19:18 +00:00
Kalle Raiskila
7f5de8b4c6
Allow load from constant on SPU.
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A 'load <4 x i32>* null' crashes llc before this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 12:00:11 +00:00
Eli Friedman
ac39bd534b
PR9377: Handle x86 str with register operand in a way consistent with gas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 00:10:17 +00:00
Bob Wilson
58f04fd22a
PR8053: Fix encoding of S bit in some ARM instructions.
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Patch by Zonr Chang!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 23:07:15 +00:00
Richard Osborne
022708f221
Optimize fprintf -> iprintf if there are no floating point arguments
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and siprintf is available on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 14:20:22 +00:00
Justin Holewinski
43b4e23bac
PTX: Fix Emacs renaming a symbol
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 14:09:40 +00:00
Richard Osborne
419454ad37
Optimize sprintf -> siprintf if there are no floating point arguments
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and siprintf is available on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 14:09:28 +00:00
Justin Holewinski
12785e87e8
PTX: Fix a couple of lint violations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 13:34:29 +00:00
Richard Osborne
3649824bec
Optimize printf -> iprintf if there are no floating point arguments
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and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 13:17:51 +00:00
Tilmann Scheller
49d7999b89
Use X86_thiscall calling convention for Win64 as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 07:49:07 +00:00
Bob Wilson
acc9e7315c
Add a readme entry for the redundant movw issue for pr9370.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126930 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 06:39:09 +00:00
Bob Wilson
181d3fe727
pr9367: Add missing predicated BLX instructions.
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Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03 01:41:01 +00:00
Kevin Enderby
d39647d913
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
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Patch by Ted Kremenek!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 23:08:33 +00:00
Renato Golin
e89a05337a
Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 21:20:09 +00:00
Tilmann Scheller
f1cc70ca93
Add Win64 thiscall calling convention.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 19:29:22 +00:00
David Greene
a20244d1ba
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
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missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 17:23:43 +00:00
Che-Liang Chiou
31c488c8bd
ptx: fix lint and compiler warnings
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 07:58:46 +00:00
Che-Liang Chiou
f48817cbf9
Add 64-bit addressing to PTX backend
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- Add '64bit' sub-target option.
- Select 32-bit/64-bit loads/stores based on '64bit' option.
- Fix function parameter order.
Patch by Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 07:36:48 +00:00
Che-Liang Chiou
fd8978b021
Extend initial support for primitive types in PTX backend
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- Allow i16, i32, i64, float, and double types, using the native .u16,
.u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.
Patch by Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 03:20:28 +00:00
Duncan Sands
c92cb649e3
Add datalayout information for the IEEE quad precision fp128 type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 20:56:50 +00:00
Bill Wendling
a656b63ee4
Narrow right shifts need to encode their immediates differently from a normal
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:00:59 +00:00
Chris Lattner
d3e768ecab
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 00:24:51 +00:00
Renato Golin
728ff0db78
Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 22:04:27 +00:00
Kevin Enderby
4da434cd40
Add missing whitespace in the formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 21:45:12 +00:00
Chris Lattner
99825b4455
fix a signed comparison warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 20:50:35 +00:00
David Greene
c4db4e5105
[AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit
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and 256-bit forms. Because the number of elements in a vector
does not determine the vector type (4 elements could be v4f32 or
v4f64), pass the full type of the vector to decode routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 19:06:56 +00:00
Kevin Enderby
d436d5b1c9
Fix the arm's disassembler for blx that was building an MCInst without the
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needed two predicate operands before the imm operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 18:46:31 +00:00
Evan Cheng
c24ab5c654
Fix a typo which cause dag combine crash. rdar://9059537.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 18:45:27 +00:00
Stuart Hastings
f222e595c0
Support for byval parameters on ARM. Will be enabled by a forthcoming
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patch to the front-end. Radar 7662569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 17:17:53 +00:00
Kalle Raiskila
2d25d247bd
Add branch hinting for SPU.
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The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 14:08:24 +00:00
Che-Liang Chiou
f71720231f
Add preliminary support for .f32 in the PTX backend.
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- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
to accept the float type.
- Add appropriate test cases.
Patch by Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 06:34:09 +00:00
Benjamin Kramer
9e9bb0871d
Silence enum conversion warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27 18:13:53 +00:00
NAKAMURA Takumi
419f232783
Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.
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It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27 08:47:19 +00:00
Benjamin Kramer
7466678003
Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
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1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible
It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-26 22:48:07 +00:00
Owen Anderson
95771afbfd
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 21:41:48 +00:00
Cameron Zwarich
f754f50805
Roll out r126425 and r126450 to see if it fixes the failures on the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 16:30:32 +00:00
Bob Wilson
da52506792
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 06:42:42 +00:00
Evan Cheng
9831f2d585
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 01:29:29 +00:00
Evan Cheng
acca09bd64
Each prologue may have multiple vpush instructions to store callee-saved
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D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.
Sorry, can't reduce a small test case.
rdar://9043312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 00:24:46 +00:00
Chris Lattner
12d18a07a0
remove command line option debugging hook.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 21:53:03 +00:00
Devang Patel
f410608271
Enable DebugInfo support for COFF object files.
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Patch by Nathan Jeffords!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 21:04:00 +00:00
Richard Osborne
21d7eb3f3b
Add XCore intrinsic for eeu instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 13:39:18 +00:00
Evan Cheng
7558e2e415
Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory
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operands starts at index 2, not 1.
rdar://9045024
PR9305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 02:36:52 +00:00
Richard Osborne
d04b4937d1
Add XCore intrinsic for clre instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 18:52:05 +00:00
Richard Osborne
9935bd0819
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
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events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 18:35:59 +00:00
Richard Osborne
292f62e06f
Add XCore intrinsic for the setv instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 16:46:37 +00:00
Richard Osborne
2254d0eaa1
Fix format for setc instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 15:20:16 +00:00
Richard Osborne
2a2cb28526
Add XCore intrinsic for settw instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 14:45:03 +00:00
Evan Cheng
2b943566f3
Change VFPNeonA8 definition to make the code easier to read.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 02:35:33 +00:00
Evan Cheng
e573fb3255
More fcopysign correctness and performance fix.
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The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 02:24:55 +00:00
David Greene
fbf05d32b4
[AVX] General VUNPCKL codegen support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 23:31:46 +00:00