6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-01 11:49:58 +00:00
Code Issues Projects Releases Wiki Activity
11,330 Commits 9 Branches 121 Tags 498 MiB
42ba6d1281
Commit Graph

1490 Commits

Author SHA1 Message Date
Thomas Harte
beca7a01c2 Treat a phase mismatch as ending DMA. 2022-09-15 16:34:06 -04:00
Thomas Harte
2d8e260671 Take a shot at the phase mismatch IRQ. 2022-09-15 16:24:06 -04:00
Thomas Harte
04f5d29ed9 Improve logging, factor out phase_matches per TODO comment. 2022-09-15 16:14:14 -04:00
Thomas Harte
df29a50738 Attempt to support the DMA interface. 2022-08-31 15:33:48 -04:00
Thomas Harte
ea4bf5f31a Provide card's SCSI ID. 2022-08-23 15:05:36 -04:00
Thomas Harte
8f2e94a1d8 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
Thomas Harte
bf03bda314 Generalise AsyncTaskQueue, DeferringAsyncTaskQueue and AsyncUpdater into a single template. 2022-07-14 16:39:26 -04:00
Thomas Harte
55af6681af Avoid unnecessary get_port_input calls. 2021-11-24 17:15:48 -05:00
Thomas Harte
2a7a42ff8f Add header for assert. 2021-11-24 16:28:18 -05:00
Thomas Harte
0ad1529f3f Retain delegate bit length for non-self-clocked data. 2021-11-24 16:15:27 -05:00
Thomas Harte
0df8173536 Merge branch 'master' into Amiga 2021-11-24 08:58:03 -05:00
Thomas Harte
f5d3d6bcea Splits the lowpass filter into push and pull variants. 2021-11-21 15:37:29 -05:00
Thomas Harte
4fc25fb798 Adds basic shift input. 2021-11-07 05:18:54 -08:00
Thomas Harte
941d9a46a2 Makes a better effort at exposition; better implements clocked line. 2021-11-07 05:18:40 -08:00
Thomas Harte
ecfe68d70f Introduce the principle that a Serial::Line can be two-wire — clock + data. 2021-11-06 16:54:20 -07:00
Thomas Harte
f102d8a4b4 Extend to allow full-[byte/word/dword] writes, in LSB or MSB order. 2021-11-06 12:01:32 -07:00
Thomas Harte
6d34432988 Starts to build in a serial line for input. 2021-11-04 18:54:28 -07:00
Thomas Harte
b827b9e33e Add necessary shift storage. 2021-11-03 19:26:45 -07:00
Thomas Harte
29e5ecc282 Add TODOs rather than complete stop on shift register acccesses. 2021-11-02 18:19:31 -07:00
Thomas Harte
9ecd43238f Correct 8520 TOD setting and getting. 2021-10-30 12:02:43 -07:00
Thomas Harte
5ffe71346c Eliminate interrupt magic constants. 2021-10-29 19:04:06 -07:00
Thomas Harte
d9d20d9d30 Walk back slightly. 2021-10-14 18:02:58 -07:00
Thomas Harte
689bfbbdb3 Be overt in initialiser list. 2021-10-14 16:57:26 -07:00
Thomas Harte
eb157f15f3 Adds index hole interrupt. 2021-10-09 04:08:59 -07:00
Thomas Harte
73e45511dc Add missing #include. 2021-10-04 05:26:38 -07:00
Thomas Harte
e47eab1d40 Merge branch 'master' into Amiga 2021-09-14 20:27:59 -04:00
Thomas Harte
dfcd1508c9 Establishes valid initial BRAM. 2021-09-10 19:56:20 -04:00
Thomas Harte
0ca4631279 Switch to zero-initialised state; be more careful about resetting data. 2021-09-09 23:08:13 -04:00
Thomas Harte
a6221ca322 Reload data only if an output is found. 2021-09-09 22:07:03 -04:00
Thomas Harte
f8380d2d4c Add 8250 feature of 'count, regardless'. 2021-08-08 22:32:41 -04:00
Thomas Harte
1f9e41e9cb Ensure TOD isn't firing from power-on. 2021-08-08 18:51:58 -04:00
Thomas Harte
98bd6fc240 Adds a further logging hint. 2021-08-06 23:16:06 -04:00
Thomas Harte
b9f78f5d33 Fix final timer B test. 2021-08-03 22:27:23 -04:00
Thomas Harte
b4ec9d70da Adds the CNT input. 2021-08-03 22:19:41 -04:00
Thomas Harte
dd91d793d9 Correct typo. 2021-08-03 21:45:44 -04:00
Thomas Harte
8e51e8eb77 Does just a touch of 6526 TOD work. 2021-08-03 21:13:08 -04:00
Thomas Harte
6210605bc7 Transfers full TOD responsibility onto the chip-specific templates. 2021-08-03 19:10:09 -04:00
Thomas Harte
0245b040b0 Splits TOD storage by model. 
TOD storage will probably end up being a full-on class.
 2021-08-03 18:50:58 -04:00
Thomas Harte
8795719c18 This counts reloads, most accurately. 2021-08-03 17:12:08 -04:00
Thomas Harte
6bbbf43341 At least attempts to chain correctly. 2021-08-03 17:03:58 -04:00
Thomas Harte
ee6039bfa5 Writes to a timer _during reload_ now have effect. 
Net: one CIA test passed.
 2021-08-03 16:57:05 -04:00
Thomas Harte
ef58ce6277 Gets a bit more rigorous about the clocking stage. 
Albeit without advancing relative to the test.
 2021-08-02 21:04:00 -04:00
Thomas Harte
15de5e98c4 Adds [partial] test for whether counters are linked. 2021-08-02 20:17:37 -04:00
Thomas Harte
38848ca2db Rationalises reload logic and cuts storage. 
Failure point is now chaining, I think.
 2021-08-02 20:14:01 -04:00
Thomas Harte
77c627e822 Ensure that reading the interrupt flags really clears the master bit. 
Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.
 2021-08-02 07:47:08 -04:00
Thomas Harte
c640132699 Reinstates clocking. 2021-08-01 21:35:08 -04:00
Thomas Harte
57dd38aef2 Reintroduces reload-on-off, adds interrupt delay. 2021-08-01 21:09:02 -04:00
Thomas Harte
460a6cb6fe Attempts a more literal implementation. 2021-08-01 18:14:10 -04:00
Thomas Harte
3d160ce85f Add another potential warning. 2021-07-30 18:21:38 -04:00
Thomas Harte
759007ffc1 Attempts to route CIA interrupts. 2021-07-28 19:36:30 -04:00
Thomas Harte
37a55c3a77 Corrects 6526 interrupt control write. 
This seems to imply that the 6526 should be interrupting too.
 2021-07-28 19:26:02 -04:00
Thomas Harte
bcb7bb5cce Improves logging further. 
To investigate the new perpetual loop.
 2021-07-26 17:02:30 -04:00
Thomas Harte
34d4420e8c Correct reading of top byte of counter 2. 2021-07-25 20:41:15 -04:00
Thomas Harte
fcd6b7b0ea Takes further aim at the conters. 
I think test cases are needed, probably.
 2021-07-24 16:06:49 -04:00
Thomas Harte
ceca32ceb3 Takes a guess at one-shot mode. 2021-07-24 15:53:18 -04:00
Thomas Harte
77a8ddb95c Edges towards working counters. 2021-07-23 22:43:47 -04:00
Thomas Harte
c733a4dbf8 Beefs up interrupt awareness. 2021-07-23 21:58:52 -04:00
Thomas Harte
d898a43dff Implements time-of-day counters, provisionally. 
Interrupts to do.
 2021-07-23 21:24:07 -04:00
Thomas Harte
6123349b79 Stubs in control registers and disables exit-on-miss. 
I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.
 2021-07-22 19:28:01 -04:00
Thomas Harte
56b62a5e49 Adds a dummy interrupt control register. 2021-07-22 16:09:32 -04:00
Thomas Harte
a030d9935e Adds port input. 2021-07-18 20:25:04 -04:00
Thomas Harte
c425dec4d5 Makes some attempt to get as far as the overlay being disabled. 2021-07-18 17:17:41 -04:00
Thomas Harte
67d53601d5 Latch and return data direction. 
Albeit with no port-handling effect yet.
 2021-07-18 12:23:47 -04:00
Thomas Harte
622cca0acf Adds sufficient address decoding to print a more helpful exit message. 2021-07-18 12:13:56 -04:00
Thomas Harte
48999c03a5 Adds concept of time, captured port handler. 2021-07-18 11:49:10 -04:00
Thomas Harte
377cc7bdcd Start to introduce a 6526/8250. 2021-07-18 11:36:13 -04:00
Thomas Harte
a5d0976c2d Eliminate unused #includes. 2021-07-18 11:35:57 -04:00
Thomas Harte
ae05010255 Improve indentation. 2021-07-18 11:29:26 -04:00
Thomas Harte
66cacbd0e0 Be overt about the type being supplied. 2021-07-18 11:28:18 -04:00
Thomas Harte
c8699d9770 Correct Disk II sleeping test to allow for spin-down. 2021-07-16 17:12:57 -04:00
Thomas Harte
69c0734975 WD1770: switch motor on even if spin-up is disabled. 2021-06-21 23:26:55 -04:00
Thomas Harte
1d5144b912 Correct no-interrupt signal. 2021-06-04 22:38:07 -04:00
Thomas Harte
b7a62e0121 Adds SZX support. 
Tweaking exposed Spectrum state object as relevant.
 2021-04-26 20:47:28 -04:00
Thomas Harte
3348167c46 Ensures AY registers are conveyed. 2021-04-26 17:39:11 -04:00
Thomas Harte
73c8157197 Retain 6850 time tracking at all times. 2021-04-20 22:26:43 -04:00
Thomas Harte
af1dc2d3b2 Switches to correct non-value sentinel. 2021-04-20 21:56:58 -04:00
Thomas Harte
1266bbb224 Makes the TMS a sequence-point-generating JustInTimeActor. 2021-04-05 21:02:37 -04:00
Thomas Harte
8a11a5832c Uses GI::AY38910::Utility far and wide. 2021-03-26 23:19:47 -04:00
Thomas Harte
f37f89a7d3 Merge branch 'master' into ZXSpectrum 2021-03-21 22:44:37 -04:00
Thomas Harte
58be770eaa Factors out some boilerplate. 
When I'm confident this is correct, I can fix up the other call sites.
 2021-03-21 00:14:48 -04:00
Thomas Harte
650b9a139b Tweak Master System blue scale. 2021-03-19 08:38:21 -04:00
Thomas Harte
6839e9e3b3 Ensures no double definition of NDEBUG. 2021-03-07 12:52:54 -05:00
Thomas Harte
86fd47545d Silences. 2021-03-03 20:51:33 -05:00
Thomas Harte
71a107fe75 Silences the IWM again, for now. 2021-02-23 21:57:19 -05:00
Thomas Harte
a3e98907ca Removes temporary printf. 2021-02-14 21:03:54 -05:00
Thomas Harte
ee5f45c979 Merge branch 'master' into AppleIIgs 2020-12-29 22:16:23 -05:00
Thomas Harte
dfe4e49110 Ensure proper in-memory ordering of the b72a2c70 ROM. 2020-12-29 22:08:48 -05:00
Thomas Harte
8ace258fbc Tackles outstanding GCC warnings. 2020-11-22 21:43:56 -05:00
Thomas Harte
9b45c5a1cd Resolves out-of-bounds reads. 2020-11-21 22:36:10 -05:00
Thomas Harte
4a42de4f18 Attempts to add 5.25" drive support to the IIgs. 
I want to try some classic software.
 2020-11-20 21:37:17 -05:00
Thomas Harte
98347cb1c3 Starts in the direction of audio support. 2020-11-18 18:39:11 -05:00
Thomas Harte
cddd72876f Flips meaning of ejected bit, to please the IIgs. 2020-11-18 17:20:48 -05:00
Thomas Harte
37815a982a Much logging later, corrects 7Mhz IWM windows. 
Confirmed by mathematics — the new ones are seven-eighths the length of the established 8Mhz windows — and with reference to suitable Apple documentation.
 2020-11-13 22:05:45 -05:00
Thomas Harte
b0fc2f6ecf Amps up logging. 
Current suspicion is that the IIgs isn't getting a clean byte stream, never mind whether my assumption of exactly-Mac-style GCR holds (which it probably doesn't).
 2020-11-12 21:54:54 -05:00
Thomas Harte
81969bbea9 Improves logging, at least for now. 2020-11-12 21:17:14 -05:00
Thomas Harte
1f5908dc51 Corrects logging output. 2020-11-11 20:26:04 -05:00
Thomas Harte
72884c3ead Does a better job of shifting output; takes a new guess at the no-receiver case. 
ROM03 at least now reaches "check startup device!"
 2020-11-11 20:19:35 -05:00
Thomas Harte
80358cf5bd Shift output even if nobody is listening. 2020-11-11 20:04:48 -05:00
Thomas Harte
6d511f01a4 Ensures intended no-drive behaviour; no more risks with dangling pointers or nullptr. 2020-11-11 17:54:21 -05:00
Thomas Harte
6d3d7c6006 It seems like this fix is no longer needed. 2020-11-11 17:30:22 -05:00
Thomas Harte
03d1aff6c0 Fixes 8-bit read/write. 2020-10-30 22:17:55 -04:00
Thomas Harte
034056d0cd Adds full 8-bit clock addressing; stubs clock into the IIgs. 2020-10-29 21:38:36 -04:00
Thomas Harte
1249fb598b Factors Apple's RTC out of the Macintosh. 2020-10-29 21:03:02 -04:00
Thomas Harte
9447aa38be Removes debugging printf. 2020-09-22 22:13:54 -04:00
Thomas Harte
022ec20e75 Tries to add semantic meaning to the various auxiliary control fields. 
To consider: decoding at set?
 2020-09-22 20:50:39 -04:00
Thomas Harte
41f69405d8 Don't decrement timer 1 from the system clock when in PB6 mode. 
TODO: rest of PB6 mode.
 2020-09-21 22:39:49 -04:00
Thomas Harte
8e242eea54 Ensures timer-linked PB7 output is actually output. 2020-09-20 15:03:26 -04:00
Thomas Harte
703065a0a5 Takes a run at timer-linked PB7 output behaviour. 
Seemingly sufficiently to pass the VICE test (which I've transcribed), though with some guesswork.
 2020-09-20 14:51:59 -04:00
Thomas Harte
e807a462a1 My new reading is that only a write to the counter should affect the interrupt flag. 2020-09-17 21:31:29 -04:00
Thomas Harte
18790a90ae Ensures timer 2 doesn't use timed behaviour when in pulse mode. 2020-09-17 21:09:32 -04:00
Thomas Harte
21afc70261 Adds formal data-sheet names. 2020-09-17 19:00:46 -04:00
Thomas Harte
a17d0e428f Protects against some further uninitialised values. 2020-09-16 18:15:57 -04:00
Thomas Harte
bb57f0bcc7 Ensures all 6560 properties have a valid default value. 2020-09-16 17:24:18 -04:00
Thomas Harte
fa95a17af5 Resolves receive_bit_count-unused warnings. 2020-07-24 21:59:27 -04:00
Thomas Harte
8aeebdbc99 Remove redundant comment. 2020-07-16 23:26:45 -04:00
Thomas Harte
1288369865 Merge branch 'master' into FurtherSCC 2020-07-11 23:54:40 -04:00
Thomas Harte
2477752fa4 Adds further [[fallthrough]] attributes. 2020-06-19 23:36:51 -04:00
Thomas Harte
3cb1072c29 Adds an explicit [[fallthrough]] tag. 2020-06-19 23:10:25 -04:00
Thomas Harte
d64b4fbc26 Adds a Qt timer class. Precision seems to be 'acceptable'. 2020-05-31 23:39:08 -04:00
Thomas Harte
73131735fa Further qmake warning corrections. 2020-05-30 19:31:17 -04:00
Thomas Harte
48afc54af6 Cuts down unused parameter warnings to just a few that may well indicate implementation errors. 2020-05-30 01:06:43 -04:00
Thomas Harte
267006782f Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
Thomas Harte
512a52e88d Increases const correctness, marks some additional constructors as constexpr, switches std::atomic construction style. 2020-05-20 23:34:26 -04:00
Thomas Harte
66c2eb0414 Further tightens const and constexpr usage. 2020-05-12 22:22:21 -04:00
Thomas Harte
9458963311 Factors out shift by 7. 2020-05-10 13:57:50 -04:00
Thomas Harte
44690b1066 Halves effect of vibrato. 2020-05-10 12:05:14 -04:00
Thomas Harte
64c62c16fb Adjusts tremolo scale. 2020-05-10 00:43:46 -04:00
Thomas Harte
afef4f05fe Adds damping and phase resets for the rhythm section. 2020-05-10 00:10:51 -04:00
Thomas Harte
25996ce180 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
Thomas Harte
31c6faf3c8 Adds a bunch of consts. 2020-05-09 21:23:52 -04:00
Thomas Harte
40b60fe5d4 Renames folder as per intended scope. 2020-05-09 18:04:11 -04:00
Thomas Harte
eed357abb4 Introduces concept of 'average peak volume' in order better to normalise audio sources like the OPLL. 2020-05-09 17:57:21 -04:00
Thomas Harte
8f541602c1 Moves modulator updates a sample behind operator updates. 2020-05-08 21:14:25 -04:00
Thomas Harte
668f4b77f3 Implements feedback. 2020-05-08 21:05:23 -04:00
Thomas Harte
303965fbb8 Removes the crutch of my first-attempt implementation. 2020-05-08 20:53:34 -04:00
Thomas Harte
792aed242d Fixes the use-sustain flag. 2020-05-08 20:49:39 -04:00
Thomas Harte
dc5654b941 Attempts to implement the proper attack phase. 
It's sounding pretty good now, but for sustain.
 2020-05-08 18:59:05 -04:00
Thomas Harte
e51e2425cc Attempts to implement decay and release the right way around and with full precision. 
Higher numbers = decay/release more quickly, not more slowly.
 2020-05-08 18:40:49 -04:00
Thomas Harte
95c6b9b55d Declare proper envelope precision. 2020-05-08 17:58:50 -04:00
Thomas Harte
ea25ead19d Ensures rhythm envelope generators don't pick up should_damp state. 2020-05-08 00:18:31 -04:00
Thomas Harte
24100ec3b0 Switches snare and high-hat envelope generators. 2020-05-08 00:08:14 -04:00
Thomas Harte
32437fbf8b Attempts to use the proper rhythm mode envelope generators. 2020-05-07 23:56:15 -04:00
Thomas Harte
5219a86a41 In principle fully implements rhythm mode. 2020-05-07 23:38:51 -04:00
Thomas Harte
e12dc5d894 Reduce the amount of time spent installing instruments. 2020-05-06 00:15:28 -04:00
Thomas Harte
75315406bb Ensure all channels begin in 'release' phase, which is currently code for 'off' in conjunction with attenuation of 511. 2020-05-06 00:13:01 -04:00
Thomas Harte
ea42fe638a Corrects channel attenuation and carrier sustain level settings. 2020-05-05 23:41:15 -04:00
Thomas Harte
744211cec0 Ensures rhythm instruments are installed. 2020-05-05 23:13:13 -04:00
Thomas Harte
1a4321d7d0 Attempts better to balance attenuations. 2020-05-05 22:14:11 -04:00
Thomas Harte
b943441901 Marks up more specific TODOs. 
I think I'm already much happier with this factoring.
 2020-05-05 00:35:03 -04:00
Thomas Harte
0505b82384 Restores top bit of channel period, propagates it to the envelope generator. 2020-05-05 00:28:24 -04:00
Thomas Harte
c9fb5721cd Makes first attempt to reintroduce full-melodic output. 2020-05-05 00:16:45 -04:00
Thomas Harte
386a7ca442 Continues doing away with the attempt heavily to interleave the OPLL and OPL2, creating a new OPLL class. 2020-05-04 21:14:51 -04:00
Thomas Harte
e929d5d819 Ensures proper dereferencing of the std::optional. 2020-05-03 21:57:15 -04:00
Thomas Harte
94614ae4c3 Shifts the LFO implementation inline. 2020-05-03 21:44:22 -04:00
Thomas Harte
1223c99e0f Adds waveform generation logic to the new factoring. 2020-05-03 21:38:20 -04:00
Thomas Harte
1ff5ea0a6e Adds KeyLevelScaler, implements EnvelopeGenerator, adds reset to PhaseGenerator. 2020-05-03 16:24:55 -04:00
Thomas Harte
9d2691d1d2 Taking it as given that outstanding deficiencies are mostly due to poor design, starts breaking out the envelope and phase generators. 2020-05-01 23:46:42 -04:00
Thomas Harte
e4ef2c68bb Feeds through drum volume levels. 2020-04-30 19:35:09 -04:00
Thomas Harte
7fffafdfd4 Wires the high-hat through, possibly incorrectly. 2020-04-29 22:44:15 -04:00
Thomas Harte
c4135fad2b Attempts completely to decouple updates and audio outputs. 2020-04-29 22:07:40 -04:00
Thomas Harte
9f0c8bcae7 Attempts to add the missing noise generators. I think I may still be astray on volumes. 2020-04-26 15:51:33 -04:00
Thomas Harte
2bc36a6cde Eliminates branch within snare output. 2020-04-26 00:21:15 -04:00
Thomas Harte
ee10fe3d2c Fully separates updates and outputs in operators; takes a shot at the snare. 2020-04-26 00:18:09 -04:00
Thomas Harte
a424e867f9 Continues factoring this apart, albeit with a decision on whether to retain update-and-output still pending. 2020-04-25 23:07:40 -04:00
Thomas Harte
f52b40396a Re-ups output level. 
Though it's still quiet compared to the SN.
 2020-04-25 23:07:06 -04:00
Thomas Harte
cd2ab70a58 Moves the LFSR to the LowFrequencyOscillator. 
Possibly I should come up with a better name for that?
 2020-04-25 22:21:42 -04:00
Thomas Harte
65a3783dd2 Attempts the tom tom. 2020-04-25 19:21:55 -04:00
Thomas Harte
b9b5c2a3bc Takes a first run at proper slot mixing and the bass drum. 2020-04-25 18:01:05 -04:00
Thomas Harte
12c618642e Corrects output range. 2020-04-25 00:07:58 -04:00
Thomas Harte
6ebc93c995 Switches to maximum-rate multiplexing. Hopefully to eliminate the mixer as a consideration for now. 2020-04-24 23:50:06 -04:00
Thomas Harte
6d4e29c851 Strips mixer back to basics in search of audio issues. 2020-04-24 23:32:02 -04:00
Thomas Harte
b3979e2fda Looking towards rhythm mode, and in search of bugs: factors out ADSR. 
Further factorings to come.
 2020-04-24 18:48:32 -04:00
Thomas Harte
983c32bf75 Adds vibrato. 
This would complete melodic output, subject to bug fixes.
 2020-04-24 18:02:41 -04:00
Thomas Harte
9e3614066a Adds tremolo support, switches to global timer for ADSR stages other than attack. 2020-04-23 23:55:49 -04:00
Thomas Harte
c7ad6b1b50 Minor layout and commenting improvements. 2020-04-21 23:35:48 -04:00
Thomas Harte
676dcf7fbb Calculates the proper key scale rate, though ADSR itself is still lacking that precision. 2020-04-21 22:57:56 -04:00
Thomas Harte
50d725330c Adds missing header. 2020-04-21 22:48:52 -04:00
Thomas Harte
2886dd1dae Collapses key-level scaling to a single 2d table. 
I dare imagine I can do better; the columns in particular look like arithmetic progressions.
 2020-04-21 20:19:02 -04:00
Thomas Harte
40424ac38b Re-enables key-level scaling, with 3db and 1.5db the correct way around. 2020-04-21 20:10:40 -04:00
Thomas Harte
a4d3865394 Decreases sustain level attenuation; disables key-level scaling for now. 
The latter was definitely wrong, I also think I don't need the big four tables.
 2020-04-21 19:58:40 -04:00
Thomas Harte
bdce1c464a Takes a shot at key-level scaling. Testing to come. 2020-04-21 00:09:42 -04:00
Thomas Harte
475d75c16a Preserves fractional part of modulator phase. 2020-04-20 23:35:37 -04:00
Thomas Harte
32fd1897d0 Via a unit test, confirms and fixes relative volumes of OPLL channels. 
Also rejigs responsibility for scaling to emulator-standard volume.
 2020-04-20 23:17:29 -04:00
Thomas Harte
f19fd7c166 Pulls out common melodic update calls. 2020-04-20 18:58:31 -04:00
Thomas Harte
100fddcee1 Corrects divider, takes another whack at ADSR. 2020-04-20 18:58:10 -04:00
Thomas Harte
99fa86a67e Adds a test for lookup sine. And fixes lookup sine. 2020-04-20 18:40:47 -04:00
Thomas Harte
6568c29c54 Improves commentary. 2020-04-19 22:42:25 -04:00
Thomas Harte
c54bbc5a04 Rename Table.h; LogSin -> LogSign and make it a bit more typer. 2020-04-19 13:33:17 -04:00
Thomas Harte
92d0c466c2 Moves complete phase -> output calculation inside Operator. 
Reasoning being: otherwise I wasn't currently enforcing non-sine waveforms.
 2020-04-19 13:27:24 -04:00
Thomas Harte
020c760976 Simplifies the phase counter. 2020-04-19 00:30:14 -04:00
Thomas Harte
cdfd7de221 Minor: enables all melodic channels when rhythm mode is disabled; supports non-modulated channels. 2020-04-18 17:48:29 -04:00
Thomas Harte
3da2e91acf Adjusts range of output, makes declaration of level full owner of type information. 2020-04-17 23:29:09 -04:00
Thomas Harte
3948304172 Attempts to use table-based maths. 2020-04-17 23:23:16 -04:00
Thomas Harte
4a295cd95e Wraps log_sin in an access function to enshrine sign and mask rules; switches both functions to non-math.h clashing names. 2020-04-17 23:22:42 -04:00
Thomas Harte
6f7c8b35c5 Applies an ahead-of-time transformation to the exp table, and wraps it in a helper function. 2020-04-17 22:33:13 -04:00
Thomas Harte
e58ba27c00 Clarifies meaning of scaling. Though it isn't yet applied. 2020-04-17 22:30:10 -04:00
Thomas Harte
0aceddd088 Starts tidying up the OPL2. 
This is as a precursor to switching to using the proper table lookups, which I hope will automatically fix my range issues.
 2020-04-15 22:10:50 -04:00
Thomas Harte
30ff399218 With some fixes for scale, I think possibly this is close for melodic channels. 2020-04-15 21:27:27 -04:00
Thomas Harte
a7e63b61eb Just from printing numbers: corrects transition from attack to decay. 2020-04-15 00:26:01 -04:00
Thomas Harte
b13b0d9311 Starts towards implementing some OPL test cases. 2020-04-14 23:51:45 -04:00
Thomas Harte
d8380dc3e2 Tries to be a little neater in spelling out the work here. 
I think I'm somewhat circling here now; I need to think of a way of getting clean comparison data.
 2020-04-14 21:55:42 -04:00
Thomas Harte
d805e9a8f0 Actually, octave probably works this way around? Higher octaves = higher frequencies. 2020-04-14 21:39:12 -04:00
Thomas Harte
aa45142728 Endeavours to fix attenuation and add FM synthesis. 
I now definitely think my frequency counting is wrong.
 2020-04-14 18:32:06 -04:00
Thomas Harte
09d1aed3a5 Attempts to voice the current attenuation (and, therefore, the ADSR output), even if linearly rather than logarithmically. 2020-04-13 22:12:55 -04:00
Thomas Harte
a1f80b5142 Takes a stab at per-operator ADSR. 
Heavy caveats apply: no KSR is applied, non-ADSR attenuation isn't applied, attenuation isn't voiced in general.
 2020-04-13 21:39:06 -04:00
Thomas Harte
d3fbdba77c Add missing #include. 2020-04-12 14:20:02 -04:00
Thomas Harte
632d797c9d Adjusts frequency formula. This could be close. 
I guess next I need to get ADSR/volume in general working, before I can go FM? Then I'll worry about using the proper log-sin/exp tables.
 2020-04-12 14:15:09 -04:00
Thomas Harte
559a2d81c1 Baby step: starts trying to output the raw FM carrier, no modulation, no ADSR. 2020-04-12 12:46:40 -04:00
Thomas Harte
7a5f23c0a5 Adds accommodations for the OPLL. 2020-04-10 22:05:22 -04:00
Thomas Harte
84b115f15f Attempts to move forward in defining what the parts of an OPL are meant to do. 2020-04-10 19:13:52 -04:00
Thomas Harte
a0d14f4030 Starts trying to make sense of the various fields at play. 2020-04-08 23:15:44 -04:00
Thomas Harte
dd6769bfbc Splits OPLL and OPL2 classes. 
Logic is: they have different mixers (additive in the OPL2, time-division multiplexing in the OPLL) as well as different register sets. So I'll put operator and channel logic directly into those structs.
 2020-04-07 23:15:26 -04:00
Thomas Harte
db4b71fc9a Adds correct LSFR, something of OPLL -> OPL2 logic. 2020-04-05 22:57:53 -04:00
Thomas Harte
0ed7d257e1 Add some extra notes, implement correct mapping to only 18 operators. Not 22. 2020-04-05 14:32:55 -04:00
Thomas Harte
335a68396f Attempts to complete OPL2 register decoding. 2020-04-04 23:39:09 -04:00
Thomas Harte
84cdf6130f Starts at least trying to decode OPL2 register writes. 2020-04-04 23:29:25 -04:00
Thomas Harte
b0abc4f7bb Implements enough wiring that the Master System will instantiate and talk to an OPLL. 2020-04-03 20:05:36 -04:00
Thomas Harte
a7e1920597 Restores ColecoVision runtime options. 2020-03-18 00:06:52 -04:00
Thomas Harte
394ee61c78 Starts a switch to reflectable-style runtime options. 
The Amstrad CPC and ZX80/81 have made the jump so far, subject to caveats. The macOS build is unlikely currently to work properly.
 2020-03-16 23:25:05 -04:00
Thomas Harte
545a6177bb Makes CompoundSource mono/stereo-aware. 2020-02-16 18:45:36 -05:00
Thomas Harte
50d356be2f Ensures all audio sources, including compound sources, announce whether they're stereo correctly. 2020-02-16 18:31:45 -05:00
Thomas Harte
9835e800ec Fixed: individual audio generators now either are or are not stereo. The speaker acts accordingly. 2020-02-16 18:28:03 -05:00
Thomas Harte
337cb4fb86 Resolves implicit type conversion warnings. 2020-02-16 14:05:23 -05:00
Thomas Harte
f760a68173 Corrects stereo audio generation. 2020-02-16 00:19:49 -05:00
Thomas Harte
89d6b85b83 Adds optional stereo output for the AY. 
The real chip provides the three tone channels as separate outputs, so a variety of different mixings can exist.
 2020-02-15 18:09:17 -05:00
Thomas Harte
e02d109864 Nudges the LowpassSpeaker towards supporting stereo generation. 2020-02-15 18:03:12 -05:00
Thomas Harte
dde672701f
Merge pull request #755 from TomHarte/ExpliticLambdas 
Tries to be less lazy with lambda captures.
 2020-02-15 12:38:12 -05:00
Thomas Harte
9ca2d8f9f2 Tried to be less lazy with lambda captures. 
This is primarily defensive.
 2020-02-14 23:39:08 -05:00
Thomas Harte
763159a6f6 More neatly ties volume level 0 to silence. 2020-02-14 23:16:10 -05:00
Thomas Harte
6810a6ee58 Adjusts the AY volume scale. 
Hopefully more accurately to model the real thing.
 2020-02-14 22:51:20 -05:00
Thomas Harte
294e09f275 All these 'override's can be 'final's. 
At least for the purpose of being communicative. I doubt there's much to gain in terms of compiler output — the DiskImageHolder can avoid some virtual lookups but nothing else leaps out.
 2020-01-23 22:57:51 -05:00
Thomas Harte
9d97a294a7 Corrects the TMS' get_scaled_scan_status. 
I think all platforms are now returning credible numbers.
 2020-01-22 19:34:10 -05:00
Thomas Harte
a71c5946f0 Ensures proper manipulation of scan_statuses, leading to the correct result out of a CRTMachine. 
Possibly with the exception of the TMS, as I appear to have uncovered an unrelated issue there.
 2020-01-21 22:28:25 -05:00
Thomas Harte
d97a073d1b Adds the necessary routine for all machines to be able to respond to get_scan_status. 
They all just as the CRT, as all are currently based on the CRT. Which doesn't currently know the total clock rate it would need to in order properly to scale the answer to the question. Further thought coming.
 2020-01-20 21:45:10 -05:00
Thomas Harte
c755411636 Slightly improves comments. 2020-01-19 20:05:22 -05:00
Thomas Harte
d674fd0e67 The WD uses only the low two bits for sector size. 2020-01-18 13:40:50 -05:00
Thomas Harte
aac3d27c10 Adds activity indicators for the BD-500 and Jasmin. 
Also slightly cleans up DiskController a little further.
 2020-01-15 23:39:15 -05:00
Thomas Harte
2d233b6358 Makes a more concrete attempt at track/sector combination. 2020-01-12 22:18:31 -05:00
Thomas Harte
6a44936a7c Ensures programmatic volume level 0 is completely off. 2020-01-05 22:44:52 -05:00
Thomas Harte
c1bae49a92 Standardises on read and write for bus accesses. 
Logic being: name these things for the bus action they model, not the effect they have.
 2020-01-05 13:40:02 -05:00
Thomas Harte
153f60735d Banishes redefined macro warning. 2020-01-01 12:38:30 -05:00
Thomas Harte
e59de71d79 Disables status logging, at least until next needed. 2019-12-24 21:44:50 -05:00
Thomas Harte
4205e95883 Switches to capture of the track 0 flag during a type 1 operation. 2019-12-24 21:43:20 -05:00
Thomas Harte
dfa6b11737 Adds responsibility for an ongoing index pulse to the drive. 2019-12-24 20:53:37 -05:00
Thomas Harte
42926e72cc Adjusted: Flag::WriteProtect works in real time for a type-1 status. 2019-12-24 19:57:12 -05:00
Thomas Harte
80cb06eb33 It provisionally seems as though spin_up should be reset by a force interrupt? 2019-12-24 19:37:37 -05:00
Thomas Harte
0dae608da5 Embraces std::make_[unique/shared] in place of .reset(new . 2019-12-23 21:31:46 -05:00
Thomas Harte
ac604b30f3 Eliminates dangling static_casts in favour of construction. 2019-12-22 20:59:20 -05:00
Thomas Harte
b035b92f33 Corrects accidental use of sector contents as addresses in multi-sector reads and writes. 
As a secondary defect, this was also causing erroneous CRC error reports.
 2019-12-22 19:58:02 -05:00
Thomas Harte
d25b48878c Cleans up READ_ID macro, inter alia. 2019-12-22 17:58:33 -05:00
Thomas Harte
274867579b Deploys constexpr as a stricter const. 2019-12-22 00:22:17 -05:00
Thomas Harte
a847654ef2 Corrects various old-fashioned bits of indentation, plus the odd const. 2019-12-22 00:00:23 -05:00
Thomas Harte
57ce10418f Switches prescale logic, the better to deal with changes in prescaler. 
According to my assumptions about the behaviour, anyway.
 2019-12-20 23:33:14 -05:00
Thomas Harte
2a1520c04e Removes mostly-uninformative piece of logging. 2019-12-19 22:58:28 -05:00
Thomas Harte
45a391d69e Increases quantity of annotations. 
I'm now at almost 500 lines, and I haven't even really written anything yet.
 2019-12-18 22:57:12 -05:00
Thomas Harte
15bc18b64f Merge branch 'master' into FurtherSCC 2019-12-18 22:17:10 -05:00
Thomas Harte
206ab380c7 Introduces double-resolution envelopes for the Atari ST. 2019-12-18 22:03:02 -05:00
Thomas Harte
d85ae21b2f Adds an explicit declaration of chip type to all AY users. 2019-12-18 19:28:41 -05:00
Thomas Harte
7d9bedf7de Merge branch 'master' into FurtherSCC 2019-12-17 22:39:39 -05:00
Thomas Harte
c2646a415f Switch to faster timer implementation; it seems to work. 2019-12-09 19:23:08 -05:00
Thomas Harte
7cd11ecb7f Adds necessary #include for assert. 2019-12-08 22:43:39 -05:00
Thomas Harte
acfe2c63b8 Adds an assert to verify the interrupt line is clear after a full reset. 2019-12-08 22:34:19 -05:00
Thomas Harte
b192381928 Implements a fuller reset, takes a run at the overran flag. 2019-12-08 21:20:06 -05:00
Thomas Harte
7ff57f8cdf Starts to flesh out documentation. 2019-11-19 22:32:07 -05:00
Thomas Harte
06edeea866 Adds reload during event count mode. 
Plus a helpful bit of TODO.
 2019-11-19 22:24:32 -05:00
Thomas Harte
e0ceab6642 Pivots towards looking at Timer B as a cause of in-frame inaccuracy. 2019-11-19 21:52:50 -05:00
Thomas Harte
0ce5057fd9 Attempts to factor in event counting direction. 2019-11-18 22:37:20 -05:00
Thomas Harte
6ec3c47cc0 Ensures same-level interrupts don't double trigger. 2019-11-12 22:18:13 -05:00
Thomas Harte
d6edfa5c6d Removes the redundant state encased within interrupt_causes_. 2019-11-11 21:49:02 -05:00
Thomas Harte
072b0266af It seems status reads are not required to clear the interrupt line. 2019-11-09 20:12:09 -05:00
Thomas Harte
5fc4e57db7 Eliminates non-portable use of fls. 2019-11-09 16:03:00 -05:00
Thomas Harte
e3abbc9966 Renames what didn't end up being a whole SerialPort. 2019-11-09 15:21:51 -05:00
Thomas Harte
8c736a639a Eliminates unexpected bottleneck created by ACIA. 2019-11-09 15:00:12 -05:00
Thomas Harte
14e790746b Fixes return value when reading received data. 2019-11-02 21:25:00 -04:00
Thomas Harte
75e34b4215 Reacts to no acknowledgement. 2019-10-31 21:00:05 -04:00
Thomas Harte
a5bbf54a27 Adds the ability for the 68901 to decline an interrupt acknowledgement. 2019-10-31 19:57:36 -04:00
Thomas Harte
731dc350b4 Adds sometime real-time clocking for DMA. 2019-10-30 22:59:32 -04:00
Thomas Harte
635e18a50d Ensures the MFP requests and receives real-time clocking when needed. 2019-10-30 22:42:06 -04:00
Thomas Harte
4857ceb3eb Attempts to get a bit more systematic. 
Spotted that interrupt_enable_ isn't being used properly while doing so, hopefully that's now correct.
 2019-10-29 23:16:08 -04:00
Thomas Harte
1c154131f9 Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. 2019-10-29 22:36:29 -04:00
Thomas Harte
fd02b6fc18 Corrects in-service test; adds pending clearing upon enabled clearing. 2019-10-28 22:51:00 -04:00
Thomas Harte
553f3b6d8b Properly conforms to GPIP input/output blending. 2019-10-28 22:37:11 -04:00
Thomas Harte
a5057e6540 Ensures that stop means stop. 2019-10-28 22:12:45 -04:00
Thomas Harte
aa52652027 Adds a const. 2019-10-28 21:21:35 -04:00
Thomas Harte
5f6711b72c Ensures interrupt changes are notified to the delegate. 2019-10-28 21:13:06 -04:00
Thomas Harte
de1bfb4e24 Stores and returns timer configuration. 2019-10-27 22:38:49 -04:00
Thomas Harte
0082dc4411 Improves logging. 2019-10-27 00:02:55 -04:00
Thomas Harte
22754683f8 Ensures timer divisor values don't go out of range, adds timer interrupts. 
I suspect further timer issues remain.
 2019-10-26 23:20:13 -04:00
Thomas Harte
e89be6249d Adds a logging prefix. 2019-10-26 22:38:56 -04:00
Thomas Harte
e96386f572 Takes another stab at MFP interrupt management. 2019-10-26 15:55:19 -04:00
Thomas Harte
a8d481a764 Writes to the pending register appear to be able to clear interrupts too. 2019-10-25 22:46:30 -04:00
Thomas Harte
872897029e Attempts a complete wiring of 68901 interrupts. 2019-10-25 22:36:01 -04:00
Thomas Harte
7a2de47f58 Corrects interrupt mask generation. 2019-10-24 22:37:32 -04:00
Thomas Harte
f2f98ed60c Attempts some part of interrupt decision making. 2019-10-24 22:33:42 -04:00
Thomas Harte
77f14fa638 Starts trying to make sense of interrupts. 2019-10-23 23:09:49 -04:00
Thomas Harte
f09a240e6c Gives myself more trace details. 2019-10-21 23:20:03 -04:00
Thomas Harte
e30ba58e0d Attempts to wire ACIA interrupt signals into the MFP. 2019-10-21 23:02:30 -04:00
Thomas Harte
7cb82fccc0 Attempts properly to maintain interrupt flag; adds delegate. 2019-10-21 22:40:38 -04:00
Thomas Harte
ed9a5b0430 Adds receipt interrupt. 2019-10-21 21:27:57 -04:00
Thomas Harte
8f59a73425 Corrects incoming data capture. 2019-10-21 20:18:52 -04:00
Thomas Harte
91223b9ec8 Sets default level to high. 2019-10-21 20:18:33 -04:00
Thomas Harte
83f5f0e2ad Begins trying to receive ACIA data. 2019-10-21 20:10:19 -04:00
Thomas Harte
cf37e9f5de Remove source control markers. 2019-10-20 23:40:51 -04:00
Thomas Harte
e4f7ead894 Merge branch 'AtariST' of github.com:TomHarte/CLK into AtariST 2019-10-20 23:40:01 -04:00
Thomas Harte
4134463094 The ACIA now receives bits. 2019-10-20 23:34:30 -04:00
Thomas Harte
83d73fb088 The keyboard now responds to a reset on its serial line. 2019-10-20 23:13:44 -04:00
Thomas Harte
cf07982a9b Ensures good serial line and ACIA behaviour. 
Next stop: having the intelligent keyboard react.
 2019-10-20 22:10:05 -04:00
Thomas Harte
2e86dada1d Ensures updates even when the event queue is empty. 2019-10-20 20:38:56 -04:00
Thomas Harte
696af5c3a6 Starts to transfer serial line decoding logic into the line itself. 2019-10-20 20:38:56 -04:00
Thomas Harte
f08b38d0ae Silences, temporarily. 2019-10-20 20:38:55 -04:00
Thomas Harte
9a8352282d Mostly but not quite fixes serial work. 2019-10-20 20:38:55 -04:00
Thomas Harte
3d03cce6b1 Starts working on the GPIP functionality block. 2019-10-20 20:38:55 -04:00
Thomas Harte
34075a7674 Attempts to tie an intelligent keyboard to the other end of its serial line. 2019-10-20 20:38:55 -04:00
Thomas Harte
f79c87659f Corrects documentation error. 2019-10-20 20:38:55 -04:00
Thomas Harte
c10b64e1c0 Adds a received_data_ register, that presently can never fill. 2019-10-20 20:38:55 -04:00
Thomas Harte
5d5fe52144 Corrects transmission logic — exactly hitting write_data_time_remaining now works properly. 2019-10-20 20:38:55 -04:00
Thomas Harte
d461331fd2 Ensures remaining_delays_ is set properly after [reset/flush]_writing. 2019-10-20 20:38:55 -04:00
Thomas Harte
ff62eb6dce The ACIA actually has two clocks, though on an ST they're both 500,000 Hz. 2019-10-20 20:38:55 -04:00
Thomas Harte
374439693e Ensures serial lines know their writer's clock rate. 2019-10-20 20:38:55 -04:00
Thomas Harte
c4ef33b23f JustInTimeActors can now specify a clock divider. 2019-10-20 20:38:55 -04:00
Thomas Harte
a7ed357569 Attempts to implement transmission interrupts and ClockingHint::Source. 2019-10-20 20:38:55 -04:00
Thomas Harte
4e5b440145 Attempts mostly to implement 6850 output. 2019-10-20 20:38:55 -04:00
Thomas Harte
2bd7be13b5 Decodes the 6850 control register, and starts working on standardised serial ports. 2019-10-20 20:38:55 -04:00
Thomas Harte
4b09d7c41d Nudges 6850 towards coherence. 2019-10-20 20:38:55 -04:00
Thomas Harte
b0f5f7bd37 Attempts to start producing actual video. 2019-10-20 20:38:55 -04:00
Thomas Harte
4ead905c3c Adds an empty shell for the ACIA. 2019-10-20 20:38:55 -04:00
Thomas Harte
127bb043e7 Adds enough logic to advance to an ACIA access error. 2019-10-20 20:38:55 -04:00
Thomas Harte
2cf52fb89c Makes an unsuccessful first attempt at some timer functionality. 2019-10-20 20:38:54 -04:00
Thomas Harte
6e1b606adf Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-20 20:38:54 -04:00
Thomas Harte
e095a622d3 Ensures updates even when the event queue is empty. 2019-10-17 23:59:43 -04:00
Thomas Harte
9ab49065cd Starts to transfer serial line decoding logic into the line itself. 2019-10-17 23:34:39 -04:00
Thomas Harte
ab50f17d87 Silences, temporarily. 2019-10-16 23:34:49 -04:00
Thomas Harte
f5a2e180f9 Mostly but not quite fixes serial work. 2019-10-16 23:34:37 -04:00
Thomas Harte
f2e1584275 Starts working on the GPIP functionality block. 2019-10-16 23:21:25 -04:00
Thomas Harte
0fd8813ddb Attempts to tie an intelligent keyboard to the other end of its serial line. 2019-10-16 23:21:14 -04:00
Thomas Harte
b69180ba01 Corrects documentation error. 2019-10-16 23:19:42 -04:00
Thomas Harte
c352d8ae8c Adds a received_data_ register, that presently can never fill. 2019-10-13 23:04:57 -04:00
Thomas Harte
530e831064 Corrects transmission logic — exactly hitting write_data_time_remaining now works properly. 2019-10-13 21:40:46 -04:00
Thomas Harte
3b165a78f2 Ensures remaining_delays_ is set properly after [reset/flush]_writing. 2019-10-13 21:39:25 -04:00
Thomas Harte
8d87e9eb1c The ACIA actually has two clocks, though on an ST they're both 500,000 Hz. 2019-10-13 21:32:34 -04:00
Thomas Harte
f86dc082bb Ensures serial lines know their writer's clock rate. 2019-10-13 20:41:08 -04:00
Thomas Harte
d7982aa84e JustInTimeActors can now specify a clock divider. 2019-10-13 18:19:39 -04:00
Thomas Harte
516d78f5a8 Attempts to implement transmission interrupts and ClockingHint::Source. 2019-10-12 23:46:57 -04:00
Thomas Harte
8b50a7d6e3 Attempts mostly to implement 6850 output. 2019-10-12 23:14:29 -04:00
Thomas Harte
4bf81d3b90 Decodes the 6850 control register, and starts working on standardised serial ports. 2019-10-12 18:19:55 -04:00
Thomas Harte
cd75978e4e Nudges 6850 towards coherence. 2019-10-12 00:04:02 -04:00
Thomas Harte
c5ebf75351 Attempts to start producing actual video. 2019-10-10 22:46:58 -04:00
Thomas Harte
d7ce2c26e8 Adds an empty shell for the ACIA. 2019-10-10 20:54:29 -04:00
Thomas Harte
f88e1b1373 Adds enough logic to advance to an ACIA access error. 2019-10-09 23:01:11 -04:00
Thomas Harte
1de1818ebb Makes an unsuccessful first attempt at some timer functionality. 2019-10-07 22:44:35 -04:00
Thomas Harte
885f890df1 Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-06 23:14:05 -04:00
Thomas Harte
6c99048211 Copies in a few more hardware notes. 2019-10-02 19:18:09 -04:00
Thomas Harte
2638a901d9 Improves documentation of existing degree of implementation. 2019-09-30 21:36:37 -04:00
Thomas Harte
929475d31e Minor correction: round down, not up. 2019-09-28 23:49:32 -04:00
Thomas Harte
7758f9d0a9 Improves nomenclature. 2019-09-24 22:31:36 -04:00
Thomas Harte
8d4a96683a Reduces output noise. 2019-09-18 21:41:29 -04:00
Thomas Harte
f53411a319 Removes local NDEBUG. 2019-09-18 21:35:26 -04:00
Thomas Harte
962275c22a Removes clock for NCR 5380. 
It doesn't have one in real life, and now can live off the time counting that occurs on the SCSI bus.
 2019-09-18 20:17:47 -04:00
Thomas Harte
2f6c366668 Makes a concerted effort at properly wrapping a hard disk image. 2019-09-17 21:30:04 -04:00
Thomas Harte
2ce1f0a3b1 Implements multi-sector read/write. 
This once again unblocks Apple HD SC Setup. Progress!
 2019-09-16 22:20:42 -04:00
Thomas Harte
960b289e70 Edges closer towards proper DMA operation. 
Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
 2019-09-15 15:03:06 -04:00
Thomas Harte
243e40cd79 Adds signalling of DACK. 2019-09-14 13:48:33 -04:00
Thomas Harte
64dad35026 Decreases logging, at least temporarily. 2019-09-03 22:40:32 -04:00
Thomas Harte
1c7e0f3c9d Fixes control line modification by the 5380 and SCSI target command chaining. 
So now I'm back to trying to guess how a SCSI command terminates re: the relative meanings of a message phase and a status phase.
 2019-09-02 23:14:37 -04:00
Thomas Harte
ca08716c52 Introduces real hard disk images to the nascent world of SCSI. 2019-08-25 17:03:41 -04:00
Thomas Harte
c86db12f1c Starts implementing DMA support on the 5380. 
The Macintosh doesn't actually use the DMA signals, but uses pseudo-DMA mode so they nevertheless need to be appropriate.
 2019-08-24 22:47:11 -04:00
Thomas Harte
2d82855f26 Attempts to provide a data out phase. 2019-08-22 23:16:58 -04:00
Thomas Harte
faec516a2c Starts pushing towards figuring out a proper infrastructure for mass storage. 2019-08-21 23:22:58 -04:00
Thomas Harte
bb1a0a0b76 Sketches out further SCSI infrastructure. 2019-08-21 22:37:39 -04:00
Thomas Harte
252650808d Starts seeking to unbind SCSI bus logic and command performance. 2019-08-19 22:47:01 -04:00
Thomas Harte
e3d9254555 Implements phase-match bit. 
Seemingly causing the command phase to proceed.
 2019-08-18 23:15:54 -04:00
Thomas Harte
955e909e61 Attempts to nudge the command phase further towards functioning. 2019-08-18 22:39:27 -04:00
Thomas Harte
8339e2044c Switches to proper SCSI terminology and better attempts a command phase. 2019-08-18 15:10:07 -04:00
Thomas Harte
0e0c789b02 Starts attempting to introduce a direct access device. 
Without having access to the SCSI-1 standard, a lot of this is guesswork.
 2019-08-17 23:43:42 -04:00
Thomas Harte
7e001c1d03 Corrects data line loading. 
Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
 2019-08-17 21:30:59 -04:00
Thomas Harte
9047932b81 Corrected basic error. Arbitration now seems to succeed. 
This is seemingly followed by a pattern of signalling BUSY+SEL followed by just SEL with the various other potential device IDs in turn. To which nothing ever responds as currently implemented.
 2019-08-15 23:28:30 -04:00
Thomas Harte
f668e4a54c Makes an attempt at getting the 5380 past arbitration. 
Not entirely successful. Also gets a bit smarter with `final` on ClockingHint::Sources.
 2019-08-15 23:14:40 -04:00
Thomas Harte
ce1c96d68c Starts thinking out the mechanics of emulating a SCSI-1 bus. 2019-08-13 23:09:11 -04:00
Thomas Harte
0f67e490e8 Adjusts NCR address decoding to produce a more plausible initial interaction. 2019-08-11 22:43:25 -04:00
Thomas Harte
a90a74a512 Stubs in just enough of the 5380 to get a Mac Plus too boot. 2019-08-11 20:55:20 -04:00
Thomas Harte
949c1e1668 Adds an empty shell for what will be my 5380 implementation. 2019-08-10 23:53:52 -04:00
Thomas Harte
96005261c7 Adds activity lights for Macintosh disk activity. 
Prompting a quick fix to drives not spinning down.
 2019-08-02 16:26:23 -04:00
Thomas Harte
335dda3d55 Attempts more accurately to match Apple's windowing logic. 2019-08-02 12:49:45 -04:00
Thomas Harte
9bbccd89d3 Adds an extended rationale for current implementation. 
Also strips some cruft of prior guesses.
 2019-07-31 23:19:46 -04:00
Thomas Harte
2aa308efdd Tweaks magic formulas. 
The computer now at least seeks outward, until this attempt at drive speed calculation fails.
 2019-07-30 16:18:36 -04:00
Thomas Harte
74c18d7861 Attempts a full wiring up of 400kb drive speed. 2019-07-30 15:08:55 -04:00
Thomas Harte
a43ada82b2 Experiments with a JustInTimeActor in the Master System. 2019-07-29 15:38:41 -04:00
Thomas Harte
85cf8d89bc Ensures an initial non-zero value. 2019-07-25 21:47:44 -04:00
Thomas Harte
0469f0240b Moves interrupt level selection outside the loop. 2019-07-23 23:13:03 -04:00
Thomas Harte
d69aee4972 Removes stray \n. 2019-07-23 22:17:46 -04:00
Thomas Harte
ee8d853fcb Ensures you can't get a phase 2 for free with run_for(0). 2019-07-17 14:20:27 -04:00
Thomas Harte
67055d8b56 Reduces CheckingWriteProtect costs, negligibly. 2019-07-15 22:39:55 -04:00
Thomas Harte
7baad61746 Attempts a full implementation of asynchronous write mode. 2019-07-15 17:11:12 -04:00
Thomas Harte
1d1e0d74f8 Corrects and introduces new parts. 2019-07-12 21:37:33 -04:00
Thomas Harte
d53d1c616f Continues trying to get to write support. 2019-07-12 21:20:05 -04:00
Thomas Harte
2c39229b13 Adds has-new-disk flag, allowing mounting of software from the desktop. 2019-07-12 13:17:24 -04:00
Thomas Harte
b730ac5d5a Reintroduces 1-second disable implementation. 2019-07-11 23:02:47 -04:00
Thomas Harte
c8917e677b Edging towards implementing IWM write support, but mainly tidied up. 2019-07-11 21:42:34 -04:00
Thomas Harte
cac97a9663 Devolves drive responsibility. 2019-07-10 22:39:56 -04:00
Thomas Harte
be251d6b03 Begins substituting the DoubleDensityDrive for the Sony. 2019-07-10 16:24:48 -04:00
Thomas Harte
6cfaf920ee Added attribution and commentary on rotation speeds. 2019-07-10 16:22:06 -04:00
Thomas Harte
1657f8768c Transfers and slightly extends drive logic into the drive. 2019-07-10 16:17:51 -04:00
Thomas Harte
c4ab0bb867 Starts sketching out an interface for IWM drives, eliminating a dangling use of unsigned as it goes. 2019-07-10 16:05:59 -04:00
Thomas Harte
fb6da1de4a Reduces logging temporarily. 2019-07-08 17:37:15 -04:00
Thomas Harte
245e27c893 Solidifies belief that the shift register bit is cleared on read/write. 2019-07-08 16:45:15 -04:00
Thomas Harte
28de629c08 Fixes the 6522 sufficiently to fix keyboard input. 2019-07-08 15:29:34 -04:00
Thomas Harte
210bcaa56d Introduces an initial shift unit test, and makes it pass. 2019-07-07 22:13:36 -04:00
Thomas Harte
191a7a9386 Reintroduces an empty second drive. 
This prevents the uninitialised disk error. Which is a clue.
 2019-07-02 16:59:00 -04:00
Thomas Harte
b9c2c42bc0 Switches drives to using floats for time counting. 
Hopefully to eliminate a lot of unnecessary `Time` work; inaccuracies should still be within tolerable range.
 2019-07-02 15:43:03 -04:00
Thomas Harte
6c588a1510 Makes some further random swings at tracking the startup procedure. 2019-06-28 13:03:47 -04:00
Thomas Harte
00c32e4b59 Further miscellaneous changes to debug logging. All temporary. 2019-06-18 10:34:31 -04:00
Thomas Harte
877b46d2c1 Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'. 2019-06-15 16:08:54 -04:00
Thomas Harte
cc7226ae9f Starts trying to get a bit more rigorous about collected meanings. 2019-06-13 22:48:10 -04:00
Thomas Harte
bde975a3b9 Possibly mights the tiniest bit of headway with 'the IWM'. 
I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
 2019-06-13 22:38:09 -04:00
Thomas Harte
f6f9024631 Corrects Macintosh aspect ratio (and framing). 2019-06-13 18:41:38 -04:00
Thomas Harte
535747e3f2 Restores single-line logging format. 2019-06-13 13:35:03 -04:00
Thomas Harte
d6150645c0 By hook or by crook, mouse input now works. 2019-06-12 22:19:25 -04:00
Thomas Harte
ccd2cb44a2 Fills in enough of the SCC to allow completion of the Macintosh side of that relationship. 2019-06-12 17:51:50 -04:00
Thomas Harte
ad8b68c998 Switches to a proper form of zero-upon-read data. 
Not that it's necessarily correct.
 2019-06-11 19:53:51 -04:00
Thomas Harte
3c075e9542 Switches drives 0 and 1. 2019-06-10 14:58:39 -04:00
Thomas Harte
9230969f43 Corrects enough of the 6522 and Keyboard to get an initial command seemingly working. 2019-06-10 09:28:27 -04:00
Thomas Harte
0e16c67805 Improves shift register connection, towards having the keyboard function properly. 
It now seems not to receive a command terminator, but is at least getting a command.
 2019-06-08 23:04:55 -04:00
Thomas Harte
697e094a4e Sketches out the absolute basics of an SCC interface. 2019-06-08 18:47:11 -04:00
Thomas Harte
50d37798a2 Eradicates magic constants. 2019-06-06 21:37:43 -04:00
Thomas Harte
e9d0676e75 Fiddles further with the tachometer. 2019-06-06 21:36:19 -04:00
Thomas Harte
7591906777 Numerous IWM fixes: the machine now seems to be trying to measure the tachometer. 2019-06-06 18:32:11 -04:00
Thomas Harte
a413ae11cb Makes some sort of first attempt at having the IWM read. 2019-06-04 22:13:00 -04:00
Thomas Harte
b8a1553368 Adds putative support for PlusToo-style BIN files. 
Albeit a bit of a guess, since it's not intended to be an emulator file format.
 2019-06-04 21:41:09 -04:00
Thomas Harte
8557558bd8 Mildly improves investigatory reporting. 2019-06-03 21:51:45 -04:00
Thomas Harte
abe55fe950 Adds Timer 1 toggling of PB7. 2019-06-03 15:39:20 -04:00
Thomas Harte
da2b190288 Stores expected bit length. 2019-06-01 19:08:29 -04:00
Thomas Harte
48d837c636 Attempts to respond more sensibly to various queries. 
Including adding a 1-second delay on motor off.
 2019-06-01 18:43:47 -04:00
Thomas Harte
723137c0d4 With some time additions to the 6522, starts wiring in Macintosh audio. 
The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
 2019-06-01 14:39:40 -04:00
Thomas Harte
4197c6f149 Attempts to make some further semantic sense of the various IWM controls. 2019-05-30 22:17:49 -04:00
Thomas Harte
4632be4fe5 Wires up the final IWM signal, SEL, preparatory to an implementation. 2019-05-30 12:08:00 -04:00
Thomas Harte
8293b18278 Adds a TODO on what I think might be an incorrect implementation? 2019-05-08 15:06:40 -04:00
Thomas Harte
2ba0364850 Adds the shift register interrupt. 2019-05-08 15:02:07 -04:00
Thomas Harte
2e7bc0b98a Attempts the shift register. 2019-05-08 14:54:40 -04:00
Thomas Harte
8278809383 Attempts to get more rigorous on communicating outward control line changes. 2019-05-08 13:33:22 -04:00
Thomas Harte
4367459cf2 Takes a first go at handshake and pulse modes. 2019-05-08 12:48:29 -04:00
Thomas Harte
254132b83d Eliminates 6522Base in pursuit of working handshake modes. 
Specifically: this means that the places from which the BusHandler may be called are more numerous.
 2019-05-08 12:35:17 -04:00
Thomas Harte
7e6d4f5a3e Adds emulation of the real-time clock. 2019-05-08 00:12:19 -04:00
Thomas Harte
ce099a297a Eliminates RAM writes in ROM area. 
I no longer think that logic is correct.
 2019-05-07 17:16:22 -04:00
Thomas Harte
96facc103a Adds an IWM shim and corrects graphics output. 
... now that there is some.
 2019-05-05 21:55:34 -04:00
Thomas Harte
62a1d69cee Implements proper AY IO output behaviour. 2019-03-05 20:20:26 -05:00
Thomas Harte
d97348dd38 Eliminates dangling uses of printf. 2019-03-02 18:07:05 -05:00
Thomas Harte
7030abca97 Corrects PAL colours for the Vic-20. 2019-02-25 19:28:52 -05:00
Thomas Harte
e5addb27ec Corrects log output. 2019-02-18 20:49:01 -05:00
Thomas Harte
2ef6d4327c Resolves further build warnings. 2019-01-13 20:37:50 -05:00
Thomas Harte
248a8efd2f Corrects declared pixel clock GCD. 2019-01-06 16:32:13 -05:00