2012-02-18 12:03:15 +00:00
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//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
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//
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2004-02-25 19:28:19 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2012-02-18 12:03:15 +00:00
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//
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2004-02-25 19:28:19 +00:00
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//===----------------------------------------------------------------------===//
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//
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2006-02-05 05:50:24 +00:00
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// This file describes the Sparc instructions in TableGen format.
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2004-02-25 19:28:19 +00:00
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//
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//===----------------------------------------------------------------------===//
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2004-02-25 21:02:21 +00:00
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//===----------------------------------------------------------------------===//
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2004-02-26 00:37:12 +00:00
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// Instruction format superclass
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2004-02-25 21:02:21 +00:00
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//===----------------------------------------------------------------------===//
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2004-02-25 19:28:19 +00:00
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2006-02-05 05:50:24 +00:00
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include "SparcInstrFormats.td"
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2004-02-25 19:28:19 +00:00
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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2013-04-02 04:09:06 +00:00
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// True when generating 32-bit code.
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def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
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// True when generating 64-bit code. This also implies HasV9.
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def Is64Bit : Predicate<"Subtarget.is64Bit()">;
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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// HasV9 - This predicate is true when the target processor supports V9
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// instructions. Note that the machine may be running in 32-bit mode.
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def HasV9 : Predicate<"Subtarget.isV9()">;
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2006-01-30 05:48:37 +00:00
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// HasNoV9 - This predicate is true when the target doesn't have V9
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// instructions. Use of this is just a hack for the isel not having proper
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// costs for V8 instructions that are more expensive than their V9 ones.
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def HasNoV9 : Predicate<"!Subtarget.isV9()">;
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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// HasVIS - This is true when the target processor has VIS extensions.
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def HasVIS : Predicate<"Subtarget.isVIS()">;
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// UseDeprecatedInsts - This predicate is true when the target processor is a
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// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
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// to use when appropriate. In either of these cases, the instruction selector
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// will pick deprecated instructions.
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def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
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Add some simple integer patterns. This allows us to compile this:
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %sp
add %i0, 1, %l0
xor %l0, 123, %i0
restore %g0, %g0, %g0
retl
nop
for example. I guess it would make sense to add reg/reg versions too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24774 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 08:26:38 +00:00
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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2010-08-17 18:17:12 +00:00
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def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
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2006-01-31 06:18:16 +00:00
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2010-08-17 18:17:12 +00:00
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def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
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Add some simple integer patterns. This allows us to compile this:
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %sp
add %i0, 1, %l0
xor %l0, 123, %i0
restore %g0, %g0, %g0
retl
nop
for example. I guess it would make sense to add reg/reg versions too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24774 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 08:26:38 +00:00
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2005-12-17 19:41:43 +00:00
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def LO10 : SDNodeXForm<imm, [{
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2008-09-12 16:56:44 +00:00
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return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
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2009-08-11 20:47:22 +00:00
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MVT::i32);
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2005-12-17 19:41:43 +00:00
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}]>;
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2005-12-17 19:37:00 +00:00
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def HI22 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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2009-08-11 20:47:22 +00:00
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return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
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2005-12-17 19:37:00 +00:00
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}]>;
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def SETHIimm : PatLeaf<(imm), [{
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2008-09-12 16:56:44 +00:00
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return (((unsigned)N->getZExtValue() >> 10) << 10) ==
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(unsigned)N->getZExtValue();
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2005-12-17 19:37:00 +00:00
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}], HI22>;
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2005-12-17 20:04:49 +00:00
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// Addressing modes.
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2013-04-02 04:08:54 +00:00
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def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
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def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
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2005-12-17 20:04:49 +00:00
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// Address operands
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2013-04-02 04:08:54 +00:00
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def MEMrr : Operand<iPTR> {
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2005-12-17 20:04:49 +00:00
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let PrintMethod = "printMemOperand";
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2013-04-02 04:08:54 +00:00
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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2005-12-17 20:04:49 +00:00
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}
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2013-04-02 04:08:54 +00:00
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def MEMri : Operand<iPTR> {
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2005-12-17 20:04:49 +00:00
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let PrintMethod = "printMemOperand";
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2013-04-02 04:08:54 +00:00
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let MIOperandInfo = (ops ptr_rc, i32imm);
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2005-12-17 20:04:49 +00:00
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}
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2005-12-18 01:46:58 +00:00
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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2005-12-18 15:55:15 +00:00
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def calltarget : Operand<i32>;
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2005-12-18 01:46:58 +00:00
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2006-01-31 06:49:09 +00:00
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// Operand for printing out a condition code.
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2006-02-05 05:50:24 +00:00
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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2006-01-31 06:49:09 +00:00
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2006-02-05 05:50:24 +00:00
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def SDTSPcmpfcc :
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2006-02-10 06:58:25 +00:00
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SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
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2006-02-05 05:50:24 +00:00
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def SDTSPbrcc :
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2006-02-10 06:58:25 +00:00
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SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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2006-02-05 05:50:24 +00:00
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def SDTSPselectcc :
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2006-02-10 06:58:25 +00:00
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
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2006-02-05 05:50:24 +00:00
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def SDTSPFTOI :
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2005-12-23 05:00:16 +00:00
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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2006-02-05 05:50:24 +00:00
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def SDTSPITOF :
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2005-12-23 05:00:16 +00:00
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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2005-12-18 01:20:35 +00:00
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2010-12-23 18:28:41 +00:00
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def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>;
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def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
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def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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2013-04-03 04:41:44 +00:00
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def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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2010-12-23 18:28:41 +00:00
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def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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2005-12-18 01:20:35 +00:00
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2006-02-05 05:50:24 +00:00
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def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
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def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
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2005-12-18 01:20:35 +00:00
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2006-02-05 05:50:24 +00:00
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def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
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def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
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2005-12-18 06:59:57 +00:00
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2010-12-23 18:28:41 +00:00
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def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
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2013-04-04 03:08:00 +00:00
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def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
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2010-12-23 18:28:41 +00:00
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def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
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2005-12-18 08:13:54 +00:00
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2009-08-26 04:50:17 +00:00
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// These are target-independent nodes, but have target-specific formats.
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2007-11-13 09:19:02 +00:00
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def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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2007-11-13 00:44:25 +00:00
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2007-11-13 09:19:02 +00:00
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOutGlue]>;
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2007-11-13 09:19:02 +00:00
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
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2010-12-23 18:28:41 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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2005-12-18 15:55:15 +00:00
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2011-01-12 03:18:21 +00:00
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def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
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2006-02-05 05:50:24 +00:00
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def call : SDNode<"SPISD::CALL", SDT_SPCall,
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2011-01-12 03:18:21 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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2005-12-18 15:55:15 +00:00
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2011-02-21 03:42:44 +00:00
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def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
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2013-02-05 18:16:58 +00:00
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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2005-12-18 21:03:04 +00:00
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2011-01-21 22:00:00 +00:00
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def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
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2012-08-24 00:31:13 +00:00
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[SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
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2011-01-12 05:08:36 +00:00
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2009-09-15 17:46:24 +00:00
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def getPCX : Operand<i32> {
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let PrintMethod = "printGetPCX";
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2011-02-21 03:42:44 +00:00
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}
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2009-09-15 17:46:24 +00:00
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2006-01-30 07:43:04 +00:00
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//===----------------------------------------------------------------------===//
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// SPARC Flag Conditions
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//===----------------------------------------------------------------------===//
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2006-02-05 05:50:24 +00:00
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// Note that these values must be kept in sync with the CCOp::CondCode enum
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2006-01-30 07:43:04 +00:00
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// values.
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2006-01-31 06:56:30 +00:00
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class ICC_VAL<int N> : PatLeaf<(i32 N)>;
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2006-01-31 06:18:16 +00:00
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def ICC_NE : ICC_VAL< 9>; // Not Equal
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def ICC_E : ICC_VAL< 1>; // Equal
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def ICC_G : ICC_VAL<10>; // Greater
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def ICC_LE : ICC_VAL< 2>; // Less or Equal
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def ICC_GE : ICC_VAL<11>; // Greater or Equal
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def ICC_L : ICC_VAL< 3>; // Less
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def ICC_GU : ICC_VAL<12>; // Greater Unsigned
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def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
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def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
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def ICC_POS : ICC_VAL<14>; // Positive
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def ICC_NEG : ICC_VAL< 6>; // Negative
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def ICC_VC : ICC_VAL<15>; // Overflow Clear
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def ICC_VS : ICC_VAL< 7>; // Overflow Set
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2006-01-31 06:56:30 +00:00
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class FCC_VAL<int N> : PatLeaf<(i32 N)>;
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2006-01-31 06:18:16 +00:00
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def FCC_U : FCC_VAL<23>; // Unordered
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def FCC_G : FCC_VAL<22>; // Greater
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def FCC_UG : FCC_VAL<21>; // Unordered or Greater
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def FCC_L : FCC_VAL<20>; // Less
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def FCC_UL : FCC_VAL<19>; // Unordered or Less
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def FCC_LG : FCC_VAL<18>; // Less or Greater
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def FCC_NE : FCC_VAL<17>; // Not Equal
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def FCC_E : FCC_VAL<25>; // Equal
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def FCC_UE : FCC_VAL<24>; // Unordered or Equal
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def FCC_GE : FCC_VAL<25>; // Greater or Equal
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def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
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def FCC_LE : FCC_VAL<27>; // Less or Equal
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def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
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def FCC_O : FCC_VAL<29>; // Ordered
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2006-01-30 07:43:04 +00:00
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2006-09-01 22:28:02 +00:00
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
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multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
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def rr : F3_1<2, Op3Val,
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
2006-09-01 22:28:02 +00:00
|
|
|
!strconcat(OpcStr, " $b, $c, $dst"),
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
|
2006-09-01 22:28:02 +00:00
|
|
|
def ri : F3_2<2, Op3Val,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
2006-09-01 22:28:02 +00:00
|
|
|
!strconcat(OpcStr, " $b, $c, $dst"),
|
2013-04-02 04:08:54 +00:00
|
|
|
[(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
|
2006-09-01 22:28:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
|
|
|
|
/// pattern.
|
|
|
|
multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
|
|
|
|
def rr : F3_1<2, Op3Val,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
2006-09-01 22:28:02 +00:00
|
|
|
!strconcat(OpcStr, " $b, $c, $dst"), []>;
|
|
|
|
def ri : F3_2<2, Op3Val,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
2006-09-01 22:28:02 +00:00
|
|
|
!strconcat(OpcStr, " $b, $c, $dst"), []>;
|
|
|
|
}
|
2006-01-30 07:43:04 +00:00
|
|
|
|
2004-02-26 00:37:12 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2004-02-28 19:37:18 +00:00
|
|
|
// Pseudo instructions.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSP<outs, ins, asmstr, pattern>;
|
2005-12-18 08:21:00 +00:00
|
|
|
|
2009-09-15 17:46:24 +00:00
|
|
|
// GETPCX for PIC
|
2011-01-12 03:52:59 +00:00
|
|
|
let Defs = [O7] in {
|
2009-09-15 17:46:24 +00:00
|
|
|
def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
|
|
|
|
}
|
|
|
|
|
2007-09-11 19:55:27 +00:00
|
|
|
let Defs = [O6], Uses = [O6] in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
|
2005-12-18 15:55:15 +00:00
|
|
|
"!ADJCALLSTACKDOWN $amt",
|
2008-10-11 22:08:30 +00:00
|
|
|
[(callseq_start timm:$amt)]>;
|
2007-11-13 00:44:25 +00:00
|
|
|
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
|
|
|
"!ADJCALLSTACKUP $amt1",
|
2008-10-11 22:08:30 +00:00
|
|
|
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
2007-09-11 19:55:27 +00:00
|
|
|
}
|
2007-12-12 23:12:09 +00:00
|
|
|
|
2011-01-21 22:00:00 +00:00
|
|
|
let hasSideEffects = 1, mayStore = 1 in {
|
|
|
|
let rd = 0, rs1 = 0, rs2 = 0 in
|
|
|
|
def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
|
|
|
|
"flushw",
|
|
|
|
[(flushw)]>, Requires<[HasV9]>;
|
|
|
|
let rd = 0, rs1 = 1, simm13 = 3 in
|
|
|
|
def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
|
|
|
|
"ta 3",
|
|
|
|
[(flushw)]>;
|
|
|
|
}
|
2011-01-12 05:08:36 +00:00
|
|
|
|
2011-02-21 03:42:44 +00:00
|
|
|
def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
|
|
|
|
"unimp $val", []>;
|
|
|
|
|
2005-12-19 00:50:12 +00:00
|
|
|
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
|
|
|
|
// fpmover pass.
|
2006-02-21 18:04:32 +00:00
|
|
|
let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
2006-01-30 05:48:37 +00:00
|
|
|
"!FpMOVD $src, $dst", []>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
2006-01-30 05:48:37 +00:00
|
|
|
"!FpNEGD $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fneg f64:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
2006-01-30 05:48:37 +00:00
|
|
|
"!FpABSD $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fabs f64:$src))]>;
|
2006-01-30 05:48:37 +00:00
|
|
|
}
|
2005-12-18 08:13:54 +00:00
|
|
|
|
2009-10-29 18:10:34 +00:00
|
|
|
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
|
|
|
|
// instruction selection into a branch sequence. This has to handle all
|
|
|
|
// permutations of selection between i32/f32/f64 on ICC and FCC.
|
2011-01-11 22:38:28 +00:00
|
|
|
// Expanded after instruction selection.
|
|
|
|
let Uses = [ICC], usesCustomInserter = 1 in {
|
2005-12-18 08:13:54 +00:00
|
|
|
def SELECT_CC_Int_ICC
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
|
2005-12-18 08:13:54 +00:00
|
|
|
"; SELECT_CC_Int_ICC PSEUDO!",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
|
2011-01-11 22:38:28 +00:00
|
|
|
def SELECT_CC_FP_ICC
|
|
|
|
: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
|
|
|
|
"; SELECT_CC_FP_ICC PSEUDO!",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
|
2011-01-11 22:38:28 +00:00
|
|
|
|
|
|
|
def SELECT_CC_DFP_ICC
|
|
|
|
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
|
|
|
|
"; SELECT_CC_DFP_ICC PSEUDO!",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
|
2011-01-11 22:38:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
let usesCustomInserter = 1, Uses = [FCC] in {
|
|
|
|
|
2005-12-18 08:13:54 +00:00
|
|
|
def SELECT_CC_Int_FCC
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
|
2005-12-18 08:13:54 +00:00
|
|
|
"; SELECT_CC_Int_FCC PSEUDO!",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
|
2010-12-28 20:39:17 +00:00
|
|
|
|
2005-12-18 08:13:54 +00:00
|
|
|
def SELECT_CC_FP_FCC
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
|
2005-12-18 08:13:54 +00:00
|
|
|
"; SELECT_CC_FP_FCC PSEUDO!",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
|
2005-12-18 08:13:54 +00:00
|
|
|
def SELECT_CC_DFP_FCC
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
|
2005-12-18 08:13:54 +00:00
|
|
|
"; SELECT_CC_DFP_FCC PSEUDO!",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
|
2004-02-28 19:37:18 +00:00
|
|
|
}
|
|
|
|
|
First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
|
|
|
|
2004-03-06 05:32:13 +00:00
|
|
|
// Section A.3 - Synthetic Instructions, p. 85
|
2004-05-08 04:21:32 +00:00
|
|
|
// special cases of JMPL:
|
2009-11-11 18:11:07 +00:00
|
|
|
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
|
2011-02-21 03:42:44 +00:00
|
|
|
let rd = O7.Num, rs1 = G0.Num in
|
|
|
|
def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
|
|
|
|
"jmp %o7+$val", [(retflag simm13:$val)]>;
|
2011-01-20 05:08:26 +00:00
|
|
|
|
2011-02-21 03:42:44 +00:00
|
|
|
let rd = I7.Num, rs1 = G0.Num in
|
|
|
|
def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
|
|
|
|
"jmp %i7+$val", []>;
|
2004-10-14 22:32:49 +00:00
|
|
|
}
|
2004-04-02 20:53:37 +00:00
|
|
|
|
|
|
|
// Section B.1 - Load Integer Instructions, p. 90
|
2005-12-17 20:26:45 +00:00
|
|
|
def LDSBrr : F3_1<3, 0b001001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:26:45 +00:00
|
|
|
"ldsb [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def LDSBri : F3_2<3, 0b001001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:18:24 +00:00
|
|
|
"ldsb [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
|
2005-12-17 20:26:45 +00:00
|
|
|
def LDSHrr : F3_1<3, 0b001010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:26:45 +00:00
|
|
|
"ldsh [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def LDSHri : F3_2<3, 0b001010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:18:24 +00:00
|
|
|
"ldsh [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
|
2005-12-17 20:26:45 +00:00
|
|
|
def LDUBrr : F3_1<3, 0b000001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:26:45 +00:00
|
|
|
"ldub [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def LDUBri : F3_2<3, 0b000001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:18:24 +00:00
|
|
|
"ldub [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
|
2005-12-17 20:26:45 +00:00
|
|
|
def LDUHrr : F3_1<3, 0b000010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:26:45 +00:00
|
|
|
"lduh [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def LDUHri : F3_2<3, 0b000010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:18:24 +00:00
|
|
|
"lduh [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
|
2005-12-17 20:26:45 +00:00
|
|
|
def LDrr : F3_1<3, 0b000000,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:26:45 +00:00
|
|
|
"ld [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (load ADDRrr:$addr))]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def LDri : F3_2<3, 0b000000,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:18:24 +00:00
|
|
|
"ld [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (load ADDRri:$addr))]>;
|
2004-04-02 20:53:37 +00:00
|
|
|
|
2004-06-18 05:19:27 +00:00
|
|
|
// Section B.2 - Load Floating-point Instructions, p. 92
|
2005-12-16 06:25:42 +00:00
|
|
|
def LDFrr : F3_1<3, 0b100000,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:32:47 +00:00
|
|
|
"ld [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (load ADDRrr:$addr))]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def LDFri : F3_2<3, 0b100000,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:32:47 +00:00
|
|
|
"ld [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (load ADDRri:$addr))]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def LDDFrr : F3_1<3, 0b100011,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins MEMrr:$addr),
|
2005-12-17 20:32:47 +00:00
|
|
|
"ldd [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (load ADDRrr:$addr))]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def LDDFri : F3_2<3, 0b100011,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins MEMri:$addr),
|
2005-12-17 20:32:47 +00:00
|
|
|
"ldd [$addr], $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (load ADDRri:$addr))]>;
|
2004-06-18 05:19:27 +00:00
|
|
|
|
2004-04-02 20:53:37 +00:00
|
|
|
// Section B.4 - Store Integer Instructions, p. 95
|
2005-12-17 20:44:36 +00:00
|
|
|
def STBrr : F3_1<3, 0b000101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMrr:$addr, IntRegs:$src),
|
2005-12-17 20:44:36 +00:00
|
|
|
"stb $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(truncstorei8 i32:$src, ADDRrr:$addr)]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def STBri : F3_2<3, 0b000101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMri:$addr, IntRegs:$src),
|
2005-12-17 20:42:55 +00:00
|
|
|
"stb $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(truncstorei8 i32:$src, ADDRri:$addr)]>;
|
2005-12-17 20:44:36 +00:00
|
|
|
def STHrr : F3_1<3, 0b000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMrr:$addr, IntRegs:$src),
|
2005-12-17 20:44:36 +00:00
|
|
|
"sth $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(truncstorei16 i32:$src, ADDRrr:$addr)]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def STHri : F3_2<3, 0b000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMri:$addr, IntRegs:$src),
|
2005-12-17 20:42:55 +00:00
|
|
|
"sth $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(truncstorei16 i32:$src, ADDRri:$addr)]>;
|
2005-12-17 20:44:36 +00:00
|
|
|
def STrr : F3_1<3, 0b000100,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMrr:$addr, IntRegs:$src),
|
2005-12-17 20:44:36 +00:00
|
|
|
"st $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(store i32:$src, ADDRrr:$addr)]>;
|
2005-12-17 20:18:24 +00:00
|
|
|
def STri : F3_2<3, 0b000100,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMri:$addr, IntRegs:$src),
|
2005-12-17 20:42:55 +00:00
|
|
|
"st $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(store i32:$src, ADDRri:$addr)]>;
|
2004-06-24 07:36:59 +00:00
|
|
|
|
|
|
|
// Section B.5 - Store Floating-point Instructions, p. 97
|
2005-12-16 06:25:42 +00:00
|
|
|
def STFrr : F3_1<3, 0b100100,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMrr:$addr, FPRegs:$src),
|
2005-12-17 20:47:16 +00:00
|
|
|
"st $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(store f32:$src, ADDRrr:$addr)]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def STFri : F3_2<3, 0b100100,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMri:$addr, FPRegs:$src),
|
2005-12-17 20:47:16 +00:00
|
|
|
"st $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(store f32:$src, ADDRri:$addr)]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def STDFrr : F3_1<3, 0b100111,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMrr:$addr, DFPRegs:$src),
|
2005-12-17 20:47:16 +00:00
|
|
|
"std $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(store f64:$src, ADDRrr:$addr)]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def STDFri : F3_2<3, 0b100111,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs), (ins MEMri:$addr, DFPRegs:$src),
|
2005-12-17 20:47:16 +00:00
|
|
|
"std $src, [$addr]",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(store f64:$src, ADDRri:$addr)]>;
|
2004-02-26 00:37:12 +00:00
|
|
|
|
2004-03-04 04:37:45 +00:00
|
|
|
// Section B.9 - SETHI Instruction, p. 104
|
2005-12-16 07:18:48 +00:00
|
|
|
def SETHIi: F2_1<0b100,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins i32imm:$src),
|
2005-12-17 19:37:00 +00:00
|
|
|
"sethi $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, SETHIimm:$src)]>;
|
2004-03-04 00:56:25 +00:00
|
|
|
|
2004-04-02 20:53:37 +00:00
|
|
|
// Section B.10 - NOP Instruction, p. 105
|
|
|
|
// (It's a special case of SETHI)
|
2004-10-14 22:33:32 +00:00
|
|
|
let rd = 0, imm22 = 0 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
|
2004-04-02 20:53:37 +00:00
|
|
|
|
2004-03-03 23:03:14 +00:00
|
|
|
// Section B.11 - Logical Instructions, p. 106
|
2006-09-01 22:28:02 +00:00
|
|
|
defm AND : F3_12<"and", 0b000001, and>;
|
|
|
|
|
2005-12-16 06:25:42 +00:00
|
|
|
def ANDNrr : F3_1<2, 0b000101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
add andn/orn/xorn patterns. This allows us to compile this:
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
save -96, %sp, %sp
andn %i4, %i2, %i0
andn %i5, %i3, %i1
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
xor %i2, -1, %l0
xor %i3, -1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
The simpleisel emits: :(
test:
save -96, %sp, %sp
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l1
xor %i2, %l0, %l0
xor %i3, %l1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24793 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 21:05:49 +00:00
|
|
|
"andn $b, $c, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def ANDNri : F3_2<2, 0b000101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
2005-12-17 08:06:43 +00:00
|
|
|
"andn $b, $c, $dst", []>;
|
2006-09-01 22:28:02 +00:00
|
|
|
|
|
|
|
defm OR : F3_12<"or", 0b000010, or>;
|
|
|
|
|
2005-12-16 06:25:42 +00:00
|
|
|
def ORNrr : F3_1<2, 0b000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
add andn/orn/xorn patterns. This allows us to compile this:
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
save -96, %sp, %sp
andn %i4, %i2, %i0
andn %i5, %i3, %i1
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
xor %i2, -1, %l0
xor %i3, -1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
The simpleisel emits: :(
test:
save -96, %sp, %sp
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l1
xor %i2, %l0, %l0
xor %i3, %l1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24793 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 21:05:49 +00:00
|
|
|
"orn $b, $c, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def ORNri : F3_2<2, 0b000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
2005-12-17 08:06:43 +00:00
|
|
|
"orn $b, $c, $dst", []>;
|
2006-09-01 22:28:02 +00:00
|
|
|
defm XOR : F3_12<"xor", 0b000011, xor>;
|
|
|
|
|
2005-12-16 06:25:42 +00:00
|
|
|
def XNORrr : F3_1<2, 0b000111,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
add andn/orn/xorn patterns. This allows us to compile this:
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
save -96, %sp, %sp
andn %i4, %i2, %i0
andn %i5, %i3, %i1
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
xor %i2, -1, %l0
xor %i3, -1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
The simpleisel emits: :(
test:
save -96, %sp, %sp
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l1
xor %i2, %l0, %l0
xor %i3, %l1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24793 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 21:05:49 +00:00
|
|
|
"xnor $b, $c, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
|
2005-12-16 06:25:42 +00:00
|
|
|
def XNORri : F3_2<2, 0b000111,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
2005-12-17 08:06:43 +00:00
|
|
|
"xnor $b, $c, $dst", []>;
|
2004-03-03 23:03:14 +00:00
|
|
|
|
|
|
|
// Section B.12 - Shift Instructions, p. 107
|
2006-09-01 22:28:02 +00:00
|
|
|
defm SLL : F3_12<"sll", 0b100101, shl>;
|
|
|
|
defm SRL : F3_12<"srl", 0b100110, srl>;
|
|
|
|
defm SRA : F3_12<"sra", 0b100111, sra>;
|
2004-03-03 23:03:14 +00:00
|
|
|
|
|
|
|
// Section B.13 - Add Instructions, p. 108
|
2006-09-01 22:28:02 +00:00
|
|
|
defm ADD : F3_12<"add", 0b000000, add>;
|
2006-02-10 07:35:42 +00:00
|
|
|
|
|
|
|
// "LEA" forms of add (patterns to make tblgen happy)
|
|
|
|
def LEA_ADDri : F3_2<2, 0b000000,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs IntRegs:$dst), (ins MEMri:$addr),
|
2006-02-10 07:35:42 +00:00
|
|
|
"add ${addr:arith}, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set i32:$dst, ADDRri:$addr)]>;
|
2009-09-15 17:46:24 +00:00
|
|
|
|
|
|
|
let Defs = [ICC] in
|
|
|
|
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
|
|
|
|
|
2011-01-11 22:38:28 +00:00
|
|
|
let Uses = [ICC] in
|
|
|
|
defm ADDX : F3_12<"addx", 0b001000, adde>;
|
2004-03-03 23:03:14 +00:00
|
|
|
|
2004-03-04 04:37:45 +00:00
|
|
|
// Section B.15 - Subtract Instructions, p. 110
|
2006-09-01 22:28:02 +00:00
|
|
|
defm SUB : F3_12 <"sub" , 0b000100, sub>;
|
2010-12-28 20:39:17 +00:00
|
|
|
let Uses = [ICC] in
|
|
|
|
defm SUBX : F3_12 <"subx" , 0b001100, sube>;
|
2006-09-01 22:28:02 +00:00
|
|
|
|
2010-12-28 20:39:17 +00:00
|
|
|
let Defs = [ICC] in
|
2009-09-15 17:46:24 +00:00
|
|
|
defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
|
|
|
|
|
2010-12-28 20:39:17 +00:00
|
|
|
let Uses = [ICC], Defs = [ICC] in
|
2009-09-15 17:46:24 +00:00
|
|
|
def SUBXCCrr: F3_1<2, 0b011100,
|
|
|
|
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
|
|
|
"subxcc $b, $c, $dst", []>;
|
2004-03-04 04:37:45 +00:00
|
|
|
|
2004-03-16 22:37:13 +00:00
|
|
|
|
2010-12-28 20:39:17 +00:00
|
|
|
// Section B.18 - Multiply Instructions, p. 113
|
|
|
|
let Defs = [Y] in {
|
|
|
|
defm UMUL : F3_12np<"umul", 0b001010>;
|
|
|
|
defm SMUL : F3_12 <"smul", 0b001011, mul>;
|
|
|
|
}
|
2006-02-09 05:06:36 +00:00
|
|
|
|
2004-04-07 04:01:00 +00:00
|
|
|
// Section B.19 - Divide Instructions, p. 115
|
2010-12-28 20:39:17 +00:00
|
|
|
let Defs = [Y] in {
|
|
|
|
defm UDIV : F3_12np<"udiv", 0b001110>;
|
|
|
|
defm SDIV : F3_12np<"sdiv", 0b001111>;
|
|
|
|
}
|
2004-04-07 04:01:00 +00:00
|
|
|
|
2004-03-06 05:32:13 +00:00
|
|
|
// Section B.20 - SAVE and RESTORE, p. 117
|
2006-09-01 22:28:02 +00:00
|
|
|
defm SAVE : F3_12np<"save" , 0b111100>;
|
|
|
|
defm RESTORE : F3_12np<"restore", 0b111101>;
|
2004-03-06 05:32:13 +00:00
|
|
|
|
2004-05-08 04:21:32 +00:00
|
|
|
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
|
2004-06-17 22:34:29 +00:00
|
|
|
|
|
|
|
// conditional branch class:
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
|
2004-06-17 22:34:29 +00:00
|
|
|
let isBranch = 1;
|
|
|
|
let isTerminator = 1;
|
2004-09-30 04:04:48 +00:00
|
|
|
let hasDelaySlot = 1;
|
2004-06-17 22:34:29 +00:00
|
|
|
}
|
2004-07-31 02:24:37 +00:00
|
|
|
|
|
|
|
let isBarrier = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
def BA : BranchSP<0b1000, (ins brtarget:$dst),
|
2005-12-18 01:46:58 +00:00
|
|
|
"ba $dst",
|
|
|
|
[(br bb:$dst)]>;
|
2009-09-15 17:46:24 +00:00
|
|
|
|
2006-01-31 06:56:30 +00:00
|
|
|
// FIXME: the encoding for the JIT should look at the condition field.
|
2009-09-15 17:46:24 +00:00
|
|
|
let Uses = [ICC] in
|
|
|
|
def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
|
|
|
|
"b$cc $dst",
|
|
|
|
[(SPbricc bb:$dst, imm:$cc)]>;
|
2006-01-30 07:43:04 +00:00
|
|
|
|
2004-05-08 04:21:32 +00:00
|
|
|
|
2004-07-08 09:08:22 +00:00
|
|
|
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
|
|
|
|
|
|
|
|
// floating-point conditional branch class:
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
|
2004-07-08 09:08:22 +00:00
|
|
|
let isBranch = 1;
|
|
|
|
let isTerminator = 1;
|
2004-09-30 04:04:48 +00:00
|
|
|
let hasDelaySlot = 1;
|
2004-07-08 09:08:22 +00:00
|
|
|
}
|
|
|
|
|
2006-01-31 06:56:30 +00:00
|
|
|
// FIXME: the encoding for the JIT should look at the condition field.
|
2009-09-15 17:46:24 +00:00
|
|
|
let Uses = [FCC] in
|
|
|
|
def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
|
|
|
|
"fb$cc $dst",
|
|
|
|
[(SPbrfcc bb:$dst, imm:$cc)]>;
|
2004-11-16 07:32:09 +00:00
|
|
|
|
|
|
|
|
2004-04-02 20:53:37 +00:00
|
|
|
// Section B.24 - Call and Link Instruction, p. 125
|
2004-03-06 05:32:13 +00:00
|
|
|
// This is the only Format 1 instruction
|
2011-01-12 03:18:21 +00:00
|
|
|
let Uses = [O6],
|
2007-07-21 00:34:19 +00:00
|
|
|
hasDelaySlot = 1, isCall = 1,
|
2005-12-18 15:55:15 +00:00
|
|
|
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
|
2011-01-20 05:08:26 +00:00
|
|
|
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
|
|
|
|
ICC, FCC, Y] in {
|
2011-01-12 03:18:21 +00:00
|
|
|
def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
|
2005-12-23 22:14:32 +00:00
|
|
|
"call $dst", []> {
|
2004-09-29 20:45:05 +00:00
|
|
|
bits<30> disp;
|
|
|
|
let op = 1;
|
|
|
|
let Inst{29-0} = disp;
|
|
|
|
}
|
2005-12-23 22:14:32 +00:00
|
|
|
|
2005-12-18 15:55:15 +00:00
|
|
|
// indirect calls
|
2005-12-16 06:52:00 +00:00
|
|
|
def JMPLrr : F3_1<2, 0b111000,
|
2011-01-12 03:18:21 +00:00
|
|
|
(outs), (ins MEMrr:$ptr, variable_ops),
|
2005-12-19 01:22:53 +00:00
|
|
|
"call $ptr",
|
2010-03-18 23:57:57 +00:00
|
|
|
[(call ADDRrr:$ptr)]>;
|
2005-12-18 15:55:15 +00:00
|
|
|
def JMPLri : F3_2<2, 0b111000,
|
2011-01-12 03:18:21 +00:00
|
|
|
(outs), (ins MEMri:$ptr, variable_ops),
|
2005-12-19 01:22:53 +00:00
|
|
|
"call $ptr",
|
2010-03-18 23:57:57 +00:00
|
|
|
[(call ADDRri:$ptr)]>;
|
2004-09-29 20:45:05 +00:00
|
|
|
}
|
2004-02-26 00:37:12 +00:00
|
|
|
|
2005-12-17 22:22:53 +00:00
|
|
|
// Section B.28 - Read State Register Instructions
|
2010-12-28 20:39:17 +00:00
|
|
|
let Uses = [Y] in
|
|
|
|
def RDY : F3_1<2, 0b101000,
|
|
|
|
(outs IntRegs:$dst), (ins),
|
|
|
|
"rd %y, $dst", []>;
|
2005-12-17 22:22:53 +00:00
|
|
|
|
2004-04-07 04:06:46 +00:00
|
|
|
// Section B.29 - Write State Register Instructions
|
2010-12-28 20:39:17 +00:00
|
|
|
let Defs = [Y] in {
|
|
|
|
def WRYrr : F3_1<2, 0b110000,
|
|
|
|
(outs), (ins IntRegs:$b, IntRegs:$c),
|
|
|
|
"wr $b, $c, %y", []>;
|
|
|
|
def WRYri : F3_2<2, 0b110000,
|
|
|
|
(outs), (ins IntRegs:$b, i32imm:$c),
|
|
|
|
"wr $b, $c, %y", []>;
|
|
|
|
}
|
2004-06-27 22:53:56 +00:00
|
|
|
// Convert Integer to Floating-point Instructions, p. 141
|
2005-12-17 06:32:52 +00:00
|
|
|
def FITOS : F3_3<2, 0b110100, 0b011000100,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src),
|
2005-12-18 06:59:57 +00:00
|
|
|
"fitos $src, $dst",
|
2006-02-05 05:50:24 +00:00
|
|
|
[(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FITOD : F3_3<2, 0b110100, 0b011001000,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins FPRegs:$src),
|
2005-12-18 06:59:57 +00:00
|
|
|
"fitod $src, $dst",
|
2006-02-05 05:50:24 +00:00
|
|
|
[(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
|
2004-06-27 22:53:56 +00:00
|
|
|
|
2004-10-14 19:39:35 +00:00
|
|
|
// Convert Floating-point to Integer Instructions, p. 142
|
2005-12-17 06:32:52 +00:00
|
|
|
def FSTOI : F3_3<2, 0b110100, 0b011010001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src),
|
2005-12-18 06:59:57 +00:00
|
|
|
"fstoi $src, $dst",
|
2006-02-05 05:50:24 +00:00
|
|
|
[(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FDTOI : F3_3<2, 0b110100, 0b011010010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins DFPRegs:$src),
|
2005-12-18 06:59:57 +00:00
|
|
|
"fdtoi $src, $dst",
|
2006-02-05 05:50:24 +00:00
|
|
|
[(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
|
2004-10-14 19:39:35 +00:00
|
|
|
|
2004-06-24 21:22:09 +00:00
|
|
|
// Convert between Floating-point Formats Instructions, p. 143
|
2005-12-17 06:32:52 +00:00
|
|
|
def FSTOD : F3_3<2, 0b110100, 0b011001001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins FPRegs:$src),
|
2005-12-17 23:14:30 +00:00
|
|
|
"fstod $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fextend f32:$src))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FDTOS : F3_3<2, 0b110100, 0b011000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins DFPRegs:$src),
|
2005-12-17 23:14:30 +00:00
|
|
|
"fdtos $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fround f64:$src))]>;
|
2004-06-24 21:22:09 +00:00
|
|
|
|
2004-06-18 06:28:10 +00:00
|
|
|
// Floating-point Move Instructions, p. 144
|
2005-12-17 06:32:52 +00:00
|
|
|
def FMOVS : F3_3<2, 0b110100, 0b000000001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src),
|
2005-12-17 23:05:35 +00:00
|
|
|
"fmovs $src, $dst", []>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FNEGS : F3_3<2, 0b110100, 0b000000101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src),
|
2005-12-17 23:20:27 +00:00
|
|
|
"fnegs $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fneg f32:$src))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FABSS : F3_3<2, 0b110100, 0b000001001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src),
|
2005-12-17 23:20:27 +00:00
|
|
|
"fabss $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fabs f32:$src))]>;
|
2005-12-17 23:52:08 +00:00
|
|
|
|
2005-12-17 23:20:27 +00:00
|
|
|
|
|
|
|
// Floating-point Square Root Instructions, p.145
|
|
|
|
def FSQRTS : F3_3<2, 0b110100, 0b000101001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src),
|
2005-12-17 23:20:27 +00:00
|
|
|
"fsqrts $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fsqrt f32:$src))]>;
|
2005-12-17 23:20:27 +00:00
|
|
|
def FSQRTD : F3_3<2, 0b110100, 0b000101010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
2005-12-17 23:20:27 +00:00
|
|
|
"fsqrtd $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fsqrt f64:$src))]>;
|
2005-12-17 23:20:27 +00:00
|
|
|
|
|
|
|
|
2004-06-18 06:28:10 +00:00
|
|
|
|
2004-06-27 22:53:56 +00:00
|
|
|
// Floating-point Add and Subtract Instructions, p. 146
|
2005-12-17 06:32:52 +00:00
|
|
|
def FADDS : F3_3<2, 0b110100, 0b001000001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fadds $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FADDD : F3_3<2, 0b110100, 0b001000010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"faddd $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FSUBS : F3_3<2, 0b110100, 0b001000101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fsubs $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FSUBD : F3_3<2, 0b110100, 0b001000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fsubd $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
|
2004-06-27 22:53:56 +00:00
|
|
|
|
|
|
|
// Floating-point Multiply and Divide Instructions, p. 147
|
2005-12-17 06:32:52 +00:00
|
|
|
def FMULS : F3_3<2, 0b110100, 0b001001001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fmuls $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FMULD : F3_3<2, 0b110100, 0b001001010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fmuld $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FSMULD : F3_3<2, 0b110100, 0b001101001,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
2005-12-17 23:14:30 +00:00
|
|
|
"fsmuld $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fmul (fextend f32:$src1),
|
|
|
|
(fextend f32:$src2)))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FDIVS : F3_3<2, 0b110100, 0b001001101,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fdivs $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
|
2005-12-17 06:32:52 +00:00
|
|
|
def FDIVD : F3_3<2, 0b110100, 0b001001110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
2005-12-17 23:10:46 +00:00
|
|
|
"fdivd $src1, $src2, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
|
2004-06-24 21:22:09 +00:00
|
|
|
|
2004-07-08 09:08:22 +00:00
|
|
|
// Floating-point Compare Instructions, p. 148
|
2004-09-30 04:04:48 +00:00
|
|
|
// Note: the 2nd template arg is different for these guys.
|
|
|
|
// Note 2: the result of a FCMP is not available until the 2nd cycle
|
|
|
|
// after the instr is retired, but there is no interlock. This behavior
|
2005-12-17 06:32:52 +00:00
|
|
|
// is modelled with a forced noop after the instruction.
|
2009-09-15 17:46:24 +00:00
|
|
|
let Defs = [FCC] in {
|
|
|
|
def FCMPS : F3_3<2, 0b110101, 0b001010001,
|
|
|
|
(outs), (ins FPRegs:$src1, FPRegs:$src2),
|
|
|
|
"fcmps $src1, $src2\n\tnop",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(SPcmpfcc f32:$src1, f32:$src2)]>;
|
2009-09-15 17:46:24 +00:00
|
|
|
def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
|
|
|
(outs), (ins DFPRegs:$src1, DFPRegs:$src2),
|
|
|
|
"fcmpd $src1, $src2\n\tnop",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(SPcmpfcc f64:$src1, f64:$src2)]>;
|
2009-09-15 17:46:24 +00:00
|
|
|
}
|
First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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//===----------------------------------------------------------------------===//
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// V9 Instructions
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//===----------------------------------------------------------------------===//
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// V9 Conditional Moves.
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2010-06-21 20:22:35 +00:00
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let Predicates = [HasV9], Constraints = "$T = $dst" in {
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2006-01-31 06:24:29 +00:00
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// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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// FIXME: Add instruction encodings for the JIT some day.
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2011-01-22 11:36:24 +00:00
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let Uses = [ICC] in {
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def MOVICCrr
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set i32:$dst, (SPselecticc i32:$F, i32:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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def MOVICCri
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set i32:$dst, (SPselecticc simm11:$F, i32:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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}
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let Uses = [FCC] in {
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def MOVFCCrr
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set i32:$dst, (SPselectfcc i32:$F, i32:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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def MOVFCCri
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set i32:$dst, (SPselectfcc simm11:$F, i32:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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}
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let Uses = [ICC] in {
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def FMOVS_ICC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %icc, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set f32:$dst,
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(SPselecticc f32:$F, f32:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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def FMOVD_ICC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %icc, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set f64:$dst, (SPselecticc f64:$F, f64:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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}
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let Uses = [FCC] in {
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def FMOVS_FCC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %fcc0, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set f32:$dst, (SPselectfcc f32:$F, f32:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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def FMOVD_FCC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %fcc0, $F, $dst",
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2013-03-24 00:56:20 +00:00
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[(set f64:$dst, (SPselectfcc f64:$F, f64:$T, imm:$cc))]>;
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2011-01-22 11:36:24 +00:00
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}
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2006-01-31 07:26:55 +00:00
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|
First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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}
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2006-01-30 05:48:37 +00:00
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// Floating-Point Move Instructions, p. 164 of the V9 manual.
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let Predicates = [HasV9] in {
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def FMOVD : F3_3<2, 0b110100, 0b000000010,
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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2006-01-30 05:48:37 +00:00
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"fmovd $src, $dst", []>;
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def FNEGD : F3_3<2, 0b110100, 0b000000110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
2006-01-30 05:48:37 +00:00
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"fnegd $src, $dst",
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2013-03-24 00:56:20 +00:00
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[(set f64:$dst, (fneg f64:$src))]>;
|
2006-01-30 05:48:37 +00:00
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def FABSD : F3_3<2, 0b110100, 0b000001010,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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2006-01-30 05:48:37 +00:00
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|
|
"fabsd $src, $dst",
|
2013-03-24 00:56:20 +00:00
|
|
|
[(set f64:$dst, (fabs f64:$src))]>;
|
2006-01-30 05:48:37 +00:00
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}
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2006-01-30 06:14:02 +00:00
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|
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
|
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|
// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
|
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|
def POPCrr : F3_1<2, 0b101110,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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(outs IntRegs:$dst), (ins IntRegs:$src),
|
2006-01-30 06:14:02 +00:00
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"popc $src, $dst", []>, Requires<[HasV9]>;
|
2013-03-23 20:35:05 +00:00
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def : Pat<(ctpop i32:$src),
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2013-03-24 19:37:04 +00:00
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(POPCrr (SLLri $src, 0))>;
|
2006-01-30 06:14:02 +00:00
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|
2005-12-17 19:07:57 +00:00
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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|
//===----------------------------------------------------------------------===//
|
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// Small immediates.
|
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def : Pat<(i32 simm13:$val),
|
2013-04-02 04:08:54 +00:00
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(ORri (i32 G0), imm:$val)>;
|
2005-12-17 19:41:43 +00:00
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// Arbitrary immediates.
|
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def : Pat<(i32 imm:$val),
|
2005-12-17 20:04:49 +00:00
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
|
2005-12-18 02:10:39 +00:00
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|
2006-02-17 05:43:56 +00:00
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// subc
|
2013-03-23 20:35:05 +00:00
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def : Pat<(subc i32:$b, i32:$c),
|
2013-03-24 19:37:04 +00:00
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|
(SUBCCrr $b, $c)>;
|
2013-03-23 20:35:05 +00:00
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def : Pat<(subc i32:$b, simm13:$val),
|
2013-03-24 19:37:04 +00:00
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(SUBCCri $b, imm:$val)>;
|
2006-02-17 05:43:56 +00:00
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2005-12-18 02:37:35 +00:00
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// Global addresses, constant pool entries
|
2006-02-05 05:50:24 +00:00
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|
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
|
2013-04-02 04:08:54 +00:00
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def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
|
2006-02-05 05:50:24 +00:00
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def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
|
2013-04-02 04:08:54 +00:00
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def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
|
2005-12-18 21:03:04 +00:00
|
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|
Don't print a label for the first MBB in a function.
Compile this:
%_2E_str_8 = external global [75 x sbyte]
implementation ; Functions:
declare int %printf(sbyte*, ...)
void %test()
%tmp.101 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([75 x sbyte]* %_2E_str_8, int 0, int 0) ) ; <int> [#uses=0]
unreachable
}
to this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
add %l0, %lo(_2E_str_8), %o0
call printf
nop
instead of this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
or %g0, %lo(_2E_str_8), %l1 ;; extra instruction
add %l1, %l0, %o0
call printf
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25335 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-15 09:26:27 +00:00
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// Add reg, lo. This is used when taking the addr of a global/constpool entry.
|
2013-03-23 20:35:05 +00:00
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def : Pat<(add i32:$r, (SPlo tglobaladdr:$in)),
|
2013-03-24 19:37:04 +00:00
|
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(ADDri $r, tglobaladdr:$in)>;
|
2013-03-23 20:35:05 +00:00
|
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def : Pat<(add i32:$r, (SPlo tconstpool:$in)),
|
2013-03-24 19:37:04 +00:00
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(ADDri $r, tconstpool:$in)>;
|
Don't print a label for the first MBB in a function.
Compile this:
%_2E_str_8 = external global [75 x sbyte]
implementation ; Functions:
declare int %printf(sbyte*, ...)
void %test()
%tmp.101 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([75 x sbyte]* %_2E_str_8, int 0, int 0) ) ; <int> [#uses=0]
unreachable
}
to this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
add %l0, %lo(_2E_str_8), %o0
call printf
nop
instead of this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
or %g0, %lo(_2E_str_8), %l1 ;; extra instruction
add %l1, %l0, %o0
call printf
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25335 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-15 09:26:27 +00:00
|
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|
2005-12-23 22:14:32 +00:00
|
|
|
// Calls:
|
|
|
|
def : Pat<(call tglobaladdr:$dst),
|
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|
|
(CALL tglobaladdr:$dst)>;
|
2006-02-10 07:35:42 +00:00
|
|
|
def : Pat<(call texternalsym:$dst),
|
|
|
|
(CALL texternalsym:$dst)>;
|
2005-12-23 22:14:32 +00:00
|
|
|
|
2005-12-18 23:18:37 +00:00
|
|
|
// Map integer extload's to zextloads.
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
|
|
|
|
def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
|
|
|
|
def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
|
|
|
|
def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
|
|
|
|
def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
|
|
|
|
def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
|
2005-12-19 00:19:21 +00:00
|
|
|
|
2005-12-19 01:43:04 +00:00
|
|
|
// zextload bool -> zextload byte
|
2006-10-09 20:57:25 +00:00
|
|
|
def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
|
|
|
|
def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
|
2013-04-02 04:09:12 +00:00
|
|
|
|
|
|
|
include "SparcInstr64Bit.td"
|