Commit Graph

4641 Commits

Author SHA1 Message Date
Owen Anderson
ed1088afb5 A select between a constant and zero, when fed by a bit test, can be efficiently
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:58:22 +00:00
Cameron Esfahani
4af1eaee70 Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:35:21 +00:00
Chris Lattner
1eb1b68e3a Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:49:14 +00:00
Chris Lattner
f93b90c5df reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:39:11 +00:00
Chris Lattner
40d66052f4 linux has a different stack alignment than the mac, relax this a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:46:26 +00:00
Chris Lattner
8864155a35 give VZEXT_LOAD a memory operand, it now works with segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:34:38 +00:00
Chris Lattner
0b79cfee15 revert r114386 now that address modes work correctly, we get a nice
call through gs-relative memory now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7 give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:59:42 +00:00
Chris Lattner
b72d53d8ef filecheckize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:57:27 +00:00
Evan Cheng
691e64a54c OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:49:07 +00:00
Owen Anderson
8614167572 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:51:46 +00:00
Devang Patel
161f0caaf9 Use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:50:32 +00:00
Owen Anderson
c004eec71b When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:19 +00:00
Chris Lattner
08bad54baf fix rdar://8453210, a crash handling a call through a GS relative load.
For now, just disable folding the load into the call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 03:37:00 +00:00
Evan Cheng
44be1a8d66 Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 22:52:00 +00:00
Owen Anderson
765fd9c62d CombinerAA is now reordering these stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:56:29 +00:00
Owen Anderson
4a9f150926 When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:39:59 +00:00
Jim Grosbach
1dc335a79f Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:32:20 +00:00
NAKAMURA Takumi
e6af80d11d test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen.
r114297 raises 3 failures. They might fail also on mingw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 21:58:55 +00:00
Eric Christopher
50880d08ec Add the exit instruction to the PTX target.
Patch by Che-Liang Chiou <clchiou@gmail.com>!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 18:52:28 +00:00
Owen Anderson
14ac1dd2be Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is
NO path to the destination containing side effects, not that SOME path contains no side effects.
In  practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 04:45:14 +00:00
Bob Wilson
75f0288b7d Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
and shift instructions on ARM. Update the tests to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Evan Cheng
6edb0eac87 Teach machine sink to
1) Do forward copy propagation. This makes it easier to estimate the cost of the
   instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
   PHI nodes.
Critical edge splitting is not yet enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
9ce75625eb Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:58:46 +00:00
Jim Grosbach
db664ad71e FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:46:16 +00:00
Jim Grosbach
1aaf4cb393 Move thumb2 tests to the thumb2 directory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:34:09 +00:00
Jim Grosbach
c0911c3b3e tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:27:26 +00:00
Dan Gohman
d8c0a51362 Avoid emitting a PIC base register if no PIC addresses are needed.
This fixes rdar://8396318.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:24:24 +00:00
Jim Grosbach
d4ef24344a tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:21:03 +00:00
Jim Grosbach
48afc24274 tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:17:41 +00:00
Dale Johannesen
677c6ecd08 When substituting sunkaddrs into indirect arguments an asm, we were
walking the asm arguments once and stashing their Values.  This is
wrong because the same memory location can be in the list twice, and
if the first one has a sunkaddr substituted, the stashed value for the
second one will be wrong (use-after-free).  PR 8154.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 18:30:55 +00:00
Kalle Raiskila
1cd1b0b283 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Bob Wilson
3a951829fe Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
encountered while building llvm-gcc for arm.  This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:12:08 +00:00
Gabor Greif
7602993f2d the darwin9-powerpc buildbot keeps consistently crashing,
backing out following to get it back to green,
so I can investigate in peace:

svn merge -c -113840  llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:53:07 +00:00
Gabor Greif
6f9eea87f7 forgot the testcase change for r113839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 09:30:17 +00:00
Gabor Greif
4e05b32509 test for and-tst peephole optimization
documents the status-quo with its opportunities

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 08:50:43 +00:00
Owen Anderson
2c5f19db2e Re-apply r113679, which was reverted in r113720, which added a paid of new instcombine transforms
to expose greater opportunities for store narrowing in codegen.  This patch fixes a potential
infinite loop in instcombine caused by one of the introduced transforms being overly aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113763 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 17:59:27 +00:00
Eric Christopher
298c45e845 Revert 113679, it was causing an infinite loop in a testcase that I've sent
on to Owen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-12 06:09:23 +00:00
Evan Cheng
3dc0bb3afd Fix test so it passes on non-Darwin hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 06:20:01 +00:00
Bob Wilson
efe7d9a12f Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands.  I changed that to just count the operands but forgot to adjust for
the size of D registers.  This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 05:15:04 +00:00
Evan Cheng
3ef1c8759a Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
Bruno Cardoso Lopes
ae4f7421c0 Add one more pattern to fallback movddup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113522 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:48:34 +00:00
Bob Wilson
0f1e9457a5 Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
the VST pseudos.  The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 05:40:26 +00:00
Jim Grosbach
d0bd76b0fb Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
Re-running some nightly testers w/ it enabled to verify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 20:12:02 +00:00
Eric Christopher
f2605419ea Remove ssp from this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113392 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 19:32:34 +00:00
Kalle Raiskila
0b4ab0cfe0 Fix CellSPU vector shuffles, again.
Some cases of lowering to rotate were miscompiled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 11:53:38 +00:00
Jim Grosbach
e1e6d18786 disable for the moment while tracking down a few Thumb2-O0 failure that look
related. (attempt deux, complete w/ test update this time)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 02:00:34 +00:00
Devang Patel
af3c8024b1 remove these tests for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 22:03:44 +00:00
Devang Patel
1dde7c257a There is no need to force target if the test is going to run on other x86 platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113285 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 20:59:09 +00:00
Devang Patel
49be606954 Fix command line used to link these test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:17:56 +00:00
Devang Patel
fa7f82ce5c Reintroduce dbg-declare tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:01:49 +00:00
Devang Patel
1fa4a97624 Remove last three tests. I need to make them independent of my setup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 17:08:57 +00:00
Devang Patel
85b0258e64 Add a test case to check handling of dbg-declare during hybrid mode where we begin using fast-isel but switch back to DAG building at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113210 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 17:03:44 +00:00
Devang Patel
5a0f9bf63e Add a test case to check handling of dbg-declare by selection DAG builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 16:56:35 +00:00
Devang Patel
db44c12b85 Add a test case to check handling of dbg-declare by fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 16:40:53 +00:00
Chris Lattner
beac75da37 implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 02:18:34 +00:00
Dale Johannesen
caa9ba228d Remove the rest of the nonexistent 64-bit AVX instructions.
Bruno, please review.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 21:23:00 +00:00
Jim Grosbach
65482b1bb8 Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 18:37:12 +00:00
Daniel Dunbar
6a8700301c Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 15:26:42 +00:00
NAKAMURA Takumi
9dceb1305c test/CodeGen/X86: Add explicit -mtriple=(i686|x86_64)-linux for Win32 host.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 03:24:08 +00:00
Bruno Cardoso Lopes
95f1e2d6b5 AVX doesn't support mm operations neither its instrinsics.
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 02:08:45 +00:00
Bob Wilson
eb0c3d3729 Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
vabd intrinsic and add and/or zext operations.  In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests.  Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:35:08 +00:00
Anton Korobeynikov
ace53f2fbc Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 23:03:46 +00:00
Jim Grosbach
1755b3964f For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.

rdar://7352504
rdar://8374540
rdar://8355680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:29:01 +00:00
Dan Gohman
24bde5bce1 Don't narrow the load and store in a load+twiddle+store sequence unless
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 21:18:42 +00:00
Sandeep Patel
b7a11b5399 Fix an unnecessary XFAIL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 20:19:24 +00:00
Jim Grosbach
e7c1416263 Now that register allocation properly considers reserved regs, simplify the
ARM register class allocation order functions to take advantage of that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 18:14:29 +00:00
Bob Wilson
ffde080ae6 Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 16:00:54 +00:00
NAKAMURA Takumi
b51633b476 test/loop-strength-reduce4: Add explicit triplet for Win32 host.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 03:45:58 +00:00
NAKAMURA Takumi
fd03a5124d test/twoaddr-coalesce: Do not use @main.
Win32 codegen emits implicit invoking __main into, to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 03:45:51 +00:00
Bob Wilson
d0b69cf119 Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests.  Add auto-upgrade support for the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 23:50:19 +00:00
Bruno Cardoso Lopes
29c353b9c3 Using target specific nodes for shuffle nodes makes the mask
check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:

  movaps  (%rdi), %xmm0
  movaps  (%rax), %xmm1
  movaps  %xmm0, %xmm2
  movss %xmm1, %xmm2
  shufps  $36, %xmm2, %xmm0

now is generated as:

  movaps  (%rdi), %xmm0
  movaps  %xmm0, %xmm1
  movlps  (%rax), %xmm1
  shufps  $36, %xmm1, %xmm0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:33:20 +00:00
Jakob Stoklund Olesen
0077114efc Teach RemoveCopyByCommutingDef to check all aliases, not just subregisters.
This caused a miscompilation in WebKit where %RAX had conflicting defs when
RemoveCopyByCommutingDef was commuting a %EAX use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112751 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:15:35 +00:00
Chris Lattner
5bcb8a6112 temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 16:00:50 +00:00
Dan Gohman
191bd64a39 Revert 112442 and 112440 until the compile time problems introduced
by 112440 are resolved.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 01:45:53 +00:00
Bill Wendling
43a6c5e2fc We have a chance for an optimization. Consider this code:
int x(int t) {
  if (t & 256)
    return -26;
  return 0;
}

We generate this:

     tst.w   r0, #256
     mvn     r0, #25
     it      eq
     moveq   r0, #0

while gcc generates this:

     ands    r0, r0, #256
     it      ne
     mvnne   r0, #25
     bx      lr

Scandalous really!

During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):

  %r0 = ISD::AND ...
  ARMISD::CMPZ %r0, 0         @ sets [CPSR]
  %r0 = ARMISD::MOVCC 0, -26  @ reads [CPSR]

All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 22:41:22 +00:00
Jim Grosbach
85e75afc8e Update test for 112609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 17:58:47 +00:00
Anton Korobeynikov
5c1919e55d Fix borken test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 23:41:49 +00:00
Bob Wilson
973a074345 Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
Auto-upgrade the old intrinsic and update tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 20:02:30 +00:00
Chris Lattner
1875ce4ad9 two changes:
1) nuke ConstDataCoalSection, which is dead.
2) revise my previous patch for rdar://8018335,
  which was completely wrong.  Specifically, it doesn't 
  make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS,
  because it is for readonly data.  templates (it turns out)
  go to const_coal_nt.  The real fix for rdar://8018335 was
  to give ConstTextCoalSection a section kind of ReadOnly 
  instead of Text.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 18:12:35 +00:00
Duncan Sands
cdd4f8c7cb Correct bogus module triple specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 10:48:29 +00:00
Dan Gohman
eaa40ff74e Make IVUsers iterative instead of recursive.
This has the side effect of reversing the order of most of
IVUser's results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 16:40:03 +00:00
Dan Gohman
2b5258c5f9 Make this test less dependent on register allocation choices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112426 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 14:49:42 +00:00
Kalle Raiskila
bd887df8b9 Fix lowering of INSERT_VECTOR_ELT in SPU.
The IDX was treated as byte index, not element index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 12:41:50 +00:00
Bob Wilson
04d6c289ab Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 05:57:34 +00:00
Chris Lattner
82457d08f9 merge a bunch of shuffle tests into sse2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:19:04 +00:00
Chris Lattner
c19b9477c9 add some nounwind's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:07:47 +00:00
Chris Lattner
24faf611a3 fix the buildvector->insertp[sd] logic to not always create a redundant
insertp[sd] $0, which is a noop.  Before:

_f32:                                   ## @f32
	pshufd	$1, %xmm1, %xmm2
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm2, %xmm3
	addss	%xmm1, %xmm0
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
	insertps	$0, %xmm0, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

after:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movdqa	%xmm2, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

The extra movs are due to a random (poor) scheduling decision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 17:59:08 +00:00
Chris Lattner
3ddcc43040 fix the BuildVector -> unpcklps logic to not do pointless shuffles
when the top elements of a vector are undefined.  This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined.  For example, on:

_Complex float f32(_Complex float A, _Complex float B) {
  return A+B;
}

We used to produce (with SSE2, SSE4.1+ uses insertps):

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$16, %xmm2, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm0
	addss	%xmm1, %xmm0
	pshufd	$16, %xmm0, %xmm1
	movdqa	%xmm2, %xmm0
	unpcklps	%xmm1, %xmm0
	ret

We now produce:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movaps	%xmm2, %xmm0
	unpcklps	%xmm3, %xmm0
	ret

This implements rdar://8368414


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 17:28:30 +00:00
Dan Gohman
badcda4afa Completely disable tail calls when fast-isel is enabled, as fast-isel
doesn't currently support dealing with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 00:51:03 +00:00
Bob Wilson
d4bfd54ec2 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:18:17 +00:00
Chris Lattner
e197fd5182 get this test passing on linux builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 18:49:08 +00:00
Bob Wilson
7a9ef44b3b Add alignment arguments to all the NEON load/store intrinsics.
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 17:13:24 +00:00
Daniel Dunbar
d8d36e61fd X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112250 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 01:30:14 +00:00
Chris Lattner
341fa09a3c Add a hackaround for PR7993 which is causing failures on x86 builders that lack sse2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 06:57:07 +00:00
Chris Lattner
4bbdb4c78c I think enough general codegen bugs are fixed to allow this to work
on random hosts, lets see!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:52:42 +00:00
Chris Lattner
8306968c14 implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:51:22 +00:00
Chris Lattner
8de3bdb16a Make sure this forces the x86 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112169 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:25:05 +00:00
Chris Lattner
97a2a56f43 fix sse1 only codegen in x86-64 mode, which is something we
apparently try to support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:24:29 +00:00
Jim Grosbach
ae47c6d69e Enable pre-RA virtual frame base register allocation. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 00:58:06 +00:00
Bob Wilson
2ac124c561 Revert svn 107892 (with changes to work with trunk). It caused a crash if
a VLD result was not used (Radar 8355607).  It should also fix pr7988, but
I haven't verified that yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 00:13:36 +00:00
Chris Lattner
c87a6d4fb0 temporarily disable this, which started failing on the llvm-i686-linux
builder.  I will investigate tonight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112113 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 23:43:14 +00:00
Chris Lattner
e6f7c267df Change handling of illegal vector types to widen when possible instead of
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats.  This
affects two places in the code: handling cross block values and handling
function return and arguments.  Since vectors are already widened by 
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.

For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
 %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
 %C = fadd <2 x float> %B, %B
  br label %BB
BB:
 %D = fadd <2 x float> %C, %C
 %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ret <4 x float> %E
}

Now compiles into:

_test2:                                 ## @test2
## BB#0:
 addps %xmm0, %xmm0
 addps %xmm0, %xmm0
 ret

previously it compiled into:

_test2:                                 ## @test2
## BB#0:
 addps %xmm0, %xmm0
 pshufd $1, %xmm0, %xmm1
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
 insertps $0, %xmm0, %xmm0
 insertps $16, %xmm1, %xmm0
 addps %xmm0, %xmm0
 ret

This implements rdar://8230384



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 22:49:25 +00:00
Daniel Dunbar
3cc3283fcb ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
comparison that would overflow.
 - The other under/overflow cases can't actually happen because the immediates
   which would trigger them are legal (so we don't enter this code), but
   adjusted the style to make it clear the transform is always valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 16:58:05 +00:00
Eric Christopher
c430223677 Add another basic test cribbed from the x86 fast-isel tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112036 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:57:29 +00:00
Eric Christopher
e8d274c8c9 Run this on thumb and arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:53:15 +00:00
Eric Christopher
dc3d8b812f Make this testcase actually executed with fast-isel on arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:47:00 +00:00
Bruno Cardoso Lopes
ddd10affab Convert test to use filecheck and make it more specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 01:47:16 +00:00
Dan Gohman
92b651fb19 Fix X86's isLegalAddressingMode to recognize that static addresses
need not be RIP-relative in small mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 15:55:12 +00:00
Kalle Raiskila
55aebef654 Fix SPU BE to use all the available return registers.
llc used to assert on the added testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 11:50:48 +00:00
Chris Lattner
d80c7e1232 Add a new llvm.x86.int intrinsic, allowing access to the
x86 int and int3 instructions.  Patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 19:39:25 +00:00
Dan Gohman
8bef744518 Fix x86 fast-isel's cmp+branch folding to avoid folding when the
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-21 02:32:36 +00:00
Bob Wilson
d58b51e67c Replace some NEON vmovl intrinsic that I missed earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 23:22:43 +00:00
Bob Wilson
b31a11b466 Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
zero-extend operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 04:54:02 +00:00
Evan Cheng
e5e7946018 It's possible to sink a def if its local uses are PHI's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 18:33:29 +00:00
Dan Gohman
4bb4641784 When sending stats output to stdout for grepping, don't emit normal
output to standard output also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 22:22:44 +00:00
Dan Gohman
4a8d7db6cf When sending stats output to stdout for grepping, don't emit normal
output to standard output also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 20:32:46 +00:00
Kalle Raiskila
ca9460f5a0 Fix a bug with insertelement on SPU.
The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 10:20:29 +00:00
Kalle Raiskila
86a791284a Remove all traces of v2[i,f]32 on SPU.
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are 
expanded. This causes changes to some dejagnu tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 10:04:39 +00:00
Kalle Raiskila
44ff5f5435 Change SPU C calling convention to match that described in
"SPU Application Binary Interface Specification, v1.9" by
IBM. 
Specifically: use r3-r74 to pass parameters and the return value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 09:50:30 +00:00
Bob Wilson
2003bcfbd2 Expand ZERO_EXTEND operations for NEON vector types.
Testcase from Nick Lewycky.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 01:45:52 +00:00
Dan Gohman
bbc1da8ded Tweak IVUsers' concept of "interesting" to exclude add recurrences
where the step value is an induction variable from an outer loop, to
avoid trouble trying to re-expand such expressions. This effectively
hides such expressions from indvars and lsr, which prevents them
from getting into trouble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 22:50:37 +00:00
Evan Cheng
b9072fdaad Add nounwind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 22:35:20 +00:00
Dale Johannesen
6cf64a631a Make fast scheduler handle asm clobbers correctly.
PR 7882.  Follows suggestion by Amaury Pouly, thanks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 22:17:24 +00:00
Bob Wilson
f955f290c9 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 17:23:19 +00:00
Bob Wilson
7aaf5bf3db Allow more cases of undef shuffle indices and add tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 05:54:34 +00:00
Evan Cheng
97b9b97853 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994
good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 01:20:36 +00:00
Bob Wilson
8f58a2e8e1 Add a testcase for svn 111208.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 23:44:29 +00:00
Bob Wilson
dc66edaced Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
that the high halfword is zero.  The shift need not be exactly 16 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 22:26:55 +00:00
Bob Wilson
b05b80160a Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 22:21:13 +00:00
Bob Wilson
e269ead8c6 Convert a test to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 17:05:27 +00:00
Benjamin Kramer
bde87c4d2a Test expects SSE, give him SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-15 23:32:03 +00:00
Benjamin Kramer
1d81e0eed3 Restore arch on these test, they fail on arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-15 20:42:56 +00:00
Dale Johannesen
a01818c292 Mark as XFAIL on darwin 8. PR 7886.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-15 19:40:29 +00:00
Bob Wilson
703af3ab12 Temporarily disable tail calls on ARM to work around some linker problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 22:43:33 +00:00
Dale Johannesen
1b4051095d Revert 110491. While not wrong, it was based on a
misanalysis and is undesirable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
642eb02045 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
8c05a850f4 Begin to support some vector operations for AVX 256-bit intructions. The long
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 02:06:36 +00:00
Devang Patel
fd56f3c91a This is x86 only test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110887 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:17:38 +00:00
Bruno Cardoso Lopes
4fd393cc26 Add testcases for all AVX 256-bit intrinsics added in the last couple days
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 21:12:09 +00:00
Bruno Cardoso Lopes
1d72aeebf9 Reapply r109881 using a more strict command line for llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:39:23 +00:00
Jim Grosbach
b5aa11f2d6 fix silly typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:32:46 +00:00
Jim Grosbach
7166e622d7 Add a target triple, as the runtime library invocation varies a bit by
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:31:12 +00:00
Evan Cheng
e1f0859789 Fix test and re-enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:25:51 +00:00
Dan Gohman
3cc5d13f58 Temporarily disable some failing tests, until they can be
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 16:36:07 +00:00
Jim Grosbach
fcba5e6b64 cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 15:44:15 +00:00
Dan Gohman
f63fed141e Temporarily disable some failing tests, until they can be
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 15:09:00 +00:00
Bill Wendling
de2b151dbf Consider this code snippet:
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 08:43:16 +00:00
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:17:46 +00:00
Evan Cheng
d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:51:54 +00:00
Evan Cheng
c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:30:38 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:22:01 +00:00
Bill Wendling
d771041828 Update test to match output of optimize compares for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 01:05:02 +00:00
Bill Wendling
bb47d3b471 The optimize comparisons pass removes the "cmp" instruction this is checking for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110739 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 22:16:05 +00:00
Evan Cheng
ac096808a3 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 19:30:19 +00:00
Daniel Dunbar
4bd828f781 Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 18:32:02 +00:00
Jakob Stoklund Olesen
dc0830947a Fix test for more architectures. Patch by Tobias Grosser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 16:48:24 +00:00
Tobias Grosser
0e28b1507f Fix failing testcase.
Those look like typos to me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 09:54:29 +00:00
Devang Patel
2936807564 Handle TAG_constant for integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 07:11:13 +00:00
Evan Cheng
c9aed19747 Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 06:26:49 +00:00
Kalle Raiskila
99534bb81a Have SPU handle halfvec stores aligned by 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 16:33:00 +00:00
Dale Johannesen
7f6eb639bd Use sdmem and sse_load_f64 (etc.) for the vector
form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-07 00:33:42 +00:00
Rafael Espindola
55e9587469 Fix eabi calling convention when a 64 bit value shadows r3.
Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 15:35:32 +00:00
Eric Christopher
e74a088d92 Add an option to always emit realignment code for a particular module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:57:43 +00:00
Devang Patel
baefea4498 Move x86 specific tests into test/CodeGen/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 20:25:37 +00:00
Dan Gohman
a34c885d51 Move x86-specific tests out of test/Transforms/LoopStrengthReduce and
into test/CodeGen/X86, so that they aren't run when the x86 target is
not enabled.

Fix uglygep.ll to not be x86-specific.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 17:04:15 +00:00
Daniel Dunbar
feaac8f7ff tests: CodeGen/X86/GC tests require X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 15:45:33 +00:00
Bill Wendling
af33b7b4a7 The lower invoke pass needs to have unreachable code elimination run after it
because it could create such things. This fixes a MingW buildbot test failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 23:36:02 +00:00
Eli Friedman
7752442bfa PR7814: Truncates cannot be ignored for signed comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 22:40:58 +00:00
Bill Wendling
547b6ed16e Testcase for r110248.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 21:56:30 +00:00
Stuart Hastings
b884666a38 call-imm.ll test case regex fix. Patch by Dimitry Andric!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 15:31:35 +00:00
Kalle Raiskila
bc2697cca0 Make SPU backend handle insertelement and
store for "half vectors"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 13:59:48 +00:00
Bob Wilson
67b453b0d1 Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA
(absolute difference with accumulate) intrinsics.  Radar 8228576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 00:12:08 +00:00
Jakob Stoklund Olesen
0055f97f72 OK, that's it. This test is going away now. But don't worry, I am taking it to a
nice farm in the country where it can play with other tests. And bunnies.

It is not clear what is being tested, and the revision history shows a bunch of
random changes to the expected instruction count. Clearly, we are just fudging
it to pass whenever it fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-03 17:21:14 +00:00
Kalle Raiskila
e1c9159f63 More SPU v2f32 stuff added: insertelement and shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 11:22:10 +00:00
Kalle Raiskila
c9fda996fc Add preliminary v2f32 support for SPU. Like with v2i32, we just
duplicate the instructions and operate on half vectors. 

Also reorder code in SPUInstrInfo.td for better coherency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110037 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 10:25:47 +00:00
Kalle Raiskila
82fe467ca5 Add preliminary v2i32 support for SPU backend. As there are no
such registers in SPU, this support boils down to "emulating" 
them by duplicating instructions on the general purpose registers. 

This adds the most basic operations on v2i32: passing parameters,
addition, subtraction, multiplication and a few others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 08:54:39 +00:00
Eli Friedman
e3837014d6 PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 00:18:19 +00:00
Eli Friedman
348e02600e PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually
improves the generated code in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-01 21:13:28 +00:00
Bob Wilson
6945ef380c Revert new AVX intrinsic tests. They are breaking buildbots and Bruno is
away from a computer now.
--- Reverse-merging r109881 into '.':
D    test/CodeGen/X86/avx-intrinsics-x86.ll
D    test/CodeGen/X86/avx-intrinsics-x86_64.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109959 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31 22:36:03 +00:00
Bruno Cardoso Lopes
74273b8822 A *bunch* of tests for AVX intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 19:57:56 +00:00
Eli Friedman
ad78a88711 Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly
check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 06:44:31 +00:00
Jim Grosbach
6ccfc507dc Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
Dale Johannesen
f630c712b1 Implement vector constants which are splat of
integers with mov + vdup.  8003375.  This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 20:10:08 +00:00
Nate Begeman
51409214d7 Implement a vectorized algorithm for <16 x i8> << <16 x i8>
This is about 4x faster and smaller than the existing scalarization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 00:21:48 +00:00
Nate Begeman
bdcb5afb77 ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches.
For:

define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
  %shl = shl <4 x i32> %r, %a                     ; <<4 x i32>> [#uses=1]
  %tmp2 = bitcast <4 x i32> %shl to <2 x i64>     ; <<2 x i64>> [#uses=1]
  ret <2 x i64> %tmp2
}

We get:

_shl:                                   ## @shl
	pslld	$23, %xmm1
	paddd	LCPI0_0, %xmm1
	cvttps2dq	%xmm1, %xmm1
	pmulld	%xmm1, %xmm0
	ret

Instead of:

_shl:                                   ## @shl
	pshufd	$3, %xmm0, %xmm2
	movd	%xmm2, %eax
	pshufd	$3, %xmm1, %xmm2
	movd	%xmm2, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	pshufd	$1, %xmm0, %xmm3
	movd	%xmm3, %eax
	pshufd	$1, %xmm1, %xmm3
	movd	%xmm3, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm3
	punpckldq	%xmm2, %xmm3
	movd	%xmm0, %eax
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	movhlps	%xmm0, %xmm0
	movd	%xmm0, %eax
	movhlps	%xmm1, %xmm1
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm0
	punpckldq	%xmm0, %xmm2
	movdqa	%xmm2, %xmm0
	punpckldq	%xmm3, %xmm0
	ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 22:37:06 +00:00
Nate Begeman
e0efc216eb Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 18:02:18 +00:00
Anton Korobeynikov
b5a0ef99f8 Currently EH lowering code expects typeinfo to be global only.
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 18:45:39 +00:00
Evan Cheng
3144687df7 - Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:39:59 +00:00
Dan Gohman
cd20c6fb18 Use the proper type for shift counts. This fixes a bootstrap error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 21:08:12 +00:00
Dan Gohman
a4f4d699ec DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
are not demanded. This often allows the anyext to be folded away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 18:03:30 +00:00
Eric Christopher
9a9d275dc7 Custom lower the memory barrier instructions and add support
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 02:48:34 +00:00
Evan Cheng
4a863e2c75 More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 23:53:58 +00:00
Eric Christopher
ab695889c6 Baby steps towards ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 22:26:11 +00:00
Rafael Espindola
bc56501435 Fix calling convention on ARM if vfp2+ is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 11:38:30 +00:00
Dan Gohman
fc3678a346 Fix SCEV denormalization of expressions where the exit value from
one loop is involved in the increment of an addrec for another
loop. This fixes rdar://8168938.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 17:06:20 +00:00
Jim Grosbach
f27ca42552 update tests for smarter BIC usage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 16:16:48 +00:00
Duncan Sands
6bf8eee264 The same problem was being tracked in PR7652.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 15:52:32 +00:00
Bruno Cardoso Lopes
46773793cb Fix PR7174, a couple o Mips fixes:
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.

Patch by stetorvs@gmail.com



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 08:37:04 +00:00
Bruno Cardoso Lopes
29e9daa750 Fix Mips PR7473. Patch by stetorvs@gmail.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 07:58:51 +00:00
Dan Gohman
c6e59b71f5 After a custom inserter, in a block which has constant instructions,
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 22:48:56 +00:00
Owen Anderson
54026c0f1b Remove r108639 now that it is handled by InstCombine instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 08:10:24 +00:00
Owen Anderson
fd73c9162e Add a testcase for r108639.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 08:57:19 +00:00
Jim Grosbach
5423856e44 Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 03:30:54 +00:00
Jim Grosbach
469bbdb597 Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 23:05:05 +00:00
Bill Wendling
dc86704114 Consider this function:
void foo() { __builtin_unreachable(); }

It will output the following on Darwin X86:

_func1:
Leh_func_begin0:
        pushq %rbp
Ltmp0:
        movq %rsp, %rbp
Ltmp1:
Leh_func_end0:

This prolog adds a new Call Frame Information (CFI) row to the FDE with an
address that is not within the address range of the code it describes -- part is
equal to the end of the function -- and therefore results in an invalid EH
frame. If we emit a nop in this situation, then the CFI row is now within the
address range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108568 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:51:10 +00:00
Jakob Stoklund Olesen
468a2a44e2 Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 17:41:44 +00:00
Benjamin Kramer
3df1d5c408 Feed the right output into FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 10:58:02 +00:00
Jakob Stoklund Olesen
04c528a0c8 Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
TII::isMoveInstr is going tobe completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 04:45:42 +00:00
Jakob Stoklund Olesen
18c479c600 Add forgotten test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 04:45:35 +00:00
Dan Gohman
e667e01723 Use the source-order scheduler instead of the "fast" scheduler at -O0,
because it's more likely to keep debug line information in its original
order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 02:01:19 +00:00
Dale Johannesen
bdc09d9b09 The SelectionDAGBuilder's handling of debug info, on rare
occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place.  7797940 (6/29/2010..7/15/2010).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 00:02:08 +00:00
Bill Wendling
a60f0e7f81 Revert. This isn't the correct way to go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 23:42:21 +00:00
Bill Wendling
e9bf7e692e Handle code gen for the unreachable instruction if it's the only instruction in
the function. We'll just turn it into a "trap" instruction instead.

The problem with not handling this is that it might generate a prologue without
the equivalent epilogue to go with it:

$ cat t.ll
define void @foo() {
entry:
  unreachable
}
$ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables
        .section        __TEXT,__text,regular,pure_instructions
        .globl  _foo
        .align  4, 0x90
_foo:                                   ## @foo
Leh_func_begin0:
## BB#0:                                ## %entry
        pushq   %rbp
Ltmp0:
        movq    %rsp, %rbp
Ltmp1:
Leh_func_end0:
...

The unwind tables then have bad data in them causing all sorts of problems.

Fixes <rdar://problem/8096481>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 23:32:40 +00:00
Evan Cheng
60108e96bb Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 22:07:12 +00:00
Chris Lattner
6a624a65f4 fix the definitions of ConstTextCoalSection/ConstDataCoalSection
to keep "Text" in sync with the "pure instructions" section attribute.
Lack of this attribute was preventing the assembler from emitting
multibyte noops instructions for templates (and inlines, and other
coalesced stuff) and was causing the assembler to mismatch .o files.

This fixes rdar://8018335



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 21:22:00 +00:00
Devang Patel
07538ad975 Fix crash reported in PR7653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108441 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 18:45:27 +00:00
Dan Gohman
c88c1a4581 Watch out for a constant offset cancelling out a base register, forming
a zero. This situation arrises in Fortran code with induction variables
that start at 1 instead of 0. This fixes PR7651.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 15:14:45 +00:00
Devang Patel
c7c601ea5a Make it a .ll test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 23:12:52 +00:00
Jim Grosbach
502e0aa628 Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 17:45:16 +00:00
Dan Gohman
2dd50e656f Delete fast-isel's trivial load optimization; it breaks debugging because
it can look past points where a debugger might modify user variables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 17:25:37 +00:00
Bob Wilson
7a52e65ca6 Fix test to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 16:43:47 +00:00
Evan Cheng
dedd974e7e Fix for PR7193 was overly conservative. The only case where sibcall callee
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:44:01 +00:00
Bob Wilson
7e3f0d2690 Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:31:50 +00:00
Evan Cheng
44a44ad3bc Re-enable the test with fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 05:49:23 +00:00
Chris Lattner
f4e594740f temporarily disable to test to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 02:21:59 +00:00
Evan Cheng
db89809037 Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:22:19 +00:00
Bob Wilson
9e82bf12a0 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:22:12 +00:00
Bob Wilson
cba270d042 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
NEON VMOV-immediate instructions.  This simplifies some things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:16:48 +00:00
Dale Johannesen
b5611a6230 In inline asm treat indirect 'X' constraint as 'm'.
This may not be right in all cases, but it's better
than asserting which it was doing before.  PR 7528.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 20:17:05 +00:00
Evan Cheng
218977b53e Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 19:27:42 +00:00
Evan Cheng
ea4cdb7ead -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 18:46:14 +00:00
Dale Johannesen
24bb7bdb1e Fix PR number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 18:14:47 +00:00
Dan Gohman
cfbf0ed8b0 Apply the SSE dependence idiom for SSE unary operations to
SD instructions too, in addition to SS instructions. And
add a comment about it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:46:04 +00:00
Jakob Stoklund Olesen
744b3a5acd Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 17:01:17 +00:00
Rafael Espindola
cbeeae23c3 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 04:01:49 +00:00
Dan Gohman
e695de0c5f Fix this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:42:12 +00:00
Jakob Stoklund Olesen
5d6f892197 FileCheckize inline asm FP stack tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108046 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 16:30:25 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 09:00:22 +00:00
Jakob Stoklund Olesen
9c50e8b890 Fix a few tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:09 +00:00
Jim Grosbach
6c7d3a16b3 In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:27:06 +00:00
Dan Gohman
f870e566ee Add a target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108003 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 19:17:36 +00:00
Dan Gohman
aa7426070d Fix MachineLICM to actually visit inner loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:49:45 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:37:18 +00:00
Jakob Stoklund Olesen
cfcb2f6898 Fix test to be less sensitive of regalloc accidents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:32:11 +00:00
Bob Wilson
a0148c360e Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:47:20 +00:00
Dan Gohman
bf87e24917 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:39:23 +00:00
Bob Wilson
f1d93ca920 Reenable DAG combining for vector shuffles. It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
Bill Wendling
c930cbcada Extension of r107506. Make sure that we don't mark a function as having a call
if the inline ASM doesn't need a stack frame.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:38:02 +00:00