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1372 Commits

Author SHA1 Message Date
Thomas Harte
e1f4187430 Introduce failing ASL test. 2022-04-20 20:22:56 -04:00
Thomas Harte
3af93ada6f Test and correct Bcc, BSR, CLR, NEGX, NEG. 2022-04-20 20:19:56 -04:00
Thomas Harte
fa4dee8cfd Import two-operand DBccs. 2022-04-20 20:07:20 -04:00
Thomas Harte
3888492f0d Import corrected DBccs and JSRs. 2022-04-20 19:57:54 -04:00
Thomas Harte
dc16928f74 Add appropriate exclusions for JSR, JMP, Scc. 2022-04-20 16:56:26 -04:00
Thomas Harte
a4e440527b Import corrected CMPA references. 2022-04-20 16:46:05 -04:00
Thomas Harte
80ff146620 Add CMP, CMPA and TST tests and exclusions. 2022-04-20 16:29:45 -04:00
Thomas Harte
85a0af03c1 Import more standard JSON; start validating. 2022-04-20 09:17:00 -04:00
Thomas Harte
e0d2baae58 Test ANDI/ORI/EORI SR/CCR, and fail BTST/BCLR/BCHG/BSET. 2022-04-20 08:39:43 -04:00
Thomas Harte
437de19ecb Correct MOVE USP entries. 2022-04-20 08:34:10 -04:00
Thomas Harte
fab064641f Add Move[to/from][SR/CCR/USP] tests, correct decodings. 2022-04-20 07:59:13 -04:00
Thomas Harte
cc69d01bdc Strip dead code. 2022-04-19 20:41:39 -04:00
Thomas Harte
461a95d7ff Introduce missing register numbers for PEA, and elsewhere. 2022-04-19 20:39:01 -04:00
Thomas Harte
aa1665acce Fix LEA transcription problems. 2022-04-19 20:24:03 -04:00
Thomas Harte
6aabc5e7b0 Test LEA, PEA, add name for MOVEq. 2022-04-19 19:45:51 -04:00
Thomas Harte
2707887a65 Indicate MOVEAs. 2022-04-19 17:17:19 -04:00
Thomas Harte
ef87d09cfa Clear up MOVEs, fail on MOVEAs. 2022-04-19 17:13:23 -04:00
Thomas Harte
de0432b317 Include register numbers in MOVEs. 2022-04-19 16:34:22 -04:00
Thomas Harte
de40fed248 Test MOVEs and add operand validation. 2022-04-19 16:31:03 -04:00
Thomas Harte
76d7e0e1f8 Test and correct SUBs. 2022-04-19 16:27:20 -04:00
Thomas Harte
bfa551ec08 Correct ADDX and SUBX listings. 2022-04-19 16:21:40 -04:00
Thomas Harte
740e564bc7 Improve validation, add all ADDs. 
It now looks like probably the ADDXs in the JSON are incorrect.
 2022-04-19 14:45:15 -04:00
Thomas Harte
5de8fb0d08 Disallow four illegal NBCD addressing modes. 2022-04-19 09:59:02 -04:00
Thomas Harte
9b61830a55 Add ADD.b as a note to self that .q decoding is also required. 2022-04-19 08:44:44 -04:00
Thomas Harte
f29fec33a2 Eliminate mismatches due to unsupported addressing modes. 2022-04-19 08:37:53 -04:00
Thomas Harte
5509f20025 Fix MOVEfrom/toSR and NBCD listings. 2022-04-19 08:07:34 -04:00
Thomas Harte
fc4fd41be4 Reorder from most specific to least. 2022-04-19 08:00:52 -04:00
Thomas Harte
3ffca20001 Uncover various discrepancies with NBCD. 2022-04-19 07:15:54 -04:00
Thomas Harte
7c29305788 Test all ABCDs. 2022-04-18 20:00:39 -04:00
Thomas Harte
0fbfb41fa8 Expand on none-matching text. 2022-04-18 07:42:14 -04:00
Thomas Harte
1991ed0804 Introduce failing [partial-]test of new 68000 decoder. 2022-04-18 07:23:25 -04:00
Thomas Harte
e782b92a80 Add exposition. 2022-04-17 19:56:39 -04:00
Thomas Harte
07635ea2be Add register names, Q values. 2022-04-17 19:46:21 -04:00
Thomas Harte
1916bd3bd0 Import a first effort at listing all 68000 instruction specs. 2022-04-17 07:57:59 -04:00
Thomas Harte
21328d9e37 Normalise macros, remove unused AssertEqualOperationNameO. 2022-04-09 21:25:00 -04:00
Thomas Harte
5177fe1db7 Update tests. 2022-04-09 21:11:58 -04:00
Thomas Harte
1f44ad1723 Completes test cases. 2022-04-06 21:09:58 -04:00
Thomas Harte
d23c714ec7 Build in an optional post hoc validation. 
TODO: validate.
 2022-04-05 11:23:54 -04:00
Thomas Harte
ac524532e7 Handle the synonym test cases. 2022-04-04 08:09:59 -04:00
Thomas Harte
31276de5c3 Complete 'misc instructions' tests. 2022-04-03 20:33:32 -04:00
Thomas Harte
c581aef11d Test as far as mffs. 2022-04-03 18:29:40 -04:00
Thomas Harte
7f6a955a71 Complete the cmp set. 2022-04-03 15:50:03 -04:00
Thomas Harte
125d97cc41 Complete floating point tests. 2022-04-03 08:55:28 -04:00
Thomas Harte
de7d9ba471 Add further floating point tests. 2022-04-03 08:06:59 -04:00
Thomas Harte
ad54b44235 Begin documentation and testing of the floating point instructions. 2022-04-02 19:58:21 -04:00
Thomas Harte
42532ec0f5 Test floating point loads and stores. 2022-04-02 15:40:17 -04:00
Thomas Harte
b84fa619da Test integer loads and stores. 2022-04-02 15:27:12 -04:00
Thomas Harte
20b4736a1f Test tw, twi. 2022-04-02 10:09:35 -04:00
Thomas Harte
d5967f7834 Correct decoding of stwcx. and stdcx. 2022-04-01 20:37:36 -04:00
Thomas Harte
d5f7650ac1 Test synchronising loads and stores, further expand documentation. 2022-04-01 18:30:48 -04:00
Thomas Harte
6330caffde Test logical immediates. 2022-04-01 17:52:38 -04:00
Thomas Harte
4671b8db5c Add tests for non-immediate logicals. 2022-04-01 17:35:47 -04:00
Thomas Harte
7c8f044380 Complete shift tests. 2022-04-01 17:22:32 -04:00
Thomas Harte
a3b110aee5 Clean up. Shifts next. 2022-03-30 17:04:41 -04:00
Thomas Harte
84f0b0a84c Test rotates. 2022-03-30 16:43:09 -04:00
Thomas Harte
c9c5adc650 Test crand ... crxor. 2022-03-30 12:40:57 -04:00
Thomas Harte
b89c8decd4 Test addx–divwx and mtcrf; document fields for crand, etc. 2022-03-29 20:48:43 -04:00
Thomas Harte
e696624da0 Now passes negx, subfex, subfzex, subfmex, dozx, absx, nabsx. 2022-03-28 20:47:32 -04:00
Thomas Harte
99ad40f3e0 Test subfcx, subfx; correct decoding of oe(). 2022-03-28 20:39:52 -04:00
Thomas Harte
8ad1f2d4f5 Add bad attempt to catch subfc. 2022-03-28 20:18:41 -04:00
Thomas Harte
d84c72afe5 Test loads and stores, and immediate arithmetic. 2022-03-27 08:47:01 -04:00
Thomas Harte
4f6a9917c6 Test lbzx, lbzux. 2022-03-26 08:45:07 -04:00
Thomas Harte
3d48183753 Test lwzux. 2022-03-25 20:31:47 -04:00
Thomas Harte
33c31eb798 Test lwzx. 2022-03-25 20:23:21 -04:00
Thomas Harte
73ae7ad82f Resolve final branch test: aa() applies. 2022-03-25 20:10:08 -04:00
Thomas Harte
1a5d3bb69c Match majority of branch tests. 2022-03-25 08:41:57 -04:00
Thomas Harte
7d4fe55d63 Handle bclrx set and clear. 2022-03-25 06:25:06 -04:00
Thomas Harte
089e03afe8 Navigates bcctrx tests, adding simplified bo() helpers and bi() helpers. 2022-03-24 20:44:03 -04:00
Thomas Harte
e5af5b57ad Add documentation for bx, bcx, bcctrx. 
Catch bcx tests.
 2022-03-18 19:55:26 -04:00
Thomas Harte
f05d3e6af3 Introduce dingusdev tests, do just enough to check bx. 2022-03-18 17:24:12 -04:00
Thomas Harte
dc1d1f132e Add one more address size modifier test. 2022-03-11 13:01:02 -05:00
Thomas Harte
9b4048ec6e The address size modifier doesn't seem to affect far address sizes. 
It's meant to affect only instructions with operands that reside in memory, I think. So probably only ::DirectAddress in my nomenclature. More research to do.
 2022-03-11 12:46:07 -05:00
Thomas Harte
727342134c Add 8086 length limit test. 2022-03-11 11:55:41 -05:00
Thomas Harte
40cafb95ed Add 286 and 386 instruction length tests. 2022-03-11 09:48:51 -05:00
Thomas Harte
a2ae3771eb Add test for switch to Source::IndirectNoBase. 2022-03-10 15:45:56 -05:00
Thomas Harte
673ffc50da Switch to intended compact version of Instruction. 2022-03-10 15:14:50 -05:00
Thomas Harte
c1cc4f96df Switch to const auto. 2022-03-09 16:56:32 -05:00
Thomas Harte
bbf925a27e Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute]. 2022-03-09 16:48:06 -05:00
Thomas Harte
9f2d18b7ba Improve comment formatting. 2022-03-09 15:25:46 -05:00
Thomas Harte
acd9df6745 Fix segment/offset sizes for far calls. 2022-03-09 15:23:43 -05:00
Thomas Harte
f96c051932 Record PUSH immediate operation size. 2022-03-09 14:24:57 -05:00
Thomas Harte
67b2e40fae Fixed: INs and OUTs remain single byte. 2022-03-09 10:51:16 -05:00
Thomas Harte
081a2acd61 Fix shift group operand size. 2022-03-09 09:33:25 -05:00
Thomas Harte
de79acc790 Fix RegAddr/AddrRegs and group 2 decoding. 2022-03-09 08:38:34 -05:00
Thomas Harte
a125bc7242 Fill in more of test32bitSequence. 2022-03-08 20:16:19 -05:00
Thomas Harte
ebed4cd728 Introduce failing 32-bit parsing test. 2022-03-08 19:57:10 -05:00
Thomas Harte
926a373591 Extend SIB test, correct decoder. 2022-03-08 15:03:37 -05:00
Thomas Harte
0cbb481fa4 Add a formal SIB test. 2022-03-08 14:56:27 -05:00
Thomas Harte
a954f23642 Attempt 32-bit modregrm + SIB parsing. 2022-03-08 14:39:49 -05:00
Thomas Harte
e7aaf4dd2e Add LDS, LES, LSS test. 2022-03-06 12:10:25 -05:00
Thomas Harte
8a0902a83b Adapts existing opcodes for 32-bit parsing. 2022-03-05 13:52:07 -05:00
Thomas Harte
8080d1d961 Extend test case slightly. 2022-03-01 20:22:43 -05:00
Thomas Harte
8ee62b4789 Simplify address size semantics. 
Since it'll no longer be a mode-dependant toggle, but a fully-retained value.
 2022-03-01 17:29:26 -05:00
Thomas Harte
5e7a142ff1 Fix is_write errors, update comment, add additional source for asserts. 2022-03-01 16:51:54 -05:00
Thomas Harte
d8601ef01f Add missing hex specifier. Test now passes. 2022-02-28 09:54:29 -05:00
Thomas Harte
afbc57cc0c Incorporate displacement, switch macro flag. 2022-02-28 09:53:23 -05:00
Thomas Harte
9f12c009d6 Correct data size when accessing address registers. 2022-02-27 19:45:03 -05:00
Thomas Harte
84ac68a58b Fix indirect memory read/write 2022-02-27 18:43:00 -05:00
Thomas Harte
27d1df4699 Introduce enough of a DataPointerResolver test to build but fail. 2022-02-27 18:27:58 -05:00
Thomas Harte
0d7a7dc7c9 Introduce DataPointerResolver, to codify the meaning of DataPointer and validate that enough information is present. 2022-02-27 11:25:02 -05:00
Thomas Harte
60bf1ef7ea Rename SourceSIB to DataPointer, extend to allow for an absent base. 2022-02-23 08:28:20 -05:00
Thomas Harte
dc37b692cf Switch to templated test function. 2022-02-23 04:33:28 -05:00
Thomas Harte
76814588b8 Template Instruction on its content size. 2022-02-21 12:36:03 -05:00
Thomas Harte
1934c7faa2 Switch Decoder into a template. 2022-02-21 12:21:57 -05:00
Thomas Harte
9e9e160c43 Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase. 2022-02-21 11:45:46 -05:00
Thomas Harte
a5113998e2 Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX. 2022-02-20 17:15:01 -05:00
Thomas Harte
c257b91552 Update tests to preference away from [A/B/C/D]L. 2022-02-18 16:32:28 -05:00
Thomas Harte
1c3935eb40
Add README.md 
As a warning.
 2021-12-07 18:19:51 -05:00
Thomas Harte
610c85a354 Correct test logic. 
All tests now pass.
 2021-11-25 04:11:20 -05:00
Thomas Harte
012084b37b Fix exclusive fill, sizing, eliminate ECS call-ins. 
The clock test now proceeds further, but still doesn't seem to pass.
 2021-11-24 17:25:32 -05:00
Thomas Harte
8ef9a932aa Adds inclusive fill test; fixes inclusive fills. 2021-11-07 14:26:13 -08:00
Thomas Harte
2c1f2edcf2 Introduce failing 'clock' test case. 
i.e. a few seconds of the Workbench 1.0 clock application.
 2021-10-31 16:12:51 -07:00
Thomas Harte
9e6ffaad7d Introduce test case for fill mode. 2021-10-31 14:12:26 -07:00
Thomas Harte
edb75e69cb Implement bitplane modulos. 2021-10-29 11:29:22 -07:00
Thomas Harte
5ebc59dd1f Introduce additional test cases. 2021-10-26 20:58:38 -07:00
Thomas Harte
4d7ce3792f Use additional test cases. 2021-10-25 21:48:43 -07:00
Thomas Harte
dc8701a929 Introduce some additional Blitter test cases. 2021-10-25 21:40:20 -07:00
Thomas Harte
15ed4a0d09 Introduce failing test case for sector decoding. 2021-10-16 10:48:32 -07:00
Thomas Harte
aa6b0f07b7 Correct filename. 2021-10-16 05:37:46 -07:00
Thomas Harte
6b0dd19442 Name file appropriately: the logo comes from Kickstart. 2021-10-09 08:02:15 -07:00
Thomas Harte
da286d5ae8 Switch spaces to tabs. 2021-10-04 05:27:25 -07:00
Thomas Harte
ad90c6b6ce Now that this is getting close, don't stop at the first error. 2021-09-29 22:19:34 -04:00
Thomas Harte
0c998d60cb Correct test logic for line draws that repeatedly write to the same address. 2021-09-28 21:45:55 -04:00
Thomas Harte
1dfc36f311 Flip loop, add modulo mappings. 2021-09-26 18:15:32 -04:00
Thomas Harte
1c03ff1d37 Fix bltdptl to bltbptl misstatement; remove pre-DMA writes. 2021-09-26 18:14:50 -04:00
Thomas Harte
19dd2f92bd Implements test case. Failing at present, naturally. 2021-09-25 21:52:41 -04:00
Thomas Harte
acfaa016a0 Adds a capture of traffic leading up to the Workbench boot logo. 
Around which to construct a test case.
 2021-09-25 18:10:07 -04:00
Thomas Harte
fa800bb809 Introduces code for minterm application. 2021-09-20 19:13:23 -04:00
Thomas Harte
e402e690b0 Assume and test that divide-by-zero posts the PC of the offending instruction. 2021-08-07 17:51:00 -04:00
Thomas Harte
b4ec9d70da Adds the CNT input. 2021-08-03 22:19:41 -04:00
Thomas Harte
738999a8b7 Further expands list of applied tests. 2021-08-03 22:08:50 -04:00
Thomas Harte
34c1cc5693 Adds entry points for all remaining tests. 
Failing now: the TB123s, which are TOD related, both CIA2 tests, and CIA1TAB (which I think needs me to implement Port B output toggling).
 2021-08-03 17:19:35 -04:00
Thomas Harte
f0ef45f0ca Introduces two further tests. 2021-08-03 16:58:51 -04:00
Thomas Harte
f576baf214 I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests. 2021-07-30 21:21:16 -04:00
Thomas Harte
94907b51aa Remove redundant parameter. 2021-07-06 20:47:49 -04:00
Thomas Harte
0085265d13 Test for a longer period; fix expected tone 1 count. 2021-07-06 20:46:22 -04:00
Thomas Harte
8e0893bd42 Clarifies control flow. 2021-07-06 20:28:32 -04:00
Thomas Harte
704dc9bdcb Improves test, to assert that state toggles happen at interrupts. 2021-07-06 20:25:32 -04:00
Thomas Harte
3e6b804896 Switches to linked 1/50/1000 Hz timers, and per-interrupt state toggling. 2021-07-06 20:12:44 -04:00
Thomas Harte
f371221dba Add a quick test of tone generator 1. 2021-07-02 23:57:11 -04:00
Thomas Harte
27b0579ec6 Avoid stack-error test case. 
Also test that the interrupt is generated on the downward stroke.
 2021-07-02 23:55:43 -04:00
Thomas Harte
283092cfbc With a unit test in aid, corrects some lingering TimedInterruptSource issues. 2021-07-02 23:41:19 -04:00
Thomas Harte
fbf1adef05 Introduces unit test and thereby seemingly fixes get_next_sequence_point. 
There's still improper output in the actual machine though, so maybe something else is afoot?
 2021-06-18 17:44:17 -04:00
Thomas Harte
f27e331462 Updates autotests to new RomFetcher world. 2021-06-06 20:34:55 -04:00
Thomas Harte
37dcf61130 Add timing tests, fix +3 discrepancy. 2021-04-23 22:29:57 -04:00
Thomas Harte
a1511f9600 Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone. 2021-04-14 20:15:40 -04:00
Thomas Harte
68a04f4e6a Adds IN/OUT I/D [R] to complete tests. 2021-04-13 22:00:24 -04:00
Thomas Harte
0d61902b10 Adds CP[I/D/IR/DR] tests. 2021-04-13 20:03:11 -04:00
Thomas Harte
3eec210b30 Adds LDI/LDD/LDIR/LDDR tests. 2021-04-13 20:00:29 -04:00
Thomas Harte
2e70b5eb9f Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}. 2021-04-13 19:45:29 -04:00
Thomas Harte
8a3bfb8672 Adds an IN/OUT test. 2021-04-13 17:55:51 -04:00
Thomas Harte
06f1e64177 Advances to IO. 2021-04-12 21:41:20 -04:00
Thomas Harte
b42780173a Establishes that there really is no Read4 and Read4Pre distinction. 
Will finish these unit tests, then clean up.
 2021-04-12 20:54:10 -04:00
Thomas Harte
36c8821c4c Reaches the halfway point in tests. 2021-04-12 17:29:03 -04:00
Thomas Harte
9347fe5f44 Advances to next failing test: LD (ii+n), n. 2021-04-12 17:11:58 -04:00
Thomas Harte
e82367def3 Switches to test-conformant behaviour for (IX/IY+n) opcode fetches. 2021-04-11 23:01:00 -04:00
Thomas Harte
47c5a243aa Restructures, the better to explore errors. 2021-04-10 21:32:42 -04:00
Thomas Harte
070e359d82 Introduces failing test for BIT b, (ii+n). 2021-04-10 18:00:23 -04:00
Thomas Harte
400f54e508 Introduces failing test for bit b, (hl). 2021-04-10 12:04:48 -04:00
Thomas Harte
e0736435f8 Makes assumption that the address bus just holds its value during an internal operation. 2021-04-10 12:00:53 -04:00
Thomas Harte
b09c5538c6 Adds failing test for simple (ii+n) tests. 2021-04-09 21:28:35 -04:00
Thomas Harte
ce3d2913bf Advances to 9 source table rows tested out of 37. 2021-04-09 20:38:17 -04:00
Thomas Harte
87202a2a27 Add two further tests, add checking of collected data size for all tests. 2021-04-09 18:32:03 -04:00
Thomas Harte
818a4dff25 Corrects ADD HL, dd test. 
Or, at least, likely corrects. The bus cycle breakdown in the Z80 data sheet implies these accesses should come after completion of the refresh cycle, not during its long tail, so I think +1 is correct.
 2021-04-08 22:23:15 -04:00
Thomas Harte
9e506c3206 Adds failing ADD hl, dd test. 2021-04-08 22:19:22 -04:00
Thomas Harte
50f53f7d97 Adds INC/DEC rr and LD SP, HL tests. 2021-04-08 22:14:53 -04:00
Thomas Harte
73fbd89c85 Correct opcodes, ability to terminate on a single-cycle contention. 2021-04-08 22:09:33 -04:00
Thomas Harte
f74fa06f2d Introduces failing test for LD [A/I/R], [A/I/R]. 2021-04-08 20:28:55 -04:00
Thomas Harte
ee989ab762 Fills in the rest of the simple two-byte instructions. 2021-04-08 20:13:52 -04:00
Thomas Harte
818655a9b6 Starts on two-bus-cycle instructions, correcting validators. 2021-04-08 20:01:46 -04:00
Thomas Harte
57a7e0834f Corrects sampling of MREQ. 2021-04-08 19:21:35 -04:00
Thomas Harte
cd787486d2 Tests all of the single-byte, no-access opcodes. 2021-04-07 22:07:52 -04:00
Thomas Harte
67fd6787a6 Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH. 2021-04-07 21:57:40 -04:00
Thomas Harte
094d623485 Updates unit tests. 2021-04-05 21:33:04 -04:00
C.W. Betts
5758693b7d Minor pokes to the test files code. 2021-03-19 02:19:49 -06:00
Thomas Harte
e5076b295b Corrects namespace. 2021-01-21 18:58:11 -05:00
Thomas Harte
3c20e1f037 Adds files for the M50740 and corrects namespace errors elsewhere. 2021-01-15 21:30:30 -05:00
Thomas Harte
15bedc74d4 Merge branch 'master' into AppleIIgs 2021-01-15 21:15:10 -05:00
Thomas Harte
ddb4bb1421 Better plans project layout. 2021-01-15 18:16:01 -05:00
Thomas Harte
ca94e9038e Introduces 'far' test, fixes parsing. 2021-01-14 22:15:38 -05:00
Thomas Harte
2c72a77a25 Adds byte-by-byte decoder test; corrects divergences. 2021-01-13 21:51:18 -05:00
Thomas Harte
8c0e06e645 Adds a test for 0x83 and fixes sign extension. 
ODA doesn't seem to accept 0x82, but testing 0x83 adds some confidence.
 2021-01-13 20:42:21 -05:00
Thomas Harte
5058a8b96a Completes the first test stream. 
... and improves decoding consistency in conjunction.
 2021-01-12 21:49:22 -05:00
Thomas Harte
762ecab3aa Adds operand/displacement capture. 
This gets unit test as far as a disagreement over how to handle bad 0xc4 suffixes.
 2021-01-10 22:55:25 -05:00
Thomas Harte
9ba5b7c1d4 Adds a few more asserts. 
It's still just operands and displacements failing, which is nice.
 2021-01-08 23:21:01 -05:00
Thomas Harte
5f807b6e47 Ensures that the operand is the only thing failing in decoding of the first instruction. 2021-01-08 23:02:06 -05:00
Thomas Harte
86577b772b Rethinks size; packs all captured information into an x86 Instruction. 
Albeit that operand and displacement are't yet captured. Or extractable.
 2021-01-08 22:22:07 -05:00
Thomas Harte
3b55d3f158 Nudges up to a need to decode operation from the ModRegRM byte. 2021-01-05 21:25:12 -05:00
Thomas Harte
a8738b533a Switch for now to block-level decoding. 
It's easier to step debug.
 2021-01-03 20:07:46 -05:00
Thomas Harte
11b6c1d4b5 Proceeds to three instructions correctly decoded. 'Wow'. 2021-01-03 17:03:50 -05:00
Thomas Harte
367cb1789d Starts building an x86 test. 2021-01-03 16:37:35 -05:00
Thomas Harte
adf1484ecc Introduces third test sequence, uneventfully. 2021-01-03 16:21:23 -05:00
Thomas Harte
eb8d0eefd5 Factors out some boilerplate and introduces second sequence. 2021-01-03 11:14:30 -05:00
Thomas Harte
c934e22cee Introduces a first test of PowerPC decoding. 
Corrected as a result: the bcx conditional, that stdu is 64-bit only, extraction of the li field.
 2021-01-02 22:47:42 -05:00
Thomas Harte
3b2e97e77c Introduces basic auxiliary switch tests. 
All of which pass. Grrr.
 2020-12-11 21:30:03 -05:00
Thomas Harte
c978a95463 Increases asserts and adds a test. 
Thereby discovers and fixes a problem with set_main_paging().
 2020-12-10 21:49:23 -05:00
Thomas Harte
d35def4bbc Ensures a consistent initial state. 2020-12-06 22:01:59 -05:00
Thomas Harte
d5f209366a Extends testing to disabling IO space. 2020-12-06 21:53:53 -05:00
Thomas Harte
9062e80e9d Adds anti-IO protection. 2020-12-06 21:46:04 -05:00
Thomas Harte
fd3760cedc Adds passing test of basic $00 -> $01 -> $e1 shadowing. 2020-12-06 21:19:38 -05:00
Thomas Harte
9b73331ee9 Resolves deprecated use of scanHexInt32. 2020-12-06 20:49:12 -05:00
Thomas Harte
b0efc647f1 An OpenGL context is neither still necessary nor desirable. 2020-11-26 13:49:41 -05:00
Thomas Harte
4f9d06d8c7
Merge pull request #846 from MaddTheSane/maddsIIgs 
Use url(forResource:... instead of path(forResource:…
 2020-11-06 09:39:27 -05:00
C.W. Betts
189a468ad4 Use url(forResource:... instead of path(forResource:… as it cuts down on creating a URL struct. 2020-11-05 14:42:39 -07:00
C.W. Betts
a3414c2673
Update 65816kromTests.swift 
Only have one runTest method.
 2020-11-05 14:36:34 -07:00
Thomas Harte
5126163c5d Attempts to reduce pull request heft. 
Given that the licensing of krom's tests is uncertain, and I've given credit and an appropriate link, I needn't include the original code.
 2020-11-04 21:49:45 -05:00
Thomas Harte
e3147b6b45 Introduces a pre-STP/WAI limit for the MSC test. 
This way I retain testing of NOP, BRK, COP and WDM.
 2020-11-03 20:59:07 -05:00
Thomas Harte
cc5ec78156 Provides something on WAI/STP; sizes STY by the x flag; disables MSC test. 2020-11-03 20:17:44 -05:00
Thomas Harte
5cbb91f352 Fixes COP vector, ensures WDM skips a byte. 2020-11-03 20:01:02 -05:00
Thomas Harte
bf85d71674 Brings ADC into conformance. Fixes JML. 2020-11-03 18:12:10 -05:00
Thomas Harte
426e90eebf Adds logic to work around Nintendo dependence in the krom tests. 
Let the real work begin!
 2020-11-03 14:18:40 -05:00
Thomas Harte
3889646d6b Takes a swing at incorporating krom's 65816 test suite. At least as far as ADC. 2020-11-02 21:09:32 -05:00
Thomas Harte
bdda84dfde Adds a very basic shadowing test. 
For the record, I'm aware that there's a lot here that I'm not testing. I think the smart move is to get towards a running machine and see which configurations it actually tries to set up, then follow along with appropriate testing; it might cause me to discover a flaw in my comprehension before I've made the same mistake in both the code and a test.
 2020-10-27 19:59:41 -04:00
Thomas Harte
74f9f6ad3b Tests and corrects ROM access beyond bank $00. 2020-10-27 19:02:15 -04:00
Thomas Harte
f830f6a57a Adds failing test of initial ROM mirroring. 
It's the end of the evening, so this is it for today.
 2020-10-25 22:13:54 -04:00
Thomas Harte
82c733c68c Adds some very basic actual tests. 2020-10-25 21:40:50 -04:00
Thomas Harte
ed510409c4 Starts memory map test class, already finding a typo. 2020-10-25 21:31:21 -04:00
Thomas Harte
ab07814614 Eliminates now-broken 65816 flow test. 2020-10-19 21:02:46 -04:00
Thomas Harte
1653abdf88 Adds the .lst; otherwise I'll probably just lose it. 2020-10-19 20:58:24 -04:00
Thomas Harte
b3ab9fff9b Imports a custom-built copy of Klaus Dormann's 65C02 test, with only 65816-compatible parts. 
Thereby fixes another couple of 65816 issues — BRK(, etc) not clearing the decimal flag, and `TRB d` being mismapped.
 2020-10-19 19:27:16 -04:00
Thomas Harte
69509f6502 Attempts to bring a little more consistency to my use of Swift in test code. 2020-10-17 22:42:54 -04:00
Thomas Harte
c3187fdbe1 Makes minor formatting improvement. 2020-10-17 22:31:51 -04:00
Thomas Harte
42228ea955 Adds 65C02As6502 test, to round out the set. 2020-10-17 22:31:32 -04:00
Thomas Harte
3c6adc1ff4 Completes 65816 addressing mode tests and corresponding fixes. 2020-10-14 22:00:52 -04:00
Thomas Harte
e511d33a7c Adds test for [d], y; fixes implementation. 2020-10-14 21:42:41 -04:00
Thomas Harte
c35969d677 Adds tests for (d, x) and (d), y. Both amply tested in emulation mode, so no problems. 
Five to go, all potentially troublesome.
 2020-10-14 21:38:00 -04:00
Thomas Harte
27afb8f0a7 Adds direct indirect long test, and thereby fixes addressing mode. 
Nine to go!
 2020-10-14 21:26:20 -04:00
Thomas Harte
327ab81436 Fills in direct, x and (direct) tests, fixing implementation of the latter. 
10 to go.
 2020-10-14 21:17:28 -04:00
Thomas Harte
db7178495f Implements direct and final absolute test. 
14 to go.
 2020-10-14 20:57:47 -04:00
Thomas Harte
979186e71d Transcribes the English-language versions of the outstanding tests. 
Passing these will make me willing to call the 65816 functionality provisionally done, other than making sureI signal VPA, VDA, VPB, etc, correctly.
 2020-10-14 13:56:37 -04:00
Thomas Harte
f05e0d956b Adds a TODO list in order to keep an end in sight. 2020-10-13 21:43:42 -04:00
Thomas Harte
b22aa5d699 Starts transcribing the addressing examples I have into tests. 
Correspondingly extends the exposed register set and test-machine addressing range.
 2020-10-13 21:38:30 -04:00
Thomas Harte
3e6a2adaaf Corrects absolute, x and absolute, y addressing modes. 2020-10-13 20:30:39 -04:00
Thomas Harte
6a47571d17 Stops truncating tests by two bytes. 
Not that it seems to have been problematic.
 2020-10-12 21:53:27 -04:00
Thomas Harte
28da1a724a Introduces Jeek816 test case. 2020-10-12 21:43:44 -04:00
Thomas Harte
5dc3cd3a2f Starts using Jeek816 for a basic native-mode audit. Fixes absolute long addressing. 2020-10-11 22:02:46 -04:00
Thomas Harte
486324ecab This test isn't actually 65816-compatible. 2020-10-10 18:19:48 -04:00
Thomas Harte
340ad093a6 Adds 65816 runs of the final tranche of applicable tests. 2020-10-10 17:26:41 -04:00
Thomas Harte
0fe09cd1e4 Knocks SBC into producing likely results; disables Lorenz testing. 2020-10-10 17:13:16 -04:00
Thomas Harte
09fba72d58 Adds flag manipulation, ADC and SBC 65816 tests. 
The latter two fail.
 2020-10-10 11:30:15 -04:00
Thomas Harte
7966592fae Corrects ROL d. 2020-10-10 11:22:23 -04:00
Thomas Harte
6efe4e1753 Fixes AND, EOR, ORA. Takes an unsuccessful shot at ROL. 2020-10-10 10:53:17 -04:00
Thomas Harte
536c4d45c1 Adds additional 65816 tests, some failing; seeks to improve carry behaviour in ASL and ROL. 2020-10-10 10:11:57 -04:00
Thomas Harte
a02f88fe7c Confirms a couple more of the easy sets. 2020-10-10 09:34:29 -04:00
Thomas Harte
d9be6ab806 Confirms that a few other simple tests work immediately on the 65816. 2020-10-09 23:26:35 -04:00
Thomas Harte
290598429a Applies indirect page zero emulation mode addressing constraint to ix addressing. 
Lorenz's LDA tests now pass in emulation mode.
 2020-10-09 23:22:48 -04:00
Thomas Harte
776f014dbe Attempts LDA tests against the 65816. 
Result: ix is faulty. Which we already knew.
 2020-10-09 22:23:54 -04:00
Thomas Harte
88293909f4 Enables running of a first test on the 65816. 2020-10-09 21:44:47 -04:00
Thomas Harte
9b6c48631d Removes usage of a JAM instruction to spot end-of-tests. 2020-10-09 21:39:34 -04:00
Thomas Harte
0418f51ef2 Takes a shot at emulation-mode 'exceptions'. 
It's just RTI and correct decimal SBC left of the official 6502s now, I think.
 2020-10-08 17:52:13 -04:00
Thomas Harte
b578240993 Adds a further error. 
Clearly I've severely overloaded 'JMP' and not fully thought through where it gets its addresses from.
 2020-10-07 21:47:58 -04:00
Thomas Harte
1ba0a117e7 Corrects PLB, PLD, PLP. 2020-10-07 20:23:53 -04:00
Thomas Harte
f7b119ffe1 Moves temporary logging, fixes branch instructions. 2020-10-07 19:57:58 -04:00
Thomas Harte
a4cec95db1 Corrects load and transfer flag oversights. 2020-10-07 19:36:23 -04:00
Thomas Harte
84c4fa197b Corrects DEX mapping, notes new Dormann failure case. 2020-10-07 18:48:03 -04:00
Thomas Harte
a72ac8294c Adds 65816 alternates to Klaus Dormann's tests. 
While also correcting a couple of misspellings of his name. Apologies, Klaus!
 2020-09-29 18:49:58 -04:00
Thomas Harte
ef1a514785 Introduces 6502Selector, for picking either a 6502 or a 65816 based on a single template parameter. 2020-09-28 21:35:46 -04:00
Thomas Harte
b96cd4d18b Resolves another unsafe pointer assumption. 2020-09-27 22:20:13 -04:00
Thomas Harte
8641494809 Resolve various test-case warnings. 2020-09-27 15:10:29 -04:00
Thomas Harte
5449e90b34 Edges towards offering the 65816 as another type of 6502 for testing. 2020-09-26 22:31:50 -04:00
Thomas Harte
703065a0a5 Takes a run at timer-linked PB7 output behaviour. 
Seemingly sufficiently to pass the VICE test (which I've transcribed), though with some guesswork.
 2020-09-20 14:51:59 -04:00
Thomas Harte
291aa42fe1 Corrects test target. 2020-09-19 21:20:37 -04:00
Thomas Harte
eadda6a967 Further strips OpenGL from the macOS target. 2020-08-09 22:17:27 -04:00
Thomas Harte
267006782f Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
Thomas Harte
0505b82384 Restores top bit of channel period, propagates it to the envelope generator. 2020-05-05 00:28:24 -04:00
Thomas Harte
5896288edd Adapts to new interface. 2020-04-29 22:08:36 -04:00
Thomas Harte
f899af0eef Fixes OPL tests. 2020-04-28 20:17:16 -04:00
Thomas Harte
32fd1897d0 Via a unit test, confirms and fixes relative volumes of OPLL channels. 
Also rejigs responsibility for scaling to emulator-standard volume.
 2020-04-20 23:17:29 -04:00
Thomas Harte
39e6a28730 Rearranges file. 2020-04-20 19:41:04 -04:00
Thomas Harte
3852e119aa Adds test data for FM wave generation. 2020-04-20 19:33:03 -04:00
Thomas Harte
99fa86a67e Adds a test for lookup sine. And fixes lookup sine. 2020-04-20 18:40:47 -04:00
Thomas Harte
a7e63b61eb Just from printing numbers: corrects transition from attack to decay. 2020-04-15 00:26:01 -04:00
Thomas Harte
b13b0d9311 Starts towards implementing some OPL test cases. 2020-04-14 23:51:45 -04:00
Thomas Harte
3f64cdaff8 Improves documentation. 2020-02-27 22:33:34 -05:00
Thomas Harte
7ac0ea8529 Corrects test cases, as far as they go. 2020-02-27 22:33:18 -05:00
Thomas Harte
a3569d7201 Corrects so as not to test header. Both Zexall and Zexdoc pass. 2020-02-27 22:09:56 -05:00
Thomas Harte
01faffd5bf Corrects memptr behaviour of OTIR/OTDR and INIR/INDR. 
This seemingly perfects memptr.
 2020-02-27 20:55:43 -05:00
Thomas Harte
26de5be07c Corrects memptr behaviour of LDIR/LDDR and CPIR/CPDR. 2020-02-27 20:44:53 -05:00
Thomas Harte
87474d5916 Corrects memptr behaviour of OUT (C), 0. 2020-02-27 20:38:27 -05:00
Thomas Harte
a366077509 Updates failure count. 2020-02-26 22:26:23 -05:00
Thomas Harte
3b0df172a7 Corrects memptr behaviour of JP nn. 2020-02-26 22:02:15 -05:00
Thomas Harte
8878396339 Corrects DJNZ memptr behaviour. 2020-02-26 21:42:31 -05:00
Thomas Harte
da6d5e2e24 Adds memptr testing. 
30 failures, for the record.
 2020-02-26 20:05:14 -05:00
Thomas Harte
18bb90329a Apparently tStates is decimal. Of course it is. 2020-02-26 20:04:55 -05:00
Thomas Harte
604bb50adf Imports and converts updated FUSE tests. 
Now with added MEMPTR.
 2020-02-25 23:15:27 -05:00
Thomas Harte
e4887c0c56 Corrects JR cc tests. 2020-02-24 23:36:05 -05:00
Thomas Harte
3097c4ccae Improves MEMPTR testing and some results. 2020-02-24 23:32:18 -05:00
Thomas Harte
7959d243f6 Adds single-stepping. Of a kind. 2020-02-24 23:31:42 -05:00
Thomas Harte
79dd402bc8 Consolidates different test port input selection. 2020-02-23 16:12:28 -05:00
Thomas Harte
3f3229851b Implements MEMPTR for IN. 2020-02-23 00:32:33 -05:00
Thomas Harte
989628a024 Switches to looking for "Result: all tests passed." as a success/failure test. 2020-02-22 23:07:14 -05:00
Thomas Harte
e0475343f5 Makes collated text easier to read. 2020-02-22 18:58:24 -05:00
Thomas Harte
da0a9113d4 Introduces the full range of tests. 
Albeit that I don't know the correct output yet.
 2020-02-22 18:44:15 -05:00
Thomas Harte
cf7ab97451 Gets the first test to run (and terminate). 2020-02-22 18:42:23 -05:00
Thomas Harte
2370575eb5 Starts introducing the Patrik Rak tests. 2020-02-22 15:49:36 -05:00
Thomas Harte
825b68e5c4 Adds separate entry points for zexall and zexdoc. 2020-02-22 12:34:47 -05:00
Thomas Harte
851cba0b25 Corrects lambda capture. 2020-02-22 12:34:16 -05:00
Thomas Harte
9ca2d8f9f2 Tried to be less lazy with lambda captures. 
This is primarily defensive.
 2020-02-14 23:39:08 -05:00
Thomas Harte
085529ed72 Makes the shifter behaviour conform to its documentation. 2020-02-02 17:26:39 -05:00
Thomas Harte
8b1f183198 Reduce test duration much closer to two frames. 2020-01-28 23:25:01 -05:00
Thomas Harte
5c4623e9f7 Adds a sequence-point test for 72Hz mode. 
Which immediately appears to trigger the hsync issue I'm also seeing in manual testing.
 2020-01-28 20:27:24 -05:00
Thomas Harte
189122ab84 Fixes test units. 2020-01-27 20:35:58 -05:00
Thomas Harte
294e09f275 All these 'override's can be 'final's. 
At least for the purpose of being communicative. I doubt there's much to gain in terms of compiler output — the DiskImageHolder can avoid some virtual lookups but nothing else leaps out.
 2020-01-23 22:57:51 -05:00
Thomas Harte
f42655a0fc Promote DigitalPhaseLockedLoop to a template, simplify to O(1) add_pulse. 2020-01-12 17:25:21 -05:00
Thomas Harte
6595f8f527 Introduces a timing test for LSL. Which already passes. 2020-01-08 22:35:28 -05:00
Thomas Harte
c1bae49a92 Standardises on read and write for bus accesses. 
Logic being: name these things for the bus action they model, not the effect they have.
 2020-01-05 13:40:02 -05:00
Thomas Harte
9f2f547932 Adds and satisfies test on the function code word. 
Thanks to ijor's "68000 Address and Bus Error Stack Frame" re: contents.
 2020-01-04 23:58:07 -05:00
Thomas Harte
f0d5bbecf2 Introduces a test of stack contents after an address error. 
Fixes: stacked PC, address of fault.
 2020-01-04 23:22:07 -05:00
Thomas Harte
a28c52c250 Fixes A7-relative JSRs. 
I completely withdraw my earlier statement re: the test cases.
 2020-01-04 22:22:33 -05:00
Thomas Harte
937cba8978 After rerunning all tests, adds some notes on questionable results. 
Also renames a file. But no code changes are currently suggested, at least until I can learn more about DIVU/DIVS.
 2020-01-04 16:31:45 -05:00
Thomas Harte
ca12ba297b Renames all files that test multiple opcodes; introduces DIV and MUL tests. 2020-01-03 22:43:24 -05:00
Thomas Harte
617e0bada9 Adds some minor extra testing. Highly duplicative, to be honest. 2020-01-02 23:14:05 -05:00
Thomas Harte
cb7d6c185c Further expands test coverage. 2020-01-01 20:00:37 -05:00
Thomas Harte
5be30b1f7b Introduces further comparative tests, prompting a new CHK fix. 
Specifically: how to set N when both is_under and is_over are true, and to eliminate a failure fully to prefetch in the longer addressing modes.
 2020-01-01 19:11:36 -05:00
Thomas Harte
b33218c61e Fixes reload test, which really needs to sense the CRT-headed vsync output. 
i.e. not the one heading back to the CPU.
 2019-12-29 20:55:34 -05:00
Thomas Harte
5361ee2526 Adds specific Union Demo test. 2019-12-29 17:48:43 -05:00
Thomas Harte
214b6a254a Adds a delay on visibility of the hsync signal, and a test on address reload. 2019-12-29 17:37:09 -05:00
Thomas Harte
93f6964d8a Introduces some preliminary line length unit tests. 
Thereby fixes one potential issue with load_ toggling.
 2019-12-28 22:50:34 -05:00
Thomas Harte
d26ce65236 Introduces an RTR test. 2019-12-25 19:50:12 -05:00
Thomas Harte
ed831e5912 Fixes test syntax errors. 2019-12-23 22:13:25 -05:00
Thomas Harte
0dae608da5 Embraces std::make_[unique/shared] in place of .reset(new . 2019-12-23 21:31:46 -05:00
Thomas Harte
a847654ef2 Corrects various old-fashioned bits of indentation, plus the odd const. 2019-12-22 00:00:23 -05:00
Thomas Harte
9464658d1e Adds a count summary. 2019-12-17 22:19:23 -05:00
Thomas Harte
e969b386f1 Eliminates DIVU/S and MULU/S from this file. 2019-12-17 20:15:11 -05:00
Thomas Harte
0d23f141d6 Regenerates without accidentally hitting MODE to SR. 2019-12-16 22:37:57 -05:00
Thomas Harte
ba2436206f Withdraws test of CHK (exception taken). 2019-12-16 20:00:42 -05:00
Thomas Harte
60a9b260b1 Corrects collection of instruction codes. 2019-12-16 00:01:18 -05:00
Thomas Harte
e603fc6aaa Simplifies failure output for me. 2019-12-15 21:26:47 -05:00
Thomas Harte
81cc278b98 Introduces a barrage of further tests. 2019-12-15 21:26:35 -05:00
Thomas Harte
1bf4686c59 Adds plentiful additional tests. Though still only a fraction of the anticipated total. 2019-12-14 22:58:51 -05:00
Thomas Harte
a500fbcd73 Expands tests to most of ORI, EORI, ANDI, ADDI and SUBI. 2019-12-14 22:23:40 -05:00
Thomas Harte
d0ef41f11e Adds a temporary manual escape clause for testing specific features. 2019-12-14 21:40:21 -05:00
Thomas Harte
adf6723bf6 Ensures state is evaluated directly at opcode end. 2019-12-14 15:09:06 -05:00
Thomas Harte
37e26c0c37 Eliminates a class of incorrect sign comparison errors. 2019-12-14 14:50:39 -05:00
Thomas Harte
ac1575be27 Resolves false negatives from checking wrong state. 2019-12-14 14:46:00 -05:00
Thomas Harte
923287bf01 Attempts to introduce a basic means for comparative 68000 testing. 
i.e. mine versus another source.
 2019-12-14 14:26:33 -05:00
Thomas Harte
4536c6a224 Resolves printf type errors. 2019-12-08 11:56:05 -05:00
Thomas Harte
72cb3a1cf6 Integrates basic unit test for Atari ST video event prediction. 2019-11-19 21:54:13 -05:00
Thomas Harte
ade8df7217 Permits a delay on DE propagation back to the CPU. Plus tests. 
Currently set at 28 cycles, but I don't know.
 2019-11-18 22:12:24 -05:00
Thomas Harte
1c154131f9 Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. 2019-10-29 22:36:29 -04:00
Thomas Harte
1aba1db62c Corrects test. 2019-10-27 21:30:58 -04:00
Thomas Harte
f88dc23c71 Corrects comment. 2019-08-04 20:30:41 -04:00
Thomas Harte
e334abfe20 Partitions the 68000 arithmetic tests, to allow easier per-instruction execution. 2019-08-03 17:44:47 -04:00
Thomas Harte
f2ae04597f Updates test case. 2019-07-24 22:07:17 -04:00
Thomas Harte
0187fd8eae Hides all runtime Program member accesses behind macros. 
... and fixes unit tests.
 2019-07-24 12:01:30 -04:00
Thomas Harte
5a9f3cfc1e Completes Mac GCR decoding and its associated test. 2019-07-11 17:37:07 -04:00
Thomas Harte
8f28b33342 Starts work on Macintosh GCR decoding. 2019-07-11 16:28:52 -04:00
Thomas Harte
886946cc8c Rejigs time-until-event tracking. 2019-07-09 23:27:27 -04:00
Thomas Harte
210bcaa56d Introduces an initial shift unit test, and makes it pass. 2019-07-07 22:13:36 -04:00
Thomas Harte
a5f0761a43 Copies in notes for required test functions. 2019-07-07 14:13:00 -04:00
Thomas Harte
ebb6313eef Corrects missing file. 2019-07-01 18:18:46 -04:00
Thomas Harte
11d8f765b2 Corrects divide-by-zero exception length, enables all other DIVS checks. 2019-07-01 15:46:04 -04:00
Thomas Harte
514e57b3e9 Corrects DIVU timing and flags, improves DIVS. 2019-07-01 14:24:32 -04:00
Thomas Harte
d30e7504c2 Factors out MOVE tests, and ensures test machine RAM is zero initialised. 2019-06-30 21:43:30 -04:00
Thomas Harte
8d0cd356fd Corrects TRAP, TRAPV and CHK timing. 2019-06-29 21:25:22 -04:00
Thomas Harte
aff40bf00a Imports AND tests. 2019-06-29 20:16:10 -04:00
Thomas Harte
eedf7358b4 Imports first part of AND tests. 2019-06-29 16:29:47 -04:00
Thomas Harte
26aebcc167 Imports ROXL and ROXR tests. 
Confirming the significant deficiencies I suspected.
 2019-06-29 15:26:09 -04:00
Thomas Harte
9d420c727e Factors out rolls and shifts. 2019-06-29 14:12:52 -04:00
Thomas Harte
60fe84ad16 Imports Bcc tests. 2019-06-29 14:07:21 -04:00
Thomas Harte
6a44c682ad Factors out control flow tests. 2019-06-29 13:47:05 -04:00
Thomas Harte
60df44f0ca Imports CMPI tests. 2019-06-29 13:40:02 -04:00
Thomas Harte
ac926f5070 Factors BCD out of general arithmetic. 2019-06-29 13:31:24 -04:00
Thomas Harte
6e9a4a48f7 Imports TAS tests. 2019-06-28 22:56:35 -04:00
Thomas Harte
a8894b308a Splits out arithmetic tests, as so far implemented. 
Further subdivision may be advisable.
 2019-06-28 22:08:32 -04:00
Thomas Harte
7cc91e1bc5 Factors the bitwise tests out of the main bundle, as that pushes up towards 6,000 lines. 2019-06-28 21:58:38 -04:00
Thomas Harte
9eb51f164c Imports ANDI, ORI and EORI tests. 2019-06-28 21:42:58 -04:00
Thomas Harte
a1c00e9318 Adds BSR tests. 2019-06-28 21:31:41 -04:00
Thomas Harte
241d29ff7c Imports SBCD and NBCD tests, and fixes corresponding operation. 2019-06-28 19:39:08 -04:00
Thomas Harte
c5039a4719 Imports ANDI, ORI and EORI to SR tests. 
Hence corrects supervisor/user privileges for SR/CCR.
 2019-06-28 15:05:46 -04:00
Thomas Harte
fd604048db Imports SUBX tests. 2019-06-28 14:30:26 -04:00
Thomas Harte
6a77ed1e07 Imports SUBI test. 2019-06-28 13:53:53 -04:00
Thomas Harte
9e38815ec4 Imports SUBQ tests. 2019-06-28 13:48:02 -04:00
Thomas Harte
86c325c4ec Imports MOVEA tests. 2019-06-28 13:41:37 -04:00
Thomas Harte
bfcc6cf12c Imports MULU tests. 
Timing is wrong for now.
 2019-06-28 13:33:41 -04:00
Thomas Harte
8ba8cf7c23 Imports TST tests. 2019-06-28 13:17:21 -04:00
Thomas Harte
651fd9c4a5 Imports EOR tests. 2019-06-28 13:03:27 -04:00
Thomas Harte
5d0db2198c Imports BRA, EORI CCR and ORI CCR tests, extends PEA tests. 2019-06-27 23:05:00 -04:00
Thomas Harte
da351a3e32 Imports MOVEQ tests. 2019-06-26 22:36:48 -04:00
Thomas Harte
c0591090f5 Imports DIVU tests. 2019-06-26 22:25:48 -04:00
Thomas Harte
538aecb46e Imports CMP tests, and fixes CMP.l timing. 2019-06-26 22:02:04 -04:00
Thomas Harte
dbdbea85c2 Imports CMPA tests, and fixes CMPA.w. 2019-06-26 21:42:48 -04:00
Thomas Harte
ba2224dd06 Imports NEGX tests and thereby fixes NEGX's zero flag. 2019-06-26 19:39:04 -04:00
Thomas Harte
44e2aa9183 Imports MOVEP tests; code corrections to come. 2019-06-26 19:01:09 -04:00
Thomas Harte
202bff70fe Imports BCLR and BTST tests. 2019-06-26 17:51:07 -04:00
Thomas Harte
26c0cd7f7c Imports ADDI tests. 2019-06-26 16:42:23 -04:00
Thomas Harte
cb76301fbe Imports BCHG tests. 2019-06-26 16:33:23 -04:00
Thomas Harte
8bfa12edf1 Adds lengths to ADD tests, imports ANDI ,CCR and MOVE to CCR. 2019-06-26 16:12:27 -04:00
Thomas Harte
7daa969a5a Imports SUBA tests. 2019-06-26 15:47:59 -04:00
Thomas Harte
4aeb60100d Completes import of MOVEM tests. 2019-06-26 15:31:21 -04:00
Thomas Harte
e2c7aaac5a Imports CLR tests. 2019-06-25 22:47:30 -04:00
Thomas Harte
6ff661c30d Imports OR tests. 2019-06-25 22:34:04 -04:00
Thomas Harte
79066f8628 Imports NOT tests, fixes NOT overflow and carry flags. 2019-06-25 22:18:11 -04:00
Thomas Harte
2c813a2692 Imports CMPM tests and fixes CMPM.bw source/destination order. 2019-06-25 21:46:01 -04:00
Thomas Harte
cc4abcb00a Imports ADDQ tests. 2019-06-25 21:19:04 -04:00
Thomas Harte
c1ca85987f Incorporates MOVE to SR test. 2019-06-25 19:30:51 -04:00
Thomas Harte
ecb5a0b8cc Incorporates ADDX tests and fixes ADDX PreDec. 2019-06-25 19:18:07 -04:00
Thomas Harte
e12e8fc616 Incorporates ASR tests, and fixes ASR (xxx).w. 
... which was re-injecting the wrong bit to preserve sign.
 2019-06-25 18:44:31 -04:00
Thomas Harte
1fbbf32cd2 Adds ASL tests, and corrects ASL (xxx).w. 
Overflow is wrong on other ASLs though, I think.
 2019-06-25 18:09:01 -04:00
Thomas Harte
d7883d18d4 Imports CHK tests. 
Proving that I need to do some research on CHK's flags.
 2019-06-25 14:55:03 -04:00
Thomas Harte
40100773d3 Imports LSR tests. 2019-06-25 13:57:42 -04:00
Thomas Harte
4048ed3a33 Imports ROR tests. 2019-06-25 13:16:44 -04:00
Thomas Harte
11f2d3cea7 Imports EXT tests. 2019-06-24 22:12:29 -04:00
Thomas Harte
aa656a39b8 Imports SUB tests. 2019-06-24 22:00:37 -04:00
Thomas Harte
e830d23533 Incorporates TRAPV tests. 2019-06-24 21:21:35 -04:00
Thomas Harte
9a666fb8cc Imports NEG tests and fixes NEG.l Dn timing. 2019-06-24 19:43:30 -04:00
Thomas Harte
0e208ed432 Fixes cycle counting in the test machine. 2019-06-24 17:55:09 -04:00
Thomas Harte
c8b769de8a Completes import of LSL tests and fixes various LSL issues. 
Including LSL (xxx).w actually being LSR, and the carry flag generally being questionable.
 2019-06-24 17:45:38 -04:00
Thomas Harte
c447655047 Resolves assumption that shifts greater than the bit count of the relevant int are well-defined in C. 2019-06-24 16:51:43 -04:00
Thomas Harte
3ec9a1d869 Incorporates JMP tests, fixes JSR (xxx).l timing. 2019-06-24 15:36:33 -04:00
Thomas Harte
d326886852 Completes BSET tests. 2019-06-24 14:04:08 -04:00
Thomas Harte
faef917cbd Improves resizeable microcycle test. 2019-06-24 10:55:22 -04:00
Thomas Harte
d27ba90c07 Attempts to introduce more rigour to variable-length instruction handling. 2019-06-24 10:43:28 -04:00
Thomas Harte
db4ca746e3 Introduces BSET tests, fixes BSET timing. 2019-06-23 22:53:37 -04:00
Thomas Harte
d50fbfb506 Imports EXG and PEA tests, and fixes EXG timing. 2019-06-23 22:21:25 -04:00
Thomas Harte
5d283a9f1f Imports LEA tests. 2019-06-23 21:48:47 -04:00
Thomas Harte
86fdc75feb Incorporates RTR test, adding a ProcessorState helper. 2019-06-23 18:37:32 -04:00
Thomas Harte
b63231523a Completes import of ROL tests. 2019-06-23 17:33:12 -04:00
Thomas Harte
70e296674d Starts import of ROL tests. 
Including time tests, this time.
 2019-06-22 22:42:57 -04:00
Thomas Harte
5089fcd2f6 Makes a slightly futile attempt to resolve Heisen-failures. 2019-06-22 18:52:06 -04:00
Thomas Harte
df2ce8ca6f Imports MOVE tests. 2019-06-21 22:03:27 -04:00
Thomas Harte
7e209353bb Imports UNLINK and NOP tests. 2019-06-21 21:29:02 -04:00
Thomas Harte
c2806a94e2 Imports further MOVEM tests. 2019-06-21 21:20:13 -04:00
Thomas Harte
d428120776 Completes import of LINK tests. 2019-06-21 18:33:44 -04:00
Thomas Harte
6b996ae57d Improves test machine and incorporates a first test of LINK. 2019-06-21 18:20:13 -04:00
Thomas Harte
ccfe1b13cb Imports DIVS, MULS and MOVE from SR tests. 
Not all passing.
 2019-06-21 16:03:11 -04:00
Thomas Harte
0c1c10bc66 Introduces a test that proves that DIVS' attempt to set proper timing isn't working. 2019-06-20 19:29:02 -04:00
Thomas Harte
fafd1801fe Introduces first DIVS test, and associated fixes. 2019-06-20 19:02:03 -04:00
Thomas Harte
bcf6f665b8 Simplifies and completes DBcc tests. 
Subject to omitting a few that look to me like duplicates.
 2019-06-20 17:19:25 -04:00
Thomas Harte
bd069490b5 Incorporates approximately half of the DBcc tests. 2019-06-20 16:29:32 -04:00
Thomas Harte
624b0b6372 Adds Scc tests. No implementation fixes required. 2019-06-19 21:42:54 -04:00
Thomas Harte
7976cf5b3c Adds ADDA tests. All passing without 68000 changes. 2019-06-19 21:31:14 -04:00
Thomas Harte
440f52c943 Incorporates TRAP test. 2019-06-19 21:18:30 -04:00
Thomas Harte
47b1218a68 Adds a couple of the one-shots: SWAP, MOVE USP. 2019-06-19 19:10:36 -04:00
Thomas Harte
91ced056d2 Adds tests for ADD. No failures. 2019-06-19 18:56:21 -04:00
Thomas Harte
8dace34e63 Imports third-party tests for ABCD, and thereby fixes ABCD. 2019-06-19 18:13:06 -04:00
Thomas Harte
b98f10cb45 Substitutes working GCR test. 2019-06-18 14:24:55 -04:00
Thomas Harte
df56e6fe53 Fixed: the sector number also goes into sector bodies. 
Also the checksum is written in the other order, and the final byte of data isn't output.
 2019-06-18 10:34:10 -04:00
Thomas Harte
5c8aacdc17 Fixes the more obvious issues with GCR encoding: byte order, top bit selection. 2019-06-16 17:17:24 -04:00
Thomas Harte
745a5ab749 Introduces failing test of Macintosh GCR data encoding. 2019-06-16 16:53:03 -04:00
Thomas Harte
fe0dc4df88 Starts building out some tests for Apple GCR encoding. 2019-06-15 22:48:24 -04:00
Thomas Harte
5e2496d59c Simplifies and corrects MOVE logic. 2019-05-28 15:17:03 -04:00
Thomas Harte
c52da9d802 Adds some logging preparatory to a MOVE change. 2019-05-28 15:05:42 -04:00
Thomas Harte
4f9f73ca81 Corrects tests affected by change in run_for_instructions semantics and new program base address. 2019-05-03 15:05:14 -04:00
Thomas Harte
93616a4903 Completes test of a vectored interrupt. 
Correcting issues uncovered.
 2019-05-02 00:00:09 -04:00
Thomas Harte
bb07206c55 Corrects internet response to work as currently implemented. 
Also makes corrections to the bus error and address error exceptions.
 2019-05-01 21:59:06 -04:00
Thomas Harte
e430f2658f Adds a test and by that means fixes divide-by-zero exception return addresses. 2019-04-29 23:09:50 -04:00
Thomas Harte
7332c64964 Improves testing of function as distinct from timing. 2019-04-29 22:08:37 -04:00
Thomas Harte
d6e16d0042 Adds a test of TOS 1.00, as far as it goes without meaningful hardware. 2019-04-29 18:04:57 -04:00
Thomas Harte
8e02d29ae6 Trims test to length of trace capture. 2019-04-29 17:56:49 -04:00
Thomas Harte
c0e9c37cc7 Improves memory map model, as far as it goes. 2019-04-29 17:27:44 -04:00
Thomas Harte
5b5bfc8445 Applies trace testing to EmuTOS. 2019-04-29 16:55:21 -04:00
Thomas Harte
c466b6f9e7 Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler. 2019-04-29 16:11:01 -04:00
Thomas Harte
407643c575 Tweaks test length slightly to ensure this doesn't run beyond the final line's end. 2019-04-29 15:40:17 -04:00
Thomas Harte
d9071ee9f1 Starts sketching out the asynchronous bus. 2019-04-29 13:45:53 -04:00
Thomas Harte
d9278e9827 Attempts to complete the list of things I can't disassemble. 
Mysteries to be solved here, definitely. But: 13 missing opcodes remaining.
 2019-04-28 23:11:49 -04:00
Thomas Harte
0298b1b3b7 Implements LINK and UNLINK. 
Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against.

Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
 2019-04-28 17:12:31 -04:00
Thomas Harte
cf547ef569 Improves semantic communications and temporarily omits A- and F-line instructions. 
So it looks like 2773 instructions left to go.
 2019-04-27 15:15:03 -04:00
Thomas Harte
40f68b70c1 Adds quantification of reports. 
Depressingly; 11,841 opcodes are still missing. Better get on with it!
 2019-04-26 13:25:34 -04:00
Thomas Harte
a3b6d2d16e Corrects test and resolves all instances of opcodes that are valid but shouldn't be. 
The converse case will require implementation of the remaining instructions.
 2019-04-25 22:54:58 -04:00
Thomas Harte
3983f8303f Introduces failing test of 68000 opcode coverage. 2019-04-25 22:06:05 -04:00
Thomas Harte
7cbd5e0ef6 Imports additional files used as test cases. 2019-04-25 21:43:47 -04:00
Thomas Harte
7df85ea695 Cleans up and formally introduces a comparative source for QL startup. 2019-04-25 15:42:41 -04:00
Thomas Harte
a08043ae88 Ensures that MOVE.b #, (xxx).l writes only a byte. 
Also rearranges some of the temporary logging functionality.
 2019-04-23 19:01:58 -04:00
Thomas Harte
6d6046757d Fixes predecrementing MOVEM to leave the proper address in the relevant register. 2019-04-22 15:41:09 -04:00
Thomas Harte
44eb4e51ed Ensures DBcc properly signals program fetches. 2019-04-21 22:54:20 -04:00
Thomas Harte
3cb042a49d Corrects the carry and extend flags for various long-word operations. 2019-04-21 22:08:18 -04:00
Thomas Harte
0be9a0cb88 Corrects Scc (and other conditionals) for complex addressing modes. 2019-04-20 18:35:19 -04:00
Thomas Harte
ef33b004f9 Corrects word access order of MOVEM.l. 2019-04-20 15:13:12 -04:00
Thomas Harte
2cac4b0d74 Corrects EA usage for ADDA and SUBA. 2019-04-19 23:02:41 -04:00
Thomas Harte
a49f516265 Corrects direction of MOVE [to/from] USP. 2019-04-19 22:41:06 -04:00
Thomas Harte
2d97fc1f59 Beefs up documentation and developer support. 2019-04-19 13:29:35 -04:00
Thomas Harte
ee7ae11e90 Implements EXG and SWAP. 2019-04-19 11:27:43 -04:00
Thomas Harte
c265ea9847 Corrects byte writes in both test machines. 2019-04-17 16:39:10 -04:00
Thomas Harte
b64da2710a Corrects a few MOVE #s. 2019-04-17 10:00:14 -04:00
Thomas Harte
82b08d0e3a Corrects addressing behaviour of nRd[+-]. 2019-04-17 08:53:34 -04:00
Thomas Harte
62e4c23961 Corrects memory map, causing the RAM test no longer to fail. 2019-04-15 13:03:32 -04:00
Thomas Harte
a223cd90a1 Adds predecrement TSTs, increases QL running time, reduces logging. 2019-04-15 12:36:08 -04:00
Thomas Harte
fba210f7ce Corrects MOVE.l Dn, (An)[+]. 2019-04-15 09:30:49 -04:00
Thomas Harte
52e33e861c Starts to introduce the QL as a second source for 68000 testing. 
It's advantageous over the ST in that a commented disassembly of the ROM is available.
 2019-04-14 22:15:09 -04:00
Thomas Harte
2ba66c4457 Corrects MOVEA, adds extra test safeguards. 2019-04-12 16:10:17 -04:00
Thomas Harte
06a2f59bd0 Implements DBcc. 2019-04-06 23:21:01 -04:00
Thomas Harte
0af57806da Adds a hard-coded value sufficient to advance in TOS startup. 2019-04-06 20:00:34 -04:00
Thomas Harte
73e1c8c780 Corrects now-unimplemented ADD/SUB. 2019-04-03 19:43:54 -04:00
Thomas Harte
2c5ff9ada0 Switches to running the real TOS, at least temporarily, and enables better testing. 2019-03-31 22:27:57 -04:00
Thomas Harte
b0b2798f39 Updates to track Swift. 2019-03-27 21:25:51 -04:00
Thomas Harte
47359dc8f1 Adds tests for MOVE.l (An), Dn, and thereby correct their implementation. 2019-03-23 21:41:47 -04:00
Thomas Harte
d7c3d4ce52 Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof. 2019-03-22 23:27:48 -04:00
Thomas Harte
87420881c8 Extends to a failing test. 2019-03-21 23:32:03 -04:00
Thomas Harte
fdc598f2e1 Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths. 2019-03-21 22:30:41 -04:00
Thomas Harte
0d7bbdad54 Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix. 2019-03-17 21:57:00 -04:00
Thomas Harte
388d808536 Switches to providing UDS and LDS implicitly via address. 
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
 2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d Adds an implementation of SBCD and slightly neatens syntax for building programs. 2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956 This might very well be the 68000's first real gasp: performing an ABCD. 2019-03-14 19:32:15 -04:00
Thomas Harte
9e8928aad9 Implements as much as I currently care about of the Atari ST memory map. 2019-03-11 22:47:37 -04:00
Thomas Harte
89c71f9119 Introduces EmuTOS, and starts constructing test cases around it. 2019-03-10 18:40:12 -04:00
Thomas Harte
a4f6db6719 Removes ArrayBuilderTests as the ArrayBuilder is long gone. Disables TIA tests for now. 2019-03-10 18:07:23 -04:00
Thomas Harte
6a93d2d006 Corrects some minor spaces-instead-of-tabs errors. 2019-01-24 22:59:03 -05:00
Thomas Harte
ee89be6730 Removes many stray spaces. 2018-11-23 22:32:32 -05:00
Thomas Harte
a8645f80bf Introduces 'non-exclusive' emulator-space keyboards. 
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
 2018-10-24 21:59:30 -04:00
Thomas Harte
c07f9fed99 Corrects test and implementation to pass the exhaustive VDP interrupt prediction test. 2018-10-21 18:42:49 -04:00
Thomas Harte
616777517d Makes the failing test more communicative, in the hope of more easily debugging errors. 2018-10-21 14:35:44 -04:00
Thomas Harte
b3f1677da5 Introduces new failing test for rational continuous interrupt prediction. 2018-10-21 13:59:14 -04:00
Thomas Harte
725b364bbc Improves testing; now tests for time to the first interrupt. 2018-10-20 18:25:55 -04:00
Thomas Harte
acdc84e08c Improves test slightly, and fixes line interrupt reload value setting. 2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549 Introduces a first unit test for line interrupts and corrects backup behaviour. 2018-10-09 21:49:21 -04:00
Thomas Harte
fc84ae611e Resolves various instances of spaces in place of tabs. 2018-09-09 20:33:56 -04:00
Thomas Harte
ddf45a0010 Ensures NMI and RST reset D on 65C02s. 2018-08-14 19:49:14 -04:00
Thomas Harte
261fb3d4f8 Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing. 
This gets Klaus Dorman's test to pass.
 2018-08-10 22:42:35 -04:00
Thomas Harte
b63e0cff72 Improves has-completed test. 2018-08-10 22:27:01 -04:00
Thomas Harte
5d6e479338 Implements RMB and SMB, and fixes SBC (zero). 2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5 Implements TSB and TRB, and adds the extra BIT instructions. 2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e Implements STZ. 2018-08-10 21:17:02 -04:00
Thomas Harte
95164b79c9 Attempted implementation of (zp) addressing mode. 2018-08-09 21:51:14 -04:00
Thomas Harte
bb680b40d8 Implements the 65C02's JMPs. 2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994 Implements the 65C02 NOPs. 2018-08-08 20:00:14 -04:00
Thomas Harte
32338bea4d Implements BRA. 2018-08-06 22:37:30 -04:00
Thomas Harte
1a44ef0469 Introduces Klaus Dorman's 65C02 tests. All failing. 2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51 Fixes test target. 2018-08-06 21:15:13 -04:00
Thomas Harte
abca38a548 Makes an initial removal of PCMPatchedTrack. Farewell, old friend. 2018-07-01 22:49:57 -04:00
Thomas Harte
853261364e Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32. 2018-05-23 22:21:57 -04:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
05e31d7594 Mutates testComplicatedTrackSeek into an actual test. 
Which frustratingly passes.
 2018-05-01 19:52:12 -04:00
Thomas Harte
f4097290c2 Made various corrections following a quick for-loop constness audit. 2018-04-30 22:23:57 -04:00
Thomas Harte
b32538f3c8 Adds an additional test. 2018-04-30 22:05:44 -04:00
Thomas Harte
e7618bb32e Corrects types (/chickens out). 2018-04-30 22:04:05 -04:00
Thomas Harte
e599e65087 Switches to use of the TargetList typedef wherever possible. 2018-04-14 19:46:38 -04:00
Thomas Harte
389979923e Performs update to and satisfaction of Xcode 9.3's preferred warnings. 2018-03-30 10:25:01 -04:00
Thomas Harte
f0f9d5a6af Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour. 2018-03-08 20:30:22 -05:00
Thomas Harte
fdef914137 Corrects test target regression. 2018-03-06 18:32:21 -05:00
Thomas Harte
66faed4008 Gives MachineForTargets complete responsibility for initial machine state. 2018-01-25 18:28:19 -05:00
Thomas Harte
21efb32b6f Integrates the static and nascent dynamic analyser namespaces. 2018-01-24 21:48:44 -05:00
Thomas Harte
ed564cb810 Implements the main four cartridge banking schemes. 
Slightly proof of concept for now.
 2018-01-04 22:18:18 -05:00
Thomas Harte
c8367a017f Cleans up test and makes attempt to factor in cartridge type popularity. 2018-01-01 21:21:05 -05:00
Thomas Harte
344a12566b Tweaks a couple of expected cartridge types. 2018-01-01 20:14:56 -05:00
Thomas Harte
c07113ea95 Ensures no illegal accesses while testing MSX ROM type detection. 
Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
 2018-01-01 17:38:26 -05:00
Thomas Harte
bc2879c412 Corrects the MSX ROM unit test. 
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
 2018-01-01 17:35:13 -05:00
Thomas Harte
db25b4554b Introduces failing tests of the MSX static analyser. 2018-01-01 16:38:26 -05:00
Thomas Harte
05b95ea2e0 Corrects Xcode tests. 2018-01-01 16:04:13 -05:00
Thomas Harte
6e1d69581c Eliminates a variety of end-of-line spaces. 2017-11-07 22:54:22 -05:00
Thomas Harte
f95515ae81 Eliminates a large number of instance of end-of-line tabs. 2017-11-07 22:51:06 -05:00
Thomas Harte
064f1dfdbc Removes usages of deprecated initialiser. 2017-10-05 18:10:47 -04:00
Thomas Harte
ff24e1de31 Corrects 6522 bridge per has-a-not-is-a template switch. 2017-09-04 21:56:21 -04:00
Thomas Harte
7af3de010e Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments. 2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable. 2017-08-21 21:56:42 -04:00
Thomas Harte
761afad118 Corrected timestamp return, and its testing by the 6502 timing tests. 2017-07-27 21:19:16 -04:00
Thomas Harte
37950143fc Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests. 2017-07-27 20:17:13 -04:00
Thomas Harte
9257a3f6d7 Added test for 16-bit arithmetic, and fixed implementation. 2017-07-26 19:04:52 -04:00
Thomas Harte
728143247d Added a test for RLD and RRD. Which already passes. 2017-07-26 18:56:35 -04:00
Thomas Harte
6ec4e4e3d7 Merge branch 'master' into Memptr 2017-07-25 23:01:34 -04:00
Thomas Harte
37ccb9d3b6 Fixed 6502 timing tests. 2017-07-25 23:00:39 -04:00
Thomas Harte
3c254360ba Completed fixture of the 6502 BCD test. 2017-07-25 22:55:45 -04:00
Thomas Harte
3ca51bedc6 Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses. 2017-07-25 22:48:44 -04:00
Thomas Harte
36076b7ea5 Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams. 2017-07-25 22:38:26 -04:00
Thomas Harte
df4732be2e Corrected test. 2017-07-24 22:33:49 -04:00
Thomas Harte
9435c1e12a The 1540 is now a ClockReceiver. 2017-07-24 22:32:41 -04:00
Thomas Harte
2912d7055b The 6532 is now a ClockReceiver. 2017-07-24 21:57:24 -04:00
Thomas Harte
13f7aa4063 The TIA is now a ClockReceiver. 2017-07-24 21:48:34 -04:00
Thomas Harte
b3ae920746 Converted the DPLL and disk controller classes to be ClockReceivers. 2017-07-24 21:04:47 -04:00
Thomas Harte
e6578defcd It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in. 2017-07-23 22:22:50 -04:00
Thomas Harte
ace8e30818 Bubbled the Z80's move into clock receiver territory up into the Z80 test machine. 2017-07-23 22:21:39 -04:00
Thomas Harte
b0c2325adc Corrected run call, and accepted that jam handling is gone forever. 2017-07-22 22:21:26 -04:00
Thomas Harte
4ea835e50b Added test for EX (SP), rp, which passes. 2017-07-22 17:17:32 -04:00
Thomas Harte
6437c43147 Added CPI and CPD tests: at last two that pass without requiring implementation changes! 2017-07-22 12:38:18 -04:00
Thomas Harte
5928a24803 Transcribed missing tests as TODOs. 2017-07-22 11:44:17 -04:00
Thomas Harte
20a6bcc676 Added tests for the various LD (nn), rr instructions and corrected implementation to pass. 2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6 Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass. 2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204 Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test. 2017-07-21 23:01:35 -04:00
Thomas Harte
660f0e4c40 Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails. 2017-07-21 22:52:25 -04:00
Thomas Harte
7b5f93510b Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests. 2017-07-16 20:55:57 -04:00
Thomas Harte
8ddd686049 Removed redundant variable. 2017-07-16 19:04:03 -04:00
Thomas Harte
2fb0aea990 Updated the C1540 test vessel to the new world. 2017-07-16 17:00:39 -04:00
Thomas Harte
95a6b0f85c Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter. 2017-06-22 21:09:26 -04:00
Thomas Harte
0e0ce379b4 Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle. 2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505 Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line. 2017-06-21 20:32:08 -04:00
Thomas Harte
108da64562 Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss. 2017-06-20 22:25:00 -04:00
Thomas Harte
184b371649 Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess. 2017-06-20 21:48:50 -04:00
Thomas Harte
27ac342928 Corrected conditional call timing, and its test. 2017-06-20 20:57:23 -04:00
Thomas Harte
6752f165db Added failing tests for both kinds of CALL. 2017-06-19 22:03:29 -04:00
Thomas Harte
e05076b258 Added tests for everything except CALL. All passing. 2017-06-19 22:00:04 -04:00
Thomas Harte
fadbfdf801 Added DJNZ test. 2017-06-19 21:31:56 -04:00
Thomas Harte
cb277b8d1e Added JP and JR tests. 2017-06-19 21:27:23 -04:00
Thomas Harte
234f14dbbe Tests were at fault; all passing now. 2017-06-19 21:14:40 -04:00
Thomas Harte
99ede3a9ef BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d). 2017-06-19 21:04:14 -04:00
Thomas Harte
378233f53d Extended to BITs and SETs, accruing three new failures. 2017-06-19 21:01:30 -04:00
Thomas Harte
f903408980 Caught up on comments. 2017-06-19 20:53:22 -04:00
Thomas Harte
b684254908 Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed. 2017-06-19 20:33:34 -04:00
Thomas Harte
351d90ca55 Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL. 2017-06-19 20:04:55 -04:00
Thomas Harte
23177df26a Added various tests of the basic ALU ops. 2017-06-19 19:53:26 -04:00
Thomas Harte
ba15371948 Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here. 2017-06-19 19:47:00 -04:00
Thomas Harte
8d60734737 Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect. 2017-06-19 19:17:54 -04:00
Thomas Harte
002098d496 The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests. 2017-06-19 07:45:41 -04:00
Thomas Harte
85c5c4405a Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse. 2017-06-19 07:30:01 -04:00
Thomas Harte
d668879ba6 Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates. 2017-06-18 22:03:13 -04:00
Thomas Harte
e1a2580b2a Renamed BusOperation to MachineCycle::Operation. 2017-06-17 21:53:45 -04:00
Thomas Harte
b6f51474ff Ensured that -description can handle the newly-captured bus actions. 2017-06-17 18:20:30 -04:00
Thomas Harte
0f18768091 Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do. 2017-06-17 18:19:25 -04:00
Thomas Harte
50cd617bd9 Ensured test raises only the intentional failure exceptions. 2017-06-15 22:33:46 -04:00
Thomas Harte
838b818cd3 Finished transcribing first page of machine cycle documentation; several failures contained. 2017-06-15 22:19:49 -04:00
Thomas Harte
cf795562bf Continued filling in tests, fleshing out what the test machine captures as a result. 2017-06-15 20:59:59 -04:00
Thomas Harte
ac37424878 Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on. 2017-06-15 19:06:59 -04:00
Thomas Harte
aed2827e7b Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected. 2017-06-12 22:22:00 -04:00
Thomas Harte
50be3a24fe Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be. 2017-06-11 13:30:08 -04:00
Thomas Harte
2190f60a89 Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool. 2017-06-04 15:46:35 -04:00
Thomas Harte
0eebfdb4cc Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines. 2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f Started sneaking in memptr emulation, hopefully to get to a working BIT (hl). 2017-06-04 15:07:07 -04:00
Thomas Harte
87095b0578 Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures. 2017-06-04 14:04:26 -04:00
Thomas Harte
b642d9f712 Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs. 2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5 Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502. 2017-06-03 21:22:16 -04:00
Thomas Harte
b3da16911f Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2. 2017-06-03 18:42:54 -04:00
Thomas Harte
e52892f75b Added a test of interrupt mode 1. 2017-06-03 18:16:13 -04:00
Thomas Harte
8c41a0f0ed Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine. 2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed. 2017-06-03 17:41:45 -04:00
Thomas Harte
d14902700a Minor syntax and wiring fixes. 2017-06-01 22:33:05 -04:00
Thomas Harte
c95c32a9fe Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine. 2017-06-01 22:31:04 -04:00
Thomas Harte
494ce073b5 Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging. 2017-05-31 19:58:57 -04:00
Thomas Harte
5ff73faf48 Ensured Zexall can pass. 2017-05-31 19:55:06 -04:00
Thomas Harte
2f7f11e2e5 Added diagnosis props. 2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122 Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function. 2017-05-30 22:41:23 -04:00
Thomas Harte
244b5ba3c2 Added a proper termination condition for Zexall and, for now, a Mhz counter. 2017-05-30 18:32:38 -04:00
Thomas Harte
960de7bd7b Marginally reduced test machine costs based on usage. 2017-05-30 11:59:07 -04:00
Thomas Harte
4d4695032c Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end. 2017-05-29 21:46:00 -04:00
Thomas Harte
6d22f6fcd5 Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being. 2017-05-29 17:17:17 -04:00
Thomas Harte
8bfaa487ce Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit). 2017-05-29 17:13:24 -04:00
Thomas Harte
267b2add9a Adjusted for where FUSE nominally places timestamps. Down to 92 failures. 2017-05-29 16:44:07 -04:00
Thomas Harte
d290e3d99e Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!) 2017-05-29 16:35:00 -04:00
Thomas Harte
a6a4c5a936 Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures. 2017-05-29 15:57:27 -04:00
Thomas Harte
ed7b07c8b1 Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct. 2017-05-29 11:54:27 -04:00
Thomas Harte
d83dd17738 [DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed. 2017-05-29 11:40:56 -04:00
Thomas Harte
9ade0dcae3 One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison. 2017-05-29 11:06:23 -04:00
Thomas Harte
a329d85697 Instituted memory value checks, flushing out seven new failures. 2017-05-29 11:01:45 -04:00
Thomas Harte
c322410783 Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation. 2017-05-29 10:52:54 -04:00
Thomas Harte
b67331e018 Fixing the OUT repetition group reduces the code to one failing test. 2017-05-29 10:48:53 -04:00
Thomas Harte
ad56a9215c Implemented IN[I/D]x. 18 failures remaining. 2017-05-29 10:12:33 -04:00
Thomas Harte
c56a5344b9 Implemented CP[I/D]x. 2017-05-29 08:54:00 -04:00
Thomas Harte
409c82ce73 Implemented RLD and RRD. 34 failures remaining. 2017-05-28 16:46:27 -04:00
Thomas Harte
6e83b7d6df Attempted to add a proper exit condition for Zexall. 2017-05-28 15:13:47 -04:00
Thomas Harte
5a4d448cc1 Corrected logical flags; now down to 68 failures, all of them on the ED page. 2017-05-28 15:09:58 -04:00
Thomas Harte
6b66c8f304 Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84. 2017-05-28 14:50:51 -04:00
Thomas Harte
035df316aa FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures. 2017-05-27 23:54:53 -04:00
Thomas Harte
c7cb47a1d8 Readded and then disabled my temporary one-test-only patch. Failures are currently at 237. 2017-05-27 21:10:25 -04:00
Thomas Harte
98423c6e41 Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues. 2017-05-27 16:19:15 -04:00
Thomas Harte
33c3fa21e3 Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672. 2017-05-27 15:54:24 -04:00
Thomas Harte
9bc2b48d9b Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures. 2017-05-26 23:23:33 -04:00
Thomas Harte
e4e71a1e5f Switched back to descriptive failures, but put a cap on them. 2017-05-25 21:08:24 -04:00
Thomas Harte
fba5af280e Shortened failure message, at least for now. 2017-05-25 21:05:47 -04:00
Thomas Harte
2cadc706e2 Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started. 2017-05-25 21:00:33 -04:00
Thomas Harte
3c6f63abcc Started towards running the FUSE tests. Just need to deal with the memory segments. 2017-05-25 19:12:59 -04:00
Thomas Harte
00cd7e7e9c After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON. 2017-05-25 18:20:13 -04:00
Thomas Harte
055c860b43 Sealed off RegisterState as immutable, and started trying to parse the .expected file. 2017-05-23 22:32:36 -04:00