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816 Commits

Author SHA1 Message Date
Jim Grosbach
f1aa47dc1a ARM Pseudo-ize tBR_JTr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 19:32:47 +00:00
Jim Grosbach
11fbff8085 The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to 
get the pretty-printer. That's handled explicityly by the MC lowering now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120305 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:53:24 +00:00
Jim Grosbach
2dc7768d73 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 18:37:44 +00:00
Eric Christopher
9d89311df8 Pseudos default to 4byte size, let the instruction size field notice 
that branch tables are special.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 23:38:19 +00:00
Bill Wendling
af2b573614 Add encoding for ARM "trap" instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 11:05:29 +00:00
Jim Grosbach
0eb49c57f0 BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119918 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-21 01:26:01 +00:00
Jim Grosbach
078e239f69 Fix ARM LDR* post-indexed operand encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 23:14:43 +00:00
Jim Grosbach
6571101cb7 Fix encoding for ARM MLS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:22:37 +00:00
Jim Grosbach
2aeb6121a1 Add ARM encoding information for STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:14:31 +00:00
Jim Grosbach
a1b4175b8e Shuffle things around a bit to keep like things together. Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 22:06:57 +00:00
Jim Grosbach
953557f445 Factor out operand encoding bits for ARM addressing mode 2 store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:35:06 +00:00
Jim Grosbach
9ef65cbbc6 Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119841 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:14:02 +00:00
Jim Grosbach
9558b4cdc4 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 21:07:51 +00:00
Jim Grosbach
9cb15b5be5 Add ARM binary encoding information for the rest of the indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119821 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 19:41:26 +00:00
Jim Grosbach
f1ce7cc1d1 ARM LDRD binary encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 18:16:46 +00:00
Jim Grosbach
817c1a6ddd Minor cleanups to a few llvm_unreachable() calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 00:27:09 +00:00
Jason W Kim
837caa9313 Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. 
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:37:15 +00:00
Jim Grosbach
75b7b879c0 ARM Encoding information for UXTAH and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 23:24:22 +00:00
Jim Grosbach
99594eb1de ARM PseudoInst instructions don't need or use an assembler string. Get rid of 
the operand to the pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119607 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:38:26 +00:00
Jim Grosbach
53694265a9 Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 
just pretend to be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 01:15:56 +00:00
Jim Grosbach
160f8f0e67 Refactor a few ARM load instructions to better parameterize things and re-use 
common encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-18 00:46:58 +00:00
Jim Grosbach
85eb54cf0c Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark 
it as such. Add some encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 23:33:14 +00:00
Jim Grosbach
f8dabac604 Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly 
in the MC lowering process.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 21:05:55 +00:00
Evan Cheng
c4af4638df Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, 
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 20:13:28 +00:00
Jim Grosbach
89e14c7579 More ARM encoding bits. LDRH now encodes properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 18:11:11 +00:00
Bill Wendling
0f63075613 Proper encoding for VLDM and VSTM instructions. The register lists for these 
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-17 04:32:08 +00:00
Bill Wendling
3380f6a4d0 Use the correct variable names so that the encodings will be correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 23:44:49 +00:00
Jim Grosbach
7911916cf7 ARM conditional mov encoding fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 18:13:42 +00:00
Bill Wendling
7b71878d9f - Remove dead patterns. 
- Add encodings to the *LDMIA_RET instrs. Probably not needed...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 02:08:45 +00:00
Bill Wendling
73fe34a3ee Encode the multi-load/store instructions with their respective modes ('ia', 
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-16 01:16:36 +00:00
Jim Grosbach
99f53d13ef ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 20:47:07 +00:00
Jim Grosbach
17e967eac2 Nuke redundant encoding bit set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 18:17:24 +00:00
Chris Lattner
2ac190238e add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-15 05:19:05 +00:00
Bill Wendling
c93989a060 Comment out the defms until they're activated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 11:20:05 +00:00
Bill Wendling
ddc918b379 Add uses of the *_ldst_multi multiclasses. These aren't used yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 10:57:02 +00:00
Bill Wendling
1f4abcfa5c Convert the modes to lower case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 10:43:34 +00:00
Bill Wendling
04863d06fb Minor cleanups: 
- Get the opcode once.
- Add a ParserMatchClass to reglist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 10:40:19 +00:00
Bill Wendling
6c470b806f Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the 
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 09:09:38 +00:00
Evan Cheng
c47f7d643e Conditional moves are slightly more expensive than moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 05:14:20 +00:00
Evan Cheng
63f3544a7f Add conditional move of large immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 02:25:14 +00:00
Jim Grosbach
df7e0f8d5d Swap multiclass operand order for consistency with other patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 01:28:30 +00:00
Jim Grosbach
0f6e33b0c8 Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 01:07:20 +00:00
Jim Grosbach
9e0bfb5829 More ARM load/store indexed refactoring. Also fix an incorrect IndexMode 
flag for the LDRT/STRT family instructions as a side effect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-13 00:35:48 +00:00
Evan Cheng
11c11f8ab0 For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:46:13 +00:00
Evan Cheng
893d7fe209 Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 23:03:38 +00:00
Evan Cheng
875a6ac09a Add conditional mvn instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 22:42:47 +00:00
Jim Grosbach
e1634e9351 Zap a copy/paste-o bit of dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118926 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:29:10 +00:00
Jim Grosbach
2716e25c2c Refactor to parameterize some ARM load/store encoding patterns. Preparatory 
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 21:28:15 +00:00
Jim Grosbach
d75c3f136b Fill in the default predication bits for ARM unconditional branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-12 18:13:26 +00:00
Jim Grosbach
d1d5a39cad ARM fixup encoding for direct call instructions (BL). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:05:40 +00:00
Jim Grosbach
c466b937db Encoding of destination fixup for ARM branch and conditional branch 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:04:49 +00:00
Jim Grosbach
7eab97f260 Encoding for ARM LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 16:55:29 +00:00
Jim Grosbach
928f3325a7 Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616 Fix encoding of Ra register for ARM smla* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691 ARM STRH encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381 ARM LDM encoding for the mode (ia, ib, da, db) operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e Fix ARM encoding of non-return LDM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca Fix ARM encoding of LDM+Return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:12:48 +00:00
Jim Grosbach
e0ee08e367 Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 18:43:54 +00:00
Jim Grosbach
54fea632b1 Add encoder method for ARM load/store shifted register offset operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:20:53 +00:00
Bill Wendling
5e559a22c1 Revert r118457 and r118458. These won't hold for GPRs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 00:30:18 +00:00
Bill Wendling
3734ef3fb4 reglist has two operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:50:20 +00:00
Bill Wendling
5991487c10 Make RegList an ASM operand so that TableGen will generate code for it. This is 
an initial implementation and may change once reglists are fully fleshed out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 00:39:58 +00:00
Evan Cheng
416941d50f Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 05:19:35 +00:00
Evan Cheng
dfed19fe2c Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 05:14:24 +00:00
Bill Wendling
92b5a2eb16 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:49:29 +00:00
Jim Grosbach
e6913600c7 Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:01:43 +00:00
Chris Lattner
a1ca91af4e Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:40:41 +00:00
Bill Wendling
5df0e0a61d Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:31:46 +00:00
Owen Anderson
a2b50b300e Rename encoder methods to match naming convention. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:28:01 +00:00
Jim Grosbach
28b108250d Sort bit assignments. Cosmetic change only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:59:04 +00:00
Owen Anderson
cf667be17b Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:24:55 +00:00
Owen Anderson
d9aa7d30aa Add correct NEON encodings for the "multiple single elements" form of vld. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 00:05:05 +00:00
Bob Wilson
665814b6be Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:51 +00:00
Jim Grosbach
833c93c795 Mark ARM subtarget features that are available for the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 16:59:54 +00:00
Chris Lattner
39ee036f40 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:10:56 +00:00
Chris Lattner
8b2f0822f3 revert r117858 while I check out a failure I missed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:05:32 +00:00
Chris Lattner
efa53760fe the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 18:48:12 +00:00
Bob Wilson
f74a429816 Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 00:54:37 +00:00
Jim Grosbach
6b5252db2d Encode the register list operands for ARM mode LDM/STM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 00:37:59 +00:00
Jim Grosbach
0d2d2e9246 s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand 
encoder functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:19:55 +00:00
Jim Grosbach
8e0a3eb957 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 21:35:25 +00:00
Jim Grosbach
e317b13a2d Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 20:21:49 +00:00
Jim Grosbach
f32ecc69e5 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 20:21:36 +00:00
Jim Grosbach
86875a2463 ARM mode LDREX*/STREX* binary encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 19:58:57 +00:00
Jim Grosbach
27e900888e Encoding information for ARM conditional move instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 19:28:17 +00:00
Chris Lattner
14b93851cc add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 00:27:31 +00:00
Jim Grosbach
ab682a2090 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 18:34:10 +00:00
Evan Cheng
7e2fe9150f Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 06:47:08 +00:00
Evan Cheng
9e08ee5d16 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 02:00:25 +00:00
Evan Cheng
0104d9de04 - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 01:49:06 +00:00
Evan Cheng
f40deed62f Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:41:30 +00:00
Jim Grosbach
7e3383c007 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 22:49:00 +00:00
Jim Grosbach
f31430f6ec ARM JIT fix for LDRi12 and company. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 19:55:59 +00:00
Jim Grosbach
c1d30212e9 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:19:44 +00:00
Jim Grosbach
28e3fe961f Since I parameterized this bit, I should probably actually use said parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 23:58:04 +00:00
Jim Grosbach
3e55612472 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 22:37:02 +00:00
Jim Grosbach
a9a968d1ef Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 23:48:29 +00:00
Jim Grosbach
f8da5f5dfa ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 22:12:16 +00:00
Jim Grosbach
385e136dce Add the encoding information for the rest of the ARM mode multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 19:15:30 +00:00
Jim Grosbach
3870b750e6 More ARM multiply instuction binary encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:35:16 +00:00
Jim Grosbach
929a7056d8 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 17:42:06 +00:00
Jim Grosbach
9463d0e400 More ARM multiply instruction encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 17:16:17 +00:00
Jim Grosbach
f50af8b5b8 ARM binary encoding for some of the multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:52:30 +00:00
Jim Grosbach
3686046a2c ARM binary encodings for MVN variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:19:32 +00:00
Jim Grosbach
3fea19105d ARM Binary encoding information for BFC/BFI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:03:21 +00:00
Jim Grosbach
e4ad387a5a Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 23:27:08 +00:00
Jim Grosbach
70987fbc60 ARM encoding information for [SU]SAT* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 23:35:38 +00:00
Jim Grosbach
5ad01c7728 Encoding information for the various ARM saturating add/sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 19:49:46 +00:00
Jim Grosbach
84760885e1 ARM binary encoding information for RSB and RSC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:42:41 +00:00
Jim Grosbach
8abe32af38 ARM mode encoding information for UBFX and SBFX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:15:16 +00:00
Bob Wilson
1dd5a2f4e1 Remove unused ARMISD::AND selection DAG node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 04:34:40 +00:00
Jim Grosbach
197a8df640 Encoding info for extension instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 02:29:58 +00:00
Jim Grosbach
58456c0b04 Add missing Rd encoding for MOVs instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 23:28:31 +00:00
Jim Grosbach
7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69 MOVi16 and MOVT ARM mode encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 18:54:27 +00:00
Jim Grosbach
2d294f564b Simplify encoding information and add 'dst' operand info for TAILJMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 17:24:28 +00:00
Jim Grosbach
b4b07b93ea Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c Add operand encoding bits for SMC and SVC in ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062 More encoding cleanup. Also add register Rd operands for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7 Simplify some ARM encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:48:54 +00:00
Jim Grosbach
6c354fd3f5 Add a FIXME. The ADR instruction is a bit odd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:00:04 +00:00
Jim Grosbach
596307e133 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509 Fix encoding for compares. No Rd register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:00:52 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:50:27 +00:00
Jim Grosbach
ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:53:58 +00:00
Jim Grosbach
2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:18:08 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:16:21 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:51:51 +00:00
Jim Grosbach
56ac907c57 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 21:45:55 +00:00
Jim Grosbach
3bbdcea49a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:42:42 +00:00
Jim Grosbach
3c38f96af2 Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:36:43 +00:00
Evan Cheng
a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:27:31 +00:00
Jim Grosbach
adde5da638 Nuke a bunch of no-longer-needed comment-only asm strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 23:09:33 +00:00
Jim Grosbach
a3fbadfcd8 Nuke a few more unused asm strings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 19:53:58 +00:00
Jim Grosbach
71d933a49e The asm strings are never used at all, so just nuke 'em entirely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 16:56:53 +00:00
Jim Grosbach
7ebc863c15 Go ahead and jump! 
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 02:18:06 +00:00
Evan Cheng
0e55fd61ae ARM instruction itinerary fixes: 
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 01:08:25 +00:00
Jim Grosbach
828916203a Add specializations of addrmode2 that allow differentiating those forms 
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 19:03:54 +00:00
Evan Cheng
5d42c567c9 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 00:49:25 +00:00
Evan Cheng
7e1bf305cf Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 00:27:46 +00:00
Evan Cheng
576a3968a2 Fix zero and sign extension instructions scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 00:49:35 +00:00
Evan Cheng
5be3922321 Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 22:03:46 +00:00
Owen Anderson
f523e476c2 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further 
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:45:25 +00:00
Jim Grosbach
b327e13740 #+4 --> #4 for consistency with other asm output 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:32:38 +00:00
Jim Grosbach
45d6c1777c Fix formatting of output .s code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:03:26 +00:00
Owen Anderson
71e416ac3a Add isConditionalMove bits to X86 and ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 22:57:01 +00:00
Jim Grosbach
2e6ae13bf6 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:05:37 +00:00
Chris Lattner
52a261b3c1 fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 20:31:19 +00:00
Bill Wendling
c8714bb144 Reword since this may not be a bug but intended behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113584 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 10:31:11 +00:00
Evan Cheng
7602acbf3b Fix LDM_RET schedule itinery. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 22:57:08 +00:00
Chris Lattner
5bcb8a6112 temporarily revert r112664, it is causing a decoding conflict, and 
the testcases should be merged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 16:00:50 +00:00
Bill Wendling
43a6c5e2fc We have a chance for an optimization. Consider this code: 
int x(int t) {
  if (t & 256)
    return -26;
  return 0;
}

We generate this:

     tst.w   r0, #256
     mvn     r0, #25
     it      eq
     moveq   r0, #0

while gcc generates this:

     ands    r0, r0, #256
     it      ne
     mvnne   r0, #25
     bx      lr

Scandalous really!

During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):

  %r0 = ISD::AND ...
  ARMISD::CMPZ %r0, 0         @ sets [CPSR]
  %r0 = ARMISD::MOVCC 0, -26  @ reads [CPSR]

All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 22:41:22 +00:00
Bill Wendling
2d811d38d4 And ANDS pattern to match the t2ANDS pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-31 22:05:37 +00:00
Jim Grosbach
663e339e20 Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should 
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-30 19:49:58 +00:00
Bill Wendling
10ce7f3116 Fix whitespaces. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-29 11:31:07 +00:00
Bill Wendling
ac3b935362 File missing from last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-29 03:02:28 +00:00
Bill Wendling
6165e87824 Reapply r112176 without removing the other CMN patterns (that was unintentional). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-26 18:33:51 +00:00
Jakob Stoklund Olesen
00d3dda86f Don't call tablegen'ed Predicate_* functions in the ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 20:39:04 +00:00
Jim Grosbach
c5ed0134a7 80 column cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 18:39:16 +00:00
Bob Wilson
f955f290c9 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:23:19 +00:00
Bob Wilson
dc66edaced Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 22:26:55 +00:00
Bob Wilson
22f5dc79c0 Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 18:27:34 +00:00
Bob Wilson
45cdd7fd61 Remove unused code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 17:06:03 +00:00
Johnny Chen
1adc40cac3 Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:46:17 +00:00
Johnny Chen
7def14f40f Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:35:12 +00:00
Bob Wilson
eaf1c98a7c Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:10:46 +00:00
Evan Cheng
ee34987fd5 Really control isel of barrier instructions with cpu feature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:31 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:22:01 +00:00
Bill Wendling
0cce3dd326 Mark ARM compare instructions as isCompare. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:22:27 +00:00
Bob Wilson
9a1c189d9e Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:01:18 +00:00
Bob Wilson
751aaf8ac5 Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110363 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 19:00:21 +00:00
Bob Wilson
a1d410d512 Add an ARM RSCrr instruction for disassembly only. 
Partial fix for PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 18:59:36 +00:00
Bob Wilson
cff7178844 Add an ARM RSBrr instruction for disassembly only. 
Partial fix for PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 18:23:43 +00:00
Bob Wilson
d4d188e502 Move newlines before inline jumptables from the asm strings in .td files to 
the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-31 06:28:10 +00:00
Nate Begeman
0e0a20eb38 Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-29 22:48:09 +00:00
Nate Begeman
692433bc2d Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions. 
Behave identically to __qadd & __qsub RealView instruction intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-29 17:56:55 +00:00
Jim Grosbach
542f642684 ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109696 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 23:25:44 +00:00
Jim Grosbach
469bbdb597 Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction 
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 23:05:05 +00:00
Jim Grosbach
502e0aa628 Improve 64-subtraction of immediates when parts of the immediate can fit 
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 17:45:16 +00:00
Evan Cheng
218977b53e Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 19:27:42 +00:00
Dale Johannesen
7835f1fcdb Changes to ARM tail calls, mostly cosmetic. 
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 01:18:23 +00:00
Jim Grosbach
a967d1121a LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:27 +00:00
Dale Johannesen
b0ccb757b3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:21:49 +00:00
Evan Cheng
6523d2ff7f Indentation and remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:11:54 +00:00
Dale Johannesen
51bd47edbc Fix ARM/Thumb reversal in previous attempt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:07:47 +00:00
Dale Johannesen
10416803c1 An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:28 +00:00
Dale Johannesen
df50d7e238 Last round of changes for ARM tail calls. 
Not turning them on yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:11 +00:00
Dale Johannesen
38d5f0441c Add file missing from previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:24:08 +00:00
Dale Johannesen
51e28e6348 Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 21:09:53 +00:00
Jim Grosbach
18f30e6f5e Clean up 80 column violations. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 21:53:11 +00:00
Jim Grosbach
bc213209bf correct retattr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 18:03:48 +00:00
Jim Grosbach
5caeff5c01 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:37:40 +00:00
Jim Grosbach
0798eddd07 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:49:24 +00:00
Jim Grosbach
23ff7cff52 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 20:22:18 +00:00
Jim Grosbach
5eb1951539 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:06:18 +00:00
Evan Cheng
27fa722311 Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 07:26:50 +00:00
Evan Cheng
5fd1c9be2d Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:07:03 +00:00
Evan Cheng
ea420b20d4 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 01:52:25 +00:00
Anton Korobeynikov
bd91ea53f8 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 09:15:36 +00:00
Anton Korobeynikov
418d1d954d "trap" pseudo-op turned out to be apple-local. 
Temporary emit it as raw bytes until it will be added to binutils as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 17:19:20 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 23:44:43 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:44:35 +00:00
Johnny Chen
2fb10f17d8 Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed 
to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 19:33:23 +00:00
Johnny Chen
1cfa094562 Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not 
am2offset.  Modified the instruction table entry and added a new test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 23:12:47 +00:00
Bob Wilson
ec80e2693a Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets 
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-09 20:41:18 +00:00
Jim Grosbach
2676737e5e Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:31:46 +00:00
Bob Wilson
226036ee73 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:13:40 +00:00
Johnny Chen
e86425f224 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 23:50:27 +00:00
Bob Wilson
76a312b7d1 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 22:51:32 +00:00
Chris Lattner
60e9eac357 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:33:51 +00:00
Anton Korobeynikov
341ab138fb Get rid of target-specific fp <-> int nodes when still I'm here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 22:35:45 +00:00
Bob Wilson
a43e6bf690 Revert 98683. It is breaking something in the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 23:01:13 +00:00
Bob Wilson
bb6c77e6b9 Remove redundant writeback flag from ARM address mode 6. Also remove the 
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 21:44:40 +00:00
Johnny Chen
2b0272e43d Disambiguate the *_UPD and * variants by specifying the writeback flag as 1. 
This is for the disassembly work.

There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 21:25:05 +00:00
Bob Wilson
ab3460519e Remove the writeback flag from ARM's address mode 4. Now that we have separate 
instructions for ld/st with writeback, the flag is completely redundant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 17:46:45 +00:00
Bob Wilson
bffb5b39be Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new 
base register updating load/store-multiple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 07:34:35 +00:00
Bob Wilson
815baebe1c Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 01:08:20 +00:00
Johnny Chen
dd0f3cf189 Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero 
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-10 18:59:38 +00:00
Johnny Chen
a2c618a0f0 MSR (Move to Special Register from ARM core register) requires a mask to specify 
what fields of the CPSR or SPSR are affected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-09 21:39:34 +00:00
Chris Lattner
d10a53d5a1 fix a bunch of partially ambiguous patterns on ARM. As an 
example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-08 18:51:21 +00:00
Anton Korobeynikov
ce7bf1c55f Initial bits of ARMv4-only support. 
Patch by John Tytgat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-06 19:39:36 +00:00
Johnny Chen
7cfa51ebd8 Change some asm shift opcode strings to lowercase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97567 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-02 17:03:18 +00:00
Johnny Chen
ad4df4c0da Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W 
bit should be set to 0 instead of 1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-01 19:22:00 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 23:47:46 +00:00
Johnny Chen
adc7733a64 Added the follwoing 32-bit Thumb instructions for disassembly only: 
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-26 22:04:29 +00:00
Jim Grosbach
4642ad3af1 Updated version of r96634 (which was reverted due to failing 176.gcc and 
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-22 23:10:38 +00:00
Johnny Chen
2ec5e49a2b Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, 
for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-22 21:50:40 +00:00
Johnny Chen
667d127b0b Added a bunch of instructions for disassembly only: 
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-22 18:50:54 +00:00
Johnny Chen
b92a23fcfc Undo r96654. The printing of ARM shift instructions in canonical forms can be 
handled in ARMInstPrinter.cpp.

And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96719 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-21 04:42:01 +00:00
Johnny Chen
8f5e04098f Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints 
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.

DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	asr	r0, r0, #1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-19 02:12:06 +00:00
Johnny Chen
39a4bb3527 Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96619 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-18 22:31:18 +00:00
Johnny Chen
adb561d4e0 Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors 
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-18 03:27:42 +00:00
Johnny Chen
fd6037d613 Added for disassembly only the variants of DMB, DSB, and ISB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-18 00:19:08 +00:00
Johnny Chen
b943627915 Added CLREX (Clear-Exclusive) for disassembly only. 
A8.6.30


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96523 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-17 22:37:58 +00:00
Johnny Chen
fb566795c6 Added RFE for disassembly only. 
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-17 21:39:10 +00:00
Johnny Chen
b2503c096f Added BFI for disassembly only. 
A8.6.18  BFI - Bitfield insert (Encoding A1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-17 06:31:48 +00:00
Johnny Chen
0296f3e504 Add SMC (Secure Monitor Call) system instruction for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:59:54 +00:00
Jim Grosbach
80dc116ce3 80 column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:23:02 +00:00
Jim Grosbach
6417171026 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:07:46 +00:00
Jim Grosbach
39be8fcfdc Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but 
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 20:42:29 +00:00
Jim Grosbach
cd862b19b8 Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 20:35:59 +00:00
Jim Grosbach
0a145f3d90 First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates. 
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 20:17:57 +00:00
Johnny Chen
64dfb7835d Added for disassembly the following instructions: 
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 20:04:27 +00:00
Bob Wilson
1665b0a224 Fix pr6111: Avoid using the LR register for the target address of an indirect 
branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 17:24:15 +00:00
Bob Wilson
7dc9747e89 Put repeated empty pattern into the AQI instruction class. 
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96297 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-15 23:43:47 +00:00
Johnny Chen
2faf3919d4 Try to factorize the specification of saturating add/subtract operations a bit, 
as suggested by Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96153 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-14 06:32:20 +00:00
Johnny Chen
a1e7621510 Add SETEND and BXJ instructions for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96075 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 02:51:09 +00:00
Johnny Chen
08b85f371e Added a bunch of saturating add/subtract instructions for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 01:21:01 +00:00
Johnny Chen
f4d81051ff Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:53:19 +00:00
Johnny Chen
83498e55e2 Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96019 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 21:59:23 +00:00
Johnny Chen
b3e1bf54b2 Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 20:48:24 +00:00
Johnny Chen
b98e160318 Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 18:55:33 +00:00
Johnny Chen
906d57ffe8 Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, 
MRRC, MRRc2.  For disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:44:23 +00:00
Johnny Chen
e4c7f0f6ec Added LDRT/LDRBT/STRT/STRBT for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 20:31:08 +00:00
Johnny Chen
c6f7b27fda Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 18:12:29 +00:00
Johnny Chen
ba6e033f4f Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21 
as the "Permanently UNDEFINED" instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95873 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 17:14:31 +00:00
Johnny Chen
85d5a89f8d Added NOP, DBG, SVC to the instruction table for disassembly purpose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-10 18:02:25 +00:00
Jim Grosbach
a87ded2695 tighten up eh.setjmp sequence a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-08 23:22:00 +00:00
Johnny Chen
92e63d817f MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a 
Rn operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95025 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-01 23:06:04 +00:00
Johnny Chen
48d5ccf86a For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-31 11:22:28 +00:00
Jim Grosbach
d5d2baec26 Fix PR5694. The CMN instructions set the flags differently from CMP, so they 
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-22 00:08:13 +00:00
Evan Cheng
f609bb8466 Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-19 00:44:15 +00:00
Jim Grosbach
3482c8003a Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-18 19:58:49 +00:00
Dan Gohman
eeb3a00b84 Change SelectCode's argument from SDValue to SDNode *, to make it more 
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 01:24:18 +00:00
Jim Grosbach
587b072f23 Mark STREX* as earlyclobber for the success result register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 19:44:06 +00:00
Johnny Chen
ec689151f2 Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate 
between BR_JTr and STREXD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91339 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:51:34 +00:00
Jim Grosbach
80dd125e17 v6 sync insn copy/paste error 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91333 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:33:32 +00:00
Jim Grosbach
7c03dbd8ed Add ARMv6 memory and sync barrier instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:24:16 +00:00
Johnny Chen
c474796438 Fixed encoding bits typo of ldrexd/strexd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91327 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:01:46 +00:00
Jim Grosbach
a623f5a58d correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 19:24:11 +00:00
Jim Grosbach
015d3b5704 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91307 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 18:36:32 +00:00
Jim Grosbach
f6b2862e81 ARM memory barrier instructions are not predicable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91305 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 18:31:20 +00:00
Jim Grosbach
d7d72d66b7 add ldrexd/strexd instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91284 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 17:02:55 +00:00
Jim Grosbach
e801dc4a7b Framework for atomic binary operations. The emitter for the pseudo instructions 
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 01:40:06 +00:00
Jim Grosbach
c8f9e4fdc5 memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91150 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 20:29:53 +00:00
Jim Grosbach
66869104dd Update properties. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91140 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 18:52:41 +00:00
Jim Grosbach
5278eb802f Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 01:42:04 +00:00
Jim Grosbach
cbd77d2cb1 Add instruction encoding for DMB/DSB 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91053 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-10 18:35:32 +00:00
Jim Grosbach
3728e96a6c Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91003 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-10 00:11:09 +00:00
Bob Wilson
afa1df467b Fix some more ARM unified syntax warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90141 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-30 17:47:19 +00:00
Anton Korobeynikov
5cdc3a949a Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-24 00:44:37 +00:00
Dan Gohman
735afe14ee Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. 
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 23:20:51 +00:00
Jim Grosbach
15e6ef886d fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89694 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 20:35:53 +00:00
Evan Cheng
4aedb61d03 Remat VLDRD from constpool. Clean up some instruction property specifications. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 19:57:15 +00:00
Bob Wilson
a3003004aa Fix a few places that were missed when we converted to unified syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89214 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-18 18:10:35 +00:00
Johnny Chen
a9ea9ec194 Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to 
distinguish between them and the more generic instructions (add, mov, and ldr).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89108 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 17:17:50 +00:00
Johnny Chen
9d52e8db8a Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to 
0b1110 (ALways).  This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89000 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 23:57:56 +00:00