Anton Korobeynikov
2e1da9fea4
64-bit FP loads & stores operate on both NEON and VFP pipelines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:11:06 +00:00
Jim Grosbach
8cd0a8cb82
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
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them for scalar floating point operations for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:57:36 +00:00
Jim Grosbach
07d236ba88
Update test to be more explicit about what instruction sequences are expected for each operation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85689 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 21:52:58 +00:00
Jim Grosbach
bcf2f2c159
Expand 64-bit logical shift right inline
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304
Expand 64-bit arithmetic shift right inline
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe
Expand 64 bit left shift inline rather than using the libcall. For now, this
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is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 19:38:01 +00:00
Benjamin Kramer
823bdbc770
Add missing colons for FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85674 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 19:22:24 +00:00
Jim Grosbach
4a26092248
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 19:06:53 +00:00
Rafael Espindola
c1382b745f
This fixes functions like
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void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30 14:33:14 +00:00
Evan Cheng
39382427f1
Use fconsts and fconstd to materialize small fp constants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 01:44:26 +00:00
Rafael Espindola
2bda533e1c
Add missing testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85266 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 17:59:03 +00:00
Bob Wilson
b9350315d2
Fix the rest of the ARM failures by converting them to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85208 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 06:16:45 +00:00
Bob Wilson
13e80bdb71
Fix some more failures by converting to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 05:50:28 +00:00
Bob Wilson
8bb080e71b
Convert to FileCheck, fixing failure due to tab change in the process.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85204 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 05:30:47 +00:00
Evan Cheng
cc7a5b91de
Update tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85050 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 07:53:48 +00:00
Bob Wilson
bac6ed4ba4
Revert 84843. Evan, this was breaking some of the if-conversion tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 16:52:21 +00:00
Evan Cheng
87689d3b70
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 06:48:32 +00:00
Evan Cheng
8000c6c535
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 00:40:00 +00:00
Evan Cheng
2095659a85
Match more patterns to movt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 08:15:52 +00:00
Anton Korobeynikov
2bcf60a9cc
Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign)
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transform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84683 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 21:37:45 +00:00
Chris Lattner
7bf4bc5a1d
convert to filecheck syntax and make a lot more aggressive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:27:56 +00:00
Chris Lattner
baa989ed6e
rename test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84515 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 18:18:07 +00:00
Evan Cheng
d3dd50fec0
Enable post-alloc scheduling for all ARM variants except for Thumb1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:11:08 +00:00
Bob Wilson
765cc0b9d5
Revise ARM inline assembly memory operands to require the memory address to
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be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 20:50:28 +00:00
Sandeep Patel
47eedaa8fa
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 18:59:48 +00:00
Benjamin Kramer
90869455b5
Eliminate some redundant llvm-as calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83837 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 09:31:55 +00:00
Dan Gohman
cda49a0b29
Update this test; the code is the same but it gets counted as one
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fewer remat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 23:31:04 +00:00
Bob Wilson
83815aeb29
Merge a bunch of NEON tests into larger files so they run faster.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83667 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 20:20:54 +00:00
Bob Wilson
e8e72be33a
Convert some ARM tests with lots of greps to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83651 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 17:20:46 +00:00
Bob Wilson
8795070d50
Commit one last NEON test to use FileCheck. That's all of them now!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83617 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 05:31:56 +00:00
Bob Wilson
0305dd745e
Convert more NEON tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83616 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 05:14:48 +00:00
Bob Wilson
5631139a69
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 00:01:36 +00:00
Bob Wilson
8cdb269686
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 23:51:31 +00:00
Bob Wilson
c5c6edb74f
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 23:38:24 +00:00
Bob Wilson
4cf0189d5a
Convert more NEON tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83595 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 23:33:03 +00:00
Bob Wilson
62e053e5a1
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 22:53:57 +00:00
Bob Wilson
5d78275493
Convert more NEON tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83587 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 22:33:53 +00:00
Bob Wilson
0bf7d998b4
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 22:27:33 +00:00
Anton Korobeynikov
632606c724
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 20:43:22 +00:00
Bob Wilson
30aea9d96e
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 18:56:10 +00:00
Bob Wilson
67a6103a34
Convert more NEON tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 06:02:10 +00:00
Bob Wilson
deb3141cf5
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 05:18:18 +00:00
Bob Wilson
5adf60c03b
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 00:21:01 +00:00
Bob Wilson
0ea38bb939
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:54:04 +00:00
Bob Wilson
fe27c512e8
Convert more NEON tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:47:21 +00:00
Bob Wilson
c67160c010
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:57:01 +00:00
Bob Wilson
b2cae81ac4
Convert more NEON tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83497 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:30:19 +00:00
Bob Wilson
99c372e723
Convert test to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83487 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:51:42 +00:00
Bob Wilson
63c9063434
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:30:08 +00:00
Bob Wilson
d285575f87
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 18:47:39 +00:00
Bob Wilson
7708c22baa
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 18:09:32 +00:00
Bob Wilson
ff8952e8a9
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 17:24:55 +00:00
Bob Wilson
967f87578d
Add tests for vld2 of 128-bit vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 17:19:13 +00:00
Bob Wilson
ec1d81c389
Update NEON struct names to match llvm-gcc changes.
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(This is not required for correctness but might help with sanity.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83415 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-06 21:16:19 +00:00
Evan Cheng
3825ce8c24
Fix tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83241 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 06:53:57 +00:00
Evan Cheng
62a1b5db44
Move load / store multiple before post-alloc scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 04:57:15 +00:00
David Goodwin
9843a93e83
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00
David Goodwin
471850ab84
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 21:46:35 +00:00
David Goodwin
0dad89fa94
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 00:10:16 +00:00
David Goodwin
8971c4a30e
Post-RA regressions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83075 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 17:10:26 +00:00
Evan Cheng
fa1be5d991
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 07:07:30 +00:00
Evan Cheng
0e6b590b91
Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of
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physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.
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2009-09-28 05:28:43 +00:00
Anton Korobeynikov
6a2fa325c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
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This should be better than single load from constpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 23:52:58 +00:00
Evan Cheng
2fcf85efe7
Remove this test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82869 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 18:51:37 +00:00
Daniel Dunbar
c8e9314a41
"Update" tests for -disable-if-conversion removal. I think branch.ll should just
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be removed, but I XFAIL'd it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 05:29:36 +00:00
Evan Cheng
9fde6ca2c7
Convert test to filecheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:41:17 +00:00
Evan Cheng
483011018e
Flip -disable-post-RA-scheduler to -post-RA-scheduler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 21:38:11 +00:00
Dan Gohman
c76909abfe
Improve MachineMemOperand handling.
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- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 20:36:54 +00:00
Bob Wilson
0035f9c3b9
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
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For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
Bob Wilson
08ae76c042
Convert to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82710 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 20:23:02 +00:00
Evan Cheng
393e277ecd
Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.
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LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g.
BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ...
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%reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool]
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%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>
When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose
%reg1031<def> = FOO <cp#1>, %D0<imp-def>
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%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>
When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness.
Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82677 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 02:27:09 +00:00
Evan Cheng
296925dc16
Fix PR5024. LiveVariables physical register defs should *commit* only after all
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of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82616 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-23 06:28:31 +00:00
Evan Cheng
60c7df2c93
Fix PR5024. LiveVariables::FindLastPartialDef should return a set of sub-registers that were defined by the last partial def, not just a single sub-register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-22 08:34:46 +00:00
Evan Cheng
014d624a28
Fix a pasto. Also simplify for Bill's benefit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82505 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-22 01:48:19 +00:00
Evan Cheng
cf985a9545
Clean up spill weight computation. Also some changes to give loop induction
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variable increment / decrement slighter high priority.
This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 21:12:25 +00:00
Evan Cheng
b0f5973bee
Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 04:32:32 +00:00
Bob Wilson
9b379dc526
Convert more tests to FileCheck.
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2009-09-15 20:58:02 +00:00
Sandeep Patel
85111a9c07
Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81878 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 17:53:11 +00:00
Anton Korobeynikov
20c35ec427
Define proper subreg sets for arm - this should fix bunch of subtle problems
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with subreg - superreg mapping and also fix PR4965.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-13 00:59:43 +00:00
Dan Gohman
55a7877cac
Remove an unnecessary -f.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81546 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:41:06 +00:00
Dan Gohman
b7c0b246da
Convert more tests to avoid llvm-as.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:36:27 +00:00
Bob Wilson
92ad363f58
Don't swap the operands of a subtraction when trying to create a
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post-decrement load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10 22:09:31 +00:00
Bob Wilson
cd3b9a4f17
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
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See the bug report for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 23:14:54 +00:00
Dan Gohman
fce288fc91
Eliminate more uses of llvm-as and llvm-dis.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Anton Korobeynikov
2ba62ef7f2
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08 22:51:43 +00:00
Anton Korobeynikov
6ca0b9e722
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
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makes the code faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08 15:22:32 +00:00
Daniel Dunbar
e57dc10985
Remove stale greps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-04 05:07:52 +00:00
Bob Wilson
6aa9775888
Convert tests to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80983 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-04 04:07:19 +00:00
Bob Wilson
5ffe917f72
Convert a test to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80975 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-04 00:32:31 +00:00
Evan Cheng
63476a8040
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-03 07:04:02 +00:00
Anton Korobeynikov
69d1c1aebf
More missed vdup patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80838 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-02 21:21:28 +00:00
Bob Wilson
8a3198b770
Add support for generating code for vst{234}lane intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 18:51:56 +00:00
Bob Wilson
2af658fcc0
Fix incorrect declarations of intrinsics in this test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80705 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 18:50:43 +00:00
Bob Wilson
c011005912
Add test for vld{234}_lane instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80658 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 04:27:10 +00:00
Bob Wilson
71124f698b
Fix pr4843: When an instruction has multiple destination registers that are
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tied to different source registers, the TwoAddressInstructionPass needs to
be smarter. Change it to check before replacing a source register whether
that source register is tied to a different destination register, and if so,
defer handling it until a subsequent iteration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80654 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 04:18:40 +00:00
Jim Grosbach
46e0faa81c
SJLJ is arm/darwin only for now. force the triple for the test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80651 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 02:34:49 +00:00
Jim Grosbach
3fb2b1ede3
Clean up LSDA name generation and use for SJLJ exception handling. This
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makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01 01:57:56 +00:00
David Goodwin
a3251db21a
Don't mark a register live at an undef use.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80621 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-31 20:47:02 +00:00
Anton Korobeynikov
d91aafd005
Add missed pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-30 19:06:39 +00:00
Anton Korobeynikov
b00c03bb35
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
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Remove the assertion and generalize the code for ARM NEON stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80498 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-30 17:14:54 +00:00
Anton Korobeynikov
71624cc786
Do not assert on too wide splats we don't support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80409 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-29 00:08:18 +00:00
Anton Korobeynikov
2324bdc1ee
Add missed extract_element pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80408 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 23:41:26 +00:00
Evan Cheng
e4e4ed3b56
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 23:18:09 +00:00
Evan Cheng
0e87e23f6e
v4, v5 does not support sxtb / sxth.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 00:31:43 +00:00
Anton Korobeynikov
2a82a7aa60
scalar_to_vector is fully legal now (implemented as subreg accesses)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27 16:04:47 +00:00
Anton Korobeynikov
3a0f1b3ed0
Ok, sometimes it's profitable to turn scalar_to_vector stuff into subreg access.
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Add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80246 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27 14:51:42 +00:00
Evan Cheng
cdbb3f5d33
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27 01:23:50 +00:00
Bob Wilson
e4696cf03d
Convert some more Neon tests to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80120 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-26 18:11:50 +00:00
Anton Korobeynikov
1cb852b0ea
Expand scalar_to_vector - we don't have any isel logic for it now
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80107 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-26 16:26:09 +00:00
David Goodwin
88a589c4b3
Fixup register kills after scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-25 17:03:05 +00:00
Dan Gohman
fea1dd0804
Remove obsolete -f flags.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-25 15:38:29 +00:00
Dale Johannesen
a3f2b21aff
Split test into 3.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79926 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24 17:51:19 +00:00
Eli Friedman
ce392eb3ea
Make x86 test actually test x86 code generation. Fix the
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construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22 03:13:10 +00:00
Bob Wilson
b6c68f9e74
Use CHECK-NEXT to make sure we're only getting one copy of each shuffle
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instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79702 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22 00:13:23 +00:00
Bob Wilson
c692cb77aa
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
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now using shuffles instead of intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21 20:54:19 +00:00
Bob Wilson
3b83287c4e
Add some tests for vext.16 and vext.32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21 16:35:24 +00:00
Bob Wilson
d4b4cf524b
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
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vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21 00:01:42 +00:00
Bob Wilson
de95c1b88b
Add support for Neon VEXT (vector extract) shuffles.
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This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 17:03:43 +00:00
Bill Wendling
af56634058
Reapply r79127. It was fixed by d0k.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:21:19 +00:00
Bill Wendling
f865ea85bd
Revert r79127. It was causing compilation errors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:14:01 +00:00
Evan Cheng
088880cb19
Change allowsUnalignedMemoryAccesses to take type argument since some targets
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
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2009-08-15 19:23:44 +00:00
Jakob Stoklund Olesen
16b794d25a
Refine EarlyClobber assert in register scavenger.
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It is legal for an inline asm operand to use an earlyclobber register if the
use operand is tied to the earlyclobber operand. The issue is discussed here:
http://gcc.gnu.org/ml/gcc/1999-04n/msg00431.html
We should perhaps let only the machine code verifier worry about these finer
details. EarlyClobber operands are not really interesting to the scavenger.
This fixes PR4528 for the third time.
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2009-08-15 18:16:58 +00:00
Jakob Stoklund Olesen
d62c9a697b
Don't setCalleeSavedInfoValid() until spills are interted.
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In a naked function, the flag is never set and getPristineRegs() returns an
empty list. That means naked functions are able to clobber callee saved
registers, but that is the whole point of naked functions.
This fixes PR4716.
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2009-08-15 13:10:46 +00:00
Bob Wilson
114a266c94
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 20:51:55 +00:00
Chris Lattner
d3fe75e2bf
now that these are in file-check format, we can merge them together
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into one bigger test (which runs faster)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 15:54:17 +00:00
Bob Wilson
d1fa3f58a0
Convert more Neon tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78648 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 05:51:19 +00:00
Bob Wilson
b0abb4dc42
Use vAny type to get rid of Neon intrinsics that differed only in whether
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the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 05:39:44 +00:00
Bob Wilson
f24bd401eb
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 01:15:26 +00:00
David Goodwin
c5cfea3c02
Use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 23:14:14 +00:00
David Goodwin
4980187dd9
Use FileCheck... its good for you...
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2009-08-10 23:06:57 +00:00
David Goodwin
af37f341df
Fix test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78611 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:58:08 +00:00
David Goodwin
aeb66fe54e
Fix test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78606 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:31:04 +00:00
David Goodwin
338268c67f
Use NEON for single-precision int<->FP conversions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78604 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:17:39 +00:00
Dan Gohman
5743a3f201
Add nounwind keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 16:48:40 +00:00
Chris Lattner
ff4bc460c5
Make the big switch: Change MCSectionMachO to represent a section *semantically*
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instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
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2009-08-10 01:39:42 +00:00
Bob Wilson
22cd2547fe
Add tests for Neon VZIP and VUZP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78529 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 06:48:29 +00:00
Bob Wilson
4861fd5d0c
Add a test for Neon VTRN instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78528 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 06:30:46 +00:00
Bob Wilson
e9ce5d5ef9
Convert more Neon tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78433 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:45:02 +00:00
David Goodwin
767a952a6f
Make NEON single-precision FP support the default for cortex-a8 (again).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:32:33 +00:00
Anton Korobeynikov
32a1b25781
2 more vdup.32 cases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 22:36:50 +00:00
Bob Wilson
b36ec86c01
Implement Neon VST[234] operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 18:47:44 +00:00
Bob Wilson
004f7c7049
Fix incorrect intrinsic declarations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 18:46:26 +00:00
Bob Wilson
9b600c60af
Add tests for new NEON vld instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 00:38:31 +00:00
Bob Wilson
3765d0f1a7
Convert more Neon tests to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78261 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 23:51:20 +00:00
Anton Korobeynikov
567d14f07c
Missed pieces for ARM HardFP ABI.
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Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78225 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 19:04:42 +00:00
Bob Wilson
42cdcb9a86
Convert more Neon tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78111 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 22:01:41 +00:00
Bob Wilson
ad5312ad70
Convert a few Neon tests to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78108 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:33:22 +00:00
Jakob Stoklund Olesen
323e7d32ab
Clean up the handling of two-address operands in RegScavenger.
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This fixes PR4528.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78107 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:30:30 +00:00
David Goodwin
53e4471adc
Add NEON single-precision FP support for fabs and fneg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 20:39:05 +00:00
David Goodwin
b84f3d427c
Match common pattern for FNMAC. Add NEON SP support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 18:44:29 +00:00
David Goodwin
831b500ec1
Improve tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 18:11:59 +00:00
David Goodwin
42a83f2d15
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 17:53:06 +00:00
Evan Cheng
7d35249e89
Fix PR4528. This scavenger assertion is too strict. The two-address value is
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killed by another operand.
There is probably a better fix. Either 1) scavenger can look at other operands, or
2) livevariables can be smarter about kill markers. Patches welcome.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78072 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 16:52:44 +00:00
Bob Wilson
a6d658620f
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
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Add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 20:36:38 +00:00
Jakob Stoklund Olesen
980daea857
Fix Bug 4657: register scavenger asserts with subreg lowering
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When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.
When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.
Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.
Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77989 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 20:08:18 +00:00
Chris Lattner
f9f1adbcbb
switch to filecheck format
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77841 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 00:32:26 +00:00
Evan Cheng
d600522608
Add VFP3 D registers to the DPR register class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 23:03:41 +00:00
Bob Wilson
b7d0c90c44
Change Neon VLDn intrinsics to return multiple values instead of really
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wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 16:39:22 +00:00
Bob Wilson
8bb9e48752
Add support for ARM Neon VREV instructions.
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Patch by Anton Korzh, with some modifications from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26 00:39:34 +00:00
Evan Cheng
eadf04992a
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 22:03:29 +00:00
Evan Cheng
1e0c1588b1
Ignore undef uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76799 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 21:51:42 +00:00
Evan Cheng
af9e7a7c20
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 00:31:12 +00:00
Evan Cheng
87faa1fc67
Forgot this test earlier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 21:46:42 +00:00
Chris Lattner
4fb63d088b
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
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symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75737 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 04:12:33 +00:00
Evan Cheng
9c06178e35
Remove a bogus assertion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 00:23:48 +00:00
Bob Wilson
9b4b00ad43
Handle 'a' modifier on inline assembly operands.
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This is part of the fix for pr4521.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 23:54:51 +00:00
Lang Hames
ffd1326ff8
Improved tracking of value number kills. VN kills are now represented
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as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.
A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test
condition has been updated to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75097 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 03:57:02 +00:00
Bob Wilson
2ed334694f
Implement NEON vst1 instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 20:32:02 +00:00
Bob Wilson
205a5ca6cf
Implement NEON vld1 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 18:11:30 +00:00
Chris Lattner
b2773e1ada
Change these tests to use [fi]cmp+sext instead of v[fi]cmp. No
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functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74979 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 00:46:57 +00:00
Evan Cheng
36a0aebac2
Add bfc to armv6t2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-06 22:23:46 +00:00
Evan Cheng
edcbada3d0
Added ARM::mls for armv6t2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-06 22:05:45 +00:00
Evan Cheng
d27c9fc403
Add thumb2 sign / zero extend with rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 01:43:10 +00:00
Evan Cheng
498c2903e2
CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 08:29:08 +00:00
Evan Cheng
459a7c6b6a
Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
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Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 08:19:36 +00:00
Evan Cheng
2578ba26e7
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 01:59:31 +00:00
Evan Cheng
50564ebc9e
Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 09:19:42 +00:00
Evan Cheng
4784f1fc73
Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
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The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.
This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 08:49:04 +00:00
Evan Cheng
055b0310f8
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 07:51:04 +00:00
David Goodwin
caffbd7b01
ORN and BIC tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74289 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 16:20:06 +00:00
Evan Cheng
6677f51127
Fix tests: Count -> count.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74282 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 07:05:57 +00:00
Evan Cheng
c0ad80fd9e
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74276 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 05:59:16 +00:00
Evan Cheng
6267422318
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 23:34:10 +00:00
Evan Cheng
1e249e3705
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 20:59:23 +00:00
Evan Cheng
9f76ed5127
Move thumb and thumb2 tests into separate directories.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74068 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 06:36:07 +00:00
Evan Cheng
a67efd1226
Proper patterns for thumb2 shift and rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 19:39:13 +00:00
Bob Wilson
5bafff36c7
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 23:27:02 +00:00
Evan Cheng
524961e57f
It's coalescer, not coaleser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 21:09:17 +00:00
Bob Wilson
54fc124d72
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 21:01:46 +00:00
Evan Cheng
81909b7423
Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 20:49:32 +00:00
Evan Cheng
8dcbbdd00e
hasFP should return true if frame address is taken.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 18:38:48 +00:00
Evan Cheng
694f6c81e8
Fix PR4419: handle defs of partial uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73816 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 04:34:51 +00:00
Evan Cheng
ae69a2a12b
Enable arm pre-allocation load / store multiple optimization pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 23:17:27 +00:00
Eli Friedman
6b7bb42c36
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:43:08 +00:00
Anton Korobeynikov
52237119a9
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 18:13:58 +00:00
Anton Korobeynikov
a4e968cb0e
Make the test target-neutral
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73547 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 20:25:25 +00:00
Anton Korobeynikov
2932795309
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 18:49:08 +00:00
Evan Cheng
67fcf56ac4
If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
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TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 07:12:58 +00:00
Evan Cheng
2077e18caf
ifcvt should ignore cfg where true and false successors are the same.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:24:34 +00:00
Evan Cheng
358dec5180
Part 1.
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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
e7d6df7353
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
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consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 09:12:55 +00:00
Evan Cheng
4a274e573d
If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 21:34:26 +00:00
Evan Cheng
cd799b99cb
Mark some pattern-less instructions as neverHasSideEffects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 20:46:18 +00:00
Anton Korobeynikov
f194b0edc9
Add testcase for register scanveger assertion fix in r72755
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(double def due to livevars)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:54:15 +00:00
Evan Cheng
925492279a
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 19:08:58 +00:00
Dan Gohman
ae3a0be92e
Split the Add, Sub, and Mul instruction opcodes into separate
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integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
Evan Cheng
cd0c4ac7fb
A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72888 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 20:25:48 +00:00
Evan Cheng
1488326156
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 01:15:28 +00:00
Evan Cheng
70fd60bd57
Temporarily revert 72756 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 07:40:47 +00:00
Evan Cheng
9d5fb981b0
Fold preceding / trailing base inc / dec into the single load / store as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 06:14:58 +00:00
Bob Wilson
04746eae49
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
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the stack. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 10:02:36 +00:00
Bob Wilson
224c244f56
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19 05:53:42 +00:00
Dan Gohman
04623272d2
Add nounwind to a few tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18 15:16:49 +00:00
Bob Wilson
74b0ccc577
Fix pr4195: When iterating through predecessor blocks, break out of the loop
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after finding the (unique) layout predecessor. Sometimes a block may be listed
more than once, and processing it more than once in this loop can lead to
inconsistent values for FtTBB/FtFBB, since the AnalyzeBranch method does not
clear these values. There's no point in continuing the loop regardless.
The testcase for this is reduced from the 2003-05-02-DependentPHI SingleSource
test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 03:48:10 +00:00
Bob Wilson
9d928c223f
Fix pr4100. Do not remove no-op copies when they are dead. The register
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scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.
Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move. Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move. The move ends up being a no-op, copying R3 to R3, so it is
deleted. But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.
Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
Regs have values:
Reloading %reg1028 into R3
Last use of R3[%reg1028], removing it from live set
Assigning R3 to %reg1025
Register R3 [%reg1025] is never used, removing it from live set
Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy. I couldn't see an easy way to do
either of those, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71196 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-07 23:47:03 +00:00
Evan Cheng
caab129cd1
Do not use register as base ptr of pre- and post- inc/dec load / store nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-06 18:25:01 +00:00
Dan Gohman
afc36a9520
Previously, RecursivelyDeleteDeadInstructions provided an option
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of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.
Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.
This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-02 18:29:22 +00:00
Bob Wilson
7eb793dd09
Rename file to have the correct suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 20:40:20 +00:00
Bob Wilson
1f595bb429
Use CallConvLower.h and TableGen descriptions of the calling conventions
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for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 19:07:39 +00:00
Dan Gohman
2d1be87ee4
Expand GEPs in ScalarEvolution expressions. SCEV expressions can now
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have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.
Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.
Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 03:18:22 +00:00
Dale Johannesen
442b7bfc80
Use the output of the asm so the optimizer won't
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delete it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 01:51:40 +00:00
Chris Lattner
dbf1e2b08b
move a target-specific test into its directory so it isn't run if you
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don't configure the ARM target in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-10 23:58:38 +00:00
Bob Wilson
d9df501704
Fix pr3954. The register scavenger asserts for inline assembly with
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register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 17:16:43 +00:00
Bob Wilson
83593a369b
Add testcase for PR3795.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 18:00:55 +00:00
Duncan Sands
3d0355b825
Soft float support for FREM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 16:20:57 +00:00
Duncan Sands
7beb1ec298
Soft float support for undef. Reported by Xerxes Rånby.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68607 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 13:33:37 +00:00
Bob Wilson
8f3434647d
Handle 'a' modifier in ARM inline assembly.
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Patch by Richard Pennington.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-06 21:46:51 +00:00
Bob Wilson
bf6396bed0
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
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assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-01 17:58:54 +00:00
Evan Cheng
f1c0ae9de5
Do not emit comments unless -asm-verbose.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24 00:17:40 +00:00
Chris Lattner
1285295e61
add no-unwind, remove duplicate run line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66775 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12 05:56:37 +00:00
Evan Cheng
6501153fc0
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-09 19:15:00 +00:00
Evan Cheng
4b1747430a
Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 04:02:49 +00:00
Evan Cheng
821b8560e7
If a MI uses the same register more than once, only mark one of them as 'kill'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08 03:58:35 +00:00
Evan Cheng
c8bb37a50a
Last commit accidentially deleted this code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65679 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-28 06:02:14 +00:00
Evan Cheng
04cf3e39f3
The last commit was overly conservative. It's ok to reuse value that's already marked livein.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65498 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:02:21 +00:00
Evan Cheng
58207f12ee
If a use operand is marked isKill, don't forget to add kill to its live interval as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 08:35:56 +00:00
Evan Cheng
bf18939180
A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-17 06:41:03 +00:00
Evan Cheng
8182347d70
Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64369 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12 08:59:45 +00:00
Evan Cheng
f0e366a929
Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-10 08:30:11 +00:00
Evan Cheng
8f0d99e463
Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 08:45:39 +00:00
Bill Wendling
7f51fd3ea9
Revert r63999. It was breaking self-hosting builds.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64062 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08 00:58:05 +00:00
Evan Cheng
c963b638c7
Enable machine sinking pass in non-fast mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63999 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 01:57:46 +00:00
Evan Cheng
c5d1a4ffd9
Turn on machine LICM in non-fast mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63855 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 08:46:33 +00:00
Rafael Espindola
bb46f52027
Add the private linkage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 20:18:42 +00:00
Evan Cheng
c3ccc1aaaf
Clean up some ARM GV asm printing out; minor fixes to match what gcc does.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60621 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-06 02:00:55 +00:00
Evan Cheng
d37c13cfd1
- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
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- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59697 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-20 02:32:35 +00:00
Evan Cheng
9c64bf3905
Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59559 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 22:28:38 +00:00
Evan Cheng
3eb22e835f
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04 22:19:55 +00:00
Evan Cheng
c7c77297e2
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04 19:57:48 +00:00
Devang Patel
2c9c3e7368
Implement function notes as function attributes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56716 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26 23:51:19 +00:00
Evan Cheng
870e4bef41
Unallocatable registers do not have live intervals.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56287 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 18:36:25 +00:00
Dan Gohman
5eb0cecbc5
Re-enable SelectionDAG CSE for calls. It matters in the case of
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libcalls, as in this testcase on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56226 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 19:46:03 +00:00
Evan Cheng
25f34a30d6
Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56199 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 06:28:41 +00:00
Evan Cheng
4b88702ac3
Legalizer was missing code that expand fpow to a libcall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56028 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-09 23:02:14 +00:00
Evan Cheng
711b6dce24
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54519 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-08 06:56:16 +00:00
Anton Korobeynikov
feac94b18d
Print section flags ok on platforms, which use '@' as comment string. Fix test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54460 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-07 09:55:06 +00:00
Owen Anderson
287b7b7ed7
This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54355 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-05 17:52:54 +00:00
Owen Anderson
3888aa0b7d
Remove the need for -disable-correct-folding from this test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54354 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-05 17:49:52 +00:00
Owen Anderson
2b85dc3544
Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54334 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-04 23:55:29 +00:00
Evan Cheng
d1b3da621b
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54004 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-25 00:55:17 +00:00
Duncan Sands
c3e26727c1
Softfloat support for FDIV. Patch by
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Richard Pennington.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53773 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-18 21:18:48 +00:00
Gabor Greif
f6cadc440c
sabre brings to my attention that the 'tr' suffix is also obsolete
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51349 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 21:00:03 +00:00
Gabor Greif
722243bd40
Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51328 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 19:52:04 +00:00
Evan Cheng
7a0f1851ec
More local spiller complexity!
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If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51306 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 08:13:21 +00:00
Evan Cheng
b0a6f62c9b
Don't spill dead def.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 08:10:37 +00:00
Evan Cheng
f870fbc554
If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49543 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-11 17:54:45 +00:00
Evan Cheng
b94d966716
New test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49514 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-10 23:49:09 +00:00
Evan Cheng
1dc7869025
1. IMPLICIT_DEF can *re-define* any register.
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2. Coalescer can now create an interesting situation where a register def can
reaches itself without being killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49246 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-05 01:27:09 +00:00
Evan Cheng
9845eb5b03
More soft fp fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49016 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-01 02:18:22 +00:00
Evan Cheng
110cf48752
Unbreak ARM / Thumb soft FP support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49012 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-01 01:50:16 +00:00
Evan Cheng
d68f47c6fd
Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48024 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 20:12:54 +00:00
Evan Cheng
433f6f62ca
Constant fold SIGN_EXTEND_INREG with ashr not lshr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47992 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-06 08:20:51 +00:00
Bill Wendling
65201f5a43
DCE'ed this testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47760 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-29 19:28:11 +00:00
Bill Wendling
97e3c01eb4
If we reload a virtual register that's already been assigned, we want to mark
...
that instruction as its "last use". This fixes PR1925.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47758 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-29 18:52:01 +00:00
Tanya Lattner
6263f94674
Remove llvm-upgrade.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47238 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-17 20:02:20 +00:00
Evan Cheng
b745e88bf0
It's PR1925, not PR1609.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46825 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-06 22:07:17 +00:00
Evan Cheng
2fc628d662
Fix a number of local register allocator issues: PR1609.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46821 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-06 19:16:53 +00:00
Chris Lattner
15c2351a93
Update this test. Due to dag combiner improvements, we now compile
...
f7/f11 to:
_f7:
eor r0, r0, #2 , 2 @ -2147483648
bx lr
_f11:
bic r0, r0, #2 , 2 @ -2147483648
bx lr
instead of:
_f7:
fmsr s0, r0
fnegs s0, s0
fmrs r0, s0
bx lr
_f11:
fmsr s0, r0
fabss s0, s0
fmrs r0, s0
bx lr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46423 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-27 23:26:37 +00:00
Evan Cheng
e3c1cfb181
Remove xfail. This is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45254 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-20 02:25:21 +00:00
Evan Cheng
33faddc35d
Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44660 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-06 08:54:31 +00:00
Evan Cheng
5ef3a04b54
Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-06 00:01:56 +00:00
Evan Cheng
213ee902cc
Update tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44435 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-29 10:03:54 +00:00
Chris Lattner
2adcf10a80
update this test after the fmrrd fix
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44393 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-28 05:27:07 +00:00
Tanya Lattner
727842e9d7
Fix bug in regression tests that ignored stderr output in RUN lines. Updated tests and fixed broken run lines.
...
XFAILed 3 arm regressions (will file bugs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44389 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-28 04:57:00 +00:00
Chris Lattner
a5d4a4e33e
commit testcase I forgot to svn add.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44383 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-27 22:43:37 +00:00
Lauro Ramos Venancio
e0cb36b9fb
[ARM] Implement __builtin_thread_pointer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-08 17:20:05 +00:00
Lauro Ramos Venancio
8699a97a2e
[ARM] Fix code generation for:
...
static __thread struct {
int a;
int b;
} teste = {0, 0};
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43722 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-05 18:33:37 +00:00
Evan Cheng
4102eb57bb
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-22 22:11:27 +00:00
Chris Lattner
f8f7cf3987
new testcase
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42953 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-13 06:56:18 +00:00
Evan Cheng
b7c8017208
Disable if-conversion for this test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42170 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-20 18:06:22 +00:00
Evan Cheng
4226689f44
-enable-arm-if-conversion is gone.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42169 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-20 18:03:23 +00:00
Dale Johannesen
c2ec2baf3d
Change all floating constants that are not exactly
...
representable to use hex format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41722 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-05 17:50:36 +00:00
Duncan Sands
e9685143f4
Testcases for PR1628.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41719 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-05 11:53:04 +00:00
Lauro Ramos Venancio
c90f08936d
Implement FPOWI ExpandOp.
...
Fix PR1287.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41112 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-15 22:13:27 +00:00
Evan Cheng
77f8b72af2
Test case for PR1609.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41110 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-15 20:30:10 +00:00
Dan Gohman
64d8e1b9a7
This test used "wc | grep ..."; convert it to use the count script.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41101 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-15 13:55:47 +00:00
Dan Gohman
43c3db37f6
Convert tests using "grep -c ... | grep ..." to use the count script.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41100 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-15 13:49:33 +00:00
Dan Gohman
28beeeac4d
Convert tests using "| wc -l | grep ..." to use the count script.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41097 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-15 13:36:28 +00:00
Evan Cheng
3b1d3068c3
New test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41087 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-14 23:34:50 +00:00
Lauro Ramos Venancio
f3c13c82e3
Expand unaligned loads/stores when the target doesn't support them. (PR1548)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40682 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 19:34:21 +00:00
Reid Spencer
9445e9aaa0
For PR1553:
...
Change the keywords for the zext and sext parameter attributes to be
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40069 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 23:13:04 +00:00
Dan Gohman
2a69a04afa
Add explicit triples to these tests so that llc behaves as expected on
...
non-Apple hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38455 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 13:42:32 +00:00
John Criswell
e644ef7b09
Convert .cvsignore files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-29 16:35:07 +00:00
Dan Gohman
10a7aa6dea
Fix an assertion failure in legalizing bitcast operators on targets where
...
vectors are split down to single elements as part of legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37785 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-29 00:09:08 +00:00
Evan Cheng
52974eb49a
Fix tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37693 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-21 18:22:42 +00:00
Evan Cheng
53855ca95c
New tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37686 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-21 07:40:00 +00:00
Evan Cheng
60c916bc72
Added some if-conversion tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37672 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-20 18:26:15 +00:00
Lauro Ramos Venancio
4f3485c0da
Add a test for PR1424.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37372 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-31 18:36:07 +00:00
Evan Cheng
51d2d0780f
Add a new test case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37317 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-24 02:31:15 +00:00
Dale Johannesen
7e07b30e80
new testcases for -enable-tail-merge default handling
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37287 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-22 17:19:23 +00:00
Chris Lattner
4b2e7acd6a
testcase that crashes llc
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37059 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 01:13:42 +00:00
Evan Cheng
0dbea33fff
Test for PR1406.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37051 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 21:12:43 +00:00
Lauro Ramos Venancio
69642f11ed
Enable aliases on arm-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 18:32:56 +00:00
Dale Johannesen
e163e696be
Another test for tail mergeing
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36967 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-10 01:04:28 +00:00
Evan Cheng
7de291aa8c
Can't fold bit_convert into truncating store.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36963 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-09 21:54:34 +00:00
Dale Johannesen
fe252f38dd
testcase for CodeGenPrepare bug fixed yesterday
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36940 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-08 17:44:36 +00:00
Chris Lattner
b64c2c8a2a
move this out of Codegen/Generic, because it requires the ARM backend to be
...
linked into llc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36919 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-08 02:19:56 +00:00
Evan Cheng
fd4dbf78ae
Fix tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 21:50:07 +00:00
Evan Cheng
070549eb9c
Add some tests for (conv (load x)) -> (load (conv*)x) xform.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36912 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 21:49:35 +00:00
Lauro Ramos Venancio
8f57667a5d
Fix PR1390.
...
Don't spill extra register to align the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-05 23:44:41 +00:00
Chris Lattner
2d4a5abb75
remove xfailed testcase (attached to pr)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36797 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-05 21:57:34 +00:00
Evan Cheng
8535072e88
Test load global in static mode.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36719 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 00:29:34 +00:00
Evan Cheng
874ebada58
New test case.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36717 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 23:53:36 +00:00
Dale Johannesen
4ac075c859
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 20:54:42 +00:00
Chris Lattner
f972db0f4f
match a reassociated form of fnmul
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36659 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 00:31:40 +00:00
Evan Cheng
43d44f036c
Test a dag combiner crasher.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 00:40:38 +00:00
Reid Spencer
4274e40514
For PR1370:
...
Rearrange some tests so that if PowerPC is not being built we don't try to
run PowerPC specific tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36587 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-30 05:11:58 +00:00
Chris Lattner
93e3d8f308
update syntax
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36531 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 06:03:12 +00:00
Lauro Ramos Venancio
2a3779966f
fix the test tls1.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 21:23:17 +00:00
Lauro Ramos Venancio
1bd151a851
add TLS tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36516 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 21:08:48 +00:00
Lauro Ramos Venancio
fdc9692f97
In Thumb mode, the frame register must be R7.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36512 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 17:58:03 +00:00
Lauro Ramos Venancio
305b8a5f62
remember to emit weak reference in one more case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36438 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 14:50:40 +00:00
Lauro Ramos Venancio
0ae4a3357a
Implement PIC for arm-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36324 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-22 00:04:12 +00:00
Reid Spencer
16154ef9f9
Use the llvm_supports_target function to prevent running of tests for
...
targets that LLVM is not configured to support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36315 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21 20:41:27 +00:00
Evan Cheng
8a5a75eb0f
Fix test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36150 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 18:55:46 +00:00
Reid Spencer
eb1d74e0c8
For PR1319:
...
Remove && from the end of the lines to prevent tests from throwing run
lines into the background. Also, clean up places where the same command
is run multiple times by using a temporary file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36142 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 17:36:08 +00:00
Lauro Ramos Venancio
725aed3407
Fix hello.ll test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36141 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 17:08:00 +00:00
Lauro Ramos Venancio
3138b8995f
Fix align test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36140 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 16:57:47 +00:00
Reid Spencer
4cda190ef5
For PR1319:
...
Fix test syntax per new rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36133 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 15:15:52 +00:00
Reid Spencer
4575ab2186
For PR1336:
...
XFAIL tests covered by the PR. These will be un-XFAILed as they are fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36093 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-15 23:00:46 +00:00
Reid Spencer
97e287ef8a
For PR1319: Upgrade to new test harness.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36086 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-15 20:48:50 +00:00
Reid Spencer
1c0c94d6df
For PR1319: Upgrade to use new test harness
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36076 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-15 19:11:47 +00:00
Chris Lattner
a52bfcd3f0
fix test for linux hosts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36026 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 23:04:30 +00:00
Chris Lattner
4dcedf1e85
xfail this for now
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35973 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-13 22:20:27 +00:00
Chris Lattner
3bd767b91d
new lsr testcase
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35971 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-13 20:38:14 +00:00
Reid Spencer
0f5aed5648
Make the llvm-runtest function much more amenable by eliminating all the
...
global variables that needed to be passed in. This makes it possible to
add new global variables with only a couple changes (Makefile and llvm-dg.exp)
instead of touching every single dg.exp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35918 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 19:56:59 +00:00
Chris Lattner
5b456e867b
this got better
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35908 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 16:12:27 +00:00