Bob Wilson
fed76ffa56
Add missing address register update to t2LDM_RET instruction.
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Patch by Brian Lucas. PR7636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 16:02:13 +00:00
Eli Friedman
54cc0e12da
A couple potential optimizations inspired by comment 4 in PR6773.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:58:26 +00:00
Evan Cheng
dedd974e7e
Fix for PR7193 was overly conservative. The only case where sibcall callee
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address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.
This fixes PR7610.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:44:01 +00:00
Bob Wilson
7e3f0d2690
Add support for NEON VMVN immediate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:31:50 +00:00
Bob Wilson
046afdb50b
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
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of the value of the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:30:44 +00:00
Chris Lattner
b09a97e565
fix a bug found by a warning I added to clang this morning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:57:17 +00:00
Bob Wilson
9e82bf12a0
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
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Radar 7373643.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:22:12 +00:00
Dan Gohman
a10b8494a5
Don't propagate debug locations to instructions for materializing
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constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:07:44 +00:00
Bruno Cardoso Lopes
7dbf7d8b1c
Add AVX 256-bit compare instructions and a bunch of testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 22:06:38 +00:00
Bob Wilson
cba270d042
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
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NEON VMOV-immediate instructions. This simplifies some things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:16:48 +00:00
Bruno Cardoso Lopes
87a85c7ef0
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:07:28 +00:00
Kevin Enderby
52a18aedae
Added a check that pusha cannot be encoded in 64-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 20:05:41 +00:00
Evan Cheng
218977b53e
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 19:27:42 +00:00
Evan Cheng
7a41599962
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 19:21:50 +00:00
Evan Cheng
ea4cdb7ead
-enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 18:46:14 +00:00
Gabor Greif
63d024fc9a
rotate CallInst operands
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with this commit the callee moves to the end of
the operand array (from the start) and the call
arguments now start at index 0 (formerly 1)
this ordering is now consistent with InvokeInst
this commit only flips the switch,
functionally it is equivalent to
r101465
I intend to commit several cleanups after a few
days of soak period
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 15:31:36 +00:00
Bob Wilson
6dce00ced4
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
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avoid replicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:44:34 +00:00
Chris Lattner
37a746bc85
my work on adding segment registers to LEA missed the
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disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:23:55 +00:00
Bruno Cardoso Lopes
fd920fa59a
Add AVX 256-bit packed logical forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
6991623dd7
Add AVX 256-bit unop arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
4344d85769
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 00:38:47 +00:00
David Greene
8f17bc4fbd
Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
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utility classes can be used from multiple files. This will aid
transitioning to a new refactored x86 SIMD specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 23:41:28 +00:00
Bruno Cardoso Lopes
a0d09a85e2
Add AVX 256 binary arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
f428fee70d
More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 22:41:32 +00:00
Dan Gohman
cfbf0ed8b0
Apply the SSE dependence idiom for SSE unary operations to
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SD instructions too, in addition to SS instructions. And
add a comment about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:46:04 +00:00
Bob Wilson
c7a797b82b
Remove some code that doesn't appear to do anything. All the ARM call
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instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:22:45 +00:00
Bruno Cardoso Lopes
aa099be71f
Add AVX 256-bit MOVMSK forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:06:32 +00:00
Dan Gohman
ed42f1e58f
Check begin!=end, rather than !begin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 18:12:35 +00:00
Dan Gohman
be4d10d7fa
Don't fast-isel an x87 comparison opcode, as fast-isel doesn't
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support branching on x87 comparisons yet. This fixes PR7624.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 15:46:30 +00:00
Duncan Sands
3472766f9e
Convert some tab stops into spaces.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 08:16:59 +00:00
Rafael Espindola
5a717a3ae7
Convert getLoadStoreRegOpcode to use a switch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 03:43:04 +00:00
Rafael Espindola
7e1b566322
Convert the last use of getPhysicalRegisterRegClass and remove it.
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AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.
With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 02:55:34 +00:00
Jakob Stoklund Olesen
8b78d4b5bb
A basic block that only uses RFP registers still needs the FP_REG_KILL marker.
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This fixes PR7375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 02:12:47 +00:00
Rafael Espindola
0bfd09201e
Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
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getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.
Update getLoadStoreRegOpcode to handle GR32_AD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 00:52:33 +00:00
Jakob Stoklund Olesen
600f171486
RISC architectures get their memory operand folding for free.
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The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 19:19:13 +00:00
Jakob Stoklund Olesen
a66450d227
Use target independent COPY instructions for the fake fextend and fround
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operations in x87 code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 18:19:39 +00:00
Jakob Stoklund Olesen
4cae5af54e
Remove redundant branch. Thanks, Anton!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 17:17:35 +00:00
Jakob Stoklund Olesen
aef48d7b36
Remove obsolete README_SSE note.
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We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.
The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.
The same applies to andps -> pand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 17:13:42 +00:00
Rafael Espindola
d6d7abaf4e
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 16:49:10 +00:00
Jakob Stoklund Olesen
f7d55b97f0
Replace copyRegToReg with copyPhysReg for SystemZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 16:40:46 +00:00
Jakob Stoklund Olesen
75be45cb2e
Avoid SSE instructions in FastIsel when it is not available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 16:22:13 +00:00
Chandler Carruth
c5080ba0c8
Remove two other uses of ATTRIBUTE_UNUSED for variables only used within
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assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108088 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 08:18:12 +00:00
Jakob Stoklund Olesen
a98625cdad
Replace copyRegToReg with copyPhysReg for XCore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 07:56:13 +00:00
Jakob Stoklund Olesen
8e18a1a5cf
Replace copyRegToReg with copyPhysReg for Sparc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 07:56:09 +00:00
Jakob Stoklund Olesen
377b7b7ca3
Replace copyRegToReg with copyPhysReg for CellSPU.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 07:31:03 +00:00
Jakob Stoklund Olesen
27689b0aff
Replace copyRegToReg with copyPhysReg for PowerPC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 07:31:00 +00:00
Jakob Stoklund Olesen
26a99d17de
Fix PIC16 comments referencing copyRegToReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 07:30:57 +00:00
Jakob Stoklund Olesen
d86adf3d6e
Replace copyRegToReg with copyPhysReg for PIC16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108081 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 06:53:33 +00:00
Jakob Stoklund Olesen
41ce3cfd1b
Replace copyRegToReg with copyPhysReg for MSP430.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 06:53:30 +00:00
Jakob Stoklund Olesen
e6afcf8da2
Replace copyRegToReg with copyPhysReg for MBlaze.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108079 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 06:53:27 +00:00
Jakob Stoklund Olesen
ac27366700
Replace copyRegToReg with copyPhysReg for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 06:33:54 +00:00
Jakob Stoklund Olesen
629d80742a
Replace copyRegToReg with copyPhysReg for Blackfin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108077 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 05:44:34 +00:00
Jakob Stoklund Olesen
4ea8771535
X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 05:44:30 +00:00
Jakob Stoklund Olesen
1ba318982e
Use COPY in X86FastISel::X86SelectRet.
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Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 05:17:02 +00:00
Rafael Espindola
cbeeae23c3
Fix va_arg for doubles. With this patch VAARG nodes always contain the
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correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 04:01:49 +00:00
Jakob Stoklund Olesen
5127f79913
Use COPY in FastISel everywhere it is safe and trivial.
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The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108069 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 03:31:00 +00:00
Jakob Stoklund Olesen
273c14f530
Replace copyRegToReg with copyPhysReg for Mips.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 01:08:31 +00:00
Jakob Stoklund Olesen
99666a3429
Replace copyRegToReg with copyPhysReg for Alpha.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 01:08:23 +00:00
Jakob Stoklund Olesen
3ecf1f0179
Use COPY in targets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:43:03 +00:00
Jakob Stoklund Olesen
2b336bc4fe
Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.
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Based on a patch by Rafael Espíndola.
Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.
We support:
FpSET_ST0
INLINEASM
FpSET_ST0
FpSET_ST1
INLINEASM
with and without kills on the arguments. We don't support:
FpSET_ST1
FpSET_ST0
INLINEASM
nor
FpSET_ST1
INLINEASM
Just Don't Do It!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 17:42:34 +00:00
Chandler Carruth
68eec39bca
Add parentheses yet again to satisfy GCC's warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 12:06:22 +00:00
Dan Gohman
84023e0fbe
Reapply bottom-up fast-isel, with several fixes for x86-32:
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- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 09:00:22 +00:00
Jakob Stoklund Olesen
d737fcafc4
An x86 function returns a floating point value in st(0), and we must make sure
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it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.
This will matter when CopyFromReg gets lowered to a generic COPY instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108037 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 04:04:25 +00:00
Bruno Cardoso Lopes
58dbf3784d
Declare YMM subregisters in the right way! Thanks Jakob
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:46:19 +00:00
Bruno Cardoso Lopes
d52e78efac
Add AVX 256-bit packed MOVNT variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:42:42 +00:00
Jakob Stoklund Olesen
61905c8ab3
Remember the *_TC opcodes for load/store
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:27:55 +00:00
Bruno Cardoso Lopes
2bfb8f6ef8
Add AVX 256-bit unpack and interleave
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:20:35 +00:00
Jakob Stoklund Olesen
1f32340d95
Automatically fold COPY instructions into stack load/store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:13 +00:00
Jakob Stoklund Olesen
9c50e8b890
Fix a few tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:09 +00:00
Jim Grosbach
6c7d3a16b3
In the presence of variable sized objects, allocate an emergency spill slot.
...
rdar://8131327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:27:06 +00:00
Bruno Cardoso Lopes
e86b01c153
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
...
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:27:43 +00:00
Bob Wilson
02266e29f9
--- Reverse-merging r107947 into '.':
...
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:37:18 +00:00
Bruno Cardoso Lopes
be95c15903
Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
...
fields to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:56:45 +00:00
Dan Gohman
01dcb18cf3
Fix the memoperand offsets in code generated for va_start.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:06:48 +00:00
Chris Lattner
c5f5626a29
have the mc lowering process handle a few tail call forms, lowering them to
...
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.
This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.
However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:49:41 +00:00
Bob Wilson
a0148c360e
Print "dregpair" NEON operands with a space between them, for readability and
...
consistency with other instructions that have lists of register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:47:20 +00:00
Dan Gohman
bf87e24917
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
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a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:39:23 +00:00
Bruno Cardoso Lopes
1cd050931f
Factor out x86 segment override prefix encoding, and also use it for VEX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:14 +00:00
Chris Lattner
757e8d6d2e
reject pseudo instructions early in the encoder.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:17:50 +00:00
Bruno Cardoso Lopes
96716c7b92
Remove trailing whitespaces from file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:07:19 +00:00
Chris Lattner
599b531a96
Change LEA to have 5 operands for its memory operand, just
...
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 23:46:44 +00:00
Chris Lattner
ac0ed5dc08
add some long-overdue enums to refer to the parts of the 5-operand
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X86 memory operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:41:28 +00:00
Jakob Stoklund Olesen
61c8eccf24
Remember the VR64 register class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:30:35 +00:00
Chris Lattner
834df19452
Rework segment prefix emission code to handle segments
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in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:28:12 +00:00
Chris Lattner
751e1123ce
introduce a new X86II::getMemoryOperandNo method, which
...
returns the start of the memory operand for an instruction.
Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:27:06 +00:00
Kalle Raiskila
d258c49589
Switch SPU calling convention (function arguments)
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to a Tablegen implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107913 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 21:15:22 +00:00
Evan Cheng
5d115a0ff9
Check for FiniteOnlyFPMath as well.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 20:12:24 +00:00
Jakob Stoklund Olesen
7db1e7a527
Teach the x86 floating point stackifier to handle COPY instructions.
...
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.
Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 19:46:30 +00:00
Jakob Stoklund Olesen
320bdcbfe2
Implement X86InstrInfo::copyPhysReg
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 19:46:25 +00:00
Bob Wilson
1425c6a927
The NEONPreAllocPass should never have to assign fixed registers anymore.
...
This pass can go away entirely soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 17:45:26 +00:00
Bob Wilson
8190173350
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
...
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 17:44:00 +00:00
Bob Wilson
8af4c54af1
Clean up a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:54:45 +00:00
Jakob Stoklund Olesen
0bc25f4040
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
...
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
5c00e07795
Remove references to INSERT_SUBREG after de-SSA.
...
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:15 +00:00
Benjamin Kramer
1db071f0da
Teach instcombine to transform
...
(X >s -1) ? C1 : C2 and (X <s 0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.
This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.
for
int sel(int n) {
return n >= 0 ? 60 : 100;
}
we now generate
sarl $31, %edi
andl $40, %edi
leal 60(%rdi), %eax
instead of
testl %edi, %edi
movl $60, %ecx
movl $100, %eax
cmovnsl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107866 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 11:39:10 +00:00
Eric Christopher
fb31ccb68c
A slight reworking of the custom patterns for x86-64 tpoff codegen and
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correct the testcase for valid assembly.
Needs more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 07:36:46 +00:00
Evan Cheng
4ff7ab612c
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 06:01:49 +00:00
Evan Cheng
515fe3a588
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
...
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 02:08:50 +00:00
Dale Johannesen
7835f1fcdb
Changes to ARM tail calls, mostly cosmetic.
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Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:18:23 +00:00
Dan Gohman
f595141525
Revert 107840 107839 107813 107804 107800 107797 107791.
...
Debug info intrinsics win for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:00:56 +00:00
Jakob Stoklund Olesen
5febd075df
fix copies to/from GR8_ABCD_H even more
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107832 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 23:04:56 +00:00
Jim Grosbach
03e2d44722
grammar
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:53:35 +00:00
Jim Grosbach
c7937ae025
Handle cases where the post-RA scheduler may move instructions between the
...
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:51:22 +00:00
Chris Lattner
da3051a17f
finish up support for callw: PR7195
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:35:13 +00:00
Chris Lattner
9fc05227a2
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
cc69e13a36
Add more assembly opcodes for SSE compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:24:03 +00:00
Evan Cheng
bcc8017c73
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:15:37 +00:00
Devang Patel
03753fc734
Print undefined/unknown debug value as "undef".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 21:52:21 +00:00
Jim Grosbach
26b8ef53ff
grammar and trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107811 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 21:06:51 +00:00
Jakob Stoklund Olesen
f2e4afd96c
Allow copies between GR8_ABCD_L and GR8_ABCD_H.
...
This fixes PR7540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 20:33:27 +00:00
Dan Gohman
4df83ed159
Implement bottom-up fast-isel. This has the advantage of not requiring
...
a separate DCE pass over MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 19:20:32 +00:00
Dan Gohman
f423a69839
Add X86FastISel support for return statements. This entails refactoring
...
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:32:53 +00:00
Bruno Cardoso Lopes
ced9ec9bac
Add AVX AES instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:24:20 +00:00
Dan Gohman
eabaed26c3
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
...
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 16:47:08 +00:00
Dan Gohman
a4160c3434
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
...
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 16:29:44 +00:00
Dan Gohman
c9403659a9
Split the SDValue out of OutputArg so that SelectionDAG-independent
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code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 15:54:55 +00:00
Bruno Cardoso Lopes
4f6bdf9042
Add AVX SSE4.2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
332fce49e3
Use only one multiclass to pinsrq instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
5e9fa98523
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
09df2ae0d0
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312
Add AVX SSE4.1 extractps and pinsr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:01:13 +00:00
Bob Wilson
78dfbc380d
Also use REG_SEQUENCE for VTBX instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:08:54 +00:00
Jim Grosbach
e97f968a69
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
...
they've been tested to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:07:57 +00:00
Bruno Cardoso Lopes
4fd32db6a6
Add AVX SSE4.1 Extract Integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:07:24 +00:00
Jim Grosbach
c66e150b2c
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
...
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:44:52 +00:00
Bob Wilson
d491d6ecd2
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:36:25 +00:00
Dale Johannesen
e2b448c208
Accept RIP-relative symbols with 'i' constraint, and
...
print the (%rip) only if the 'a' modifier is present.
PR 7528.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:27:00 +00:00
Jakob Stoklund Olesen
fca3a25fed
Track defs for all aliases in NEONMoveFix.
...
This means that an instruction defining an S register will affect the domain of
the parent D register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes
ee94e8297e
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
36869b69b0
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
0106680a2c
Fix comment from previous patch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
07de40629f
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:36:24 +00:00
Dan Gohman
c9af33c685
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:19:37 +00:00
Devang Patel
0d881dabc1
Propagate debug loc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:08:15 +00:00
Bob Wilson
f967ca0eaf
Represent NEON load/store alignments in bytes, not bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 21:26:18 +00:00
Dan Gohman
14152b480d
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 20:24:04 +00:00
Devang Patel
be35be614c
Fix PR7545 crash.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 18:18:32 +00:00
Rafael Espindola
a5e82a5748
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
...
if profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 16:24:34 +00:00
Dan Gohman
258c58cc62
Revert r107655.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:49:48 +00:00
Dan Gohman
c2af869d62
Make getMinimalPhysRegClass' comment mention what makes it different
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from getPhysicalRegisterRegClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:31:55 +00:00
Dan Gohman
b81c771c0d
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:18:19 +00:00
Eric Christopher
f7a0c7bf8b
Fix up -fstack-protector on linux to use the segment
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registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 05:18:56 +00:00
Eric Christopher
62f35a2c13
Have the X86 backend use Triple instead of a string and some enums.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 19:26:33 +00:00
Kalle Raiskila
5cb97d16f8
Remove some unused/redundant code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 18:40:09 +00:00
Chris Lattner
32b4b5aea6
more tidying.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 05:53:14 +00:00
Chris Lattner
c06cbad141
some notes about suboptimal insertps's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 05:48:41 +00:00
Chris Lattner
a5b412581c
rip out even more sporadic v2f32 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 04:38:33 +00:00
Chris Lattner
39aa20a981
rip out the various v2f32 "mmx" handling logic, now that
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v2f32 is illegal on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 04:36:27 +00:00
Chris Lattner
f172ecd964
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 23:07:25 +00:00
Chris Lattner
e35d9842f7
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 22:57:10 +00:00
Chris Lattner
9d19989fe3
indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 22:56:10 +00:00
Bill Wendling
f43f6bc3ec
Revert r107583. I no longer think that this is the way to solve the problem.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 09:16:57 +00:00
Bill Wendling
4a991a6fa6
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 08:59:55 +00:00
Eli Friedman
b482829abb
Minor amendment to switch-lowering improvement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107569 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 08:43:32 +00:00
Eli Friedman
b4a74c1d82
Note switch-lowering inefficiency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes
68b559e5f3
Add AVX SSE4.1 blend, mpsadbw and vdp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:49:21 +00:00
Evan Cheng
ed2ae136d2
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
2c70d4ad35
Add AVX SSE4.1 round instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
03560600b4
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
f5cd8c51e3
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 22:06:54 +00:00
Evan Cheng
dca653951c
Remove early IT block formation. It's not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 21:07:09 +00:00
Evan Cheng
98ec91ea80
- Two-address pass should not assume unfolding is always successful.
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- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 20:36:18 +00:00
Gabor Greif
135d7fe9bb
beautify output
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 19:26:28 +00:00
Gabor Greif
53ba550df1
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 19:08:46 +00:00
Bob Wilson
e45f72c833
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
...
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 17:23:44 +00:00
Gabor Greif
9d135f0ba5
use ArgOperand API (found by my previous commit)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 13:37:16 +00:00
Bruno Cardoso Lopes
f12ad66741
Shrink down SSE3 code by more multiclass refactoring
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
944facac2e
Shrink down SSE3 code by some multiclass refactoring - 1st part
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 22:33:18 +00:00
Bob Wilson
b5b5057a70
ARM function alignments were off by a power of two. svn 83242 changed
...
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 22:26:26 +00:00
Bill Wendling
5e721d7682
Implement the "linker_private_weak" linkage type. This will be used for
...
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.
For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
Currently only supported on Darwin platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 21:55:59 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61
Add AVX SSE3 packed addsub instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:08:18 +00:00
Dan Gohman
20d4be151b
Enable on-demand fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:58:57 +00:00
Dan Gohman
abd1d859b3
Fix X86FastISel's add folding to actually work, and not fall back
...
to SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
79b634c244
Add AVX SSE3 replicate and convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:33:39 +00:00
Dan Gohman
5c87bf64d6
Teach X86FastISel to fold constant offsets and scaled indices in
...
the same address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
6596a62076
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a
Move MOVD/MODQ code around, creating sections for each of them
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150
Add AVX SSE2 mask creation and conditional store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20
Add AVX SSE2 packed integer extract/insert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 17:03:03 +00:00
Gabor Greif
e1c2b9cc3d
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
876085dcfa
Add AVX SSE2 integer unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae
Add AVX SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd
Small refactoring of SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2
Add AVX SSE2 pack with saturation integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c
Add AVX SSE2 integer packed compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750
- Add AVX form of all SSE2 logical instructions
...
- Add VEX encoding bits to x86 MRM0r-MRM7r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716
Add *several* AVX integer packed binop instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 23:47:49 +00:00
Bill Wendling
07d3177117
Revert r107205 and r107207.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 22:34:52 +00:00
Eric Christopher
33634d0672
Add another bswap idiom that isn't matched.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 22:22:22 +00:00
Bruno Cardoso Lopes
2c818072cc
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e
Add AVX Move Aligned/Unaligned packed integers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 21:25:12 +00:00
Bill Wendling
207855cff9
Introducing the "linker_weak" linkage type. This will be used for Objective-C
...
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 21:24:00 +00:00
Bruno Cardoso Lopes
147b7cad2f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:35:48 +00:00
Bob Wilson
21773e716f
Add support for encoding VDUP (ARM core register) instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:13:29 +00:00
Bruno Cardoso Lopes
721ef73d88
Add AVX non-temporal stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb
Move non-temporal movs to their own section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:42:37 +00:00
Bob Wilson
d5a563de07
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:34:07 +00:00
Bruno Cardoso Lopes
ea86423cbd
Add sqrt, rsqrt and rcp AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:26:30 +00:00
Jim Grosbach
077f1bfa91
skip dbg_value instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 16:55:24 +00:00
Bob Wilson
1ab38469df
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
...
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 16:25:11 +00:00
Rafael Espindola
d31f972bd3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
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of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 14:02:34 +00:00
Duncan Sands
31a3a3ebaf
Remove pointless variable LastDef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 13:23:22 +00:00
Duncan Sands
58c86910b3
Remove unused variable Loc and pointless variables unified_syntax
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and thumb_mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 13:04:35 +00:00
Duncan Sands
978189e090
Remove an unused and a pointless variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 13:00:29 +00:00
Duncan Sands
78337b4d4d
Remove pointless and unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 12:48:49 +00:00
Duncan Sands
90c64f4aac
Remove initialized but otherwise unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 11:22:26 +00:00
Evan Cheng
c36b5b9730
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 05:38:36 +00:00
Evan Cheng
c170f66742
Change if-cvt options to something that actually as useable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 05:37:59 +00:00
Bruno Cardoso Lopes
b22dc70a5c
Refactoring of arithmetic instruction classes with unary operator
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 01:33:09 +00:00
Jakob Stoklund Olesen
628a79771b
When no memoperands are present, assume unaligned, volatile.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 01:13:07 +00:00
Bruno Cardoso Lopes
4548260ab5
Described the missing AVX forms of SSE2 convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:36:02 +00:00
Bob Wilson
5cdede43e9
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:26:13 +00:00
Bob Wilson
62d24a4b92
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
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of the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 22:23:17 +00:00
Jim Grosbach
e89c5e57cc
tidy up style. no functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:29:17 +00:00
Bob Wilson
08baddbc07
Refactor encoding function for NEON 1-register with modified immediate format.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:16:30 +00:00
Bob Wilson
d896a97dc7
Support Thumb mode encoding of NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:12:19 +00:00
Bill Wendling
c25ccf85e5
Reduce indentation via early exit. NFC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:08:32 +00:00
Jim Grosbach
e9e3f20ffb
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 04:27:01 +00:00
Gabor Greif
7a1d92a2cb
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 12:17:21 +00:00
Gabor Greif
6bec14fea0
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 12:09:10 +00:00
Gabor Greif
1cfe44a460
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 11:51:52 +00:00
Eli Friedman
a2c6f457a4
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:36:50 +00:00
Bob Wilson
52e4a0a074
Add support for encoding NEON VMOV (from scalar to core register) instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:07:15 +00:00
Evan Cheng
f6799394d5
It's now possible to run code placement pass for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 01:52:05 +00:00
Jakob Stoklund Olesen
4f5d84e4ad
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
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CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 00:39:23 +00:00
Bob Wilson
80d9bc0336
Renumber NEON instruction formats to be consecutive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 00:05:09 +00:00
Bob Wilson
184723d9be
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
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"N..." instead of "NEON..." for consistency with the other NEON format names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:56:05 +00:00
Bruno Cardoso Lopes
bdffc16d65
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:47:23 +00:00
Bob Wilson
2653263165
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
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Renumber MiscFrm to 25.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:45:37 +00:00
Bruno Cardoso Lopes
161476ec34
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:33:42 +00:00
Daniel Dunbar
e39e06af38
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
...
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:14:54 +00:00
Bruno Cardoso Lopes
95325b08a3
revert this now, it's using avx instead of sse :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:04:29 +00:00
Evan Cheng
13151432ed
Change if-conversion block size limit checks to add some flexibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:42:03 +00:00
Bob Wilson
5e7b607f72
Add support for encoding 3-register NEON instructions, and fix
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emitNEON2RegInstruction's handling of 2-address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:40:46 +00:00
Bruno Cardoso Lopes
544a95d716
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:27:51 +00:00
Dale Johannesen
1784d160e4
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:55:36 +00:00
Bob Wilson
583a2a0615
Add support for encoding 2-register NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:17:19 +00:00
Dan Gohman
ca5b8553ea
pcmpeqd and friends are Commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:05:35 +00:00
Bob Wilson
8c605c601d
Fix indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:54:44 +00:00
Bill Wendling
730c07e50d
- Reapply r106066 now that the bzip2 build regression has been fixed.
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- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
39afa908de
Move the last piece of SSE2 convert instructions to the Convert Instructions section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4
More SSE refactoring, this time with different types of MOVs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:22:12 +00:00
Jim Grosbach
57bb394803
IT instructions are considered to be scheduling hazards, but are scheduled
...
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 18:43:14 +00:00
Bruno Cardoso Lopes
0491e132fc
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 18:06:22 +00:00
Bob Wilson
ade57fa619
Add missing ARM and Thumb data layout info for vector types.
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Radar 8128745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 04:41:08 +00:00
Bob Wilson
86fe66db3a
Reduce indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 04:12:31 +00:00
Bruno Cardoso Lopes
a0ae87fd5d
Add some AVX convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727
Refactoring of SSE convert intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792
Refactoring of SSE conversion instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
e0c437333e
Refactor SSE cmp intrinsics and declare the same for AVX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
788184365a
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:48:23 +00:00
Dale Johannesen
e5ff9ef195
Disallow matching "i" constraint to symbol addresses when
...
address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106779 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:14:51 +00:00
Evan Cheng
8acf67672b
Oops. IT block formation pass needs to be run at any optimization level.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 19:10:14 +00:00
Eli Friedman
761fa7af9e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
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form so they can be narrowed to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 16:50:20 +00:00
Dan Gohman
4e39e9da0f
Reapply r106634, now that the bug it exposed is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 14:30:44 +00:00
Chris Lattner
645b209c4a
Teach the x86 mc assembler that %dr6 = %db6, this implements
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rdar://8013734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:29:18 +00:00
Chris Lattner
adabe1a92c
more cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106724 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:18:14 +00:00
Chris Lattner
02758a44e4
reduce indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:16:25 +00:00
Chris Lattner
f8cbde46fb
fix breakage from r98938 by correctly marking msp430 calls as variadic.
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Patch by Ben Ransford!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 06:46:50 +00:00
Dan Gohman
6b13cbca61
Fix a bug in the code which determines when it's safe to use the
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bt instruction, which was exposed by r106263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:59 +00:00
Eric Christopher
37106afe02
Add a couple more quick comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:57 +00:00
Devang Patel
e9916a302f
Use ValueMap instead of DenseMap.
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The ValueMapper used by various cloning utility maps MDNodes also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:33:28 +00:00
Bruno Cardoso Lopes
6539dc6e6c
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
34a491bd8e
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:15:50 +00:00
Bill Wendling
4b722108e2
We are missing opportunites to use ldm. Take code like this:
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void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 23:00:16 +00:00
Bruno Cardoso Lopes
e93e300ad0
Add AVX MOVMSK{PS,PD}rr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:10:57 +00:00
Eric Christopher
749bb7e2d9
Update according to feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:49:35 +00:00
Bruno Cardoso Lopes
7dbfd07e32
Add AVX SHUF{PS,PD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:07:15 +00:00
Nico Weber
50b9efc2a8
Add support for the x86 instructions "pusha" and "popa".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Dale Johannesen
e39fdbe118
Do not do tail calls to external symbols. If the
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branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 18:52:34 +00:00
Daniel Dunbar
cbe762b5d1
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 17:09:26 +00:00
Jim Grosbach
f1ab49e83a
The generic DAG combiner can now fold atomic fences when needed, so switch
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to using that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 16:25:07 +00:00
Jim Grosbach
5def57aaf4
When using libcall expansions for the atomic intrinsics, the explicit
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MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 16:08:49 +00:00
Eric Christopher
18ebf74781
Update uses, defs, and comments for darwin tls patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 08:01:49 +00:00
Daniel Dunbar
d24c9d5f91
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
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Conflicts:
lib/CodeGen/MachineSink.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 00:48:25 +00:00
Bruno Cardoso Lopes
62a76c6401
Add AVX compare packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b
Reapply support for AVX unpack and interleave instructions, with
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testcases this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c
Add AVX MOV{SS,SD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:38:56 +00:00
Bill Wendling
19d8597bca
Fix the formatting of the switch statement and add a missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:16:17 +00:00
Bob Wilson
a3a204664d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
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Radar 8031193.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:04:24 +00:00
Jim Grosbach
dd11ee2273
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106574 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 20:52:02 +00:00
Bruno Cardoso Lopes
d3a067bbc2
Reorganize logical and arithmetic SSE 1 & 2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 18:17:40 +00:00
Bruno Cardoso Lopes
f23919b3e9
Reorganize SSE instructions, making easier to see oportunities for refactoring
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 18:09:32 +00:00
Dan Gohman
fe60104ac9
Use pre-increment instead of post-increment when the result is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 15:08:57 +00:00
Evan Cheng
4d54e5b2dd
Tail merging pass shall not break up IT blocks. rdar://8115404
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 01:18:16 +00:00
Chris Lattner
ceea301c1d
make sure to initialize indent_level
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 00:40:26 +00:00
Chris Lattner
3284877064
add some support for blockaddress. This isn't really enough to be useful,
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but it will cover uses of blockaddress that are actually in a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106502 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 23:19:36 +00:00
Chris Lattner
1018c24c13
eliminate a mutable global variable, use raw_ostream::indent instead of
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rolling our own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 23:14:47 +00:00
Chris Lattner
7e6d7451ae
un-indent a huge amount of code out of an anonymous namespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 23:12:56 +00:00
Bruno Cardoso Lopes
c27d1e4d17
revert r106482
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 22:59:03 +00:00
Bruno Cardoso Lopes
b7cc3f6ae6
change parameter name to avoid confusion with global definition
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:28:07 +00:00
Bob Wilson
56a1a69a35
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
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Radar 8104310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:34 +00:00
Jim Grosbach
a967d1121a
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
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being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:27 +00:00
Bruno Cardoso Lopes
b44e8b2d11
Add unpack and interleave AVX instructions, encoding tests cooming soon
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:48 +00:00
Evan Cheng
d95ea2da28
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:14 +00:00
Eric Christopher
be4e066ff9
Remove isTwoAddress from SystemZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 20:25:57 +00:00
Eric Christopher
c63a404d56
Remove isTwoAddress from Sparc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 20:22:35 +00:00
Eric Christopher
c452d79c43
Remove isTwoAddress from Mips.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 20:19:21 +00:00
Eric Christopher
b82a7ea1b2
Remove isTwoAddress from Blackfin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 20:13:37 +00:00
Eric Christopher
f704408bf7
Remove isTwoAddress from MSP430.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 20:07:30 +00:00
Eric Christopher
658ebcc7ec
Make 80-column.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:56:55 +00:00
Eric Christopher
90301312d5
Remove isTwoAddress from PIC16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:55:01 +00:00
Eric Christopher
4a232f0836
Remove isTwoAddress from XCore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:51:38 +00:00
Eric Christopher
23265d0054
Remove isTwoAddress from Alpha.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:48:55 +00:00
Bruno Cardoso Lopes
c79e43aee3
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:36:04 +00:00
Bruno Cardoso Lopes
59bb6fae9a
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106436 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:22:54 +00:00
Dale Johannesen
b0ccb757b3
Fix PR 7433. Silly typo in non-Darwin ARM tail call
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handling, plus correct R9 handling in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:49 +00:00
Eric Christopher
18fb00b4b9
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
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Based on a patch by Patrick Marlier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:27 +00:00
Jim Grosbach
9cfcfeb24b
early exit for dbg_value instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 17:49:23 +00:00
Chris Lattner
9e13715fd5
remove some dead variables reported by clang++
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 17:20:18 +00:00
Kalle Raiskila
951b229ccf
Mark the SPU 'lr' instruction to never have side effects.
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This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 15:08:16 +00:00
Kalle Raiskila
91fdee125c
Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 14:42:19 +00:00
Rafael Espindola
c2b3e00cdf
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
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I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 13:31:32 +00:00
Kalle Raiskila
4794807134
Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
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used to choke llc with the attached test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 10:17:36 +00:00
Rafael Espindola
f0efafa61e
wip
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 02:17:34 +00:00
Nick Lewycky
2a3ee5e8e9
Fix warning in no-asserts build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-20 20:27:42 +00:00
Evan Cheng
859df5e9f9
Fix a crash caused by dereference of MBB.end(). rdar://8110842
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-20 00:54:38 +00:00
Bob Wilson
31ef8e6663
Remove a fixme comment that is no longer relevant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 05:32:41 +00:00
Bob Wilson
dc076da4d2
Fix error message to match function name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 05:32:09 +00:00
Bruno Cardoso Lopes
f6ff003043
Refactoring of regular logical packed instructions to prepare for AVX ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
f4f4bad696
Refactor aliased packed logical instructions, also add
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AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:44:01 +00:00
Evan Cheng
02ba9e19c7
Ignore dbg_value's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:36:21 +00:00
Bruno Cardoso Lopes
1e8d06282f
Move new sse 1 & 2 generic classes to a more appropriate place
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
efc9b69deb
Remove unnecessary arguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
17227db062
Add AVX packed intrinsics for MIN, MAX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:17:05 +00:00
Evan Cheng
0110ac66eb
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Eric Christopher
a938cfb13a
Finish ripping isTwoAddress out of X86. Some mindless formatting
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and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:40 +00:00
Bruno Cardoso Lopes
be4d595afd
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:31 +00:00
Chris Lattner
617e595022
rip out dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:14 +00:00
Chris Lattner
1cf44fc051
fix rdar://7873482 by teaching the instruction encoder to emit
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segment prefixes. Daniel wrote most of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:00 +00:00
Evan Cheng
6523d2ff7f
Indentation and remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:11:54 +00:00
Bruno Cardoso Lopes
fda1acb389
Clean up: remove now unnecessary Constraints
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:09:27 +00:00
Dan Gohman
9559e3b99a
Silence compiler warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:02:06 +00:00
Bruno Cardoso Lopes
c82f199892
more refactoring! yay! big win over the intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:00:22 +00:00
Eric Christopher
96ab7f494d
Remove isTwoAddress from here too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
ccf30bd984
Fix typo, SSE1 should be used by XS, not SSE2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:53:27 +00:00
Eric Christopher
f6bc0b9d4b
Remove isTwoAddress from 64-bit files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:51:21 +00:00
Evan Cheng
96c3da6436
Move ARM if-conversion before post-ra scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:32:07 +00:00
Dan Gohman
db4971259c
Teach regular and fast isel to set dead flags on unused implicit defs
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on calls and similar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
8af5ed9e15
Apply some refactor to packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:13:35 +00:00
Evan Cheng
3ee608c5aa
Update cmake list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:12:10 +00:00
Evan Cheng
886459456c
Thumb2 hazard recognizer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:11:35 +00:00
Evan Cheng
86050dc8cc
Allow ARM if-converter to be run after post allocation scheduling.
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- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Jim Grosbach
ef6eb9c7ab
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:03:10 +00:00
Jim Grosbach
68741be5e6
Enable Expand handling of atomics for subtargets that can't do them inline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:35:32 +00:00
Bruno Cardoso Lopes
4b8921d1c7
Use the new 'defm' class inheritance in SSE
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:10:11 +00:00
Bob Wilson
ebe99b2c19
Rewrite chained if's as switches and replace assertions with llvm_unreachable
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(as suggested in radar 8104405).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 21:32:42 +00:00
Dale Johannesen
51bd47edbc
Fix ARM/Thumb reversal in previous attempt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
52c61ec164
When using ADDri to get the address of a stack object, 255 is a conservative
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limit on the offset that can be materialized without using the register
scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:59:25 +00:00
Dan Gohman
1415a602ad
Make this comment less specific.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106311 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:45:41 +00:00
Dan Gohman
ea9f151cbc
Fix X86FastISel's address-mode folding to stay within the
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original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:44:47 +00:00
Dale Johannesen
10416803c1
An attempt to fix the problem Anton reported with
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ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:44:28 +00:00
Dale Johannesen
c66cdf74a9
Enable tail calls on ARM by default, with some
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basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:00:18 +00:00
Dan Gohman
a606d955de
Start TargetRegisterClass indices at 0 instead of 1, so that
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MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:55 +00:00
Dale Johannesen
df50d7e238
Last round of changes for ARM tail calls.
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Not turning them on yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:11 +00:00
Jakob Stoklund Olesen
0d8ba3303b
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
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does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 16:49:33 +00:00
Dan Gohman
027657db7c
Change UpdateNodeOperands' operand and return value from SDValue to
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SDNode *, since it doesn't care about the ResNo value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 15:30:29 +00:00
Dan Gohman
5ff12fc41a
Delete unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 14:32:32 +00:00
Dan Gohman
e368b460a2
Eliminate unnecessary uses of getZExtValue().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 14:22:04 +00:00
Dan Gohman
7720cb3823
isValueValidForType can be a static member function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 14:01:07 +00:00
Eric Christopher
f627dc37bf
Some assorted isTwoAddress -> Constraints cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 02:41:19 +00:00
Dan Gohman
e54081088e
Don't maintain a set of deleted nodes; instead, use a HandleSDNode
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to track a node over CSE events. This fixes PR7368.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
d7f9cc4de7
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:12:56 +00:00
Dan Gohman
8a7f7426ee
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
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which is faster, simpler, and less surprising.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:05:21 +00:00
Bruno Cardoso Lopes
597ec8ed51
Use new tablegen resources in SSE tablegen code. This will
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be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 23:05:30 +00:00
Stuart Hastings
3bf9125933
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 22:43:56 +00:00
Jim Grosbach
7072cf62a5
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
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ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 02:02:03 +00:00
Jim Grosbach
c73993b678
simplify code a bit and add a more explanatory assert for cases that
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previously would result in 'cannot yet select' errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 01:37:00 +00:00
Eric Christopher
e98ad83543
Hack to let the move lowering handle dynamic-no-pic absolute moves of
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TLVP:
movl _a@TLVP, %eax
Daniel: Please review if you get a chance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 00:51:48 +00:00
Jim Grosbach
7616b646f1
format and 80-column cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 23:45:49 +00:00
Jakob Stoklund Olesen
a2846b4bee
Don't attempt preserving conservative kill flags. We were doing it wrong.
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This is before LiveVariables anyway, where these kill flags are recalculated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 22:11:08 +00:00
Bob Wilson
07f6e805b1
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
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now, so there's no need to disable them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:34:01 +00:00
Benjamin Kramer
0f471e018f
TODO--
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 15:47:00 +00:00
Evan Cheng
46df4eb46e
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 07:35:02 +00:00
Bill Wendling
d361a77f14
Create a more targeted fix for not sinking instructions into a range where it
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will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 23:46:31 +00:00
Eric Christopher
6102549737
For 32-bit non-pic tlv mach-o addressing we don't need a pic base or
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a relative address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 23:08:42 +00:00
Dale Johannesen
38d5f0441c
Add file missing from previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:24:08 +00:00
Dale Johannesen
6470a116f1
Next round of tail call changes. Register used in a tail
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call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:08:33 +00:00
Dale Johannesen
bf37850e42
Reapply 105986 with fix for bug pointed out by Jakob:
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flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info. I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106049 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 21:36:43 +00:00
Chris Lattner
868ee9460c
fix fastisel to handle GS and FS relative pointers. Patch by
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Nelson Elhage!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:08:40 +00:00
Bob Wilson
827b2106fe
Add basic support for NEON modified immediates besides VMOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:05:35 +00:00
Daniel Dunbar
f4a7bf4ec3
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 14:50:42 +00:00
Bob Wilson
14f1d4e74b
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 05:51:27 +00:00
Dale Johannesen
69ba5c6aa8
Revert 105986; looks like I'd better try bootstrapping.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105988 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 04:55:06 +00:00
Dale Johannesen
4b559f070a
The form of BuildMI used for TAILJMPr was changing the register
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containing the target address, an input, into an output. I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 03:13:49 +00:00
Jim Grosbach
400c95fe38
Make sure to skip dbg_value instructions when finding an insertion point for
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the combined load/store instruction. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 00:41:09 +00:00
Bob Wilson
d3c4284849
Rename functions referring to VMOV immediates to refer to NEON "modified
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immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 22:19:57 +00:00
Chris Lattner
6b601536ff
fix a nasty bug where we were not treating available_externally
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symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 20:11:56 +00:00
Chris Lattner
ef66df4da8
fix a -Wbool-conversions warning from clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 18:28:57 +00:00
Eli Friedman
e103194851
Add back some possible optimizations for va_arg, with wording that makes it
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more clear what exactly is missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 07:03:30 +00:00
Rafael Espindola
21d238fdba
Merge getStoreRegOpcode and getLoadRegOpcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 20:13:29 +00:00
Eli Friedman
8c47d3b73f
Add README entry; based on testcase from Bill Hart.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 05:54:27 +00:00
Bruno Cardoso Lopes
2dcf6d6019
make the avx intrinsics 3 address
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 03:12:14 +00:00
Bruno Cardoso Lopes
11ae95c175
Add some basic fp intrinsics for AVX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105873 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 02:38:32 +00:00
Bruno Cardoso Lopes
cf125d02a0
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
7be0d2c8e9
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
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Handle OpSize TSFlag for AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
e4f6907a7a
Add some comments about REX fields
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 00:03:52 +00:00
Bruno Cardoso Lopes
c902a59f4c
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
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Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 23:50:47 +00:00
Bob Wilson
1114f568bc
Add a missing bitcast. This code used to only handle conversions between
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i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 22:45:25 +00:00
Bob Wilson
1a913ed178
Add instruction encoding for the Neon VMOV immediate instruction. This changes
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the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 21:34:50 +00:00
Evan Cheng
aa4b5429ef
Delete code that's not safe.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10 02:08:20 +00:00
Jim Grosbach
db03adb346
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
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dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 22:21:24 +00:00
Evan Cheng
68fc2daf8f
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 19:26:01 +00:00
Kalle Raiskila
43d225dc8b
Fix SPU to cope with vector insertelement to an undef position.
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We default to inserting to lane 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 09:58:17 +00:00
Kalle Raiskila
c6166c6bca
Handle loading from/storing to undef pointers on SPU by inserting a
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random load/store, rather than crashing llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 08:29:41 +00:00
Evan Cheng
34aa423814
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 03:49:12 +00:00
Eli Friedman
092f9c116a
A few new x86-64 specific README entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105674 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 02:43:17 +00:00
Evan Cheng
d847124211
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
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the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 01:46:50 +00:00
Kevin Enderby
09712b57ce
Incremental improvement to the handling of the x86 "Jump if rCX Zero"
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instruction. Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode. Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 23:48:44 +00:00
Eric Christopher
497f1eb2b8
Split out these asserts so it's more apparent why we're not assembling
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that rip-relative address when executing in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:57:33 +00:00
Jim Grosbach
6335ac67b6
fix copy/paste/modify think-o
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:53:32 +00:00
Bruno Cardoso Lopes
99405df044
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Eric Christopher
544153653b
Ensure that mov and not lea are used to stick the address into
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the register. While we're at it, make sure it's in the right one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:04:25 +00:00
Jim Grosbach
b84adb3b80
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 20:06:55 +00:00
Kalle Raiskila
e77ff11a34
Flag SPU's function call sequence together.
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Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 07:55:16 +00:00
Bob Wilson
dd726e5bce
Fix up a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 00:42:08 +00:00
Bob Wilson
53dd2454d5
Further changes for Neon vector shuffles:
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- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07 23:53:38 +00:00
Jim Grosbach
8077e76f93
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
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rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07 21:48:47 +00:00
Bill Wendling
22a5b29820
Create new accessors to get arguments for call/invoke instructions. It breaks
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encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07 19:05:06 +00:00
Duncan Sands
431c3e7404
This bug is also present in MSVC10. Requested by Elrood on IRC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 12:40:43 +00:00
Chris Lattner
1087f54ddb
revert r105521, which is breaking the buildbots with stuff like this:
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In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a
Initial AVX support for some instructions. No patterns matched
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yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 03:53:24 +00:00
Dale Johannesen
cf296fa162
Improvements to tail call code. No functional effect
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unless using -arm-tail-calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 00:51:39 +00:00
Dale Johannesen
88004c25c7
Fix some liveout handling related to tail calls, see comments.
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I don't think this ever resulted in problems on x86, but it
would on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 00:30:45 +00:00
Dale Johannesen
8fa8e7fe95
More thoroughly disable tails calls by default.
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8060143, although this doesn't fix the real problem with tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 18:04:24 +00:00
Jim Grosbach
8af44b687b
Another fix to prevent debug info from affecting codegen. rdar://7797940
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 17:57:34 +00:00
Jim Grosbach
958e4e1967
more dbg_value adjustments so debug info doesn't affect codegen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 01:23:30 +00:00
Jim Grosbach
d089a7ac70
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:15:00 +00:00
Bob Wilson
40cbe7d5d4
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
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VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:04:02 +00:00
Jim Grosbach
3de755bb40
Teach the ARM load-store optimizer to deal with dbg_value instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 22:41:15 +00:00
Dale Johannesen
51e28e6348
Early implementation of tail call for ARM.
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A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 21:09:53 +00:00
Eric Christopher
30ef0e5658
Add first pass at darwin tls compiler support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 04:07:48 +00:00
Eli Friedman
db1bf34178
Remove some already-fixed README entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 01:47:31 +00:00
Eli Friedman
a04a2c0a50
Remove README entry which no longer compiles to something sane.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 01:16:51 +00:00
Eli Friedman
2ad7e433c9
Remove a fixed item, update a couple partially-fixed items.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 01:01:48 +00:00
Jakob Stoklund Olesen
9edf7deb37
Slightly change the meaning of the reMaterialize target hook when the original
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instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 22:47:25 +00:00
Jim Grosbach
18f30e6f5e
Clean up 80 column violations. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 21:53:11 +00:00
Rafael Espindola
42d075c4fb
Remove the TargetRegisterClass member from CalleeSavedInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 20:02:30 +00:00
Eli Friedman
962f549d20
Fix comment so it doesn't include comments which are irrelevant to the x86
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backend. Add a FIXME noting what can be fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 19:35:46 +00:00
Dan Gohman
71c62a2977
Use comments to document non-obvious code rather than
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mailing list archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 19:13:40 +00:00
Bob Wilson
91a74da036
Rename canCombinedSubRegIndex method to something more grammatically correct
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and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 18:54:47 +00:00
Rafael Espindola
20fae65181
Replace ARM's getCalleeSavedRegClasses with a simpler solution
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 17:54:50 +00:00
Rafael Espindola
691820a1a0
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 15:44:20 +00:00
Rafael Espindola
6f07bd6ae8
cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 13:53:17 +00:00